Attachment 130382 Details for Bug 100320 – dmesg during

dmesg during

dmesg-during.log (text/plain), 31.06 MB, created by Jani Saarinen on 2017-03-22 16:33:56 UTC

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Creator: Jani Saarinen

Created: 2017-03-22 16:33:56 UTC

Size: 31.06 MB

patch

obsolete

>[   36.329397] Console: switching to colour dummy device 80x25
>[   36.329508] [IGT] core_auth: executing
>[   36.342549] [IGT] core_auth: starting subtest basic-auth
>[   36.342796] [IGT] core_auth: exiting, ret=0
>[   36.367732] Console: switching to colour frame buffer device 240x75
>[   36.483667] Console: switching to colour dummy device 80x25
>[   36.483757] [IGT] core_prop_blob: executing
>[   36.494567] [IGT] core_prop_blob: starting subtest basic
>[   36.494664] [IGT] core_prop_blob: exiting, ret=0
>[   36.534563] Console: switching to colour frame buffer device 240x75
>[   36.650158] Console: switching to colour dummy device 80x25
>[   36.650252] [IGT] drv_getparams_basic: executing
>[   36.659502] [IGT] drv_getparams_basic: starting subtest basic-eu-total
>[   36.659566] [IGT] drv_getparams_basic: exiting, ret=0
>[   36.701380] Console: switching to colour frame buffer device 240x75
>[   36.821380] Console: switching to colour dummy device 80x25
>[   36.821472] [IGT] drv_getparams_basic: executing
>[   36.831513] [IGT] drv_getparams_basic: starting subtest basic-subslice-total
>[   36.831576] [IGT] drv_getparams_basic: exiting, ret=0
>[   36.884873] Console: switching to colour frame buffer device 240x75
>[   37.000569] Console: switching to colour dummy device 80x25
>[   37.000660] [IGT] drv_hangman: executing
>[   37.010624] [IGT] drv_hangman: starting subtest error-state-basic
>[   37.010763] [drm:error_state_write [i915]] Resetting error state
>[   37.013528] [drm] GPU HANG: ecode 8:-1:0x00000000, reason: Manually setting wedged to 1, action: reset
>[   37.013538] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[   37.013540] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[   37.013542] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[   37.013544] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[   37.013546] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[   37.013844] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   37.013910] drm/i915: Resetting chip after gpu hang
>[   37.014696] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[   37.014823] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   37.014840] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[   37.014860] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   37.014879] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   37.014898] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   37.014916] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   37.014932] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[   37.032994] [drm:error_state_write [i915]] Resetting error state
>[   37.033164] [IGT] drv_hangman: exiting, ret=0
>[   37.051682] Console: switching to colour frame buffer device 240x75
>[   37.173929] Console: switching to colour dummy device 80x25
>[   37.174022] [IGT] gem_basic: executing
>[   37.182549] [IGT] gem_basic: starting subtest bad-close
>[   37.182611] [IGT] gem_basic: exiting, ret=0
>[   37.201846] Console: switching to colour frame buffer device 240x75
>[   37.314489] Console: switching to colour dummy device 80x25
>[   37.314579] [IGT] gem_basic: executing
>[   37.323546] [IGT] gem_basic: starting subtest create-close
>[   37.323633] [IGT] gem_basic: exiting, ret=0
>[   37.351954] Console: switching to colour frame buffer device 240x75
>[   37.461230] Console: switching to colour dummy device 80x25
>[   37.461325] [IGT] gem_basic: executing
>[   37.471557] [IGT] gem_basic: starting subtest create-fd-close
>[   37.471768] [IGT] gem_basic: exiting, ret=0
>[   37.518759] Console: switching to colour frame buffer device 240x75
>[   37.638488] Console: switching to colour dummy device 80x25
>[   37.638580] [IGT] gem_busy: executing
>[   37.649319] [IGT] gem_busy: starting subtest basic-busy-default
>[   37.669645] [IGT] gem_busy: exiting, ret=0
>[   37.718975] Console: switching to colour frame buffer device 240x75
>[   37.841515] Console: switching to colour dummy device 80x25
>[   37.841608] [IGT] gem_busy: executing
>[   37.853557] [IGT] gem_busy: starting subtest basic-hang-default
>[   53.738704] [drm] GPU HANG: ecode 8:0:0xe75ffefe, in gem_busy [6262], reason: Hang on render ring, action: reset
>[   53.738983] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   53.739103] drm/i915: Resetting chip after gpu hang
>[   53.739945] [drm:i915_gem_reset [i915]] context gem_busy[6262]/0 marked guilty (score 10) banned? no
>[   53.739970] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x168
>[   53.740186] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[   53.742505] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   53.742523] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x168, 0x0]
>[   53.742545] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[   53.742565] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   53.742585] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   53.742604] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   53.742622] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   53.742639] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[   53.743234] [IGT] gem_busy: exiting, ret=0
>[   53.783295] Console: switching to colour frame buffer device 240x75
>[   54.081511] Console: switching to colour dummy device 80x25
>[   54.081605] [IGT] gem_close_race: executing
>[   54.092165] [IGT] gem_close_race: starting subtest basic-process
>[   54.097937] [IGT] gem_close_race: exiting, ret=0
>[   54.133607] Console: switching to colour frame buffer device 240x75
>[   54.251091] Console: switching to colour dummy device 80x25
>[   54.251254] [IGT] gem_close_race: executing
>[   54.261314] [IGT] gem_close_race: starting subtest basic-threads
>[   55.337929] [IGT] gem_close_race: exiting, ret=0
>[   55.384730] Console: switching to colour frame buffer device 240x75
>[   55.506784] Console: switching to colour dummy device 80x25
>[   55.506878] [IGT] gem_cpu_reloc: executing
>[   55.515627] [IGT] gem_cpu_reloc: starting subtest basic
>[   55.519213] [IGT] gem_cpu_reloc: exiting, ret=0
>[   55.568218] Console: switching to colour frame buffer device 240x75
>[   55.685449] Console: switching to colour dummy device 80x25
>[   55.685575] [IGT] gem_cs_tlb: executing
>[   55.710418] [IGT] gem_cs_tlb: starting subtest basic-default
>[   57.131706] [IGT] gem_cs_tlb: exiting, ret=0
>[   57.169683] Console: switching to colour frame buffer device 240x75
>[   57.262220] Console: switching to colour dummy device 80x25
>[   57.262307] [IGT] gem_ctx_basic: executing
>[   60.612619] [IGT] gem_ctx_basic: exiting, ret=0
>[   60.706157] Console: switching to colour frame buffer device 240x75
>[   61.034153] Console: switching to colour dummy device 80x25
>[   61.034263] [IGT] gem_ctx_create: executing
>[   61.059532] [IGT] gem_ctx_create: starting subtest basic
>[   61.060484] [IGT] gem_ctx_create: exiting, ret=0
>[   61.106506] Console: switching to colour frame buffer device 240x75
>[   61.227773] Console: switching to colour dummy device 80x25
>[   61.227876] [IGT] gem_ctx_create: executing
>[   61.248165] [IGT] gem_ctx_create: starting subtest basic-files
>[   66.725350] [IGT] gem_ctx_create: exiting, ret=0
>[   66.778260] Console: switching to colour frame buffer device 240x75
>[   67.011169] Console: switching to colour dummy device 80x25
>[   67.011264] [IGT] gem_ctx_exec: executing
>[   67.021289] [IGT] gem_ctx_exec: starting subtest basic
>[   67.021801] [IGT] gem_ctx_exec: exiting, ret=0
>[   67.045158] Console: switching to colour frame buffer device 240x75
>[   67.173819] Console: switching to colour dummy device 80x25
>[   67.173912] [IGT] gem_ctx_param: executing
>[   67.182351] [IGT] gem_ctx_param: starting subtest basic
>[   67.182479] [IGT] gem_ctx_param: exiting, ret=0
>[   67.228636] Console: switching to colour frame buffer device 240x75
>[   67.351591] Console: switching to colour dummy device 80x25
>[   67.351685] [IGT] gem_ctx_param: executing
>[   67.361382] [IGT] gem_ctx_param: starting subtest basic-default
>[   67.361513] [IGT] gem_ctx_param: exiting, ret=0
>[   67.395452] Console: switching to colour frame buffer device 240x75
>[   67.508116] Console: switching to colour dummy device 80x25
>[   67.508214] [IGT] gem_ctx_switch: executing
>[   67.533788] [IGT] gem_ctx_switch: starting subtest basic-default
>[   72.812117] [IGT] gem_ctx_switch: exiting, ret=0
>[   72.883677] Console: switching to colour frame buffer device 240x75
>[   73.104207] Console: switching to colour dummy device 80x25
>[   73.104342] [IGT] gem_ctx_switch: executing
>[   73.114501] [IGT] gem_ctx_switch: starting subtest basic-default-heavy
>[   91.384072] [IGT] gem_ctx_switch: exiting, ret=0
>[   91.433627] Console: switching to colour frame buffer device 240x75
>[   91.722770] Console: switching to colour dummy device 80x25
>[   91.722862] [IGT] gem_exec_basic: executing
>[   91.733544] [IGT] gem_exec_basic: starting subtest basic-blt
>[   91.734489] [IGT] gem_exec_basic: exiting, ret=0
>[   91.783908] Console: switching to colour frame buffer device 240x75
>[   91.903069] Console: switching to colour dummy device 80x25
>[   91.903160] [IGT] gem_exec_basic: executing
>[   91.913469] [IGT] gem_exec_basic: starting subtest basic-bsd
>[   91.914370] [IGT] gem_exec_basic: exiting, ret=0
>[   91.950722] Console: switching to colour frame buffer device 240x75
>[   92.067881] Console: switching to colour dummy device 80x25
>[   92.067975] [IGT] gem_exec_basic: executing
>[   92.078546] [IGT] gem_exec_basic: starting subtest basic-bsd1
>[   92.079519] [IGT] gem_exec_basic: exiting, ret=0
>[   92.134222] Console: switching to colour frame buffer device 240x75
>[   92.250777] Console: switching to colour dummy device 80x25
>[   92.250871] [IGT] gem_exec_basic: executing
>[   92.260549] [IGT] gem_exec_basic: starting subtest basic-bsd2
>[   92.261517] [IGT] gem_exec_basic: exiting, ret=0
>[   92.301038] Console: switching to colour frame buffer device 240x75
>[   92.420717] Console: switching to colour dummy device 80x25
>[   92.420810] [IGT] gem_exec_basic: executing
>[   92.431562] [IGT] gem_exec_basic: starting subtest basic-default
>[   92.432498] [IGT] gem_exec_basic: exiting, ret=0
>[   92.467850] Console: switching to colour frame buffer device 240x75
>[   92.585116] Console: switching to colour dummy device 80x25
>[   92.585207] [IGT] gem_exec_basic: executing
>[   92.595515] [IGT] gem_exec_basic: starting subtest basic-render
>[   92.596428] [IGT] gem_exec_basic: exiting, ret=0
>[   92.651345] Console: switching to colour frame buffer device 240x75
>[   92.767869] Console: switching to colour dummy device 80x25
>[   92.767964] [IGT] gem_exec_basic: executing
>[   92.778570] [IGT] gem_exec_basic: starting subtest basic-vebox
>[   92.779556] [IGT] gem_exec_basic: exiting, ret=0
>[   92.834856] Console: switching to colour frame buffer device 240x75
>[   92.957930] Console: switching to colour dummy device 80x25
>[   92.958024] [IGT] gem_exec_basic: executing
>[   92.969601] [IGT] gem_exec_basic: starting subtest gtt-blt
>[   92.970908] [IGT] gem_exec_basic: exiting, ret=0
>[   93.018340] Console: switching to colour frame buffer device 240x75
>[   93.134518] Console: switching to colour dummy device 80x25
>[   93.134614] [IGT] gem_exec_basic: executing
>[   93.160289] [IGT] gem_exec_basic: starting subtest gtt-bsd
>[   93.161463] [IGT] gem_exec_basic: exiting, ret=0
>[   93.201839] Console: switching to colour frame buffer device 240x75
>[   93.319464] Console: switching to colour dummy device 80x25
>[   93.319639] [IGT] gem_exec_basic: executing
>[   93.328596] [IGT] gem_exec_basic: starting subtest gtt-bsd1
>[   93.329676] [IGT] gem_exec_basic: exiting, ret=0
>[   93.368658] Console: switching to colour frame buffer device 240x75
>[   93.486598] Console: switching to colour dummy device 80x25
>[   93.486693] [IGT] gem_exec_basic: executing
>[   93.512312] [IGT] gem_exec_basic: starting subtest gtt-bsd2
>[   93.514435] [IGT] gem_exec_basic: exiting, ret=0
>[   93.568833] Console: switching to colour frame buffer device 240x75
>[   93.685616] Console: switching to colour dummy device 80x25
>[   93.685713] [IGT] gem_exec_basic: executing
>[   93.711361] [IGT] gem_exec_basic: starting subtest gtt-default
>[   93.712492] [IGT] gem_exec_basic: exiting, ret=0
>[   93.752332] Console: switching to colour frame buffer device 240x75
>[   93.872069] Console: switching to colour dummy device 80x25
>[   93.872162] [IGT] gem_exec_basic: executing
>[   93.882615] [IGT] gem_exec_basic: starting subtest gtt-render
>[   93.883668] [IGT] gem_exec_basic: exiting, ret=0
>[   93.935830] Console: switching to colour frame buffer device 240x75
>[   94.054053] Console: switching to colour dummy device 80x25
>[   94.054147] [IGT] gem_exec_basic: executing
>[   94.063657] [IGT] gem_exec_basic: starting subtest gtt-vebox
>[   94.064833] [IGT] gem_exec_basic: exiting, ret=0
>[   94.102662] Console: switching to colour frame buffer device 240x75
>[   94.223437] Console: switching to colour dummy device 80x25
>[   94.223529] [IGT] gem_exec_basic: executing
>[   94.233663] [IGT] gem_exec_basic: starting subtest readonly-blt
>[   94.234650] [IGT] gem_exec_basic: exiting, ret=0
>[   94.286142] Console: switching to colour frame buffer device 240x75
>[   94.406300] Console: switching to colour dummy device 80x25
>[   94.406390] [IGT] gem_exec_basic: executing
>[   94.417704] [IGT] gem_exec_basic: starting subtest readonly-bsd
>[   94.418764] [IGT] gem_exec_basic: exiting, ret=0
>[   94.452962] Console: switching to colour frame buffer device 240x75
>[   94.567298] Console: switching to colour dummy device 80x25
>[   94.567390] [IGT] gem_exec_basic: executing
>[   94.576718] [IGT] gem_exec_basic: starting subtest readonly-bsd1
>[   94.577742] [IGT] gem_exec_basic: exiting, ret=0
>[   94.619787] Console: switching to colour frame buffer device 240x75
>[   94.741177] Console: switching to colour dummy device 80x25
>[   94.741274] [IGT] gem_exec_basic: executing
>[   94.751745] [IGT] gem_exec_basic: starting subtest readonly-bsd2
>[   94.752781] [IGT] gem_exec_basic: exiting, ret=0
>[   94.803271] Console: switching to colour frame buffer device 240x75
>[   94.920950] Console: switching to colour dummy device 80x25
>[   94.921042] [IGT] gem_exec_basic: executing
>[   94.930709] [IGT] gem_exec_basic: starting subtest readonly-default
>[   94.931723] [IGT] gem_exec_basic: exiting, ret=0
>[   94.986771] Console: switching to colour frame buffer device 240x75
>[   95.102778] Console: switching to colour dummy device 80x25
>[   95.102872] [IGT] gem_exec_basic: executing
>[   95.128399] [IGT] gem_exec_basic: starting subtest readonly-render
>[   95.129446] [IGT] gem_exec_basic: exiting, ret=0
>[   95.170265] Console: switching to colour frame buffer device 240x75
>[   95.297431] Console: switching to colour dummy device 80x25
>[   95.297523] [IGT] gem_exec_basic: executing
>[   95.308726] [IGT] gem_exec_basic: starting subtest readonly-vebox
>[   95.309688] [IGT] gem_exec_basic: exiting, ret=0
>[   95.353766] Console: switching to colour frame buffer device 240x75
>[   95.469731] Console: switching to colour dummy device 80x25
>[   95.469828] [IGT] gem_exec_create: executing
>[   95.495421] [IGT] gem_exec_create: starting subtest basic
>[  100.921015] [IGT] gem_exec_create: exiting, ret=0
>[  100.958800] Console: switching to colour frame buffer device 240x75
>[  101.132650] Console: switching to colour dummy device 80x25
>[  101.132742] [IGT] gem_exec_fence: executing
>[  101.142454] [IGT] gem_exec_fence: starting subtest basic-busy-default
>[  101.178115] [IGT] gem_exec_fence: exiting, ret=0
>[  101.209006] Console: switching to colour frame buffer device 240x75
>[  101.327273] Console: switching to colour dummy device 80x25
>[  101.327373] [IGT] gem_exec_fence: executing
>[  101.337515] [IGT] gem_exec_fence: starting subtest basic-wait-default
>[  101.374208] [IGT] gem_exec_fence: exiting, ret=0
>[  101.409173] Console: switching to colour frame buffer device 240x75
>[  101.530599] Console: switching to colour dummy device 80x25
>[  101.530692] [IGT] gem_exec_fence: executing
>[  101.540470] [IGT] gem_exec_fence: starting subtest basic-await-default
>[  102.547842] [IGT] gem_exec_fence: exiting, ret=0
>[  102.593567] Console: switching to colour frame buffer device 240x75
>[  102.713250] Console: switching to colour dummy device 80x25
>[  102.713345] [IGT] gem_exec_fence: executing
>[  102.734344] [IGT] gem_exec_fence: starting subtest await-hang-default
>[  106.730650] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  112.749834] [drm] GPU HANG: ecode 8:0:0xe757fefe, in gem_exec_fence [6429], reason: Hang on render ring, action: reset
>[  112.749936] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  112.749978] drm/i915: Resetting chip after gpu hang
>[  112.750525] [drm:i915_gem_reset [i915]] context gem_exec_fence[6429]/0 marked guilty (score 10) banned? no
>[  112.750546] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x3c0bc
>[  112.750631] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  112.750831] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  112.750858] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x3c0be, 0x0]
>[  112.750887] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  112.750920] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  112.750949] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  112.750979] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  112.751007] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  112.751032] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  112.751586] [IGT] gem_exec_fence: exiting, ret=0
>[  112.802704] Console: switching to colour frame buffer device 240x75
>[  113.099052] Console: switching to colour dummy device 80x25
>[  113.099150] [IGT] gem_exec_fence: executing
>[  113.109233] [IGT] gem_exec_fence: starting subtest nb-await-default
>[  114.111121] [IGT] gem_exec_fence: exiting, ret=0
>[  114.153888] Console: switching to colour frame buffer device 240x75
>[  114.274665] Console: switching to colour dummy device 80x25
>[  114.274806] [IGT] gem_exec_flush: executing
>[  114.283965] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-cmd
>[  114.285233] [IGT] gem_exec_flush: exiting, ret=77
>[  114.337389] Console: switching to colour frame buffer device 240x75
>[  114.458135] Console: switching to colour dummy device 80x25
>[  114.458227] [IGT] gem_exec_flush: executing
>[  114.472977] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-uc
>[  120.020301] [IGT] gem_exec_flush: exiting, ret=0
>[  120.075869] Console: switching to colour frame buffer device 240x75
>[  120.197226] Console: switching to colour dummy device 80x25
>[  120.197325] [IGT] gem_exec_flush: executing
>[  120.208279] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-wb
>[  125.790659] [IGT] gem_exec_flush: exiting, ret=0
>[  125.830984] Console: switching to colour frame buffer device 240x75
>[  126.077296] Console: switching to colour dummy device 80x25
>[  126.077395] [IGT] gem_exec_flush: executing
>[  126.086687] [IGT] gem_exec_flush: starting subtest basic-uc-pro-default
>[  131.462634] [IGT] gem_exec_flush: exiting, ret=0
>[  131.502680] Console: switching to colour frame buffer device 240x75
>[  131.750060] Console: switching to colour dummy device 80x25
>[  131.750154] [IGT] gem_exec_flush: executing
>[  131.765057] [IGT] gem_exec_flush: starting subtest basic-uc-prw-default
>[  137.140759] [IGT] gem_exec_flush: exiting, ret=0
>[  137.174451] Console: switching to colour frame buffer device 240x75
>[  137.432433] Console: switching to colour dummy device 80x25
>[  137.432530] [IGT] gem_exec_flush: executing
>[  137.443348] [IGT] gem_exec_flush: starting subtest basic-uc-ro-default
>[  142.819388] [IGT] gem_exec_flush: exiting, ret=0
>[  142.862838] Console: switching to colour frame buffer device 240x75
>[  143.107859] Console: switching to colour dummy device 80x25
>[  143.107956] [IGT] gem_exec_flush: executing
>[  143.118685] [IGT] gem_exec_flush: starting subtest basic-uc-rw-default
>[  148.494021] [IGT] gem_exec_flush: exiting, ret=0
>[  148.534572] Console: switching to colour frame buffer device 240x75
>[  148.796129] Console: switching to colour dummy device 80x25
>[  148.796222] [IGT] gem_exec_flush: executing
>[  148.807969] [IGT] gem_exec_flush: starting subtest basic-uc-set-default
>[  154.183802] [IGT] gem_exec_flush: exiting, ret=0
>[  154.239660] Console: switching to colour frame buffer device 240x75
>[  154.502444] Console: switching to colour dummy device 80x25
>[  154.502542] [IGT] gem_exec_flush: executing
>[  154.512394] [IGT] gem_exec_flush: starting subtest basic-wb-pro-default
>[  159.888724] [IGT] gem_exec_flush: exiting, ret=0
>[  159.928090] Console: switching to colour frame buffer device 240x75
>[  160.068051] Console: switching to colour dummy device 80x25
>[  160.068144] [IGT] gem_exec_flush: executing
>[  160.078653] [IGT] gem_exec_flush: starting subtest basic-wb-prw-default
>[  165.454307] [IGT] gem_exec_flush: exiting, ret=0
>[  165.499742] Console: switching to colour frame buffer device 240x75
>[  165.770103] Console: switching to colour dummy device 80x25
>[  165.770198] [IGT] gem_exec_flush: executing
>[  165.781051] [IGT] gem_exec_flush: starting subtest basic-wb-ro-before-default
>[  171.156321] [IGT] gem_exec_flush: exiting, ret=0
>[  171.204838] Console: switching to colour frame buffer device 240x75
>[  171.479254] Console: switching to colour dummy device 80x25
>[  171.479354] [IGT] gem_exec_flush: executing
>[  171.500069] [IGT] gem_exec_flush: starting subtest basic-wb-ro-default
>[  176.876254] [IGT] gem_exec_flush: exiting, ret=0
>[  176.926673] Console: switching to colour frame buffer device 240x75
>[  177.174151] Console: switching to colour dummy device 80x25
>[  177.174248] [IGT] gem_exec_flush: executing
>[  177.184768] [IGT] gem_exec_flush: starting subtest basic-wb-rw-before-default
>[  182.560497] [IGT] gem_exec_flush: exiting, ret=0
>[  182.598384] Console: switching to colour frame buffer device 240x75
>[  182.849226] Console: switching to colour dummy device 80x25
>[  182.849322] [IGT] gem_exec_flush: executing
>[  182.859127] [IGT] gem_exec_flush: starting subtest basic-wb-rw-default
>[  188.234972] [IGT] gem_exec_flush: exiting, ret=0
>[  188.270094] Console: switching to colour frame buffer device 240x75
>[  188.526424] Console: switching to colour dummy device 80x25
>[  188.526520] [IGT] gem_exec_flush: executing
>[  188.552086] [IGT] gem_exec_flush: starting subtest basic-wb-set-default
>[  193.927631] [IGT] gem_exec_flush: exiting, ret=0
>[  193.975178] Console: switching to colour frame buffer device 240x75
>[  194.216946] Console: switching to colour dummy device 80x25
>[  194.217038] [IGT] gem_exec_gttfill: executing
>[  194.226688] [IGT] gem_exec_gttfill: starting subtest basic
>[  194.234705] gem_exec_gttfil (6561): drop_caches: 4
>[  199.860135] [IGT] gem_exec_gttfill: exiting, ret=0
>[  199.897139] Console: switching to colour frame buffer device 240x75
>[  200.044364] Console: switching to colour dummy device 80x25
>[  200.044463] [IGT] gem_exec_nop: executing
>[  200.055346] [IGT] gem_exec_nop: starting subtest basic-parallel
>[  210.388513] [IGT] gem_exec_nop: exiting, ret=0
>[  210.423200] Console: switching to colour frame buffer device 240x75
>[  210.718845] Console: switching to colour dummy device 80x25
>[  210.718938] [IGT] gem_exec_nop: executing
>[  210.729854] [IGT] gem_exec_nop: starting subtest basic-series
>[  220.983139] [IGT] gem_exec_nop: exiting, ret=0
>[  221.032683] Console: switching to colour frame buffer device 240x75
>[  221.327953] Console: switching to colour dummy device 80x25
>[  221.328048] [IGT] gem_exec_parallel: executing
>[  221.338260] [IGT] gem_exec_parallel: starting subtest basic
>[  222.262392] [IGT] gem_exec_parallel: exiting, ret=0
>[  222.317171] Console: switching to colour frame buffer device 240x75
>[  222.443605] Console: switching to colour dummy device 80x25
>[  222.443696] [IGT] gem_exec_parse: executing
>[  222.453725] [IGT] gem_exec_parse: exiting, ret=77
>[  222.483960] Console: switching to colour frame buffer device 240x75
>[  222.600769] Console: switching to colour dummy device 80x25
>[  222.600861] [IGT] gem_exec_parse: executing
>[  222.609748] [IGT] gem_exec_parse: exiting, ret=77
>[  222.634121] Console: switching to colour frame buffer device 240x75
>[  222.749028] Console: switching to colour dummy device 80x25
>[  222.749120] [IGT] gem_exec_reloc: executing
>[  222.758738] [IGT] gem_exec_reloc: starting subtest basic-cpu
>[  222.759802] [IGT] gem_exec_reloc: exiting, ret=0
>[  222.800947] Console: switching to colour frame buffer device 240x75
>[  222.928415] Console: switching to colour dummy device 80x25
>[  222.928509] [IGT] gem_exec_reloc: executing
>[  222.937751] [IGT] gem_exec_reloc: starting subtest basic-gtt
>[  222.938845] [IGT] gem_exec_reloc: exiting, ret=0
>[  222.984434] Console: switching to colour frame buffer device 240x75
>[  223.107119] Console: switching to colour dummy device 80x25
>[  223.107212] [IGT] gem_exec_reloc: executing
>[  223.116715] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt
>[  223.117897] [IGT] gem_exec_reloc: exiting, ret=0
>[  223.167928] Console: switching to colour frame buffer device 240x75
>[  223.286606] Console: switching to colour dummy device 80x25
>[  223.286700] [IGT] gem_exec_reloc: executing
>[  223.296781] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu
>[  223.297923] [IGT] gem_exec_reloc: exiting, ret=0
>[  223.334744] Console: switching to colour frame buffer device 240x75
>[  223.459243] Console: switching to colour dummy device 80x25
>[  223.459379] [IGT] gem_exec_reloc: executing
>[  223.480549] [IGT] gem_exec_reloc: starting subtest basic-cpu-read
>[  223.481627] [IGT] gem_exec_reloc: exiting, ret=0
>[  223.518252] Console: switching to colour frame buffer device 240x75
>[  223.635980] Console: switching to colour dummy device 80x25
>[  223.636075] [IGT] gem_exec_reloc: executing
>[  223.645802] [IGT] gem_exec_reloc: starting subtest basic-gtt-read
>[  223.646812] [IGT] gem_exec_reloc: exiting, ret=0
>[  223.701741] Console: switching to colour frame buffer device 240x75
>[  223.823772] Console: switching to colour dummy device 80x25
>[  223.823864] [IGT] gem_exec_reloc: executing
>[  223.833815] [IGT] gem_exec_reloc: starting subtest basic-write-cpu
>[  223.834846] [IGT] gem_exec_reloc: exiting, ret=0
>[  223.885238] Console: switching to colour frame buffer device 240x75
>[  224.005598] Console: switching to colour dummy device 80x25
>[  224.005694] [IGT] gem_exec_reloc: executing
>[  224.015811] [IGT] gem_exec_reloc: starting subtest basic-write-gtt
>[  224.016911] [IGT] gem_exec_reloc: exiting, ret=0
>[  224.068743] Console: switching to colour frame buffer device 240x75
>[  224.191641] Console: switching to colour dummy device 80x25
>[  224.191732] [IGT] gem_exec_reloc: executing
>[  224.201783] [IGT] gem_exec_reloc: starting subtest basic-write-read
>[  224.202821] [IGT] gem_exec_reloc: exiting, ret=0
>[  224.252231] Console: switching to colour frame buffer device 240x75
>[  224.376622] Console: switching to colour dummy device 80x25
>[  224.376715] [IGT] gem_exec_reloc: executing
>[  224.386799] [IGT] gem_exec_reloc: starting subtest basic-cpu-noreloc
>[  224.387870] [IGT] gem_exec_reloc: exiting, ret=0
>[  224.435726] Console: switching to colour frame buffer device 240x75
>[  224.558548] Console: switching to colour dummy device 80x25
>[  224.558643] [IGT] gem_exec_reloc: executing
>[  224.587567] [IGT] gem_exec_reloc: starting subtest basic-gtt-noreloc
>[  224.588641] [IGT] gem_exec_reloc: exiting, ret=0
>[  224.619226] Console: switching to colour frame buffer device 240x75
>[  224.742663] Console: switching to colour dummy device 80x25
>[  224.742757] [IGT] gem_exec_reloc: executing
>[  224.752844] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-noreloc
>[  224.753921] [IGT] gem_exec_reloc: exiting, ret=0
>[  224.802722] Console: switching to colour frame buffer device 240x75
>[  224.927505] Console: switching to colour dummy device 80x25
>[  224.927601] [IGT] gem_exec_reloc: executing
>[  224.952559] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-noreloc
>[  224.953599] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.002903] Console: switching to colour frame buffer device 240x75
>[  225.122258] Console: switching to colour dummy device 80x25
>[  225.122351] [IGT] gem_exec_reloc: executing
>[  225.130878] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-noreloc
>[  225.131970] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.169716] Console: switching to colour frame buffer device 240x75
>[  225.294739] Console: switching to colour dummy device 80x25
>[  225.294828] [IGT] gem_exec_reloc: executing
>[  225.304852] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-noreloc
>[  225.305860] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.353215] Console: switching to colour frame buffer device 240x75
>[  225.474176] Console: switching to colour dummy device 80x25
>[  225.474273] [IGT] gem_exec_reloc: executing
>[  225.483905] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-noreloc
>[  225.484910] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.536710] Console: switching to colour frame buffer device 240x75
>[  225.653151] Console: switching to colour dummy device 80x25
>[  225.653241] [IGT] gem_exec_reloc: executing
>[  225.662879] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-noreloc
>[  225.663869] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.703547] Console: switching to colour frame buffer device 240x75
>[  225.828362] Console: switching to colour dummy device 80x25
>[  225.828455] [IGT] gem_exec_reloc: executing
>[  225.836925] [IGT] gem_exec_reloc: starting subtest basic-write-read-noreloc
>[  225.837842] [IGT] gem_exec_reloc: exiting, ret=0
>[  225.887027] Console: switching to colour frame buffer device 240x75
>[  226.006939] Console: switching to colour dummy device 80x25
>[  226.007030] [IGT] gem_exec_reloc: executing
>[  226.016902] [IGT] gem_exec_reloc: starting subtest basic-cpu-active
>[  226.120754] [IGT] gem_exec_reloc: exiting, ret=0
>[  226.153909] Console: switching to colour frame buffer device 240x75
>[  226.274715] Console: switching to colour dummy device 80x25
>[  226.274811] [IGT] gem_exec_reloc: executing
>[  226.299695] [IGT] gem_exec_reloc: starting subtest basic-gtt-active
>[  226.402898] [IGT] gem_exec_reloc: exiting, ret=0
>[  226.454199] Console: switching to colour frame buffer device 240x75
>[  226.581710] Console: switching to colour dummy device 80x25
>[  226.581801] [IGT] gem_exec_reloc: executing
>[  226.606675] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-active
>[  226.709815] [IGT] gem_exec_reloc: exiting, ret=0
>[  226.754465] Console: switching to colour frame buffer device 240x75
>[  226.874303] Console: switching to colour dummy device 80x25
>[  226.874394] [IGT] gem_exec_reloc: executing
>[  226.884002] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-active
>[  226.987145] [IGT] gem_exec_reloc: exiting, ret=0
>[  227.021380] Console: switching to colour frame buffer device 240x75
>[  227.151343] Console: switching to colour dummy device 80x25
>[  227.151433] [IGT] gem_exec_reloc: executing
>[  227.160969] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-active
>[  227.264108] [IGT] gem_exec_reloc: exiting, ret=0
>[  227.321657] Console: switching to colour frame buffer device 240x75
>[  227.441853] Console: switching to colour dummy device 80x25
>[  227.441945] [IGT] gem_exec_reloc: executing
>[  227.451979] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-active
>[  227.555153] [IGT] gem_exec_reloc: exiting, ret=0
>[  227.605224] Console: switching to colour frame buffer device 240x75
>[  227.723225] Console: switching to colour dummy device 80x25
>[  227.723316] [IGT] gem_exec_reloc: executing
>[  227.733037] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-active
>[  227.835795] [IGT] gem_exec_reloc: exiting, ret=0
>[  227.888811] Console: switching to colour frame buffer device 240x75
>[  228.013060] Console: switching to colour dummy device 80x25
>[  228.013151] [IGT] gem_exec_reloc: executing
>[  228.023076] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-active
>[  228.125844] [IGT] gem_exec_reloc: exiting, ret=0
>[  228.172398] Console: switching to colour frame buffer device 240x75
>[  228.294142] Console: switching to colour dummy device 80x25
>[  228.294237] [IGT] gem_exec_reloc: executing
>[  228.304094] [IGT] gem_exec_reloc: starting subtest basic-write-read-active
>[  228.407147] [IGT] gem_exec_reloc: exiting, ret=0
>[  228.439306] Console: switching to colour frame buffer device 240x75
>[  228.558605] Console: switching to colour dummy device 80x25
>[  228.558766] [IGT] gem_exec_reloc: executing
>[  228.587851] [IGT] gem_exec_reloc: starting subtest basic-softpin
>[  228.588160] [IGT] gem_exec_reloc: exiting, ret=0
>[  228.622799] Console: switching to colour frame buffer device 240x75
>[  228.749163] Console: switching to colour dummy device 80x25
>[  228.749255] [IGT] gem_exec_store: executing
>[  228.758731] [IGT] gem_exec_store: starting subtest basic-all
>[  228.789699] [IGT] gem_exec_store: exiting, ret=0
>[  228.839687] Console: switching to colour frame buffer device 240x75
>[  228.960893] Console: switching to colour dummy device 80x25
>[  228.960989] [IGT] gem_exec_store: executing
>[  228.970766] [IGT] gem_exec_store: starting subtest basic-blt
>[  229.011560] [IGT] gem_exec_store: exiting, ret=0
>[  229.056524] Console: switching to colour frame buffer device 240x75
>[  229.180759] Console: switching to colour dummy device 80x25
>[  229.180857] [IGT] gem_exec_store: executing
>[  229.190831] [IGT] gem_exec_store: starting subtest basic-bsd
>[  229.231563] [IGT] gem_exec_store: exiting, ret=0
>[  229.273383] Console: switching to colour frame buffer device 240x75
>[  229.400508] Console: switching to colour dummy device 80x25
>[  229.400599] [IGT] gem_exec_store: executing
>[  229.422557] [IGT] gem_exec_store: starting subtest basic-bsd1
>[  229.455492] [IGT] gem_exec_store: exiting, ret=0
>[  229.506924] Console: switching to colour frame buffer device 240x75
>[  229.624909] Console: switching to colour dummy device 80x25
>[  229.625001] [IGT] gem_exec_store: executing
>[  229.650501] [IGT] gem_exec_store: starting subtest basic-bsd2
>[  229.682516] [IGT] gem_exec_store: exiting, ret=0
>[  229.723800] Console: switching to colour frame buffer device 240x75
>[  229.849376] Console: switching to colour dummy device 80x25
>[  229.849469] [IGT] gem_exec_store: executing
>[  229.859862] [IGT] gem_exec_store: starting subtest basic-default
>[  229.900627] [IGT] gem_exec_store: exiting, ret=0
>[  229.940645] Console: switching to colour frame buffer device 240x75
>[  230.061521] Console: switching to colour dummy device 80x25
>[  230.061617] [IGT] gem_exec_store: executing
>[  230.071820] [IGT] gem_exec_store: starting subtest basic-render
>[  230.100666] [IGT] gem_exec_store: exiting, ret=0
>[  230.140835] Console: switching to colour frame buffer device 240x75
>[  230.261837] Console: switching to colour dummy device 80x25
>[  230.261931] [IGT] gem_exec_store: executing
>[  230.292565] [IGT] gem_exec_store: starting subtest basic-vebox
>[  230.316622] [IGT] gem_exec_store: exiting, ret=0
>[  230.357686] Console: switching to colour frame buffer device 240x75
>[  230.483396] Console: switching to colour dummy device 80x25
>[  230.483487] [IGT] gem_exec_suspend: executing
>[  230.493836] [IGT] gem_exec_suspend: starting subtest basic
>[  230.614721] [IGT] gem_exec_suspend: exiting, ret=0
>[  230.657961] Console: switching to colour frame buffer device 240x75
>[  230.778146] Console: switching to colour dummy device 80x25
>[  230.778239] [IGT] gem_exec_suspend: executing
>[  230.787880] [IGT] gem_exec_suspend: starting subtest basic-S3
>[  231.591119] PM: Syncing filesystems ... done.
>[  231.618348] PM: Preparing system for sleep (mem)
>[  231.619107] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  231.620945] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  231.621971] PM: Suspending system (mem)
>[  231.622102] Suspending console(s) (use no_console_suspend to debug)
>[  231.624536] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  231.629154] e1000e: EEE TX LPI TIMER: 00000011
>[  231.635057] sd 3:0:0:0: [sda] Stopping disk
>[  231.640009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  231.642113] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  231.642175] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  231.660518] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  231.660557] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  231.660577] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  231.660600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  231.660617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  231.660635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  231.660651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  231.660666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  231.660682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  231.660699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  231.660715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  231.660730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  231.660745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  231.660759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  231.660771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  231.660811] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  231.696919] PM: suspend of devices complete after 73.643 msecs
>[  231.698326] [drm:intel_power_well_disable [i915]] disabling display
>[  231.698367] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  231.698380] [drm:intel_power_well_disable [i915]] disabling always-on
>[  231.698398] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  231.709878] PM: late suspend of devices complete after 12.953 msecs
>[  231.711550] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  231.712174] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  231.712263] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  231.724857] PM: noirq suspend of devices complete after 14.974 msecs
>[  231.725116] ACPI: Preparing to enter system sleep state S3
>[  231.747474] PM: Saving platform NVS memory
>[  231.747620] Disabling non-boot CPUs ...
>[  231.761568] smpboot: CPU 1 is now offline
>[  231.774128] Broke affinity for irq 45
>[  231.775172] smpboot: CPU 2 is now offline
>[  231.784024] Broke affinity for irq 8
>[  231.784027] Broke affinity for irq 9
>[  231.784031] Broke affinity for irq 23
>[  231.784034] Broke affinity for irq 42
>[  231.784037] Broke affinity for irq 43
>[  231.784039] Broke affinity for irq 45
>[  231.785072] smpboot: CPU 3 is now offline
>[  231.788640] ACPI: Low-level resume complete
>[  231.788764] PM: Restoring platform NVS memory
>[  231.789320] Suspended for 15.539 seconds
>[  231.790019] Enabling non-boot CPUs ...
>[  231.790360] x86: Booting SMP configuration:
>[  231.790379] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  231.792580]  cache: parent cpu1 should not be sleeping
>[  231.793690] CPU1 is up
>[  231.793777] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  231.794985]  cache: parent cpu2 should not be sleeping
>[  231.795668] CPU2 is up
>[  231.795719] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  231.796732]  cache: parent cpu3 should not be sleeping
>[  231.797817] CPU3 is up
>[  231.804274] ACPI: Waking up from system sleep state S3
>[  231.817559] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  231.829129] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  231.829136] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  231.829325] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  231.829456] PM: noirq resume of devices complete after 12.379 msecs
>[  231.832510] hpet1: lost 4370 rtc interrupts
>[  231.833279] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  231.833371] [drm:intel_power_well_enable [i915]] enabling always-on
>[  231.833390] [drm:intel_power_well_enable [i915]] enabling display
>[  231.835155] PM: early resume of devices complete after 2.389 msecs
>[  231.835565] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  231.835613] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  231.835646] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  231.835647] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  231.838579] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  231.841009] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  231.841026] [drm:intel_opregion_setup [i915]] ASLE supported
>[  231.841040] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  231.841054] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  231.841254] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  231.841276] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  231.841296] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  231.841314] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  231.841333] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  231.841350] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  231.841365] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  231.841598] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  231.841673] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  231.841693] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  231.841712] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  231.841727] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  231.841745] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  231.841759] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  231.841778] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  231.841797] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  231.841817] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  231.841834] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  231.841852] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  231.841869] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  231.841889] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  231.841908] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  231.841936] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  231.841951] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  231.841965] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  231.842004] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  231.842029] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  231.842050] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  231.842078] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  231.842095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  231.842112] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  231.842129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  231.842134] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  231.842154] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842171] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  231.842188] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  231.842205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  231.842222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  231.842240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  231.842256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  231.842274] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  231.842291] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  231.842308] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  231.842326] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  231.842343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  231.842360] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  231.842377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  231.842380] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  231.842400] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842417] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  231.842434] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  231.842451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  231.842468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  231.842485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  231.842502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  231.842519] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  231.842536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  231.842554] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  231.842572] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  231.842589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  231.842606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  231.842622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  231.842625] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  231.842645] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  231.842662] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  231.842679] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  231.842696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  231.842713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  231.842730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  231.842747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  231.842764] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  231.842781] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  231.842798] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  231.842817] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  231.842833] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  231.842847] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  231.842904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  231.842933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  231.842962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  231.842980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  231.842995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  231.843011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  231.843027] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  231.843041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  231.843055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  231.843068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  231.843081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  231.843084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  231.843097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  231.843100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  231.843113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  231.843126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  231.843139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  231.843151] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  231.843166] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  231.843178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  231.843191] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  231.843203] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  231.843215] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  231.843230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  231.843247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  231.843576] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  231.845670] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  231.845689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  231.845705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  231.845720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  231.845735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  231.845749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  231.845765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  231.845782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  231.845799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  231.845815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  231.845830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  231.845845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  231.845859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  231.845872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  231.845897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  231.845931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  231.846225] sd 3:0:0:0: [sda] Starting disk
>[  231.847983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  231.848000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  231.848017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  231.848035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  231.849547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  231.849563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  231.849576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  231.851077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  231.851092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  231.852900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  231.855908] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  231.855975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  231.856000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  231.856029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  231.856097] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  231.856119] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  231.872733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  231.872758] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  231.872796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  231.872818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  231.872843] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  231.872974] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  231.873271] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  231.875048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  231.875067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  231.877100] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  231.877105] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  231.879174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  231.879190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  231.881234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  231.881240] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  231.881244] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  231.881262] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  231.882328] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  231.883220] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  231.883236] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  231.883250] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  231.883264] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  231.884251] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  231.884266] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  231.885234] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  231.885254] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  231.887331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  231.887351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  231.889121] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  231.889128] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  231.891191] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  231.891208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  231.893262] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  231.893266] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  231.893270] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  232.152592] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  232.193611] ata4.00: configured for UDMA/133
>[  232.349425] PM: resume of devices complete after 514.234 msecs
>[  232.350682] PM: Finishing wakeup.
>[  232.350685] Restarting tasks ... 
>[  232.351004] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  232.351012] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  232.354034] done.
>[  232.358595] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  233.027999] [IGT] gem_exec_suspend: exiting, ret=0
>[  233.073884] Console: switching to colour frame buffer device 240x75
>[  233.198373] Console: switching to colour dummy device 80x25
>[  233.198470] [IGT] gem_exec_suspend: executing
>[  233.209153] [IGT] gem_exec_suspend: starting subtest basic-S4-devices
>[  233.949000] PM: Syncing filesystems ... 
>[  233.972496] PM: done.
>[  233.972500] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  233.974405] PM: Marking nosave pages: [mem 0x00000000-0x00000fff]
>[  233.974412] PM: Marking nosave pages: [mem 0x00058000-0x00058fff]
>[  233.974414] PM: Marking nosave pages: [mem 0x0009f000-0x000fffff]
>[  233.974417] PM: Marking nosave pages: [mem 0x9d8aa000-0x9dd74fff]
>[  233.974432] PM: Marking nosave pages: [mem 0xa228f000-0xa2ffefff]
>[  233.974473] PM: Marking nosave pages: [mem 0xa3000000-0xffffffff]
>[  233.975159] PM: Basic memory bitmaps created
>[  233.976094] PM: Preallocating image memory... done (allocated 210947 pages)
>[  234.238522] PM: Allocated 843788 kbytes in 0.26 seconds (3245.33 MB/s)
>[  234.238524] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  234.240989] Suspending console(s) (use no_console_suspend to debug)
>[  234.255162] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  234.255167] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  234.260332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  234.274867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  234.274900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  234.293941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  234.293965] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  234.293985] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  234.294007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  234.294026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  234.294046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  234.294078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  234.294094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  234.294111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  234.294130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  234.294147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  234.294163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  234.294187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  234.294201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  234.294215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  234.294245] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  234.297193] PM: freeze of devices complete after 56.161 msecs
>[  234.297196] PM: hibernation debug: Waiting for 5 seconds.
>[  239.491618] usb usb2: root hub lost power or was reset
>[  239.491760] usb usb3: root hub lost power or was reset
>[  239.492264] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  239.492314] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  239.492339] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  239.492462] usb usb1: root hub lost power or was reset
>[  239.496368] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
>[  239.496832] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  239.501455] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  239.501473] [drm:intel_opregion_setup [i915]] ASLE supported
>[  239.501487] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  239.501501] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  239.501654] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  239.501671] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  239.501695] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  239.501726] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  239.501756] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  239.501784] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  239.501804] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  239.502098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  239.502162] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  239.502180] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  239.502201] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  239.502218] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  239.502239] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  239.502256] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  239.502275] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  239.502295] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  239.502314] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  239.502331] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  239.502349] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  239.502366] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  239.502409] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  239.502428] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  239.502446] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  239.502461] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  239.502475] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  239.502496] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  239.502519] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  239.502547] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  239.502581] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  239.502603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  239.502625] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  239.502646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  239.502652] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.502673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  239.502678] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.502699] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  239.502720] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  239.502740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  239.502759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  239.502775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  239.502790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  239.502806] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  239.502821] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  239.502838] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  239.502854] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  239.502869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  239.502884] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  239.502896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  239.502900] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.502913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  239.502916] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.502931] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  239.502946] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  239.502958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  239.502973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  239.502990] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  239.503004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  239.503018] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  239.503033] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  239.503046] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  239.503061] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  239.503076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  239.503090] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  239.503102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  239.503105] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.503119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  239.503122] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  239.503138] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  239.503156] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  239.503170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  239.503184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  239.503201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  239.503217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  239.503229] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  239.503244] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  239.503259] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  239.503277] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  239.503291] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  239.503307] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  239.503350] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  239.503368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  239.503405] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  239.503426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  239.503440] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  239.503455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  239.503473] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  239.503490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  239.503505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  239.503520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  239.503536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  239.503539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  239.503555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  239.503557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  239.503574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  239.503586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  239.503598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  239.503613] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  239.503629] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  239.503644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  239.503661] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  239.503681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  239.503694] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  239.503710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  239.503729] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  239.503792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  239.503809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  239.503824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  239.503839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  239.503853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  239.503869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  239.503888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  239.503906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  239.503921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  239.503935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  239.503951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  239.503966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  239.503978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  239.503997] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  239.504014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  239.504197] sd 3:0:0:0: [sda] Starting disk
>[  239.506029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  239.506046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  239.506060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  239.506074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  239.507581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  239.507596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  239.507609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  239.509107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  239.509121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  239.510928] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  239.513885] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  239.513911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  239.513926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  239.513947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  239.513979] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  239.513994] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  239.530684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  239.530709] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  239.530746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  239.530765] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  239.530786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  239.530879] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  239.530929] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  239.532839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  239.532858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  239.534923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  239.534928] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  239.536995] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  239.537014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  239.539066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  239.539070] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  239.539075] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  239.539093] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  239.540118] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  239.541007] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  239.541023] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  239.541036] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  239.541050] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  239.542037] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  239.542051] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  239.542972] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  239.542989] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  239.545053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  239.545068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  239.547127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  239.547130] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  239.549191] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  239.549205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  239.551250] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  239.551253] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  239.551256] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  239.809358] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  239.811837] usb 1-1: reset high-speed USB device number 2 using ehci-pci
>[  239.850300] ata4.00: configured for UDMA/133
>[  239.871650] usb 2-7: reset full-speed USB device number 2 using xhci_hcd
>[  240.049597] PM: restore of devices complete after 558.469 msecs
>[  240.050695] PM: Image restored successfully.
>[  240.050975] PM: Basic memory bitmaps freed
>[  240.050978] Restarting tasks ... done.
>[  240.062307] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  240.740771] [IGT] gem_exec_suspend: exiting, ret=0
>[  240.781895] Console: switching to colour frame buffer device 240x75
>[  240.908774] Console: switching to colour dummy device 80x25
>[  240.908865] [IGT] gem_flink_basic: executing
>[  240.918906] [IGT] gem_flink_basic: starting subtest bad-flink
>[  240.918959] [IGT] gem_flink_basic: exiting, ret=0
>[  240.948708] Console: switching to colour frame buffer device 240x75
>[  241.073622] Console: switching to colour dummy device 80x25
>[  241.073720] [IGT] gem_flink_basic: executing
>[  241.098624] [IGT] gem_flink_basic: starting subtest bad-open
>[  241.098687] [IGT] gem_flink_basic: exiting, ret=0
>[  241.115537] Console: switching to colour frame buffer device 240x75
>[  241.231600] Console: switching to colour dummy device 80x25
>[  241.231696] [IGT] gem_flink_basic: executing
>[  241.260651] [IGT] gem_flink_basic: starting subtest basic
>[  241.260730] [IGT] gem_flink_basic: exiting, ret=0
>[  241.282338] Console: switching to colour frame buffer device 240x75
>[  241.402376] Console: switching to colour dummy device 80x25
>[  241.402470] [IGT] gem_flink_basic: executing
>[  241.411924] [IGT] gem_flink_basic: starting subtest double-flink
>[  241.412009] [IGT] gem_flink_basic: exiting, ret=0
>[  241.432471] Console: switching to colour frame buffer device 240x75
>[  241.552174] Console: switching to colour dummy device 80x25
>[  241.552269] [IGT] gem_flink_basic: executing
>[  241.561948] [IGT] gem_flink_basic: starting subtest flink-lifetime
>[  241.562167] [IGT] gem_flink_basic: exiting, ret=0
>[  241.582619] Console: switching to colour frame buffer device 240x75
>[  241.679629] Console: switching to colour dummy device 80x25
>[  241.679717] [IGT] gem_linear_blits: executing
>[  241.704666] [IGT] gem_linear_blits: starting subtest basic
>[  241.713458] [IGT] gem_linear_blits: exiting, ret=0
>[  241.749432] Console: switching to colour frame buffer device 240x75
>[  241.873083] Console: switching to colour dummy device 80x25
>[  241.873172] [IGT] gem_mmap: executing
>[  241.882949] [IGT] gem_mmap: starting subtest basic
>[  241.883169] [IGT] gem_mmap: exiting, ret=0
>[  241.932922] Console: switching to colour frame buffer device 240x75
>[  242.055406] Console: switching to colour dummy device 80x25
>[  242.055502] [IGT] gem_mmap: executing
>[  242.064953] [IGT] gem_mmap: starting subtest basic-small-bo
>[  242.243757] [IGT] gem_mmap: exiting, ret=0
>[  242.283232] Console: switching to colour frame buffer device 240x75
>[  242.429746] Console: switching to colour dummy device 80x25
>[  242.429842] [IGT] gem_mmap_gtt: executing
>[  242.450735] [IGT] gem_mmap_gtt: starting subtest basic
>[  242.450897] [IGT] gem_mmap_gtt: exiting, ret=0
>[  242.466725] Console: switching to colour frame buffer device 240x75
>[  242.593890] Console: switching to colour dummy device 80x25
>[  242.593984] [IGT] gem_mmap_gtt: executing
>[  242.604008] [IGT] gem_mmap_gtt: starting subtest basic-copy
>[  242.760929] [IGT] gem_mmap_gtt: exiting, ret=0
>[  242.800364] Console: switching to colour frame buffer device 240x75
>[  242.925030] Console: switching to colour dummy device 80x25
>[  242.925125] [IGT] gem_mmap_gtt: executing
>[  242.935015] [IGT] gem_mmap_gtt: starting subtest basic-read
>[  242.953027] [IGT] gem_mmap_gtt: exiting, ret=0
>[  243.000541] Console: switching to colour frame buffer device 240x75
>[  243.027042] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  243.132187] Console: switching to colour dummy device 80x25
>[  243.132299] [IGT] gem_mmap_gtt: executing
>[  243.157772] [IGT] gem_mmap_gtt: starting subtest basic-read-no-prefault
>[  243.157862] Setting dangerous option prefault_disable - tainting kernel
>[  243.176047] Setting dangerous option prefault_disable - tainting kernel
>[  243.176146] [IGT] gem_mmap_gtt: exiting, ret=0
>[  243.176209] Setting dangerous option prefault_disable - tainting kernel
>[  243.217396] Console: switching to colour frame buffer device 240x75
>[  243.345737] Console: switching to colour dummy device 80x25
>[  243.345830] [IGT] gem_mmap_gtt: executing
>[  243.370778] [IGT] gem_mmap_gtt: starting subtest basic-read-write
>[  243.377933] [IGT] gem_mmap_gtt: exiting, ret=0
>[  243.417580] Console: switching to colour frame buffer device 240x75
>[  243.537395] Console: switching to colour dummy device 80x25
>[  243.537489] [IGT] gem_mmap_gtt: executing
>[  243.547049] [IGT] gem_mmap_gtt: starting subtest basic-read-write-distinct
>[  243.554314] [IGT] gem_mmap_gtt: exiting, ret=0
>[  243.601072] Console: switching to colour frame buffer device 240x75
>[  243.728020] Console: switching to colour dummy device 80x25
>[  243.728111] [IGT] gem_mmap_gtt: executing
>[  243.738069] [IGT] gem_mmap_gtt: starting subtest basic-short
>[  243.750856] [IGT] gem_mmap_gtt: exiting, ret=0
>[  243.784574] Console: switching to colour frame buffer device 240x75
>[  243.906891] Console: switching to colour dummy device 80x25
>[  243.906983] [IGT] gem_mmap_gtt: executing
>[  243.917054] [IGT] gem_mmap_gtt: starting subtest basic-small-bo
>[  243.990029] [IGT] gem_mmap_gtt: exiting, ret=0
>[  244.068185] Console: switching to colour frame buffer device 240x75
>[  244.213026] Console: switching to colour dummy device 80x25
>[  244.213120] [IGT] gem_mmap_gtt: executing
>[  244.223109] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledX
>[  244.293862] [IGT] gem_mmap_gtt: exiting, ret=0
>[  244.368411] Console: switching to colour frame buffer device 240x75
>[  244.516060] Console: switching to colour dummy device 80x25
>[  244.516154] [IGT] gem_mmap_gtt: executing
>[  244.526128] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledY
>[  244.596788] [IGT] gem_mmap_gtt: exiting, ret=0
>[  244.668688] Console: switching to colour frame buffer device 240x75
>[  244.810796] Console: switching to colour dummy device 80x25
>[  244.810895] [IGT] gem_mmap_gtt: executing
>[  244.835922] [IGT] gem_mmap_gtt: starting subtest basic-small-copy
>[  245.059535] [IGT] gem_mmap_gtt: exiting, ret=0
>[  245.102419] Console: switching to colour frame buffer device 240x75
>[  245.243086] Console: switching to colour dummy device 80x25
>[  245.243179] [IGT] gem_mmap_gtt: executing
>[  245.253138] [IGT] gem_mmap_gtt: starting subtest basic-small-copy-XY
>[  245.516235] [IGT] gem_mmap_gtt: exiting, ret=0
>[  245.586181] Console: switching to colour frame buffer device 240x75
>[  245.729200] Console: switching to colour dummy device 80x25
>[  245.729294] [IGT] gem_mmap_gtt: executing
>[  245.739150] [IGT] gem_mmap_gtt: starting subtest basic-wc
>[  246.368767] [IGT] gem_mmap_gtt: exiting, ret=0
>[  246.403615] Console: switching to colour frame buffer device 240x75
>[  246.535013] Console: switching to colour dummy device 80x25
>[  246.535157] [IGT] gem_mmap_gtt: executing
>[  246.550136] [IGT] gem_mmap_gtt: starting subtest basic-write
>[  246.634391] [IGT] gem_mmap_gtt: exiting, ret=0
>[  246.670485] Console: switching to colour frame buffer device 240x75
>[  246.796942] Console: switching to colour dummy device 80x25
>[  246.797038] [IGT] gem_mmap_gtt: executing
>[  246.821968] [IGT] gem_mmap_gtt: starting subtest basic-write-cpu-read-gtt
>[  246.988358] [IGT] gem_mmap_gtt: exiting, ret=0
>[  247.037481] Console: switching to colour frame buffer device 240x75
>[  247.157848] Console: switching to colour dummy device 80x25
>[  247.157946] [IGT] gem_mmap_gtt: executing
>[  247.179054] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt
>[  247.263516] [IGT] gem_mmap_gtt: exiting, ret=0
>[  247.304386] Console: switching to colour frame buffer device 240x75
>[  247.429263] Console: switching to colour dummy device 80x25
>[  247.429357] [IGT] gem_mmap_gtt: executing
>[  247.439297] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt-no-prefault
>[  247.439372] Setting dangerous option prefault_disable - tainting kernel
>[  247.524333] Setting dangerous option prefault_disable - tainting kernel
>[  247.524436] [IGT] gem_mmap_gtt: exiting, ret=0
>[  247.524502] Setting dangerous option prefault_disable - tainting kernel
>[  247.571288] Console: switching to colour frame buffer device 240x75
>[  247.698081] Console: switching to colour dummy device 80x25
>[  247.698174] [IGT] gem_mmap_gtt: executing
>[  247.712330] [IGT] gem_mmap_gtt: starting subtest basic-write-no-prefault
>[  247.712378] Setting dangerous option prefault_disable - tainting kernel
>[  247.794186] Setting dangerous option prefault_disable - tainting kernel
>[  247.794320] [IGT] gem_mmap_gtt: exiting, ret=0
>[  247.794383] Setting dangerous option prefault_disable - tainting kernel
>[  247.838225] Console: switching to colour frame buffer device 240x75
>[  247.959824] Console: switching to colour dummy device 80x25
>[  247.959993] [IGT] gem_mmap_gtt: executing
>[  247.969317] [IGT] gem_mmap_gtt: starting subtest basic-write-read
>[  247.976481] [IGT] gem_mmap_gtt: exiting, ret=0
>[  248.021701] Console: switching to colour frame buffer device 240x75
>[  248.148208] Console: switching to colour dummy device 80x25
>[  248.148303] [IGT] gem_mmap_gtt: executing
>[  248.158338] [IGT] gem_mmap_gtt: starting subtest basic-write-read-distinct
>[  248.165598] [IGT] gem_mmap_gtt: exiting, ret=0
>[  248.205186] Console: switching to colour frame buffer device 240x75
>[  248.310713] Console: switching to colour dummy device 80x25
>[  248.310799] [IGT] gem_pread: executing
>[  248.335116] [IGT] gem_pread: starting subtest basic
>[  249.201089] [IGT] gem_pread: exiting, ret=0
>[  249.256159] Console: switching to colour frame buffer device 240x75
>[  249.360434] Console: switching to colour dummy device 80x25
>[  249.360518] [IGT] gem_pwrite: executing
>[  249.370600] [IGT] gem_pwrite: starting subtest basic
>[  250.364187] [IGT] gem_pwrite: exiting, ret=0
>[  250.407163] Console: switching to colour frame buffer device 240x75
>[  250.537643] Console: switching to colour dummy device 80x25
>[  250.537736] [IGT] gem_render_linear_blits: executing
>[  250.547478] [IGT] gem_render_linear_blits: starting subtest basic
>[  250.555331] [IGT] gem_render_linear_blits: exiting, ret=0
>[  250.590668] Console: switching to colour frame buffer device 240x75
>[  250.708238] Console: switching to colour dummy device 80x25
>[  250.708332] [IGT] gem_render_tiled_blits: executing
>[  250.717496] [IGT] gem_render_tiled_blits: starting subtest basic
>[  250.725020] [IGT] gem_render_tiled_blits: exiting, ret=0
>[  250.757472] Console: switching to colour frame buffer device 240x75
>[  250.883907] Console: switching to colour dummy device 80x25
>[  250.883999] [IGT] gem_ringfill: executing
>[  250.903334] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  250.905190] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  250.913337] [IGT] gem_ringfill: starting subtest basic-default
>[  250.938270] [IGT] gem_ringfill: exiting, ret=0
>[  250.974327] Console: switching to colour frame buffer device 240x75
>[  251.098511] Console: switching to colour dummy device 80x25
>[  251.098602] [IGT] gem_ringfill: executing
>[  251.112809] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  251.116836] [IGT] gem_ringfill: starting subtest basic-default-interruptible
>[  252.303434] [IGT] gem_ringfill: exiting, ret=0
>[  252.342235] Console: switching to colour frame buffer device 240x75
>[  252.471285] Console: switching to colour dummy device 80x25
>[  252.471381] [IGT] gem_ringfill: executing
>[  252.500439] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  252.504448] [IGT] gem_ringfill: starting subtest basic-default-forked
>[  252.540317] [IGT] gem_ringfill: exiting, ret=0
>[  252.575765] Console: switching to colour frame buffer device 240x75
>[  252.698900] Console: switching to colour dummy device 80x25
>[  252.698991] [IGT] gem_ringfill: executing
>[  252.712609] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  252.716758] [IGT] gem_ringfill: starting subtest basic-default-fd
>[  252.747393] [IGT] gem_ringfill: exiting, ret=0
>[  252.775946] Console: switching to colour frame buffer device 240x75
>[  252.904964] Console: switching to colour dummy device 80x25
>[  252.905058] [IGT] gem_ringfill: executing
>[  252.918937] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  252.923060] [IGT] gem_ringfill: starting subtest basic-default-hang
>[  256.757193] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  263.737057] [drm] GPU HANG: ecode 8:0:0xe757fffe, in gem_ringfill [8244], reason: Hang on render ring, action: reset
>[  263.737444] drm/i915: Resetting chip after gpu hang
>[  263.737517] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  263.738583] [drm:i915_gem_reset [i915]] context gem_ringfill[8244]/0 marked guilty (score 10) banned? no
>[  263.738600] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x257b8f
>[  263.738696] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  263.739044] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  263.739060] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x257c27, 0x0]
>[  263.739080] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  263.739100] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  263.739120] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  263.739137] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  263.739154] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  263.739170] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  263.762075] [IGT] gem_ringfill: exiting, ret=0
>[  263.802455] Console: switching to colour frame buffer device 240x75
>[  264.109621] Console: switching to colour dummy device 80x25
>[  264.109713] [IGT] gem_sync: executing
>[  264.120193] [IGT] gem_sync: starting subtest basic-all
>[  269.201203] [IGT] gem_sync: exiting, ret=0
>[  269.240637] Console: switching to colour frame buffer device 240x75
>[  269.488636] Console: switching to colour dummy device 80x25
>[  269.488728] [IGT] gem_sync: executing
>[  269.499446] [IGT] gem_sync: starting subtest basic-each
>[  274.652349] [IGT] gem_sync: exiting, ret=0
>[  274.695525] Console: switching to colour frame buffer device 240x75
>[  274.943877] Console: switching to colour dummy device 80x25
>[  274.943968] [IGT] gem_sync: executing
>[  274.954811] [IGT] gem_sync: starting subtest basic-many-each
>[  280.442312] [IGT] gem_sync: exiting, ret=0
>[  280.484021] Console: switching to colour frame buffer device 240x75
>[  280.736178] Console: switching to colour dummy device 80x25
>[  280.736271] [IGT] gem_sync: executing
>[  280.747139] [IGT] gem_sync: starting subtest basic-store-all
>[  286.150146] [IGT] gem_sync: exiting, ret=0
>[  286.189123] Console: switching to colour frame buffer device 240x75
>[  286.441865] Console: switching to colour dummy device 80x25
>[  286.441953] [IGT] gem_sync: executing
>[  286.452465] [IGT] gem_sync: starting subtest basic-store-each
>[  291.671595] [IGT] gem_sync: exiting, ret=0
>[  291.727408] Console: switching to colour frame buffer device 240x75
>[  291.943279] Console: switching to colour dummy device 80x25
>[  291.943365] [IGT] gem_tiled_blits: executing
>[  291.960732] [IGT] gem_tiled_blits: starting subtest basic
>[  291.971042] [IGT] gem_tiled_blits: exiting, ret=0
>[  292.010987] Console: switching to colour frame buffer device 240x75
>[  292.132447] Console: switching to colour dummy device 80x25
>[  292.132590] [IGT] gem_tiled_fence_blits: executing
>[  292.141959] [IGT] gem_tiled_fence_blits: starting subtest basic
>[  292.147985] [IGT] gem_tiled_fence_blits: exiting, ret=0
>[  292.194488] Console: switching to colour frame buffer device 240x75
>[  292.326255] Console: switching to colour dummy device 80x25
>[  292.326347] [IGT] gem_tiled_pread_basic: executing
>[  292.443158] [IGT] gem_tiled_pread_basic: exiting, ret=0
>[  292.478056] Console: switching to colour frame buffer device 240x75
>[  292.606101] Console: switching to colour dummy device 80x25
>[  292.606194] [IGT] gem_wait: executing
>[  292.617512] [IGT] gem_wait: starting subtest basic-busy-all
>[  293.138778] [IGT] gem_wait: exiting, ret=0
>[  293.178722] Console: switching to colour frame buffer device 240x75
>[  293.306180] Console: switching to colour dummy device 80x25
>[  293.306271] [IGT] gem_wait: executing
>[  293.317288] [IGT] gem_wait: starting subtest basic-wait-all
>[  294.338814] [IGT] gem_wait: exiting, ret=0
>[  294.379787] Console: switching to colour frame buffer device 240x75
>[  294.506758] Console: switching to colour dummy device 80x25
>[  294.506851] [IGT] gem_wait: executing
>[  294.533236] [IGT] gem_wait: starting subtest basic-await-all
>[  294.548731] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  295.556433] [IGT] gem_wait: exiting, ret=0
>[  295.597551] Console: switching to colour frame buffer device 240x75
>[  295.723526] Console: switching to colour dummy device 80x25
>[  295.723620] [IGT] gem_workarounds: executing
>[  295.734871] [IGT] gem_workarounds: starting subtest basic-read
>[  295.752904] [IGT] gem_workarounds: exiting, ret=0
>[  295.781022] Console: switching to colour frame buffer device 240x75
>[  295.920092] Console: switching to colour dummy device 80x25
>[  295.920185] [IGT] kms_addfb_basic: executing
>[  295.929976] [drm:drm_mode_addfb2] [FB:58]
>[  295.930154] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
>[  295.930197] [drm:intel_framebuffer_init [i915]] Unsupported fb modifier 0xffffffffffffffff!
>[  295.930202] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  295.934096] [drm:drm_mode_addfb2] [FB:58]
>[  295.934162] [IGT] kms_addfb_basic: exiting, ret=0
>[  295.981203] Console: switching to colour frame buffer device 240x75
>[  296.112169] Console: switching to colour dummy device 80x25
>[  296.112261] [IGT] kms_addfb_basic: executing
>[  296.121987] [drm:drm_mode_addfb2] [FB:76]
>[  296.122127] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling
>[  296.122146] [drm:drm_mode_addfb2] [FB:76]
>[  296.126020] [drm:drm_mode_addfb2] [FB:76]
>[  296.126087] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.164706] Console: switching to colour frame buffer device 240x75
>[  296.286383] Console: switching to colour dummy device 80x25
>[  296.286477] [IGT] kms_addfb_basic: executing
>[  296.295964] [drm:drm_mode_addfb2] [FB:58]
>[  296.296092] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
>[  296.296111] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0
>[  296.300095] [drm:drm_mode_addfb2] [FB:58]
>[  296.300163] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.348192] Console: switching to colour frame buffer device 240x75
>[  296.480267] Console: switching to colour dummy device 80x25
>[  296.480359] [IGT] kms_addfb_basic: executing
>[  296.490013] [drm:drm_mode_addfb2] [FB:76]
>[  296.490150] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled
>[  296.490169] [drm:drm_mode_addfb2] [FB:76]
>[  296.494034] [drm:drm_mode_addfb2] [FB:76]
>[  296.494100] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.531689] Console: switching to colour frame buffer device 240x75
>[  296.656192] Console: switching to colour dummy device 80x25
>[  296.656284] [IGT] kms_addfb_basic: executing
>[  296.665984] [drm:drm_mode_addfb2] [FB:58]
>[  296.666123] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled-mismatch
>[  296.666165] [drm:intel_framebuffer_init [i915]] tiling_mode doesn't match fb modifier
>[  296.666171] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  296.670182] [drm:drm_mode_addfb2] [FB:58]
>[  296.670248] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.715186] Console: switching to colour frame buffer device 240x75
>[  296.840981] Console: switching to colour dummy device 80x25
>[  296.841078] [IGT] kms_addfb_basic: executing
>[  296.854002] [drm:drm_mode_addfb2] [FB:76]
>[  296.854176] [IGT] kms_addfb_basic: starting subtest addfb25-Yf-tiled
>[  296.854221] [drm:intel_framebuffer_init [i915]] Unsupported tiling 0x100000000000003!
>[  296.854227] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  296.858158] [drm:drm_mode_addfb2] [FB:76]
>[  296.858225] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.898684] Console: switching to colour frame buffer device 240x75
>[  297.030049] Console: switching to colour dummy device 80x25
>[  297.030144] [IGT] kms_addfb_basic: executing
>[  297.040019] [drm:drm_mode_addfb2] [FB:58]
>[  297.040190] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled
>[  297.040232] [drm:intel_framebuffer_init [i915]] Unsupported tiling 0x100000000000002!
>[  297.040237] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  297.044058] [drm:drm_mode_addfb2] [FB:58]
>[  297.044123] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.098877] Console: switching to colour frame buffer device 240x75
>[  297.223482] Console: switching to colour dummy device 80x25
>[  297.223576] [IGT] kms_addfb_basic: executing
>[  297.233028] [drm:drm_mode_addfb2] [FB:76]
>[  297.233207] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled-small
>[  297.237048] [drm:drm_mode_addfb2] [FB:76]
>[  297.237113] [IGT] kms_addfb_basic: exiting, ret=77
>[  297.282369] Console: switching to colour frame buffer device 240x75
>[  297.409009] Console: switching to colour dummy device 80x25
>[  297.409105] [IGT] kms_addfb_basic: executing
>[  297.422040] [drm:drm_mode_addfb2] [FB:58]
>[  297.422105] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
>[  297.422121] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0
>[  297.426083] [drm:drm_mode_addfb2] [FB:58]
>[  297.426146] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.465879] Console: switching to colour frame buffer device 240x75
>[  297.595024] Console: switching to colour dummy device 80x25
>[  297.595118] [IGT] kms_addfb_basic: executing
>[  297.604088] [drm:drm_mode_addfb2] [FB:76]
>[  297.604156] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
>[  297.604172] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0
>[  297.608116] [drm:drm_mode_addfb2] [FB:76]
>[  297.608187] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.666036] Console: switching to colour frame buffer device 240x75
>[  297.787570] Console: switching to colour dummy device 80x25
>[  297.787662] [IGT] kms_addfb_basic: executing
>[  297.797091] [drm:drm_mode_addfb2] [FB:58]
>[  297.797155] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
>[  297.797171] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0
>[  297.801206] [drm:drm_mode_addfb2] [FB:58]
>[  297.801274] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.849541] Console: switching to colour frame buffer device 240x75
>[  297.978948] Console: switching to colour dummy device 80x25
>[  297.979042] [IGT] kms_addfb_basic: executing
>[  297.988075] [drm:drm_mode_addfb2] [FB:76]
>[  297.988140] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
>[  297.988155] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0
>[  297.992118] [drm:drm_mode_addfb2] [FB:76]
>[  297.992185] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.033041] Console: switching to colour frame buffer device 240x75
>[  298.158520] Console: switching to colour dummy device 80x25
>[  298.158615] [IGT] kms_addfb_basic: executing
>[  298.168077] [drm:drm_mode_addfb2] [FB:58]
>[  298.168144] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
>[  298.168160] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0
>[  298.172139] [drm:drm_mode_addfb2] [FB:58]
>[  298.172208] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.216539] Console: switching to colour frame buffer device 240x75
>[  298.340274] Console: switching to colour dummy device 80x25
>[  298.340366] [IGT] kms_addfb_basic: executing
>[  298.350090] [drm:drm_mode_addfb2] [FB:76]
>[  298.350156] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
>[  298.350171] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0
>[  298.354151] [drm:drm_mode_addfb2] [FB:76]
>[  298.354218] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.400028] Console: switching to colour frame buffer device 240x75
>[  298.529298] Console: switching to colour dummy device 80x25
>[  298.529390] [IGT] kms_addfb_basic: executing
>[  298.539097] [drm:drm_mode_addfb2] [FB:58]
>[  298.539165] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
>[  298.539211] [drm:intel_framebuffer_init [i915]] linear pitch (65536) must be at most 32768
>[  298.539216] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  298.543222] [drm:drm_mode_addfb2] [FB:58]
>[  298.543289] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.583522] Console: switching to colour frame buffer device 240x75
>[  298.710122] Console: switching to colour dummy device 80x25
>[  298.710216] [IGT] kms_addfb_basic: executing
>[  298.719202] [drm:drm_mode_addfb2] [FB:76]
>[  298.719268] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
>[  298.719284] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0
>[  298.723263] [drm:drm_mode_addfb2] [FB:76]
>[  298.723329] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.767048] Console: switching to colour frame buffer device 240x75
>[  298.895604] Console: switching to colour dummy device 80x25
>[  298.895695] [IGT] kms_addfb_basic: executing
>[  298.905122] [drm:drm_mode_addfb2] [FB:58]
>[  298.905188] [IGT] kms_addfb_basic: starting subtest basic
>[  298.905207] [drm:drm_mode_addfb2] [FB:58]
>[  298.909263] [drm:drm_mode_addfb2] [FB:58]
>[  298.909329] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.967202] Console: switching to colour frame buffer device 240x75
>[  299.092360] Console: switching to colour dummy device 80x25
>[  299.092451] [IGT] kms_addfb_basic: executing
>[  299.102139] [drm:drm_mode_addfb2] [FB:76]
>[  299.106145] [IGT] kms_addfb_basic: starting subtest basic-X-tiled
>[  299.106177] [drm:drm_mode_addfb2] [FB:76]
>[  299.106249] [drm:drm_mode_addfb2] [FB:76]
>[  299.106318] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.150702] Console: switching to colour frame buffer device 240x75
>[  299.276772] Console: switching to colour dummy device 80x25
>[  299.276865] [IGT] kms_addfb_basic: executing
>[  299.286145] [drm:drm_mode_addfb2] [FB:58]
>[  299.290148] [IGT] kms_addfb_basic: starting subtest basic-Y-tiled
>[  299.290197] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb
>[  299.290204] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.290273] [drm:drm_mode_addfb2] [FB:58]
>[  299.290342] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.334195] Console: switching to colour frame buffer device 240x75
>[  299.462355] Console: switching to colour dummy device 80x25
>[  299.462452] [IGT] kms_addfb_basic: executing
>[  299.472155] [drm:drm_mode_addfb2] [FB:76]
>[  299.472259] [IGT] kms_addfb_basic: starting subtest bo-too-small
>[  299.472304] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4190208 bytes)
>[  299.472309] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.476330] [drm:drm_mode_addfb2] [FB:76]
>[  299.476398] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.517694] Console: switching to colour frame buffer device 240x75
>[  299.644141] Console: switching to colour dummy device 80x25
>[  299.644235] [IGT] kms_addfb_basic: executing
>[  299.657167] [drm:drm_mode_addfb2] [FB:58]
>[  299.657268] [IGT] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  299.657321] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4194304 bytes, have 4190208 bytes)
>[  299.657326] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.661310] [drm:drm_mode_addfb2] [FB:58]
>[  299.661375] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.701191] Console: switching to colour frame buffer device 240x75
>[  299.826785] Console: switching to colour dummy device 80x25
>[  299.826877] [IGT] kms_addfb_basic: executing
>[  299.836180] [drm:drm_mode_addfb2] [FB:76]
>[  299.836218] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
>[  299.836245] [drm:drm_mode_addfb2] [FB:76]
>[  299.840305] [drm:drm_mode_addfb2] [FB:76]
>[  299.840373] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.884707] Console: switching to colour frame buffer device 240x75
>[  300.018198] Console: switching to colour dummy device 80x25
>[  300.018290] [IGT] kms_addfb_basic: executing
>[  300.028198] [drm:drm_mode_addfb2] [FB:58]
>[  300.032186] [IGT] kms_addfb_basic: starting subtest framebuffer-vs-set-tiling
>[  300.032229] [drm:drm_mode_addfb2] [FB:58]
>[  300.032308] [drm:drm_mode_addfb2] [FB:58]
>[  300.032365] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.084861] Console: switching to colour frame buffer device 240x75
>[  300.209654] Console: switching to colour dummy device 80x25
>[  300.209748] [IGT] kms_addfb_basic: executing
>[  300.219205] [drm:drm_mode_addfb2] [FB:76]
>[  300.223217] [drm:drm_mode_addfb2] [FB:76]
>[  300.223262] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
>[  300.223446] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.268357] Console: switching to colour frame buffer device 240x75
>[  300.397693] Console: switching to colour dummy device 80x25
>[  300.397787] [IGT] kms_addfb_basic: executing
>[  300.408232] [drm:drm_mode_addfb2] [FB:58]
>[  300.412230] [drm:drm_mode_addfb2] [FB:58]
>[  300.412259] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
>[  300.412346] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.451858] Console: switching to colour frame buffer device 240x75
>[  300.579558] Console: switching to colour dummy device 80x25
>[  300.579652] [IGT] kms_addfb_basic: executing
>[  300.589222] [drm:drm_mode_addfb2] [FB:76]
>[  300.593275] [drm:drm_mode_addfb2] [FB:76]
>[  300.593318] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
>[  300.593421] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.635357] Console: switching to colour frame buffer device 240x75
>[  300.762411] Console: switching to colour dummy device 80x25
>[  300.762504] [IGT] kms_addfb_basic: executing
>[  300.773243] [drm:drm_mode_addfb2] [FB:58]
>[  300.777155] [drm:drm_mode_addfb2] [FB:58]
>[  300.777199] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
>[  300.777332] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.818849] Console: switching to colour frame buffer device 240x75
>[  300.947575] Console: switching to colour dummy device 80x25
>[  300.947668] [IGT] kms_addfb_basic: executing
>[  300.957246] [drm:drm_mode_addfb2] [FB:76]
>[  300.957311] [IGT] kms_addfb_basic: starting subtest no-handle
>[  300.957326] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0
>[  300.961247] [drm:drm_mode_addfb2] [FB:76]
>[  300.961314] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.002350] Console: switching to colour frame buffer device 240x75
>[  301.127388] Console: switching to colour dummy device 80x25
>[  301.127482] [IGT] kms_addfb_basic: executing
>[  301.137264] [drm:drm_mode_addfb2] [FB:58]
>[  301.137363] [IGT] kms_addfb_basic: starting subtest size-max
>[  301.137381] [drm:drm_mode_addfb2] [FB:58]
>[  301.137391] [drm:drm_mode_addfb2] [FB:58]
>[  301.137400] [drm:drm_mode_addfb2] [FB:58]
>[  301.141273] [drm:drm_mode_addfb2] [FB:58]
>[  301.141327] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.185860] Console: switching to colour frame buffer device 240x75
>[  301.315429] Console: switching to colour dummy device 80x25
>[  301.315520] [IGT] kms_addfb_basic: executing
>[  301.329268] [drm:drm_mode_addfb2] [FB:76]
>[  301.329370] [IGT] kms_addfb_basic: starting subtest small-bo
>[  301.329390] [drm:drm_mode_addfb2] [FB:76]
>[  301.333346] [drm:drm_mode_addfb2] [FB:76]
>[  301.333412] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.386025] Console: switching to colour frame buffer device 240x75
>[  301.518515] Console: switching to colour dummy device 80x25
>[  301.518609] [IGT] kms_addfb_basic: executing
>[  301.528290] [drm:drm_mode_addfb2] [FB:58]
>[  301.532256] [IGT] kms_addfb_basic: starting subtest tile-pitch-mismatch
>[  301.532299] [drm:intel_framebuffer_init [i915]] pitch (2048) must match tiling stride (4096)
>[  301.532305] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  301.532357] [drm:drm_mode_addfb2] [FB:58]
>[  301.532402] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.569523] Console: switching to colour frame buffer device 240x75
>[  301.695660] Console: switching to colour dummy device 80x25
>[  301.695754] [IGT] kms_addfb_basic: executing
>[  301.705290] [drm:drm_mode_addfb2] [FB:76]
>[  301.705392] [IGT] kms_addfb_basic: starting subtest too-high
>[  301.705434] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  301.705439] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  301.705461] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  301.705465] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  301.705485] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  301.705489] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  301.709429] [drm:drm_mode_addfb2] [FB:76]
>[  301.709497] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.753022] Console: switching to colour frame buffer device 240x75
>[  301.883019] Console: switching to colour dummy device 80x25
>[  301.883145] [IGT] kms_addfb_basic: executing
>[  301.892319] [drm:drm_mode_addfb2] [FB:58]
>[  301.892420] [IGT] kms_addfb_basic: starting subtest too-wide
>[  301.892437] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0
>[  301.892440] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  301.892443] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  301.896400] [drm:drm_mode_addfb2] [FB:58]
>[  301.896469] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.936519] Console: switching to colour frame buffer device 240x75
>[  302.066119] Console: switching to colour dummy device 80x25
>[  302.066242] [IGT] kms_addfb_basic: executing
>[  302.075355] [drm:drm_mode_addfb2] [FB:76]
>[  302.075392] [IGT] kms_addfb_basic: starting subtest unused-handle
>[  302.075410] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1
>[  302.079374] [drm:drm_mode_addfb2] [FB:76]
>[  302.079439] [IGT] kms_addfb_basic: exiting, ret=0
>[  302.119997] Console: switching to colour frame buffer device 240x75
>[  302.243427] Console: switching to colour dummy device 80x25
>[  302.243519] [IGT] kms_addfb_basic: executing
>[  302.253325] [drm:drm_mode_addfb2] [FB:58]
>[  302.253362] [IGT] kms_addfb_basic: starting subtest unused-modifier
>[  302.253380] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1
>[  302.257441] [drm:drm_mode_addfb2] [FB:58]
>[  302.257510] [IGT] kms_addfb_basic: exiting, ret=0
>[  302.303513] Console: switching to colour frame buffer device 240x75
>[  302.433552] Console: switching to colour dummy device 80x25
>[  302.433648] [IGT] kms_addfb_basic: executing
>[  302.443341] [drm:drm_mode_addfb2] [FB:76]
>[  302.443377] [IGT] kms_addfb_basic: starting subtest unused-offsets
>[  302.443395] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1
>[  302.447422] [drm:drm_mode_addfb2] [FB:76]
>[  302.447489] [IGT] kms_addfb_basic: exiting, ret=0
>[  302.487009] Console: switching to colour frame buffer device 240x75
>[  302.612530] Console: switching to colour dummy device 80x25
>[  302.612621] [IGT] kms_addfb_basic: executing
>[  302.622356] [drm:drm_mode_addfb2] [FB:58]
>[  302.622391] [IGT] kms_addfb_basic: starting subtest unused-pitches
>[  302.622409] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1
>[  302.626412] [drm:drm_mode_addfb2] [FB:58]
>[  302.626479] [IGT] kms_addfb_basic: exiting, ret=0
>[  302.670510] Console: switching to colour frame buffer device 240x75
>[  302.797234] Console: switching to colour dummy device 80x25
>[  302.797331] [IGT] kms_busy: executing
>[  302.820304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  302.820336] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  302.822435] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  302.822466] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  302.824243] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  302.824249] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  302.826247] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  302.826267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  302.828342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  302.828348] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  302.828353] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  302.828655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  302.828678] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  302.829746] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  302.830656] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  302.830673] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  302.830688] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  302.830702] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  302.831687] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  302.831703] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  302.832838] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  302.832841] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  302.832921] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  302.832923] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  302.832927] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  302.832930] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  302.832933] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  302.832935] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  302.833049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  302.833052] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.833054] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  302.833057] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  302.833059] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  302.833062] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  302.833064] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  302.833066] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  302.833069] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  302.833071] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  302.833074] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  302.833076] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  302.833079] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  302.833081] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  302.833083] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  302.833086] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  302.833088] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  302.833091] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  302.833093] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  302.833095] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  302.833098] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  302.833100] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  302.833103] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  302.833105] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  302.833107] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  302.833110] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  302.833112] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  302.833115] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  302.833117] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  302.833120] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  302.833122] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  302.833468] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  302.833486] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  302.835244] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  302.835264] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  302.837241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  302.837247] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  302.839239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  302.839259] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  302.841239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  302.841245] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  302.841249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  302.841576] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  302.845979] [drm:drm_mode_addfb2] [FB:78]
>[  302.926866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  302.926884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  302.953993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  302.954313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  302.958423] [drm:drm_mode_addfb2] [FB:58]
>[  303.610337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.621393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  303.621478] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.621909] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  303.638790] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  303.638842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  303.638868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.638896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.638915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.638936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.638955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.638975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.638994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.639015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.639035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.639055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.639075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.639093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.639112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.639170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  303.639699] [IGT] kms_busy: exiting, ret=0
>[  303.657728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.657753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.657773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.657794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.657810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.657828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.657848] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  303.657868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  303.657888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.657908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.657927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.657932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.657951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.657954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.657974] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.657994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.658014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.658033] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  303.658053] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.658073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.658092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  303.658112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  303.658132] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  303.658153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.658175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  303.658284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.658305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.658324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.658345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.658364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.658384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.658407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.658428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.658449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.658469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.658488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.658518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  303.658543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.660585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.660601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.660615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.660629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.662153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.662169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.662183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.663681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.663696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.665505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.668217] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  303.668255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.668271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  303.668303] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.668491] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  303.668515] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  303.685014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.685040] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  303.685080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.685212] Console: switching to colour frame buffer device 240x75
>[  303.816143] Console: switching to colour dummy device 80x25
>[  303.816278] [IGT] kms_busy: executing
>[  303.835231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  303.835261] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  303.837351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  303.837371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  303.839437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  303.839443] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  303.841510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  303.841529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  303.843604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  303.843610] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  303.843615] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  303.843883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  303.843906] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  303.844940] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  303.845837] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  303.845855] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  303.845870] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  303.845884] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  303.847972] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  303.847989] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  303.849039] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  303.849042] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  303.849119] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  303.849121] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  303.849125] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  303.849127] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  303.849131] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  303.849133] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  303.849140] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  303.849143] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.849146] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.849148] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.849150] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  303.849153] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  303.849155] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  303.849158] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  303.849160] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.849163] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.849165] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  303.849167] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  303.849170] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  303.849172] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  303.849175] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  303.849177] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  303.849179] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  303.849182] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  303.849184] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  303.849187] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  303.849189] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  303.849191] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  303.849194] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  303.849196] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  303.849199] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  303.849201] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  303.849203] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  303.849206] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  303.849208] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  303.849211] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  303.849213] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  303.849534] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  303.849553] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  303.851300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  303.851319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  303.853310] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  303.853316] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  303.855393] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  303.855414] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  303.857488] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  303.857494] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  303.857498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  303.857885] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  303.862617] [drm:drm_mode_addfb2] [FB:76]
>[  303.890927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  303.890978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.901866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  303.901913] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.902217] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  303.919038] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  303.919089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  303.919112] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.919136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.919153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.919171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.919186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.919201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.919217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.919234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.919329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.919369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.919395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.919419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.919442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.919500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  303.919574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  303.919584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  303.919637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.919655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.919674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.919695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.919713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.919731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.919749] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  303.919767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  303.919785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.919803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.919820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.919825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.919842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.919845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.919863] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.919881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.919898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.919915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.919934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.919951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.919970] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  303.919987] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  303.920005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  303.920024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.920044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  303.922627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.922644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.922659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.922673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.922687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.922702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.922717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.922732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.922746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.922759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.922772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.922788] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  303.922803] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.924823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.924840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.924855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.924870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.926387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.926402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.926416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.927918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.927935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.929758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.932697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  303.932768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.932784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  303.932818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.949510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.949535] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  303.949570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.966183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  303.970367] [drm:drm_mode_addfb2] [FB:78]
>[  304.619870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.619961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  304.619998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.620057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  304.633938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  304.633957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.633978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.633994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.634012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.634026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.634041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.634057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.634074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.634090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.634105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.634121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.634135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.634149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.634181] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  304.634635] [IGT] kms_busy: exiting, ret=0
>[  304.655780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.655800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.655819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.655840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.655856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.655873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.655891] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  304.655908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  304.655924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.655939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.655954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.655958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.655973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.655975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.655990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.656004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.656019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.656033] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  304.656052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.656072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.656092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  304.656111] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  304.656131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  304.656152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.656174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  304.656240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.656260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.656280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.656314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.656333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.656353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.656375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.656397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.656418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.656437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.656457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.656478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  304.656498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.658492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.658507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.658521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.658535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.660045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.660058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.660071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.661567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.661582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.663393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.666417] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  304.666446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.666462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  304.666484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.666530] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  304.666545] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  304.683208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.683233] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  304.683270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.683412] Console: switching to colour frame buffer device 240x75
>[  304.824870] Console: switching to colour dummy device 80x25
>[  304.824960] [IGT] kms_busy: executing
>[  304.844059] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  304.844083] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  304.845376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  304.845394] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  304.847467] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  304.847474] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  304.849548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  304.849568] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  304.851645] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  304.851651] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  304.851655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  304.851917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  304.851941] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  304.852972] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  304.853862] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  304.853879] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  304.853893] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  304.853907] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  304.854902] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  304.854918] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  304.855978] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  304.855980] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  304.856060] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  304.856062] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  304.856066] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  304.856068] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  304.856072] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  304.856074] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  304.856081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  304.856084] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.856086] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  304.856089] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  304.856091] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  304.856094] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  304.856096] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  304.856099] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  304.856101] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  304.856104] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  304.856106] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  304.856108] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  304.856111] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  304.856113] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  304.856116] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  304.856118] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  304.856120] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  304.856123] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  304.856125] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  304.856128] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  304.856130] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  304.856133] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  304.856135] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  304.856137] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  304.856140] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  304.856142] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  304.856145] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  304.856147] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  304.856149] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  304.856152] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  304.856154] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  304.856459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  304.856477] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  304.858364] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  304.858382] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  304.860349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  304.860355] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  304.862369] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  304.862387] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  304.864463] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  304.864469] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  304.864472] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  304.864936] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  304.869254] [drm:drm_mode_addfb2] [FB:58]
>[  304.897361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  304.897410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.900051] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  304.900077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.900125] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  304.918081] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  304.918104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  304.918120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.918140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.918157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.918175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.918190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.918205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.918222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.918239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.918256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.918272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.918288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.918302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.918358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.918411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  304.918498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  304.918589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  304.918598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  304.918641] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.918658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.918677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.918697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.918713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.918730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.918750] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.918769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.918790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.918809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.918828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.918833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.918852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.918856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.918876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.918895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.918915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.918935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.918955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.918974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.918994] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  304.919013] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.919033] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.919053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.919075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.921603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.921622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.921638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.921653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.921667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.921682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.921702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.921722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.921742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.921760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.921778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.921798] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.921817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.923806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.923822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.923837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.923852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.925402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.925418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.925431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.926929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.926947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.928776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.931725] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.931786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.931806] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.931831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.948528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.948554] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.948589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.969217] [drm:drm_mode_addfb2] [FB:78]
>[  305.618296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.618471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.618535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.618640] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.633486] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.633505] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.633525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.633542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.633559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.633574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.633593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.633612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.633634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.633654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.633675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.633694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.633713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.633731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.633769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.634018] [IGT] kms_busy: exiting, ret=0
>[  305.651836] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.651855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.651875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.651897] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.651916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.651937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.651957] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  305.651976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  305.651997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.652016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.652035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.652040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.652059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.652062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.652082] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.652102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.652121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.652141] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  305.652161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.652180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.652200] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  305.652220] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  305.652239] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  305.652260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.652282] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  305.652358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.652401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.652421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.652441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.652461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.652481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.652503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.652525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.652546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.652565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.652584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.652606] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  305.652625] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.654620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.654636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.654649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.654663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.656173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.656187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.656199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.657695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.657709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.659534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.662558] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  305.662587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.662603] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  305.662626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.662671] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  305.662686] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  305.679338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.679380] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  305.679417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.679543] Console: switching to colour frame buffer device 240x75
>[  305.813510] Console: switching to colour dummy device 80x25
>[  305.813604] [IGT] kms_cursor_legacy: executing
>[  305.836226] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  305.836254] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  305.837428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  305.837449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  305.839524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  305.839530] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  305.841605] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  305.841626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  305.843702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  305.843708] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  305.843712] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  305.843978] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  305.844001] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  305.845032] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  305.845934] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  305.845952] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  305.845967] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  305.845981] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  305.846971] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  305.846987] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  305.848040] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  305.848043] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  305.848120] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  305.848123] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  305.848127] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  305.848129] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  305.848132] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  305.848134] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  305.848142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  305.848145] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.848147] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.848149] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.848152] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  305.848155] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  305.848157] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  305.848159] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  305.848162] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.848164] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.848167] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  305.848169] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  305.848171] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  305.848174] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  305.848176] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  305.848179] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  305.848181] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  305.848184] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  305.848186] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  305.848188] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  305.848191] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  305.848193] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  305.848196] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  305.848198] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  305.848200] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  305.848203] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  305.848205] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  305.848208] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  305.848210] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  305.848212] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  305.848215] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  305.848541] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  305.848567] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  305.850429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  305.850449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  305.852420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  305.852426] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  305.854421] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  305.854441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  305.856516] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  305.856522] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  305.856526] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  305.856864] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-atomic
>[  305.857160] [drm:drm_mode_addfb2] [FB:76]
>[  305.888321] [drm:drm_mode_addfb2] [FB:79]
>[  305.947469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.962952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  305.962978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.963018] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  305.981898] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  305.981920] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  305.981936] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.981956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.981973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.981990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.982005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.982020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.982035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.982052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.982068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.982084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.982099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.982112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.982126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.982158] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  305.982293] [IGT] kms_cursor_legacy: exiting, ret=0
>[  306.003900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.003919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.003939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.003962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.003982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.004002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.004022] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  306.004042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  306.004062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.004082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.004101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.004105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.004124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.004127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.004147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.004167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.004186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.004205] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  306.004225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.004244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.004264] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  306.004283] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  306.004303] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  306.004324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.004346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  306.004430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.004450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.004470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.004490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.004509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.004536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.004555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.004572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.004588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.004601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.004615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.004635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  306.004653] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.006653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.006669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.006683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.006698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.008211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.008225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.008237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.009739] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.009753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.011566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.014598] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  306.014626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.014642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  306.014665] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.014710] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  306.014726] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  306.031410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.031435] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.031471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.031596] Console: switching to colour frame buffer device 240x75
>[  306.155914] Console: switching to colour dummy device 80x25
>[  306.156004] [IGT] kms_cursor_legacy: executing
>[  306.175286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  306.175310] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  306.177379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.177411] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.179487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.179493] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  306.181570] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.181591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.183666] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.183672] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.183676] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  306.183943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  306.183967] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  306.185012] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  306.185912] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  306.185930] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  306.185944] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  306.185960] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  306.186972] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  306.186988] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  306.188103] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  306.188106] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  306.188185] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.188187] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.188191] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  306.188193] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  306.188197] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.188199] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.188206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  306.188209] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.188211] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.188214] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.188216] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.188219] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.188221] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.188223] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  306.188226] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.188228] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.188231] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.188233] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.188235] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.188238] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  306.188240] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.188243] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.188245] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  306.188247] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.188250] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.188252] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  306.188255] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  306.188257] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  306.188260] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  306.188262] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  306.188264] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  306.188267] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.188269] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.188272] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  306.188274] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.188276] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.188279] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  306.188597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  306.188615] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  306.190438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.190456] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.192442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.192448] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  306.194524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.194546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.196619] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.196625] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.196629] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  306.196937] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-legacy
>[  306.197230] [drm:drm_mode_addfb2] [FB:58]
>[  306.228483] [drm:drm_mode_addfb2] [FB:79]
>[  306.299559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.314951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  306.314978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.315019] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  306.333880] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  306.333902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  306.333918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.333938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.333954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.333972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.333987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.334002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.334017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.334035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.334051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.334066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.334082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.334100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.334119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.334156] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.334319] [IGT] kms_cursor_legacy: exiting, ret=0
>[  306.355808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.355827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.355847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.355868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.355884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.355902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.355920] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  306.355937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  306.355952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.355967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.355982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.355986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.356000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.356003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.356018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.356032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.356051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.356070] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  306.356091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.356110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.356130] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  306.356150] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  306.356169] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  306.356190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.356212] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  306.356277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.356297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.356317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.356337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.356357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.356376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.356398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.356434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.356456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.356475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.356495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.356516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  306.356535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.358532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.358548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.358561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.358575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.360084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.360097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.360109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.361608] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.361622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.363445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.366464] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  306.366491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.366505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  306.366526] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.366567] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  306.366582] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  306.383249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.383272] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.383308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.383451] Console: switching to colour frame buffer device 240x75
>[  306.509055] Console: switching to colour dummy device 80x25
>[  306.509147] [IGT] kms_cursor_legacy: executing
>[  306.526419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  306.526443] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  306.528514] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.528534] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.530610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.530616] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  306.532692] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.532713] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.534788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.534794] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.534799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  306.535067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  306.535090] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  306.536131] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  306.537022] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  306.537040] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  306.537055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  306.537069] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  306.538058] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  306.538074] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  306.539125] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  306.539127] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  306.539205] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.539208] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.539212] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  306.539213] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  306.539217] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.539219] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.539226] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  306.539229] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.539232] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.539234] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.539237] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.539239] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.539241] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.539244] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  306.539246] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.539249] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.539251] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.539254] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.539256] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.539258] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  306.539261] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.539263] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.539266] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  306.539268] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.539270] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.539273] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  306.539275] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  306.539278] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  306.539280] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  306.539282] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  306.539285] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  306.539287] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.539290] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.539292] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  306.539294] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.539297] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.539299] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  306.539659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  306.539683] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  306.541461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.541483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.543473] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.543478] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  306.545556] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.545578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.547653] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.547659] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.547663] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  306.547977] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-atomic
>[  306.548270] [drm:drm_mode_addfb2] [FB:76]
>[  306.579567] [drm:drm_mode_addfb2] [FB:79]
>[  306.635732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.650149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  306.650174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.650213] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  306.669065] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  306.669088] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  306.669104] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.669124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.669140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.669157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.669172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.669187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.669203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.669220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.669236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.669251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.669267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.669285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.669304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.669340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.669536] [IGT] kms_cursor_legacy: exiting, ret=0
>[  306.687917] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.687938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.687959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.687982] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.688002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.688022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.688042] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  306.688061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  306.688081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.688100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.688119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.688124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.688143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.688146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.688166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.688186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.688205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.688224] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  306.688245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.688264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.688283] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  306.688303] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  306.688323] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  306.688343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.688365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  306.688441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.688462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.688482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.688502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.688522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.688542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.688564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.688586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.688607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.688626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.688645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.688666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  306.688686] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.690680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.690696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.690710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.690724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.692234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.692247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.692260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.693755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.693769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.695580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.698412] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  306.698456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.698472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  306.698495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.698539] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  306.698556] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  306.715263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.715289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.715329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.715478] Console: switching to colour frame buffer device 240x75
>[  306.857659] Console: switching to colour dummy device 80x25
>[  306.857753] [IGT] kms_cursor_legacy: executing
>[  306.877212] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  306.877239] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  306.878489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.878511] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.880584] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  306.880592] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  306.882659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.882678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  306.884745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  306.884752] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.884756] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  306.885042] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  306.885064] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  306.886095] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  306.886994] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  306.887011] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  306.887026] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  306.887039] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  306.888040] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  306.888056] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  306.889112] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  306.889114] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  306.889196] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.889198] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.889202] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  306.889204] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  306.889208] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  306.889210] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  306.889217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  306.889220] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.889222] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.889225] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.889227] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.889230] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  306.889232] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.889234] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  306.889237] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.889239] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  306.889242] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  306.889244] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.889247] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  306.889249] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  306.889251] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.889254] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  306.889256] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  306.889259] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.889261] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  306.889263] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  306.889266] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  306.889268] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  306.889271] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  306.889273] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  306.889276] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  306.889278] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.889280] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  306.889283] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  306.889285] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.889288] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.889290] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  306.889650] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  306.889675] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  306.891496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.891515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.893483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  306.893489] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  306.895491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.895509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  306.897577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  306.897583] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  306.897586] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  306.897885] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-legacy
>[  306.898179] [drm:drm_mode_addfb2] [FB:58]
>[  306.929589] [drm:drm_mode_addfb2] [FB:79]
>[  306.999977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.015527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  307.015553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.015593] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  307.034477] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  307.034499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  307.034516] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.034536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.034552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.034570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.034585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.034600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.034616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.034634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.034650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.034666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.034681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.034695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.034709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.034741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.034882] [IGT] kms_cursor_legacy: exiting, ret=0
>[  307.052927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.052946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.052966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.052987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.053003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.053021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.053038] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  307.053055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  307.053071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.053087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.053105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.053110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.053129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.053132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.053152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.053172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.053191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.053211] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  307.053231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.053251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.053270] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  307.053290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  307.053309] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  307.053330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.053352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  307.053425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.053463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.053483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.053503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.053523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.053542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.053565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.053586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.053607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.053627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.053646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.053667] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  307.053687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.055674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.055691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.055708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.055725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.058323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.058339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.058353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.059847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.059863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.061679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.064423] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  307.064481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.064496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  307.064519] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.064572] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  307.064596] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  307.081234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.081258] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.081295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.081421] Console: switching to colour frame buffer device 240x75
>[  307.207723] Console: switching to colour dummy device 80x25
>[  307.207816] [IGT] kms_cursor_legacy: executing
>[  307.227140] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  307.227168] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  307.229248] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.229268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.231343] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.231349] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  307.233425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.233444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.235559] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.235565] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.235569] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  307.235832] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  307.235855] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  307.236887] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  307.237775] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  307.237792] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  307.237807] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  307.237821] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  307.238807] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  307.238823] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  307.239871] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  307.239874] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  307.239951] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.239953] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.239957] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  307.239959] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  307.239963] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.239965] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.239972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  307.239975] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.239977] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.239980] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.239982] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.239985] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.239987] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.239990] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  307.239992] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.239995] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.239997] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.239999] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.240002] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.240004] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  307.240007] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.240009] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.240011] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  307.240014] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.240016] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.240019] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  307.240021] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  307.240023] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  307.240026] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  307.240028] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  307.240031] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  307.240033] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.240035] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.240038] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  307.240040] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.240043] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.240045] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  307.240270] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  307.240288] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  307.242366] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.242386] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.244475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.244481] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  307.246556] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.246576] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.248642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.248647] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.248651] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  307.248954] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size
>[  307.249255] [drm:drm_mode_addfb2] [FB:76]
>[  307.280413] [drm:drm_mode_addfb2] [FB:79]
>[  307.280567] [drm:drm_mode_addfb2] [FB:80]
>[  307.350158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.364830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  307.364864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.364925] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  307.383841] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  307.383863] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  307.383879] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.383899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.383918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.383939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.383958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.383978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.383996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.384018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.384038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.384058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.384077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.384096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.384115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.384151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.384306] [IGT] kms_cursor_legacy: exiting, ret=0
>[  307.401926] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.401945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.401966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.401989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.402008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.402029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.402049] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  307.402069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  307.402088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.402108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.402127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.402131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.402151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.402154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.402174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.402193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.402213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.402232] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  307.402252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.402271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.402291] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  307.402311] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  307.402330] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  307.402351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.402373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  307.402449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.402491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.402511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.402531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.402551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.402570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.402592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.402614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.402635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.402654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.402673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.402694] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  307.402721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.404716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.404732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.404746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.404763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.406274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.406289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.406302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.407797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.407814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.409623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.412451] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  307.412491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.412507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  307.412530] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.412584] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  307.412608] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  307.429277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.429302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.429338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.429480] Console: switching to colour frame buffer device 240x75
>[  307.556096] Console: switching to colour dummy device 80x25
>[  307.556190] [IGT] kms_cursor_legacy: executing
>[  307.576394] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  307.576418] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  307.577528] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.577547] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.579621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.579627] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  307.581703] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.581723] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.583798] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.583804] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.583808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  307.584100] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  307.584123] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  307.585155] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  307.586045] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  307.586062] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  307.586077] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  307.586091] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  307.587078] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  307.587094] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  307.588151] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  307.588154] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  307.588235] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.588237] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.588241] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  307.588243] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  307.588247] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.588249] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.588256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  307.588258] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.588261] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.588263] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.588266] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.588268] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.588271] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.588273] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  307.588276] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.588278] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.588280] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.588283] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.588285] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.588288] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  307.588290] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.588292] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.588295] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  307.588297] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.588300] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.588302] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  307.588305] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  307.588307] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  307.588309] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  307.588312] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  307.588314] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  307.588317] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.588319] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.588321] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  307.588324] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.588326] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.588329] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  307.588673] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  307.588700] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  307.590771] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.590790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.592864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.592870] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  307.594945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.594964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.597031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.597036] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.597039] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  307.597351] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic
>[  307.597745] [drm:drm_mode_addfb2] [FB:58]
>[  307.629083] [drm:drm_mode_addfb2] [FB:79]
>[  307.697783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.712878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  307.712909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.712966] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  307.731871] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  307.731895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  307.731915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.731937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.731957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.731977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.731997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.732016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.732035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.732056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.732077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.732097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.732116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.732135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.732154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.732190] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.732338] [IGT] kms_cursor_legacy: exiting, ret=0
>[  307.749972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.749992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.750011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.750032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.750049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.750069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.750089] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  307.750109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  307.750128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.750148] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.750167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.750172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.750191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.750194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.750214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.750234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.750253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.750272] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  307.750293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.750312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.750331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  307.750351] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  307.750371] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  307.750391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.750413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  307.750504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.750524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.750544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.750564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.750584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.750604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.750626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.750647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.750668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.750688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.750714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.750733] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  307.750751] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.752737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.752752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.752765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.752779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.754286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.754300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.754312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.755809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.755823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.757628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.760473] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  307.760518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.760534] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  307.760557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.760611] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  307.760634] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  307.777283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.777307] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  307.777344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.777508] Console: switching to colour frame buffer device 240x75
>[  307.903903] Console: switching to colour dummy device 80x25
>[  307.903995] [IGT] kms_cursor_legacy: executing
>[  307.923429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  307.923453] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  307.925524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.925542] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.927616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  307.927623] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  307.929698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.929719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  307.931801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  307.931807] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.931811] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  307.932077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  307.932100] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  307.933268] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  307.934158] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  307.934177] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  307.934194] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  307.934211] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  307.935199] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  307.935216] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  307.936266] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  307.936269] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  307.936346] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.936348] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.936352] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  307.936354] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  307.936358] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.936360] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.936367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  307.936369] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.936372] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.936374] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.936377] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.936379] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.936382] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.936384] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  307.936386] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.936389] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.936391] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.936394] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.936396] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.936398] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  307.936401] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.936403] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.936406] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  307.936408] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.936411] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.936413] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  307.936415] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  307.936418] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  307.936420] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  307.936423] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  307.936425] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  307.936427] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.936430] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.936432] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  307.936434] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.936437] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.936439] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  307.936748] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  307.936766] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  307.938538] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.938555] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.940547] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.940553] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  307.942546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.942567] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.944545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.944550] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.944554] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  307.944861] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy
>[  307.945154] [drm:drm_mode_addfb2] [FB:76]
>[  307.976461] [drm:drm_mode_addfb2] [FB:79]
>[  308.045793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.060858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.060884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.060933] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.079798] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.079821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.079837] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.079857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.079873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.079890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.079905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.079920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.079935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.079952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.079968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.079983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.079999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.080013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.080026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.080058] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.080198] [IGT] kms_cursor_legacy: exiting, ret=0
>[  308.097976] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.097995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.098014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.098036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.098056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.098076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.098096] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.098116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.098136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.098155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.098174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.098179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.098198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.098201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.098221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.098241] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.098260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.098280] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.098300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.098319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.098338] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  308.098358] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.098377] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.098398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.098420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.098485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.098519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.098539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.098559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.098579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.098598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.098621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.098642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.098663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.098682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.098701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.098722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.098742] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.100737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.100752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.100766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.100780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.103357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.103374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.103389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.107051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.107076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.108893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.111922] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.111950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.111966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.111989] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.112034] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.112050] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.128695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.128718] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.128754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.128881] Console: switching to colour frame buffer device 240x75
>[  308.259939] Console: switching to colour dummy device 80x25
>[  308.260082] [IGT] kms_cursor_legacy: executing
>[  308.279183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  308.279207] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  308.281286] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.281307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.282450] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.282457] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  308.284536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.284557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.286633] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.286639] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.286643] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  308.286906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  308.286928] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  308.287954] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  308.288841] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  308.288858] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  308.288872] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  308.288886] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  308.289872] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  308.289887] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  308.290936] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  308.290939] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  308.291018] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.291020] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.291024] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  308.291026] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  308.291030] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.291032] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.291039] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  308.291042] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.291044] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.291047] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.291049] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.291052] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.291054] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.291057] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  308.291059] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.291061] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.291064] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.291066] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.291069] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.291071] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  308.291074] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.291076] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.291078] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  308.291081] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.291083] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.291086] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  308.291088] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  308.291090] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  308.291093] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  308.291095] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  308.291098] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  308.291100] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.291102] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.291105] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  308.291107] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.291110] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.291112] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  308.291332] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  308.291350] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  308.293418] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.293438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.295512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.295534] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  308.297618] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.297639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.299714] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.299720] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.299724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  308.300027] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size
>[  308.300313] [drm:drm_mode_addfb2] [FB:58]
>[  308.331462] [drm:drm_mode_addfb2] [FB:79]
>[  308.331609] [drm:drm_mode_addfb2] [FB:80]
>[  308.396825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.412278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.412302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.412341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.431207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.431229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.431246] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.431266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.431283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.431300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.431315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.431330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.431346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.431363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.431379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.431395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.431410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.431424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.431437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.431469] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.431717] [IGT] kms_cursor_legacy: exiting, ret=0
>[  308.450026] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.450045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.450066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.450089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.450108] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.450129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.450149] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.450168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.450188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.450208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.450227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.450231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.450251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.450254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.450274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.450293] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.450313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.450332] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.450352] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.450371] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.450391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  308.450410] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.450430] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.450451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.450473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.450563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.450581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.450599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.450617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.450636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.450653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.450674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.450693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.450713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.450730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.450748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.450767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.450786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.452773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.452789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.452806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.452824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.454334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.454349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.454363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.455858] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.455876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.457684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.460645] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.460674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.460690] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.460712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.460767] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.460791] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.477442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.477466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.477503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.477649] Console: switching to colour frame buffer device 240x75
>[  308.586647] Console: switching to colour dummy device 80x25
>[  308.586739] [IGT] kms_flip: executing
>[  308.598739] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  308.598768] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  308.600595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.600615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.602587] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.602593] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  308.604589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.604609] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.606586] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.606592] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.606597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  308.606613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  308.606636] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  308.607674] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  308.608572] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  308.608599] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  308.608616] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  308.608631] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  308.609613] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  308.609629] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  308.610688] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  308.610691] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  308.610768] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.610770] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.610774] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  308.610776] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  308.610780] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.610782] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.610789] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  308.610792] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.610794] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.610797] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.610799] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.610802] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.610804] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.610807] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  308.610809] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.610811] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.610814] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.610816] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.610819] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.610821] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  308.610823] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.610826] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.610828] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  308.610831] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.610833] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.610836] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  308.610838] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  308.610840] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  308.610843] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  308.610845] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  308.610848] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  308.610850] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.610852] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.610855] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  308.610857] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.610860] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.610862] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  308.610891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  308.610909] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  308.612584] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.612602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.614586] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.614592] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  308.616587] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.616607] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.618588] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.618594] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.618598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  308.618797] [IGT] kms_flip: starting subtest basic-flip-vs-dpms
>[  308.619200] [drm:drm_mode_addfb2] [FB:76]
>[  308.619223] [drm:drm_mode_addfb2] [FB:79]
>[  308.661789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  308.661844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.677614] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.677641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.677683] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.696538] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.696579] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.696595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.696615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.696632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.696650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.696665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.696680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.696696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.696717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.696738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.696758] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.696778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.696797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.696816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.696855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.696906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  308.696982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  308.697025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  308.697034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  308.697074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.697090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.697107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.697125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.697139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.697155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.697170] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.697185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.697199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.697212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.697225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.697229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.697242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.697245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.697258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.697271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.697284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.697296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.697311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.697324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.697336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  308.697349] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.697362] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.697377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.697393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.699949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.699969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.699988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.700007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.700025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.700043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.700064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.700083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.700103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.700121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.700139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.700159] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.700178] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.702164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.702181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.702198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.702217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.703729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.703745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.703759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.705253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.705268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.707073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.709996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.710022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.710038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.710060] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.710129] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.710145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.726776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.726801] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.726835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.760254] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.760274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.760294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.760315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.760332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.760351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.760372] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.760392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.760413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.760433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.760452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.760457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.760477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.760481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.760501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.760522] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.760542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.760601] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.760626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.760651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.760677] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.760700] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.760722] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.760748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.760773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.793495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.793520] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.793610] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.812460] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.812482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.812498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.812518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.812534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.812592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.812617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.812642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.812669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.812697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.812723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.812750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.812773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.812796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.812840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.812869] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.812899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.813129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.813146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.813164] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.813183] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.813199] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.813215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.813232] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.813248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.813267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.813286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.813305] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.813309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.813328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.813331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.813351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.813370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.813389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.813408] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.813427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.813446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.813465] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.813484] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.813503] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.813523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.813544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.813640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.813667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.813694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.813719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.813744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.813770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.813805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.813830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.813854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.813877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.813899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.813925] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.813948] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.815941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.815957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.815971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.815985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.817491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.817507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.817520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.819046] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.819061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.820897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.823833] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.823860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.823879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.823905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.823946] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.823966] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.824012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.824035] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.824070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.840750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.840770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.840790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.840811] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.840829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.840847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.840865] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.840882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.840902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.840923] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.840943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.840947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.840967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.840971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.840992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.841012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.841032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.841052] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.841073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.841093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.841114] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.841134] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.841154] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.841176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.841197] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.874006] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.874031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.874066] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.892920] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.892941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.892957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.892976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.892992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.893008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.893023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.893038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.893054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.893071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.893088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.893104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.893118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.893137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.893170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.893192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.893216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.893400] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.893420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.893440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.893462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.893481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.893500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.893520] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.893539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.893602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.893626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.893649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.893656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.893679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.893685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.893707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.893729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.893758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.893778] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.893800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.893820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.893841] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.893861] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.893880] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.893903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.893927] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.894001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.894024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.894046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.894067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.894088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.894111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.894135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.894158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.894182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.894203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.894224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.894241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.894256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.896232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.896248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.896262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.896277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.897783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.897798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.897815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.899309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.899325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.901131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.904051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.904076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.904093] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.904114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.904152] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.904171] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.904216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.904240] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.904275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.920963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.920983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.921003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.921024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.921040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.921058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.921077] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.921094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.921110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.921126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.921145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.921149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.921169] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.921173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.921194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.921215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.921235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.921255] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.921275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.921295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.921316] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.921336] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.921356] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.921377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.921399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.954190] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.954214] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.954250] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.973102] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.973124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  308.973140] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.973159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.973176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.973191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.973206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.973221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.973237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.973254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.973270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.973286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.973300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.973314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.973342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.973360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.973378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.973550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.973610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.973637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.973671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.973692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.973714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.973736] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.973758] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.973779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.973799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.973818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.973824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.973844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.973850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.973870] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.973890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.973910] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.973929] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.973953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.973975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.973997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.974018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.974039] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.974063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.974088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.974157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.974172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.974186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.974199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.974212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.974226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.974241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.974255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.974270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.974282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.974295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.974311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.974325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.976299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.976315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.976329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.976343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.977851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.977867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.977881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.979373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.979389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.981196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.984117] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.984142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.984158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.984180] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.984217] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.984233] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.984275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.984296] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.984328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.001013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.001033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.001053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.001074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.001093] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.001115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.001135] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.001156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.001176] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.001196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.001216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.001220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.001240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.001244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.001264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.001284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.001305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.001325] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.001345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.001365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.001386] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.001406] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.001426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.001447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.001468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.034253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.034278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.034312] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.053218] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.053240] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.053257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.053277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.053294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.053310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.053326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.053341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.053357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.053374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.053391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.053407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.053422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.053437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.053466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.053484] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.053503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.053807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.053828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.053850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.053873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.053892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.053914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.053934] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.053955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.053975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.053995] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.054015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.054020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.054039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.054043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.054064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.054084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.054103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.054123] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.054143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.054162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.054183] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.054203] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.054222] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.054243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.054266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.054323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.054344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.054365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.054385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.054405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.054426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.054448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.054470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.054491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.054511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.054530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.054551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.054610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.056600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.056616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.056631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.056646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.058154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.058169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.058182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.059690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.059706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.061511] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.064445] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.064472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.064489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.064511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.064549] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.064601] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.064672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.064701] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.064748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.081394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.081416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.081437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.081461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.081481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.081502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.081522] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.081542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.081563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.081625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.081652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.081660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.081685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.081692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.081718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.081743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.081768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.081792] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.081820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.081844] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.081869] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.081890] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.081914] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.081941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.081967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.114620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.114646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.114683] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.133605] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.133626] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.133642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.133662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.133679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.133694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.133713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.133733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.133752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.133773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.133793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.133813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.133832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.133851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.133883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.133906] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.133929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.134095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.134114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.134134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.134156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.134175] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.134194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.134213] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.134232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.134251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.134270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.134289] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.134293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.134312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.134315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.134335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.134361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.134379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.134396] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.134413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.134430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.134448] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.134466] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.134483] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.134501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.134520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.134601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.134628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.134653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.134676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.134699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.134723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.134749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.134774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.134799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.134821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.134844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.134870] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.134894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.136890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.136908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.136925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.136943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.138448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.138465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.138479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.139974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.139990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.141795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.144730] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.144757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.144774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.144796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.144835] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.144852] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.144895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.144916] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.144948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.161693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.161713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.161733] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.161757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.161777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.161798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.161819] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.161839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.161859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.161879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.161899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.161904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.161924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.161927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.161948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.161968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.161988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.162008] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.162028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.162048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.162069] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.162089] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.162110] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.162131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.162152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.194905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.194930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.194965] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.213827] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.213849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.213865] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.213885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.213902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.213917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.213933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.213947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.213963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.213981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.213997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.214013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.214032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.214051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.214084] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.214106] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.214129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.214316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.214336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.214362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.214381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.214395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.214412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.214428] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.214442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.214456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.214470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.214486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.214490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.214507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.214510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.214528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.214545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.214562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.214618] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.214642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.214664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.214686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.214707] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.214727] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.214750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.214774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.214847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.214869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.214889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.214912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.214933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.214956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.214980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.215004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.215027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.215048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.215069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.215095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.215118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.217114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.217130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.217144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.217159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.218671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.218686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.218700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.220192] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.220208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.222013] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.224963] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.224989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.225006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.225029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.225067] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.225086] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.225132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.225155] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.225190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.241899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.241919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.241939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.241960] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.241977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.241995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.242014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.242031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.242047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.242062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.242078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.242082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.242097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.242100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.242115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.242130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.242150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.242170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.242191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.242211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.242232] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.242252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.242272] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.242294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.242315] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.275123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.275147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.275182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.294039] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.294061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.294077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.294099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.294119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.294138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.294157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.294177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.294196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.294217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.294237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.294257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.294276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.294294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.294327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.294349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.294373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.294545] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.294565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.294628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.294657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.294680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.294707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.294731] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.294755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.294778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.294801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.294822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.294829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.294849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.294856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.294879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.294902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.294924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.294945] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.294972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.294995] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.295019] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.295042] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.295065] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.295091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.295118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.295198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.295214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.295227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.295241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.295254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.295269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.295285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.295299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.295314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.295327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.295339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.295356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.295370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.297344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.297360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.297374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.297388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.298894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.298910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.298924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.300417] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.300433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.302238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.305159] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.305185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.305201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.305223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.305260] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.305277] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.305326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.305345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.305374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.322068] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.322089] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.322109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.322129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.322146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.322164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.322182] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.322199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.322216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.322231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.322247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.322251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.322266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.322269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.322285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.322300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.322318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.322338] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.322359] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.322378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.322399] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.322420] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.322440] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.322461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.322483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.355329] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.355355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.355401] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.374270] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.374292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.374309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.374328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.374345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.374360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.374376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.374390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.374406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.374426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.374447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.374467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.374486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.374505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.374538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.374560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.374629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.374849] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.374867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.374886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.374906] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.374922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.374940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.374957] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.374973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.374992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.375012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.375031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.375036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.375055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.375059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.375079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.375098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.375118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.375138] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.375158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.375183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.375201] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.375216] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.375231] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.375247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.375265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.375316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.375330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.375348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.375366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.375384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.375401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.375420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.375439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.375458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.375476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.375493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.375512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.375529] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.377501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.377518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.377533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.377547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.379070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.379086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.379099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.380609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.380625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.382428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.385365] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.385392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.385415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.385435] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.385472] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.385488] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.385527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.385546] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.385576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.402301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.402321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.402341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.402362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.402379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.402397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.402416] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.402433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.402450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.402466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.402481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.402486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.402501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.402504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.402524] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.402545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.402565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.402624] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.402650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.402673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.402698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.402720] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.402742] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.402768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.402794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.435536] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.435560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.435767] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.454397] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.454421] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.454441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.454464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.454484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.454504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.454524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.454544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.454563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.454627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.454654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.454684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.454707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.454731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.454776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.454807] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.454839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.455028] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.455046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.455064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.455085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.455101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.455120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.455137] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.455154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.455170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.455186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.455200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.455205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.455219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.455223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.455239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.455253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.455268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.455282] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.455300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.455315] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.455330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.455344] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.455358] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.455375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.455393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.455448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.455464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.455479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.455494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.455509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.455525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.455542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.455558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.455573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.455619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.455638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.455661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.455683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.457673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.457689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.457703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.457718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.459223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.459238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.459252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.460747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.460763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.462569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.465513] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.465541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.465557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.465582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.465755] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.465772] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.465817] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.465841] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.465877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.482463] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.482484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.482504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.482527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.482547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.482568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.482649] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.482668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.482685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.482700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.482715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.482719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.482733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.482737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.482751] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.482766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.482780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.482799] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.482819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.482838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.482856] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.482876] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.482895] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.482916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.482937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.515690] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.515715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.515750] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.534627] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.534648] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.534665] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.534684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.534701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.534717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.534732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.534747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.534762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.534780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.534796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.534812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.534827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.534841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.534868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.534886] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.534905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.535081] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.535097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.535115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.535134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.535149] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.535166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.535182] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.535197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.535211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.535225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.535239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.535243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.535256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.535260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.535274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.535288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.535301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.535314] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.535330] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.535348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.535368] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.535387] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.535406] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.535426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.535447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.535503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.535523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.535542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.535561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.535581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.535631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.535659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.535686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.535711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.535734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.535755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.535781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.535805] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.537808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.537825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.537843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.537861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.539366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.539383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.539397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.540893] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.540909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.542713] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.545652] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.545679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.545696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.545718] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.545757] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.545773] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.545816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.545837] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.545869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.562575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.562613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.562633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.562656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.562676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.562697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.562718] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.562738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.562759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.562779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.562798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.562803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.562823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.562826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.562847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.562867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.562887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.562907] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.562928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.562947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.562968] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.562988] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.563009] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.563030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.563051] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.595822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.595848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.595885] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.614749] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.614771] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.614787] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.614807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.614823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.614839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.614854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.614869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.614885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.614901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.614917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.614933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.614947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.614960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.614988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.615006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.615024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.615199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.615215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.615233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.615252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.615268] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.615284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.615301] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.615316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.615332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.615346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.615359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.615363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.615377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.615380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.615394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.615408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.615421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.615435] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.615451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.615464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.615479] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.615493] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.615506] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.615522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.615539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.615590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.615653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.615673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.615693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.615713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.615733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.615756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.615779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.615802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.615821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.615841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.615864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.615885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.617873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.617888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.617902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.617917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.619420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.619435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.619449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.620945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.620962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.622768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.625708] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.625735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.625752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.625774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.625813] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.625829] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.625877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.625896] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.625925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.642679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.642698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.642717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.642736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.642754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.642774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.642794] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.642813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.642832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.642851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.642870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.642874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.642893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.642896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.642915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.642934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.642953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.642972] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.642991] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.643010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.643030] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.643049] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.643067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.643087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.643108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.675909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.675933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.675970] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.694835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.694857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.694873] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.694893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.694909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.694925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.694940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.694954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.694971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.694988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.695004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.695020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.695034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.695048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.695076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.695097] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.695121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.695295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.695315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.695335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.695357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.695376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.695395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.695422] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.695438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.695453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.695466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.695480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.695483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.695496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.695499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.695513] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.695526] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.695539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.695555] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.695573] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.695590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.695644] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.695665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.695685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.695708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.695732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.695807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.695985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.696000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.696015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.696029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.696044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.696064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.696083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.696102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.696119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.696137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.696155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.696173] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.698158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.698175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.698189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.698204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.699722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.699737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.699751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.701245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.701260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.703065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.706009] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.706036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.706053] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.706075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.706123] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.706149] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.706216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.706243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.706275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.722939] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.722959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.722979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.723000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.723016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.723034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.723053] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.723070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.723087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.723103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.723118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.723122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.723137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.723141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.723156] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.723171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.723186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.723200] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.723218] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.723233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.723248] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.723263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.723277] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.723296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.723318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.756173] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.756197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.756242] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.775109] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.775130] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.775147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.775166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.775183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.775198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.775213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.775228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.775244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.775261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.775277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.775293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.775308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.775321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.775349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.775366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.775384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.775561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.775580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.775600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.775662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.775687] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.775713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.775738] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.775761] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.775785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.775807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.775828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.775835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.775856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.775862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.775884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.775905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.775927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.775950] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.775975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.775996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.776019] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.776043] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.776065] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.776091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.776118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.776198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.776223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.776248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.776275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.776289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.776303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.776319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.776333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.776348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.776361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.776374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.776390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.776405] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.778377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.778393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.778407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.778423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.779931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.779946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.779960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.782538] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.782555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.784365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.787299] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.787327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.787343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.787365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.787414] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.787440] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.787510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.787535] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.787565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.804261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.804281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.804301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.804322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.804339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.804358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.804376] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.804393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.804410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.804426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.804442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.804446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.804461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.804465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.804480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.804496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.804510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.804530] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.804551] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.804571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.804592] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.804652] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.804676] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.804701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.804728] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.837474] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.837499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.837544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.856432] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.856456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.856474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.856496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.856514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.856532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.856548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.856565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.856582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.856601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.856664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.856694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.856719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.856745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.856795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.856826] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.856859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.857121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.857139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.857159] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.857181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.857198] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.857216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.857235] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.857252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.857268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.857284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.857299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.857304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.857319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.857322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.857338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.857353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.857368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.857383] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.857401] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.857416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.857432] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.857447] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.857462] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.857480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.857500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.857558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.857579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.857600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.857650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.857681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.857707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.857738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.857767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.857795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.857819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.857845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.857877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.857903] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.859929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.859947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.859963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.859980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.861502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.861522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.861542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.863058] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.863077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.864899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.867866] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.867895] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.867913] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.867936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.867988] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.868015] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.868085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.868116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.868150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.884787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.884808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.884829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.884850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.884867] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.884886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.884905] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.884923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.884940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.884957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.884973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.884977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.884992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.884996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.885012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.885027] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.885043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.885058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.885076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.885091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.885107] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.885123] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.885138] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.885156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.885175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.918040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.918064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.918100] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.936978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.936999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.937016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.937035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.937052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.937068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.937083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.937098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.937114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.937131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.937147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.937163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.937177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.937191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.937218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.937236] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.937254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.937432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.937448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.937466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.937485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.937500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.937519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.937538] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.937557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.937577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.937596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.937656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.937664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.937687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.937693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.937717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.937739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.937762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.937783] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.937814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.937834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.937856] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.937876] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.937896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.937919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.937942] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.938005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.938024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.938039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.938052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.938065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.938079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.938095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.938109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.938123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.938136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.938149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.938165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.938180] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.940174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.940191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.940207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.940226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.941741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.941757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.941771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.943277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.943294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.945122] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.948064] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.948090] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.948109] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.948135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.948175] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.948194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.948237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.948260] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.948295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.965035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.965055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.965075] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.965096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.965113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.965131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.965149] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.965166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.965183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.965199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.965214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.965218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.965233] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.965236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.965252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.965267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.965282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.965296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.965314] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.965329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.965344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  309.965359] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.965373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.965391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.965410] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.998263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.998287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.998323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.017199] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.017221] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.017237] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.017257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.017273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.017289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.017303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.017318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.017336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.017357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.017378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.017398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.017417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.017436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.017469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.017491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.017515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.017768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.017785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.017804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.017823] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.017838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.017855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.017871] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.017887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.017902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.017916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.017930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.017934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.017948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.017951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.017966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.017985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.018004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.018023] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.018042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.018060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.018080] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.018099] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.018118] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.018138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.018158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.018215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.018234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.018253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.018272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.018291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.018309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.018329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.018350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.018370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.018389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.018407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.018428] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.018446] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.020427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.020444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.020458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.020473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.021980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.021995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.022008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.023500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.023516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.025321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.028243] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.028268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.028284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.028306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.028353] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.028379] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.028447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.028473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.028505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.045148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.045167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.045185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.045205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.045220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.045237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.045254] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.045270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.045289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.045308] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.045327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.045331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.045350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.045354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.045373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.045392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.045411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.045430] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.045449] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.045468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.045488] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.045507] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.045526] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.045545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.045566] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.078380] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.078404] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.078447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.097350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.097372] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.097391] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.097413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.097432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.097452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.097471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.097490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.097509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.097530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.097551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.097571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.097590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.097609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.097692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.097725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.097759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.097974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.097992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.098010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.098031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.098047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.098063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.098081] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.098097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.098113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.098127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.098142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.098146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.098159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.098163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.098178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.098192] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.098207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.098220] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.098237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.098251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.098267] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.098280] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.098295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.098311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.098330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.098381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.098397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.098412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.098426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.098448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.098462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.098477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.098491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.098505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.098522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.098540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.098559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.098576] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.100569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.100586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.100600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.100615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.102217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.102233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.102248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.103751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.103767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.105578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.108498] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.108523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.108539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.108561] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.108609] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.108677] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.108739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.108770] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.108815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.125381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.125400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.125419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.125439] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.125457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.125477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.125497] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.125516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.125535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.125554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.125573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.125577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.125596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.125599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.125619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.125667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.125698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.125722] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.125750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.125773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.125799] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.125822] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.125846] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.125873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.125901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.158651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.158675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.158719] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.177558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.177581] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.177598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.177619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.177679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.177702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.177727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.177749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.177773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.177799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.177825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.177849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.177871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.177892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.177936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.177963] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.177992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.178266] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.178290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.178307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.178324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.178339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.178354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.178369] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.178383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.178397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.178410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.178423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.178427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.178440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.178443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.178456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.178469] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.178482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.178494] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.178511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.178528] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.178546] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.178564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.178582] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.178600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.178620] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.178726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.178746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.178761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.178776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.178789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.178804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.178821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.178836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.178850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.178864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.178876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.178893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.178908] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.180881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.180897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.180911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.180927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.182432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.182447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.182461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.183958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.183974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.185779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.188718] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.188747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.188766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.188792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.188845] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.188871] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.188937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.188970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.189003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.205693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.205712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.205732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.205751] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.205767] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.205784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.205801] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.205817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.205833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.205847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.205861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.205865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.205879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.205882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.205901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.205921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.205940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.205959] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.205978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.205997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.206016] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.206035] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.206054] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.206074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.206094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.238889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.238914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.238957] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.257864] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.257887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.257907] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.257929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.257948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.257968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.257987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.258006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.258025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.258046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.258066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.258087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.258105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.258124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.258157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.258179] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.258203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.258387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.258407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.258427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.258449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.258467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.258487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.258506] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.258525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.258544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.258563] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.258582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.258586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.258605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.258608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.258628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.258691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.258716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.258739] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.258764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.258787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.258812] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.258834] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.258856] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.258882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.258914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.258989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.259011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.259033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.259054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.259070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.259084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.259100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.259114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.259129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.259142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.259154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.259171] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.259185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.261178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.261194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.261209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.261223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.262735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.262750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.262764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.264256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.264271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.266077] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.269023] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.269058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.269075] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.269096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.269142] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.269165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.269226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.269252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.269283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.285946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.285966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.285986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.286007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.286024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.286042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.286061] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.286080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.286101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.286122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.286142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.286146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.286166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.286170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.286190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.286211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.286231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.286251] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.286271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.286291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.286312] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.286332] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.286352] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.286373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.286395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.319187] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.319211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.319255] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.338103] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.338124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.338143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.338165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.338184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.338204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.338223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.338242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.338261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.338282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.338302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.338322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.338341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.338360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.338393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.338415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.338438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.338624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.338691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.338716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.338742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.338763] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.338786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.338809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.338831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.338852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.338872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.338892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.338898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.338918] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.338924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.338945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.338965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.338985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.339004] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.339028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.339049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.339071] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.339092] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.339113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.339137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.339161] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.339232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.339247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.339261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.339274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.339287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.339304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.339324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.339343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.339362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.339380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.339397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.339416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.339435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.341410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.341427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.341445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.341463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.342971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.342987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.343001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.344496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.344512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.346318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.350326] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.350353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.350370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.350392] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.350440] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.350465] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.350532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.350559] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.350592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.367267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.367288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.367308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.367331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.367351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.367372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.367393] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.367413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.367433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.367453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.367473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.367478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.367497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.367501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.367522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.367542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.367562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.367582] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.367602] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.367622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.367684] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.367709] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.367732] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.367758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.367785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.400489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.400515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.400560] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.419476] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.419499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.419517] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.419538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.419559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.419579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.419600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.419621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.419641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.419711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.419741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.419769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.419795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.419821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.419867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.419900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.419930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.420097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.420115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.420134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.420155] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.420172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.420191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.420209] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.420226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.420243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.420259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.420274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.420279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.420294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.420298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.420315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.420330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.420345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.420359] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.420378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.420393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.420410] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.420424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.420439] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.420457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.420477] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.420533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.420550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.420565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.420582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.420596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.420613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.420630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.420674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.420701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.420723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.420746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.420773] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.420798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.422809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.422827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.422843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.422859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.424376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.424395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.424414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.425927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.425945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.427762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.430709] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.430735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.430752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.430775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.430823] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.430850] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.430919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.430946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.430979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.447643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.447676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.447697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.447720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.447740] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.447761] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.447781] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.447801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.447822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.447842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.447862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.447866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.447886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.447890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.447910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.447930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.447951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.447971] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.447991] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.448011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.448032] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.448052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.448072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.448093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.448115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.480871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.480895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.480939] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.499802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.499823] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.499840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.499859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.499876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.499891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.499906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.499921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.499936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.499953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.499969] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.499984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.499999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.500013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.500040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.500058] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.500076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.500253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.500269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.500287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.500305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.500320] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.500336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.500353] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.500369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.500384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.500398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.500412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.500416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.500429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.500433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.500447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.500461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.500475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.500488] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.500504] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.500518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.500533] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.500546] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.500564] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.500585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.500605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.500697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.500721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.500745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.500767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.500789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.500812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.500837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.500862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.500886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.500907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.500929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.500955] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.500978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.502972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.502988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.503002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.503016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.504519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.504534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.504548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.506043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.506059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.507863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.510797] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.510823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.510839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.510861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.510909] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.510935] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.511001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.511028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.511061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.527761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.527780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.527799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.527818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.527834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.527851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.527868] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.527884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.527899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.527914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.527928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.527932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.527946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.527949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.527964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.527978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.527991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.528004] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.528021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.528035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.528049] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.528063] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.528076] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.528092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.528109] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.560973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.560998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.561042] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.579941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.579963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.579979] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.579998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.580015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.580031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.580046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.580060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.580079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.580100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.580121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.580141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.580160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.580179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.580212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.580235] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.580258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.580429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.580449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.580469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.580491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.580510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.580529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.580548] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.580567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.580587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.580605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.580624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.580628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.580646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.580688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.580716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.580740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.580764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.580788] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.580812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.580841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.580863] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.580883] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.580903] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.580926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.580949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.581024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.581046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.581067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.581089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.581104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.581118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.581133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.581147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.581162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.581175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.581187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.581203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.581218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.583200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.583216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.583229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.583244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.584756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.584771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.584785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.586282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.586298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.588105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.591051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.591077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.591095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.591119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.591167] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.591192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.591255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.591281] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.591312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.607986] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.608008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.608029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.608052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.608072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.608093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.608114] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.608134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.608155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.608175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.608195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.608199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.608219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.608223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.608243] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.608263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.608284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.608304] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.608324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.608344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.608365] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.608385] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.608405] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.608426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.608448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.641214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.641238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.641281] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.660184] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.660206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.660223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.660243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.660261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.660277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.660293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.660308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.660324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.660342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.660359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.660375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.660390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.660404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.660433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.660452] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.660471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.660707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.660732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.660759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.660788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.660811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.660836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.660862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.660887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.660911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.660935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.660956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.660964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.660986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.660992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.661016] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.661037] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.661061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.661085] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.661109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.661132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.661154] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.661177] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.661198] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.661223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.661250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.661329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.661349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.661369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.661388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.661409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.661428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.661451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.661474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.661496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.661515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.661535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.661557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.661579] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.663576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.663592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.663606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.663621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.665130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.665145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.665158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.666659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.666688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.668497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.671436] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.671463] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.671479] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.671501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.671541] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.671558] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.671597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.671617] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.671649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.688380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.688400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.688420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.688441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.688457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.688476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.688494] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.688511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.688528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.688544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.688559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.688563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.688577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.688581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.688599] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.688619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.688640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.688699] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.688727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.688752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.688780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.688805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.688829] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.688856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.688884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.721639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.721703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.721813] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.740713] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.740736] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.740756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.740777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.740797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.740816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.740835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.740855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.740874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.740895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.740915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.740935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.740954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.740973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.741005] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.741028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.741051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.741234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.741254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.741273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.741295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.741314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.741333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.741353] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.741372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.741391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.741410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.741428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.741432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.741451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.741454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.741474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.741493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.741512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.741538] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.741555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.741571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.741587] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.741601] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.741614] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.741630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.741646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.741744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.741768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.741792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.741815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.741838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.741861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.741887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.741911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.741936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.741958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.741980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.742006] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.742029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.744023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.744040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.744058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.744076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.745609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.745625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.745640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.747167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.747182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.749016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.751960] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.751986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.752003] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.752025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.752073] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.752099] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.752165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.752193] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.752226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.768922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.768941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.768960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.768980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.768995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.769012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.769029] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.769045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.769060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.769074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.769089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.769093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.769106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.769110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.769129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.769148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.769168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.769186] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.769205] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.769224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.769244] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.769263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.769282] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.769302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.769322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.802125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.802151] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.802196] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.821059] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.821080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.821097] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.821116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.821133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.821149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.821164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.821179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.821195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.821213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.821232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.821253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.821272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.821291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.821323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.821345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.821369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.821559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.821578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.821598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.821620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.821639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.821659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.821722] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.821747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.821770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.821793] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.821815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.821822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.821843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.821849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.821871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.821893] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.821915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.821936] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.821961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.821982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.822006] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.822027] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.822050] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.822076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.822102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.822169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.822185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.822201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.822215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.822229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.822244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.822260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.822276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.822291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.822306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.822319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.822337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.822353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.824331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.824347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.824361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.824376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.825883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.825898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.825911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.827403] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.827419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.829225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.832144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.832169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.832188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.832214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.832263] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.832289] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.832356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.832382] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.832414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.849038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.849060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.849082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.849105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.849125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.849146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.849166] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.849186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.849207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.849227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.849247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.849251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.849271] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.849274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.849295] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.849315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.849335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.849355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.849376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.849395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.849416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.849436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.849456] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.849477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.849499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.882283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.882309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.882355] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.901217] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.901239] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.901255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.901274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.901291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.901306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.901325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.901344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.901363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.901384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.901405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.901425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.901444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.901463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.901495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.901518] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.901541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.901807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.901835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.901863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.901883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.901899] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.901916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.901934] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.901950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.901965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.901980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.901994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.901998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.902012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.902016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.902035] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.902054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.902074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.902094] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.902114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.902133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.902153] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.902173] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.902193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.902213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.902234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.902294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.902311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.902326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.902340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.902353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.902368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.902384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.902399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.902417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.902435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.902453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.902471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.902488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.904464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.904481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.904496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.904511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.906017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.906032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.906045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.907537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.907553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.909359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.912279] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.912304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.912320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.912341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.912389] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.912415] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.912481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.912513] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.912542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.929186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.929205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.929224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.929243] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.929258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.929275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.929292] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.929308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.929323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.929338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.929352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.929356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.929370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.929373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.929388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.929402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.929415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.929434] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.929453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.929472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.929492] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.929511] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.929530] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.929550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.929571] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.962417] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.962441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.962485] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.981351] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.981372] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.981388] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.981408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.981425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.981440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.981455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.981470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.981486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.981503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.981519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.981535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.981549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.981563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.981590] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.981608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.981626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.981907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.981925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.981944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.981963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.981979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.981997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.982014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.982031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.982046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.982062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.982076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.982080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.982094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.982098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.982113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.982132] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.982152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.982170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.982189] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.982215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.982232] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  310.982246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.982259] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.982276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.982292] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.982341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.982357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.982370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.982384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.982396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.982411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.982426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.982441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.982455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.982468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.982481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.982497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.982512] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.984486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.984502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.984516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.984531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.986037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.986052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.986066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.987559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.987574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.989380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.992300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.992326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.992342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.992364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.992412] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.992444] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.992505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.992529] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.992559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.009203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.009224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.009244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.009265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.009282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.009300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.009318] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.009335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.009352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.009372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.009392] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.009396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.009416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.009420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.009441] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.009461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.009481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.009501] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.009522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.009541] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.009562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.009583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.009603] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.009624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.009646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.042439] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.042463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.042506] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.061168] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.061188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.061203] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.061221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.061236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.061250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.061264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.061278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.061292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.061308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.061322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.061337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.061349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.061362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.061387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.061404] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.061420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.061582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.061597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.061613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.061630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.061645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.061660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.061675] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.061718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.061744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.061764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.061784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.061791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.061811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.061817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.061839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.061859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.061880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.061900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.061925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.061945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.061967] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.061987] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.062008] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.062033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.062059] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.062123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.062143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.062164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.062183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.062203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.062223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.062246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.062268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.062291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.062309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.062330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.062352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.062374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.064384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.064401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.064415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.064430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.065939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.065956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.065973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.067467] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.067484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.069290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.072223] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.072250] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.072266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.072288] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.072342] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.072366] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.072426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.072453] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.072483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.089177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.089198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.089218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.089239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.089255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.089273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.089292] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.089308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.089325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.089340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.089355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.089359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.089374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.089378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.089393] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.089408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.089423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.089437] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.089457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.089477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.089498] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.089519] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.089539] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.089560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.089582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.122400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.122425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.122470] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.141320] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.141342] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.141358] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.141377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.141393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.141409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.141424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.141439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.141455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.141472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.141488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.141504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.141518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.141532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.141560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.141577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.141596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.141839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.141866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.141894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.141916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.141932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.141949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.141973] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.141988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.142003] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.142016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.142029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.142033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.142050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.142053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.142072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.142089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.142107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.142124] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.142142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.142160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.142179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.142196] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.142215] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.142234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.142253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.142305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.142323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.142341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.142360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.142377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.142395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.142415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.142435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.142453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.142471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.142488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.142508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.142525] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.144500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.144516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.144530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.144545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.146054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.146069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.146083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.147575] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.147591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.149397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.152316] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.152342] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.152358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.152380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.152428] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.152453] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.152519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.152545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.152578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.169226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.169246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.169266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.169288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.169309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.169330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.169350] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.169371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.169391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.169411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.169431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.169435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.169455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.169459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.169479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.169499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.169519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.169539] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.169560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.169580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.169600] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.169621] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.169641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.169662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.169684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.202455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.202481] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.202527] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.221384] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.221406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.221422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.221442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.221458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.221473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.221492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.221512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.221531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.221552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.221572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.221592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.221611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.221630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.221663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.221685] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.221754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.221961] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.221977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.221994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.222013] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.222027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.222044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.222060] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.222075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.222089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.222103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.222115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.222120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.222133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.222136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.222150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.222163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.222176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.222188] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.222204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.222216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.222230] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.222243] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.222255] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.222270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.222287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.222335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.222349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.222363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.222376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.222389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.222402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.222417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.222431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.222446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.222459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.222471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.222487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.222502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.224478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.224494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.224508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.224522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.226029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.226044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.226058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.227550] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.227566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.229371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.232291] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.232317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.232333] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.232354] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.232401] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.232427] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.232493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.232519] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.232551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.249200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.249220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.249240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.249260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.249277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.249295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.249313] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.249333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.249354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.249374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.249394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.249398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.249418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.249422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.249442] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.249462] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.249483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.249503] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.249523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.249542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.249563] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.249583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.249604] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.249625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.249646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.282430] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.282454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.282498] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.302441] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.302463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.302479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.302499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.302515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.302531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.302546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.302561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.302577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.302594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.302610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.302626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.302640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.302653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.302681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.302744] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.302775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.303019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.303039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.303058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.303080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.303099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.303118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.303138] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.303157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.303176] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.303195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.303213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.303218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.303236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.303240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.303260] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.303278] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.303298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.303316] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.303335] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.303353] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.303373] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.303392] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.303411] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.303430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.303451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.303506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.303525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.303544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.303563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.303583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.303601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.303622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.303642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.303662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.303681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.303725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.303751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.303775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.305768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.305784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.305798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.305812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.307317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.307332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.307347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.308843] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.308859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.310664] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.313582] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.313608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.313627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.313653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.313702] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.313767] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.313833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.313856] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.313888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.330490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.330509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.330527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.330546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.330562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.330578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.330595] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.330611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.330627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.330641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.330660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.330664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.330683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.330721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.330749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.330772] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.330797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.330820] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.330846] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.330868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.330894] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.330916] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.330939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.330968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.330993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.363723] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.363748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.363792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.382655] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.382677] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.382693] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.382756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.382777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.382793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.382809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.382824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.382839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.382857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.382874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.382891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.382905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.382920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.382948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.382966] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.382985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.383165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.383182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.383199] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.383220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.383235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.383253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.383269] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.383285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.383300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.383315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.383329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.383334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.383348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.383351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.383367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.383380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.383395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.383408] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.383425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.383439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.383455] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.383468] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.383483] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.383499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.383517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.383570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.383586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.383601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.383616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.383629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.383644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.383668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.383682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.383718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.383739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.383758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.383781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.383802] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.385793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.385811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.385828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.385846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.387351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.387367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.387381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.388880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.388896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.390700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.393641] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.393668] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.393685] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.393746] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.393921] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.393937] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.393977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.393997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.394029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.410571] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.410592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.410614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.410637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.410657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.410678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.410698] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.410758] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.410784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.410807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.410830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.410837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.410859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.410866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.410891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.410915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.410938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.410961] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.410987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.411010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.411031] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.411046] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.411060] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.411077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.411096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.443816] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.443840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.443876] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.462483] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.462505] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.462521] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.462541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.462558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.462573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.462589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.462603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.462619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.462636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.462652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.462668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.462682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.462696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.462775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.462805] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.462835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.463115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.463132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.463152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.463174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.463192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.463212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.463231] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.463250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.463270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.463288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.463307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.463311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.463330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.463333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.463353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.463371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.463390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.463409] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.463428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.463447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.463467] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.463486] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.463504] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.463524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.463545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.463593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.463612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.463632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.463658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.463674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.463689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.463736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.463763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.463788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.463809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.463831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.463854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.463877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.465873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.465891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.465908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.465926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.467435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.467451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.467466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.468974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.468992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.470799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.473745] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.473773] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.473789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.473811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.473851] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.473874] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.473913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.473932] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.473961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.490682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.490702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.490764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.490794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.490819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.490847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.490870] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.490890] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.490910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.490930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.490949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.490953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.490972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.490976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.490996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.491016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.491035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.491054] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.491074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.491094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.491114] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.491133] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.491152] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.491173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.491194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.523907] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.523931] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.523965] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.542823] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.542845] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.542861] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.542880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.542897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.542913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.542928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.542943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.542959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.542976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.542992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.543008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.543022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.543036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.543064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.543082] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.543100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.543272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.543291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.543311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.543333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.543352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.543371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.543391] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.543410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.543429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.543448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.543466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.543470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.543489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.543493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.543512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.543537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.543552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.543566] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.543581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.543595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.543612] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.543630] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.543647] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.543665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.543684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.543786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.543809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.543831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.543852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.543872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.543893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.543916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.543939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.543963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.543984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.544005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.544028] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.544051] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.546047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.546063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.546078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.546092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.547595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.547611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.547624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.549119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.549135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.550937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.553875] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.553902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.553919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.553940] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.553980] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.553999] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.554045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.554069] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.554104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.570824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.570846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.570867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.570890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.570910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.570931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.570952] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.570972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.570993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.571013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.571033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.571037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.571057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.571060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.571081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.571101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.571121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.571141] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.571161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.571181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.571202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.571222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.571242] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.571263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.571285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.604046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.604070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.604105] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.623012] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.623033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.623049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.623068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.623085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.623100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.623116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.623130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.623146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.623163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.623179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.623195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.623209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.623223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.623250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.623268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.623286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.623465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.623480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.623496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.623514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.623528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.623543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.623558] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.623572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.623586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.623600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.623612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.623616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.623628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.623631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.623644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.623656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.623669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.623681] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.623696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.623746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.623768] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.623788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.623808] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.623830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.623854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.623928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.623950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.623970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.623991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.624008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.624023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.624038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.624053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.624068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.624085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.624102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.624120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.624138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.626110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.626127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.626144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.626162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.627669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.627685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.627699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.629236] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.629252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.631079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.634022] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.634050] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.634066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.634089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.634128] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.634145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.634189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.634211] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.634242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.650987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.651006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.651025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.651044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.651060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.651077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.651094] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.651109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.651125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.651139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.651153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.651158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.651172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.651175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.651190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.651204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.651218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.651231] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.651248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.651261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.651276] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.651290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.651303] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.651319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.651337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.684188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.684211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.684245] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.703206] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.703231] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.703250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.703272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.703291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.703309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.703326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.703342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.703361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.703380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.703399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.703421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.703443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.703465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.703502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.703528] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.703555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.703819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.703850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.703884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.703917] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.703945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.703976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.704006] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.704035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.704064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.704092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.704118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.704125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.704151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.704157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.704184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.704211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.704237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.704262] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.704292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.704318] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.704346] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.704373] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.704397] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.704426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.704457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.704551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.704579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.704607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.704634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.704662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.704690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.704720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.704781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.704807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.704829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.704852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.704879] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.704903] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.706894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.706912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.706929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.706948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.708453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.708469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.708483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.709981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.709996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.711801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.714740] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.714767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.714787] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.714812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.714852] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.714871] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.714917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.714940] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.714975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.731680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.731700] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.731720] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.731785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.731814] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.731842] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.731870] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.731895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.731920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.731944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.731967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.731973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.731994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.731999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.732023] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.732046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.732067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.732090] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.732116] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.732139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.732161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.732183] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.732206] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.732233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.732260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.764910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.764936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.764973] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.783826] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.783847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.783864] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.783883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.783900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.783916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.783931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.783946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.783962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.783979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.783995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.784011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.784025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.784039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.784067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.784085] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.784104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.784279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.784296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.784313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.784332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.784347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.784363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.784379] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.784398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.784417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.784436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.784455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.784459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.784478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.784482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.784501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.784520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.784539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.784557] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.784577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.784595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.784615] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.784634] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.784653] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.784673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.784693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.784805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.784833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.784860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.784885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.784911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.784937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.784966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.784993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.785020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.785044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.785069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.785098] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.785124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.787122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.787139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.787153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.787168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.788673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.788688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.788701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.790224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.790240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.792075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.794635] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.794663] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.794679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.794701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.794782] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.794808] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.794876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.794907] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.794958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.811560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.811580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.811600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.811624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.811644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.811665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.811686] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.811706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.811726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.811789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.811818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.811826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.811851] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.811858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.811884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.811908] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.811933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.811958] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.811985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.812009] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.812032] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.812056] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.812080] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.812108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.812136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.844779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.844805] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.844842] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.863278] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.863302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.863319] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.863339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.863356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.863373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.863389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.863405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.863421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.863440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.863457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.863473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.863488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.863503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.863532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.863552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.863571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.863797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.863825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.863853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.863885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.863911] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.863940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.863968] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.863994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.864021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.864040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.864055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.864059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.864074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.864078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.864094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.864109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.864124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.864139] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.864156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.864171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.864187] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.864201] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.864216] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.864233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.864252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.864310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.864327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.864343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.864358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.864373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.864389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.864406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.864423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.864439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.864454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.864469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.864487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.864504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.866484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.866500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.866514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.866528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.868035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.868050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.868064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.869557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.869572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.871379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.874313] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.874341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.874360] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.874386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.874427] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.874446] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.874492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.874516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.874551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.891260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.891280] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.891300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.891321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.891338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.891356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.891375] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.891392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.891409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.891425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.891440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.891444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.891464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.891468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.891488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.891509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.891529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.891550] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.891570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.891590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.891611] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.891631] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.891651] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.891672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.891694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.924488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.924513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.924550] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.943404] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.943426] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.943442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.943461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.943478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.943493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.943508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.943523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.943539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.943556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.943572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.943588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.943602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.943616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.943648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.943670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.943694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.943944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.943960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.943978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.943996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.944010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.944027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.944042] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.944057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.944072] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.944085] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.944099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.944102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.944115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.944118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.944132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.944145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.944158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.944171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.944186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.944199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.944214] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.944226] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.944240] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.944258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.944278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.944329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.944347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.944364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.944382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.944400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.944418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.944438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.944457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.944476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.944494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.944511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.944530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.944548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.946528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.946544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.946561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.946580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.948091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.948107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.948121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.949614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.949631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.951437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.954358] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.954384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.954400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.954422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.954460] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.954476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.954518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.954539] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.954570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.971258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.971279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.971299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.971320] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.971337] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.971355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.971373] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.971390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.971407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.971423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.971439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.971443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.971458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.971461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.971477] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.971492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.971507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.971522] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.971539] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.971554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.971569] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  311.971584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.971598] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.971616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.971634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.004521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.004544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.004578] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.023454] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.023476] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.023492] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.023511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.023528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.023543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.023559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.023573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.023589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.023606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.023622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.023638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.023652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.023666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.023693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.023711] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.023729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.024052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.024076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.024102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.024131] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.024154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.024179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.024203] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.024227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.024250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.024273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.024294] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.024301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.024322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.024327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.024350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.024372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.024394] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.024415] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.024440] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.024460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.024484] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.024505] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.024527] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.024551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.024577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.024644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.024666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.024694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.024714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.024734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.024772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.024796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.024820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.024844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.024864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.024886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.024912] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.024933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.026927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.026942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.026957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.026971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.028478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.028493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.028506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.030004] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.030020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.031837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.034772] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.034798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.034815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.034836] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.034889] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.034912] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.034973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.034997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.035027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.051711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.051732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.051794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.051825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.051851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.051877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.051896] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.051912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.051928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.051943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.051959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.051963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.051977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.051981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.051996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.052010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.052025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.052038] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.052059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.052078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.052099] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.052119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.052139] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.052159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.052181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.084979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.085003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.085039] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.103966] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.103991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.104009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.104031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.104050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.104067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.104085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.104101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.104119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.104139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.104157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.104175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.104197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.104219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.104256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.104282] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.104309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.104527] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.104550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.104573] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.104597] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.104619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.104641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.104663] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.104685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.104707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.104729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.104800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.104809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.104839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.104847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.104876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.104903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.104930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.104956] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.104986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.105012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.105041] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.105066] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.105093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.105125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.105157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.105251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.105277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.105305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.105329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.105356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.105381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.105410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.105439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.105467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.105491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.105516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.105544] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.105572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.107593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.107610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.107625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.107640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.109148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.109163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.109177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.110690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.110706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.112512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.115433] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.115458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.115475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.115497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.115544] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.115569] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.115635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.115661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.115694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.132321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.132340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.132359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.132379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.132398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.132418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.132437] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.132456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.132475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.132494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.132513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.132517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.132535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.132539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.132558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.132577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.132596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.132615] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.132634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.132653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.132673] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.132692] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.132710] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.132730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.132793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.165571] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.165595] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.165639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.184574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.184595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.184614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.184636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.184656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.184675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.184695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.184714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.184733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.184797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.184826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.184851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.184875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.184892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.184920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.184939] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.184958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.185137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.185154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.185172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.185194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.185214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.185234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.185254] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.185274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.185294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.185313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.185333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.185337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.185357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.185361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.185381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.185400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.185420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.185439] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.185459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.185478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.185498] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.185517] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.185544] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.185562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.185581] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.185631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.185647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.185661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.185675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.185688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.185702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.185717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.185732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.185770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.185790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.185809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.185833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.185854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.187845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.187861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.187875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.187890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.189392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.189407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.189421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.190917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.190933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.192736] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.195679] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.195712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.195728] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.195788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.195931] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.195947] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.195987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.196007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.196037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.212633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.212653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.212673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.212694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.212710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.212731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.212790] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.212814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.212840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.212862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.212884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.212891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.212912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.212919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.212943] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.212966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.212989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.213012] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.213038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.213061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.213080] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.213094] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.213108] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.213125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.213143] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.245857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.245881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.245916] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.264580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.264602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.264618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.264637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.264654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.264669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.264684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.264699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.264714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.264731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.264747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.264806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.264828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.264850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.264893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.264922] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.264953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.265118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.265135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.265154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.265173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.265189] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.265214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.265229] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.265244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.265258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.265273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.265286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.265290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.265303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.265306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.265320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.265333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.265346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.265359] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.265375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.265387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.265402] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.265414] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.265427] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.265442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.265459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.265508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.265522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.265536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.265550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.265563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.265576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.265591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.265606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.265620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.265633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.265646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.265662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.265676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.267655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.267671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.267687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.267705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.269214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.269229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.269243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.271834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.271852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.273655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.276589] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.276616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.276633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.276655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.276694] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.276713] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.276800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.276834] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.276885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.293529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.293551] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.293572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.293596] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.293616] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.293637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.293657] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.293677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.293698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.293718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.293738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.293779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.293807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.293813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.293841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.293866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.293891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.293913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.293940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.293962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.293988] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.294010] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.294032] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.294056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.294084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.326779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.326806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.326842] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.345699] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.345721] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.345737] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.345756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.345815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.345839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.345864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.345887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.345911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.345939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.345965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.345990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.346011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.346034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.346078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.346106] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.346135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.346352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.346367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.346384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.346401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.346415] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.346431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.346446] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.346460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.346474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.346487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.346500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.346503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.346515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.346518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.346531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.346544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.346557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.346569] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.346584] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.346596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.346609] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.346622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.346634] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.346649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.346664] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.346711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.346725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.346739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.346752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.346790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.346814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.346837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.346861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.346885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.346905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.346927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.346952] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.346974] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.348968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.348984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.348998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.349013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.350516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.350534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.350551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.352049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.352065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.353869] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.356808] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.356836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.356855] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.356881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.356921] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.356941] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.356986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.357010] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.357045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.373755] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.373793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.373813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.373834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.373850] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.373869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.373887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.373904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.373921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.373937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.373952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.373956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.373971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.373975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.373991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.374006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.374021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.374036] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.374056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.374076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.374097] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.374118] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.374138] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.374159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.374181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.406978] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.407003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.407037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.425892] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.425913] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.425930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.425949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.425965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.425981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.425996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.426011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.426027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.426043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.426059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.426079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.426098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.426117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.426149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.426172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.426195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.426360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.426380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.426399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.426421] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.426440] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.426460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.426479] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.426498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.426517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.426536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.426555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.426559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.426577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.426581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.426600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.426619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.426638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.426657] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.426676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.426694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.426714] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.426733] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.426752] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.426816] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.426844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.426934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.426957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.426980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.427000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.427020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.427041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.427066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.427083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.427099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.427112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.427125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.427141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.427155] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.429125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.429141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.429154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.429168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.430671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.430687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.430700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.432196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.432211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.434015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.436941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.436966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.436983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.437005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.437042] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.437059] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.437108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.437126] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.437155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.453863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.453883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.453904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.453925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.453942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.453962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.453983] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.454003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.454024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.454044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.454064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.454068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.454088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.454092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.454113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.454133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.454153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.454173] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.454194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.454213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.454235] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.454255] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.454275] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.454296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.454317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.487075] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.487099] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.487134] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.506057] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.506081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.506099] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.506121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.506139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.506157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.506173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.506190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.506207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.506226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.506244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.506262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.506278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.506293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.506323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.506343] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.506364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.506559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.506577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.506597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.506617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.506634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.506653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.506671] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.506688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.506706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.506722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.506737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.506741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.506757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.506802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.506828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.506852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.506876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.506899] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.506926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.506950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.506976] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.506999] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.507023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.507051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.507079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.507166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.507192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.507216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.507240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.507265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.507285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.507304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.507322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.507339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.507354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.507370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.507389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.507407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.509404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.509423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.509440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.509461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.510988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.511006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.511023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.512532] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.512550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.514373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.517319] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.517347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.517368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.517395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.517438] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.517458] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.517507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.517532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.517569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.534246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.534266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.534285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.534307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.534326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.534345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.534364] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.534383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.534403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.534421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.534440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.534444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.534462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.534466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.534486] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.534504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.534523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.534542] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.534561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.534580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.534600] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.534619] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.534638] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.534658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.534678] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.567483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.567507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.567542] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.587501] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.587523] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.587539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.587561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.587580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.587600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.587619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.587639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.587658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.587679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.587699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.587720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.587738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.587757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.587838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.587868] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.587902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.588119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.588137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.588156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.588176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.588192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.588209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.588226] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.588242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.588257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.588272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.588287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.588291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.588305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.588308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.588322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.588338] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.588352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.588366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.588382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.588397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.588412] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.588434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.588452] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.588471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.588491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.588545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.588563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.588581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.588599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.588618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.588636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.588655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.588674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.588693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.588711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.588728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.588747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.588764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.590768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.590796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.590811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.590826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.592332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.592348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.592361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.593869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.593885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.595715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.598647] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.598680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.598695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.598715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.598750] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.598766] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.598856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.598887] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.598933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.615595] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.615617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.615639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.615662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.615682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.615703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.615723] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.615744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.615764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.615827] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.615853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.615861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.615886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.615893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.615919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.615944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.615969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.615993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.616020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.616044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.616070] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.616094] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.616118] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.616144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.616172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.648823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.648848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.648883] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.667398] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.667419] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.667435] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.667455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.667471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.667487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.667502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.667517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.667533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.667550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.667566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.667586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.667605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.667624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.667657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.667679] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.667703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.668002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.668021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.668041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.668061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.668076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.668095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.668112] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.668132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.668152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.668171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.668191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.668196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.668215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.668219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.668239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.668258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.668277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.668297] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.668316] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.668335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.668355] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.668381] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.668397] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.668414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.668431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.668473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.668488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.668502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.668515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.668528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.668542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.668557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.668572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.668586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.668600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.668613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.668629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.668643] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.670636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.670653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.670667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.670682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.672191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.672208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.672226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.673723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.673740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.675547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.678480] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.678507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.678524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.678552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.678587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.678602] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.678642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.678661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.678691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.695409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.695429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.695450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.695474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.695494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.695515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.695535] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.695555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.695575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.695595] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.695615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.695619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.695639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.695643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.695663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.695684] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.695704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.695724] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.695744] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.695764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.695826] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.695851] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.695874] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.695899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.695925] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.728656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.728682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.728719] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.747591] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.747620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.747637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.747656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.747673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.747688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.747707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.747726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.747746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.747766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.747831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.747860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.747885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.747910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.747954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.747984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.748014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.748312] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.748336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.748362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.748390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.748412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.748437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.748459] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.748474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.748488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.748501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.748514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.748518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.748531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.748534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.748547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.748559] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.748572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.748584] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.748599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.748612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.748630] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.748648] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.748665] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.748684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.748704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.748760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.748778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.748827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.748851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.748876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.748900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.748926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.748952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.748976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.748998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.749021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.749047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.749071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.751075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.751092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.751107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.751121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.752628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.752643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.752658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.754155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.754171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.755975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.758920] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.758948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.758965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.758988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.759031] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.759047] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.759093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.759114] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.759146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.775894] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.775914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.775934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.775956] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.775973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.775991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.776009] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.776026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.776043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.776059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.776074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.776078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.776093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.776097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.776113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.776128] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.776143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.776157] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.776175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.776191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.776211] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.776232] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.776252] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.776274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.776296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.809084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.809110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.809147] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.828001] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.828024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.828044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.828066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.828085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.828105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.828124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.828144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.828163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.828183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.828204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.828224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.828243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.828262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.828294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.828317] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.828340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.828526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.828545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.828565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.828587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.828606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.828626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.828645] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.828664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.828683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.828702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.828720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.828724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.828743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.828747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.828766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.828785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.828850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.828880] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.828907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.828934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.828967] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.828990] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.829013] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.829039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.829065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.829138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.829161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.829185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.829207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.829228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.829251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.829275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.829298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.829322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.829343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.829364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.829389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.829412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.831406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.831423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.831439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.831457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.832965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.832981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.832996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.834487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.834503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.836309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.839229] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.839255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.839271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.839293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.839331] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.839348] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.839390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.839411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.839442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.856127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.856148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.856168] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.856188] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.856207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.856228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.856248] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.856268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.856289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.856309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.856329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.856334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.856353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.856357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.856378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.856398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.856418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.856438] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.856459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.856479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.856500] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.856520] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.856540] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.856561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.856583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.889367] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.889394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.889431] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.908349] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.908372] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.908392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.908414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.908433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.908452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.908472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.908491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.908510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.908531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.908552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.908572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.908590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.908609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.908642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.908664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.908687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.908968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.908993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.909020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.909047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.909069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.909093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.909118] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.909141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.909164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.909185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.909207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.909213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.909233] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.909239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.909260] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.909282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.909303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.909322] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.909346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.909367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.909390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.909410] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.909432] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.909456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.909481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.909556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.909579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.909601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.909623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.909643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.909665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.909690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.909714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.909737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.909758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.909779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.909820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.909845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.911835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.911851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.911867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.911885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.913392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.913408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.913422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.914918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.914934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.916740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.919661] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.919687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.919703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.919725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.919763] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.919780] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.919972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.919994] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.920027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.936570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.936589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.936607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.936627] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.936642] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.936659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.936676] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.936692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.936707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.936722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.936736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.936740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.936753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.936757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.936771] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.936785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.936841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.936864] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.936891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.936913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.936939] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.936961] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.936985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.937010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.937039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.969814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.969839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.969874] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.988726] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.988748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.988764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.988783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.988838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.988864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.988887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.988913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.988936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.988964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.989147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.989164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.989179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.989193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.989220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.989239] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.989258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.989413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.989430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.989448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.989467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.989482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.989499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.989518] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.989537] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.989557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.989576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.989594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.989598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.989617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.989621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.989640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.989659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.989678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.989697] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.989716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.989734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.989754] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  312.989773] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.989792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.989841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.989880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.989954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.990194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.990215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.990236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.990256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.990279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.990303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.990327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.990350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.990369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.990389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.990412] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.990434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.992434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.992452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.992467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.992481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.993995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.994010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.994024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.995521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.995536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.997350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.000287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.000314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.000330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.000352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.000392] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.000408] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.000448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.000469] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.000501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.017242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.017262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.017282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.017303] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.017320] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.017338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.017356] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.017377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.017398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.017418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.017438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.017442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.017462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.017465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.017486] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.017506] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.017526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.017547] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.017567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.017587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.017607] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.017628] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.017648] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.017669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.017690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.050483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.050518] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.050582] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.068713] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.068735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.068751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.068770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.068787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.068841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.068867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.068891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.068915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.068942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.068968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.068994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.069015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.069038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.069082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.069110] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.069140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.069376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.069396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.069416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.069438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.069457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.069476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.069495] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.069514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.069534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.069559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.069575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.069579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.069593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.069596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.069610] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.069624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.069637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.069649] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.069665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.069678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.069692] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.069704] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.069717] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.069732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.069748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.069798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.069839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.069863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.069884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.069906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.069928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.069953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.069976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.070001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.070020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.070042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.070067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.070089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.072080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.072096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.072109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.072124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.073629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.073644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.073657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.075152] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.075168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.076971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.079918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.079945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.079962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.079984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.080032] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.080058] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.080124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.080153] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.080185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.096883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.096902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.096921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.096940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.096956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.096973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.096992] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.097011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.097031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.097050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.097068] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.097073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.097091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.097095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.097114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.097133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.097152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.097171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.097190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.097208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.097228] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.097247] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.097266] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.097286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.097307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.130080] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.130105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.130148] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.148981] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.149003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.149019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.149039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.149055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.149071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.149086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.149100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.149116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.149133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.149149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.149164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.149178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.149192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.149220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.149238] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.149256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.149419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.149435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.149453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.149472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.149487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.149503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.149519] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.149534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.149549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.149563] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.149577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.149581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.149595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.149598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.149612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.149626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.149640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.149653] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.149669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.149683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.149697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.149710] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.149724] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.149740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.149757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.149851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.149875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.149899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.149922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.149945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.149967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.149994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.150021] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.150046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.150068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.150091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.150119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.150143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.152140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.152156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.152171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.152185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.153688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.153703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.153717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.155212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.155228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.157031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.159969] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.159996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.160012] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.160034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.160083] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.160109] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.160176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.160203] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.160236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.176929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.176949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.176970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.176991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.177010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.177031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.177052] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.177072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.177093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.177113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.177133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.177137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.177157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.177161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.177181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.177201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.177222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.177242] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.177262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.177282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.177303] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.177323] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.177343] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.177364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.177386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.210140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.210166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.210211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.229074] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.229096] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.229112] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.229132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.229149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.229165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.229180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.229195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.229210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.229228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.229244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.229260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.229275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.229289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.229316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.229334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.229353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.229529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.229546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.229563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.229582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.229597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.229614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.229630] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.229646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.229661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.229675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.229689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.229693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.229707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.229711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.229725] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.229739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.229753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.229766] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.229783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.229796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.229854] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.229877] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.229901] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.229928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.229956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.230036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.230058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.230081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.230102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.230126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.230148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.230175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.230205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.230228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.230248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.230268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.230292] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.230313] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.232327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.232343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.232357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.232371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.233892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.233909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.233924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.235423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.235439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.237250] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.240190] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.240217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.240234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.240256] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.240293] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.240309] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.240349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.240369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.240407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.257152] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.257172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.257192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.257212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.257229] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.257247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.257266] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.257283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.257299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.257315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.257330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.257334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.257349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.257352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.257368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.257383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.257397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.257412] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.257429] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.257448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.257469] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.257490] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.257510] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.257531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.257553] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.290391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.290415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.290451] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.309417] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.309439] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.309455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.309474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.309491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.309506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.309522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.309536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.309552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.309569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.309589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.309609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.309628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.309647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.309680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.309702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.309725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.310143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.310165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.310190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.310216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.310237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.310260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.310282] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.310304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.310325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.310346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.310365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.310371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.310390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.310395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.310417] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.310436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.310456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.310475] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.310497] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.310516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.310537] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.310556] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.310576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.310600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.310624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.310696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.310718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.310737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.310757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.310776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.310797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.310841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.310868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.310892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.310912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.310933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.310959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.310981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.312971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.312988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.313005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.313024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.314529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.314547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.314564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.316062] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.316079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.317882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.320816] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.320854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.320873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.320899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.320949] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.320976] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.321043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.321070] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.321103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.337752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.337772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.337790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.337810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.337854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.337883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.337908] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.337934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.337957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.337981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.338003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.338011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.338032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.338038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.338061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.338082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.338106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.338126] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.338152] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.338172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.338196] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.338216] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.338238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.338261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.338287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.370992] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.371016] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.371059] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.389970] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.389992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.390008] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.390027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.390044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.390060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.390075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.390090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.390106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.390123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.390140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.390156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.390170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.390184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.390211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.390229] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.390248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.390426] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.390442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.390460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.390479] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.390495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.390511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.390528] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.390543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.390558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.390572] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.390586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.390590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.390603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.390607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.390621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.390634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.390648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.390661] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.390677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.390691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.390705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.390718] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.390736] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.390757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.390777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.390872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.390894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.390918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.390938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.390960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.390982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.391007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.391032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.391057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.391077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.391098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.391124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.391145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.393141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.393157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.393171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.393186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.394689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.394704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.394718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.396213] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.396229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.398031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.400969] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.401002] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.401017] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.401037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.401081] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.401105] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.401165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.401191] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.401223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.417911] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.417931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.417951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.417972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.417989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.418007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.418026] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.418043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.418060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.418076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.418091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.418095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.418110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.418113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.418129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.418144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.418163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.418183] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.418204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.418224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.418245] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.418265] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.418285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.418306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.418328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.451140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.451166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.451210] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.469599] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.469628] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.469650] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.469675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.469698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.469719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.469739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.469764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.469790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.469818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.469901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.469939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.469971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.470004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.470061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.470100] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.470140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.470503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.470524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.470547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.470572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.470591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.470612] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.470633] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.470653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.470671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.470689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.470707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.470712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.470734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.470739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.470764] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.470787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.470811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.470867] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.470904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.470933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.470966] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.470994] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.471024] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.471059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.471094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.471194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.471224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.471251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.471279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.471305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.471334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.471366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.471397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.471428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.471454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.471482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.471512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.471542] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.473570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.473590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.473607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.473624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.475153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.475171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.475188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.476700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.476719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.478547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.481524] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.481553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.481572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.481596] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.481648] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.481677] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.481750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.481780] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.481817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.498452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.498475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.498497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.498520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.498539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.498559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.498579] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.498598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.498616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.498633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.498650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.498654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.498671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.498675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.498692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.498708] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.498725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.498747] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.498769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.498792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.498815] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.498879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.498906] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.498937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.498969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.531660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.531686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.531732] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.550580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.550602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.550621] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.550643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.550662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.550682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.550701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.550721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.550740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.550761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.550781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.550801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.550820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.550881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.550927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.550960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.550992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.551264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.551288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.551316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.551345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.551368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.551400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.551421] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.551443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.551463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.551484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.551503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.551509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.551528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.551533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.551554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.551573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.551594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.551612] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.551635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.551654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.551675] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.551694] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.551714] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.551737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.551761] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.551855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.551879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.551900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.551922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.551942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.551964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.551989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.552012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.552036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.552056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.552078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.552103] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.552125] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.554117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.554133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.554147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.554162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.555667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.555682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.555695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.557191] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.557206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.559009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.561948] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.561975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.561991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.562013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.562060] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.562086] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.562151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.562180] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.562212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.578915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.578934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.578953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.578972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.578987] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.579004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.579021] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.579037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.579052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.579067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.579080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.579084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.579098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.579101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.579115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.579129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.579143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.579156] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.579172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.579186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.579206] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.579225] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.579244] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.579264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.579285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.612119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.612145] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.612189] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.631042] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.631064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.631081] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.631100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.631117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.631132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.631147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.631162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.631178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.631195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.631211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.631226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.631241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.631255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.631287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.631310] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.631333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.631522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.631542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.631561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.631583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.631602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.631621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.631640] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.631659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.631679] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.631697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.631716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.631720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.631739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.631743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.631762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.631781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.631800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.631819] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.631881] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.631908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.631936] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.631959] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.631983] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.632012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.632040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.632120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.632142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.632167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.632189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.632211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.632233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.632264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.632287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.632310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.632329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.632349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.632372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.632394] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.634399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.634416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.634433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.634451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.635971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.635987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.636001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.637496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.637512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.639335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.642263] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.642290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.642310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.642335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.642377] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.642397] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.642440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.642469] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.642500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.659196] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.659215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.659234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.659253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.659269] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.659286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.659305] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.659324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.659343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.659362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.659381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.659385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.659404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.659408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.659427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.659446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.659465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.659484] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.659503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.659522] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.659542] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.659561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.659580] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.659600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.659620] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.692394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.692420] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.692465] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.711310] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.711332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.711351] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.711372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.711392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.711411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.711431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.711450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.711469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.711490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.711510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.711530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.711549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.711568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.711601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.711623] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.711647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.711813] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.711832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.711896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.711925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.711949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.711975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.712007] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.712029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.712050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.712070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.712090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.712096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.712116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.712122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.712143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.712162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.712182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.712203] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.712220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.712234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.712248] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.712260] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.712273] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.712289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.712305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.712354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.712369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.712382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.712396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.712409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.712423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.712438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.712453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.712467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.712480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.712492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.712508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.712522] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.714492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.714508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.714521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.714536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.716041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.716056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.716070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.717560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.717576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.719381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.722293] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.722318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.722334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.722356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.722403] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.722428] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.722494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.722521] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.722553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.739205] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.739224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.739242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.739262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.739278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.739295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.739312] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.739328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.739343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.739358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.739372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.739376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.739390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.739393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.739408] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.739421] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.739435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.739448] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.739464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.739478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.739493] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.739506] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.739520] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.739536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.739553] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.772440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.772465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.772509] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.791333] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.791355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.791371] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.791391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.791407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.791423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.791438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.791452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.791468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.791487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.791507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.791528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.791546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.791565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.791598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.791621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.791644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.791842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.791893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.791918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.791944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.791965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.791988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.792011] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.792032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.792053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.792073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.792092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.792099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.792119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.792125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.792145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.792165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.792185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.792204] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.792228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.792249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.792270] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.792291] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.792311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.792335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.792360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.792433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.792447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.792461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.792474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.792486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.792500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.792515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.792530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.792544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.792557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.792569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.792586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.792600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.794579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.794597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.794614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.794632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.796141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.796158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.796172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.797664] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.797680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.799485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.802408] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.802434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.802453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.802479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.802520] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.802540] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.802586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.802609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.802641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.819309] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.819328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.819347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.819366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.819382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.819399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.819416] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.819432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.819448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.819462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.819476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.819480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.819494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.819498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.819512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.819526] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.819539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.819553] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.819569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.819583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.819598] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.819611] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.819625] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.819641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.819659] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.852544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.852567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.852601] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.871478] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.871500] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.871517] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.871537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.871554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.871570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.871589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.871609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.871629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.871650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.871671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.871692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.871712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.871731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.871765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.871788] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.871812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.872054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.872074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.872096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.872119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.872138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.872159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.872180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.872201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.872222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.872242] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.872262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.872266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.872287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.872291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.872312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.872331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.872352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.872372] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.872392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.872412] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.872433] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.872453] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.872474] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.872496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.872517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.872575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.872596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.872614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.872630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.872651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.872671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.872693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.872715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.872736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.872756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.872776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.872796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.872816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.874824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.874841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.874882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.874909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.876417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.876432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.876445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.877954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.877972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.879807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.882740] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.882767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.882786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.882812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.882894] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.882929] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.882990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.883015] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.883045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.899691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.899711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.899731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.899752] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.899769] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.899787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.899806] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.899823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.899840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.899897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.899922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.899929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.899953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.899961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.899986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.900010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.900035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.900059] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.900086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.900110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.900135] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.900159] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.900183] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.900209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.900236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.932917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.932941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.932975] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.951834] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.951900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.951930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.951959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.951985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.952010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.952034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.952058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.952083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.952110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.952137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.952162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.952186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.952209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.952250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.952269] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.952288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.952468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.952484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.952503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.952525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.952544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.952564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.952590] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.952606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.952621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.952635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.952648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.952651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.952664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.952667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.952680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.952693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.952705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.952717] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.952732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.952745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.952758] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.952770] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.952782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.952797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.952813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.952890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.952916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.952940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.952962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.952985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.953008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.953033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.953057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.953081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.953102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.953124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.953150] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.953174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.955168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.955184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.955198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.955213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.956717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.956732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.956745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.958240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.958256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.960059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.962999] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.963026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.963043] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.963065] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.963103] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.963119] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.963162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.963182] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.963214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.979938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.979959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.979978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.979999] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.980019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.980040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.980061] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.980081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.980102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.980122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.980142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.980146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.980166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.980169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.980190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.980210] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.980230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.980250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.980271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.980290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.980311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  313.980332] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.980352] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.980373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.980394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.013168] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.013193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.013227] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.032079] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.032101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.032117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.032136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.032153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.032168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.032183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.032198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.032214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.032231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.032247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.032262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.032277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.032291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.032318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.032336] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.032354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.032526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.032542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.032560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.032579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.032594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.032610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.032627] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.032642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.032657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.032676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.032695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.032699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.032718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.032721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.032741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.032760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.032779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.032798] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.032817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.032836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.032856] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.032920] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.032950] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.032980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.033009] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.033091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.033117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.033143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.033167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.033191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.033216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.033244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.033271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.033296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.033319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.033342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.033370] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.033395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.035409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.035426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.035441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.035456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.036970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.036985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.036999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.038494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.038509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.040317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.043265] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.043293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.043312] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.043338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.043387] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.043414] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.043477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.043505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.043538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.060213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.060233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.060253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.060274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.060290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.060309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.060327] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.060344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.060361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.060377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.060396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.060401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.060421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.060425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.060445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.060466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.060486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.060506] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.060526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.060546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.060567] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.060587] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.060607] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.060629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.060650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.093460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.093485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.093530] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.112427] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.112449] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.112468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.112490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.112509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.112529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.112548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.112567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.112586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.112607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.112627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.112647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.112666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.112685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.112718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.112741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.112764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.113044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.113073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.113101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.113125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.113141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.113158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.113176] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.113192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.113208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.113227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.113249] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.113253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.113267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.113270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.113284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.113297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.113311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.113323] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.113339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.113352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.113366] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.113378] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.113391] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.113407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.113424] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.113465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.113479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.113493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.113506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.113518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.113532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.113547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.113561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.113576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.113588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.113601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.113617] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.113631] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.115613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.115629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.115644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.115663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.117175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.117190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.117206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.119764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.119782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.121594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.124518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.124543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.124560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.124581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.124630] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.124655] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.124717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.124747] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.124779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.141421] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.141441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.141459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.141482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.141501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.141521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.141540] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.141559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.141578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.141597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.141616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.141620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.141638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.141642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.141661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.141680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.141699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.141718] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.141737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.141756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.141776] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.141795] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.141814] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.141834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.141854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.174685] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.174709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.174755] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.193612] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.193634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.193650] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.193670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.193686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.193702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.193717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.193732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.193755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.193776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.193796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.193817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.193836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.193854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.193937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.193970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.194001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.194294] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.194317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.194342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.194369] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.194391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.194415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.194439] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.194461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.194484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.194505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.194526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.194532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.194552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.194558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.194579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.194600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.194621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.194639] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.194662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.194683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.194706] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.194725] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.194746] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.194769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.194794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.194870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.194914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.194938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.194961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.194984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.195007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.195033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.195057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.195081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.195103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.195125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.195151] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.195174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.197166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.197182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.197197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.197211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.198715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.198730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.198743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.200238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.200254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.202057] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.204996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.205022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.205039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.205061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.205099] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.205115] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.205158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.205178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.205210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.221981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.222000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.222019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.222038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.222054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.222071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.222088] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.222104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.222119] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.222133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.222147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.222151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.222165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.222169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.222183] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.222197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.222211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.222224] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.222240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.222254] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.222269] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.222282] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.222295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.222311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.222328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.255165] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.255190] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.255224] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.273744] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.273776] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.273800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.273828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.273853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.273877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.273958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.273993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.274032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.274074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.274113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.274150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.274183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.274218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.274282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.274324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.274367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.274660] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.274680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.274701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.274724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.274743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.274762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.274782] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.274800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.274818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.274835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.274852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.274856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.274907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.274918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.274946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.274972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.275001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.275027] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.275058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.275084] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.275114] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.275140] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.275168] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.275200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.275233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.275331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.275357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.275385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.275410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.275437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.275463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.275493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.275523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.275553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.275578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.275604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.275633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.275663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.277701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.277722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.277740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.277763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.279317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.279339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.279358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.280906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.280930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.282767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.285778] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.285810] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.285830] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.285856] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.285965] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.285997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.286073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.286111] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.286172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.302745] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.302767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.302788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.302811] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.302828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.302848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.302867] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.302934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.302964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.302993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.303022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.303031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.303058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.303066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.303095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.303123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.303150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.303177] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.303208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.303236] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.303264] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.303290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.303317] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.303345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.303376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.335935] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.335963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.336003] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.354888] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.354927] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.354947] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.354969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.354988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.355008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.355027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.355046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.355065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.355086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.355106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.355126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.355145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.355164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.355197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.355219] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.355243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.355429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.355449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.355468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.355490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.355509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.355529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.355548] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.355573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.355590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.355604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.355618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.355621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.355634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.355637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.355650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.355663] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.355676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.355688] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.355703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.355716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.355729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.355741] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.355753] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.355769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.355785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.355833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.355847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.355860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.355904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.355926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.355950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.355976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.356001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.356025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.356046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.356069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.356094] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.356117] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.358111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.358129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.358146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.358164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.359669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.359685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.359700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.361198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.361215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.363021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.365960] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.365987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.366004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.366026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.366063] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.366080] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.366122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.366143] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.366175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.382948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.382967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.382986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.383005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.383020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.383037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.383054] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.383069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.383085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.383099] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.383113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.383117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.383131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.383134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.383149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.383163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.383176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.383190] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.383206] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.383220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.383235] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.383248] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.383266] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.383287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.383307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.416130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.416154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.416190] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.435087] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.435109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.435125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.435144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.435160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.435176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.435190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.435205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.435221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.435238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.435254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.435270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.435284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.435298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.435326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.435343] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.435362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.435524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.435543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.435563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.435585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.435604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.435623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.435642] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.435661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.435678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.435697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.435716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.435720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.435738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.435742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.435761] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.435781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.435799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.435818] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.435837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.435856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.435875] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.435940] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.435970] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.435999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.436029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.436109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.436135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.436160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.436184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.436208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.436232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.436260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.436286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.436318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.436339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.436358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.436382] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.436405] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.438414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.438430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.438443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.438458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.441061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.441080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.441096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.442592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.442609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.444416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.447351] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.447378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.447395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.447417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.447455] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.447471] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.447520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.447539] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.447569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.464321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.464342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.464362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.464384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.464403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.464422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.464441] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.464460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.464480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.464499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.464517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.464521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.464540] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.464544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.464563] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.464582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.464601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.464620] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.464639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.464658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.464677] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.464696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.464715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.464735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.464755] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.497525] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.497551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.497588] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.516441] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.516463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.516479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.516499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.516515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.516531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.516546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.516561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.516577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.516594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.516610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.516626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.516640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.516654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.516681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.516699] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.516717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.516944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.516971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.517001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.517032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.517057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.517085] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.517111] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.517138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.517163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.517188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.517211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.517218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.517240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.517247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.517278] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.517299] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.517321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.517341] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.517365] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.517385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.517408] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.517429] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.517447] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.517471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.517496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.517569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.517592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.517614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.517633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.517654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.517677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.517701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.517724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.517748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.517769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.517788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.517812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.517835] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.519840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.519856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.519870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.519917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.521428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.521446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.521463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.523025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.523042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.524848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.527767] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.527793] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.527809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.527830] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.527867] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.527884] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.528077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.528099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.528131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.544697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.544716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.544734] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.544754] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.544769] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.544789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.544808] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.544828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.544847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.544866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.544884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.544927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.544956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.544963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.544991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.545017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.545042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.545068] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.545095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.545121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.545147] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.545171] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.545192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.545219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.545248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.577921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.577947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.577983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.596837] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.596859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.596876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.596941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.596970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.596997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.597023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.597047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.597073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.597101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.597128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.597153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.597177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.597200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.597251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.597278] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.597307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.597491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.597506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.597523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.597542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.597560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.597578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.597597] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.597615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.597633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.597650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.597668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.597672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.597689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.597693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.597711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.597729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.597747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.597765] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.597782] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.597800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.597819] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.597836] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.597854] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.597873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.597892] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.597992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.598019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.598044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.598068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.598092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.598116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.598143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.598169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.598194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.598216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.598238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.598273] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.598296] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.600289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.600305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.600319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.600334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.601840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.601855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.601868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.603396] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.603412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.605244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.608179] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.608205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.608221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.608242] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.608280] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.608296] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.608339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.608360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.608391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.625148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.625167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.625186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.625207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.625225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.625245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.625265] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.625284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.625303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.625322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.625340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.625344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.625363] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.625366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.625385] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.625404] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.625423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.625442] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.625461] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.625480] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.625500] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.625518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.625537] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.625557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.625578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.658353] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.658379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.658416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.676982] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.677003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.677020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.677039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.677058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.677077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.677097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.677116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.677135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.677156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.677176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.677196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.677215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.677234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.677267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.677289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.677312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.677502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.677521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.677541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.677563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.677582] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.677601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.677620] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.677639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.677656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.677675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.677693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.677697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.677716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.677720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.677739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.677758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.677777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.677796] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.677815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.677834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.677853] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.677872] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.677891] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.677957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.677990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.678074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.678101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.678127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.678152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.678178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.678203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.678240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.678264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.678287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.678310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.678332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.678358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.678381] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.680374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.680390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.680405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.680423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.681966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.681982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.681996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.683489] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.683505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.685312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.688258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.688285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.688302] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.688324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.688363] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.688379] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.688429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.688448] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.688477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.705175] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.705195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.705216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.705240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.705260] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.705280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.705301] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.705321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.705342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.705361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.705381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.705385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.705405] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.705409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.705429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.705450] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.705470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.705490] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.705510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.705530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.705551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.705571] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.705591] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.705613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.705634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.738421] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.738446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.738481] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.757394] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.757416] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.757435] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.757456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.757476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.757495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.757514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.757534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.757553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.757573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.757594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.757614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.757633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.757652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.757684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.757707] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.757730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.757962] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.757991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.758021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.758052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.758077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.758105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.758139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.758163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.758187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.758210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.758232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.758238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.758258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.758265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.758287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.758309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.758331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.758352] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.758376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.758397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.758420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.758441] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.758460] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.758484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.758509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.758581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.758604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.758627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.758647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.758668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.758690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.758715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.758738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.758762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.758784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.758803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.758828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.758851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.760859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.760875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.760890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.760938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.762448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.762464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.762477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.763989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.764008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.766940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.769869] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.769895] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.769949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.769987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.770046] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.770069] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.770132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.770165] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.770210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.786805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.786824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.786843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.786862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.786878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.786895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.786955] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.786980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.787006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.787029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.787053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.787060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.787084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.787090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.787113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.787134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.787158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.787179] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.787204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.787225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.787250] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.787271] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.787292] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.787318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.787343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.820032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.820056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.820092] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.838964] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.838988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.839007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.839029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.839049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.839068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.839087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.839107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.839126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.839147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.839167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.839187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.839206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.839224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.839257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.839279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.839302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.839476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.839496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.839516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.839537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.839556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.839576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.839595] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.839614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.839633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.839652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.839670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.839674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.839693] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.839697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.839716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.839735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.839754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.839773] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.839792] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.839811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.839830] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.839849] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.839868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.839888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.839955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.840034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.840059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.840084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.840107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.840130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.840154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.840180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.840205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.840460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.840483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.840506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.840532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.840555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.842549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.842566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.842583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.842601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.844110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.844126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.844140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.845632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.845648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.847454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.850376] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.850402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.850418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.850440] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.850478] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.850494] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.850539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.850563] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.850598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.867279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.867299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.867319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.867340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.867357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.867375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.867392] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.867410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.867426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.867442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.867457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.867462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.867477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.867480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.867496] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.867511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.867526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.867541] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.867559] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.867574] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.867589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.867609] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.867630] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.867651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.867673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.900513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.900539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.900576] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.919438] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.919461] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.919481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.919503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.919522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.919541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.919561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.919580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.919599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.919620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.919640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.919660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.919679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.919698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.919731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.919753] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.919777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.920033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.920058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.920084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.920111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.920134] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.920159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.920183] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.920207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.920230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.920251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.920273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.920278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.920299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.920304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.920326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.920347] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.920369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.920390] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.920414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.920435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.920458] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.920480] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.920501] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.920525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.920550] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.920623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.920646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.920668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.920690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.920712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.920733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.920757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.920781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.920804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.920825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.920846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.920871] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.920894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.922898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.922925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.922940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.922954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.924469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.924485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.924498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.926009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.926027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.927864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.930800] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.930827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.930846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.930872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.930913] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.930977] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.931040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.931072] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.931124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.947749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.947769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.947789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.947810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.947827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.947846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.947864] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.947881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.947898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.947956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.947981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.947989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.948013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.948019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.948044] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.948068] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.948093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.948117] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.948144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.948168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.948194] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  314.948218] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.948242] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.948269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.948296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.981006] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.981032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.981069] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.999909] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.999949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.999965] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.999985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.000001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.000017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.000032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.000046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.000062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.000079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.000095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.000111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.000125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.000139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.000167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.000184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.000203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.000358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.000375] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.000392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.000411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.000426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.000443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.000459] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.000474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.000489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.000503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.000517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.000520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.000534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.000537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.000551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.000565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.000579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.000592] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.000608] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.000622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.000636] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.000649] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.000662] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.000678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.000696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.000754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.000768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.000781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.000794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.000812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.000829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.000848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.000867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.000886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.000903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.000947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.000976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.000998] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.002991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.003008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.003022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.003037] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.004543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.004558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.004572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.006069] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.006085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.007890] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.010825] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.010852] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.010868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.010890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.010975] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.010997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.011057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.011086] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.011132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.027793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.027813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.027832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.027852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.027867] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.027884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.027901] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.027956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.027983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.028008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.028031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.028039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.028062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.028068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.028093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.028115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.028358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.028380] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.028406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.028427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.028451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.028473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.028495] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.028520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.028547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.060988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.061013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.061050] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.079921] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.079960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.079977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.079996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.080013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.080029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.080044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.080062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.080082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.080102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.080123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.080143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.080162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.080181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.080214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.080236] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.080259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.080448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.080468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.080488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.080510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.080529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.080555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.080573] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.080588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.080602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.080619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.080636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.080640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.080657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.080660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.080678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.080696] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.080713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.080730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.080748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.080765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.080783] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.080800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.080818] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.080836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.080855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.080906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.080950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.080975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.080999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.081020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.081044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.081070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.081095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.081120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.081140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.081162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.081188] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.081210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.083205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.083221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.083236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.083251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.084755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.084773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.084790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.086288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.086305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.088111] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.091046] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.091073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.091090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.091112] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.091160] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.091185] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.091251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.091279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.091311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.108005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.108025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.108046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.108069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.108089] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.108110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.108130] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.108150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.108171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.108191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.108210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.108215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.108235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.108239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.108259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.108280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.108300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.108320] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.108340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.108360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.108381] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.108402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.108422] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.108443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.108464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.141220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.141245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.141288] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.160138] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.160160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.160176] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.160196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.160212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.160231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.160251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.160270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.160289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.160310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.160330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.160351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.160369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.160388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.160421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.160443] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.160467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.160646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.160665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.160685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.160707] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.160726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.160745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.160765] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.160784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.160800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.160819] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.160838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.160842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.160860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.160864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.160884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.160903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.160922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.160983] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.161010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.161037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.161065] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.161088] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.161113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.161141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.161169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.161250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.161273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.161297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.161320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.161343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.161365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.161398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.161421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.161444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.161463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.161483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.161507] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.161528] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.163522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.163538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.163552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.163567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.165073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.165088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.165102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.166596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.166612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.168433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.171370] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.171395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.171412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.171434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.171481] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.171506] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.171578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.171603] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.171636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.188315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.188335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.188355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.188376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.188393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.188411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.188431] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.188452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.188473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.188493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.188513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.188517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.188537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.188540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.188561] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.188582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.188602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.188622] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.188642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.188662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.188683] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.188703] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.188723] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.188745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.188766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.221542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.221566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.221610] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.240486] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.240507] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.240524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.240543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.240560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.240575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.240594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.240613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.240632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.240653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.240674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.240694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.240713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.240732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.240764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.240787] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.240810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.241079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.241104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.241131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.241159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.241181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.241213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.241235] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.241256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.241277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.241298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.241317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.241323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.241343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.241348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.241370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.241389] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.241409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.241428] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.241450] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.241469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.241491] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.241509] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.241530] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.241551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.241575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.241647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.241669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.241688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.241709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.241728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.241749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.241773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.241796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.241818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.241837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.241857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.241879] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.241901] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.243908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.243926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.243974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.244002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.245585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.245601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.245615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.247111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.247127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.248950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.251870] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.251896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.251912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.251974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.252031] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.252054] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.252120] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.252151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.252200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.268763] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.268785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.268807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.268830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.268848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.268869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.268890] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.268910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.268930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.268992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.269017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.269024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.269047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.269053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.269078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.269215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.269230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.269245] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.269262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.269277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.269293] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.269307] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.269321] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.269338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.269357] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.302009] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.302033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.302069] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.320924] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.320963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.320979] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.320999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.321015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.321031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.321046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.321061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.321077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.321094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.321110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.321126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.321141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.321155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.321183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.321205] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.321228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.321412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.321432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.321452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.321474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.321493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.321512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.321532] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.321550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.321570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.321589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.321607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.321611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.321630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.321633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.321653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.321672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.321690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.321709] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.321728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.321746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.321766] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.321785] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.321804] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.321824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.321845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.321900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.321920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.321971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.321997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.322026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.322048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.322072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.322095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.322118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.322138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.322158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.322182] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.322203] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.324191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.324207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.324221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.324235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.325739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.325754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.325768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.327264] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.327279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.329085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.332023] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.332051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.332067] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.332089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.332127] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.332144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.332190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.332221] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.332252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.348985] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.349006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.349028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.349051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.349069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.349090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.349110] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.349130] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.349151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.349171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.349191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.349195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.349215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.349219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.349240] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.349260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.349280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.349300] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.349320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.349340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.349361] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.349382] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.349402] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.349423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.349445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.382194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.382220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.382256] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.401115] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.401136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.401153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.401172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.401191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.401211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.401230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.401249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.401268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.401289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.401309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.401330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.401349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.401367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.401400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.401422] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.401446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.401629] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.401649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.401668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.401690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.401707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.401726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.401745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.401765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.401791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.401808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.401823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.401827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.401841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.401844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.401858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.401871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.401884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.401900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.401918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.401935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.401991] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.402013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.402034] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.402057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.402081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.402156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.402179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.402200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.402222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.402244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.402266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.402291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.402315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.402338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.402360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.402381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.402406] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.402429] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.404410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.404426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.404440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.404455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.405978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.405993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.406007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.407499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.407515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.409325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.412273] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.412300] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.412316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.412338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.412376] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.412393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.412437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.412458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.412492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.429208] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.429229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.429249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.429271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.429287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.429307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.429326] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.429345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.429365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.429383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.429402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.429406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.429424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.429428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.429447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.429466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.429485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.429504] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.429523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.429541] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.429561] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.429580] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.429599] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.429618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.429639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.462434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.462457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.462491] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.481442] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.481473] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.481500] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.481529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.481555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.481581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.481607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.481633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.481658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.481687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.481714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.481742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.481767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.481792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.481836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.481866] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.481897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.482322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.482699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.482722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.482749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.482770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.482790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.482811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.482834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.482856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.482876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.482896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.482914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.482932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.483028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.483276] [drm:drm_mode_addfb2] [FB:76]
>[  315.483307] [drm:drm_mode_addfb2] [FB:78]
>[  315.506455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.506542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.506599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  315.506653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.506662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.506715] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.506733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.506751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.506771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.506786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.506804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.506820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.506836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.506852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.506866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.506880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.506884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.506898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.506901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.506915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.506929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.506943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.506992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.507017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.507038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.507060] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  315.507083] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.507105] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.507130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.507157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.509779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.509795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.509810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.509824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.509837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.509851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.509867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.509882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.509897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.509910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.509923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.509939] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.509992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.511998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.512015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.512030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.512045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.513552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.513568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.513582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.515079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.515095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.516902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.519836] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.519865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.519881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.519904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.536652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.536676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.536710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.570149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.570169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.570187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.570207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.570223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.570241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.570258] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.570274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.570290] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.570304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.570318] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.570322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.570336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.570339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.570353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.570367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.570381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.570395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.570411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.570425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.570439] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.570453] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.570466] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.570483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.570503] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.586740] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.586763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.586798] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.605168] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.605187] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.605207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.605224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.605240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.605256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.605270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.605286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.605303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.605319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.605335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.605350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.605364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.605392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.605410] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.605428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.605603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.605620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.605638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.605657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.605672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.605689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.605705] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.605721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.605736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.605751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.605765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.605768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.605782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.605785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.605800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.605818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.605838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.605857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.605876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.605895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.605914] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.605934] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.605953] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.606018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.606046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.606121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.606142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.606163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.606183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.606205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.606227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.606251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.606276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.606300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.606321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.606342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.606367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.606390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.608384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.608400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.608414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.608429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.609949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.609981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.609996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.611500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.611516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.613347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.616288] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.616312] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.616328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.616348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.616402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.616422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.616453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.633235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.633256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.633276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.633297] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.633316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.633337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.633358] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.633378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.633399] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.633419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.633439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.633443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.633463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.633467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.633488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.633508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.633528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.633548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.633568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.633588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.633609] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.633629] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.633650] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.633671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.633692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.649860] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.649884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.649920] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.668807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.668826] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.668846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.668863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.668878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.668893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.668908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.668924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.668941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.669002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.669029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.669051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.669074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.669118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.669148] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.669178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.669345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.669365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.669386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.669408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.669427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.669447] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.669467] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.669487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.669506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.669526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.669552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.669557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.669573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.669577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.669592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.669607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.669620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.669634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.669650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.669664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.669678] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.669692] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.669705] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.669721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.669737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.669786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.669801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.669814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.669827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.669845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.669863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.669882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.669902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.669921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.669939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.669957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.669999] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.670023] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.672014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.672030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.672044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.672059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.673569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.673585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.673599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.675098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.675114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.676921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.679854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.679881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.679898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.679920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.680021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.680055] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.680106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.696795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.696814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.696833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.696852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.696868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.696885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.696902] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.696918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.696934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.696948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.697006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.697015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.697040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.697047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.697072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.697097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.697122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.697146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.697173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.697198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.697224] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.697409] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.697433] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.697460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.697487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.713434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.713458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.713495] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.732362] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.732381] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.732401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.732418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.732434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.732449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.732464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.732482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.732503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.732524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.732544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.732563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.732582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.732615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.732637] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.732660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.732847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.732866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.732886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.732908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.732927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.732946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.733017] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.733045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.733069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.733093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.733115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.733122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.733144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.733150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.733172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.733194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.733216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.733238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.733263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.733284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.733308] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.733330] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.733352] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.733376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.733402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.733478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.733501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.733523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.733544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.733565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.733588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.733612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.733635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.733659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.733680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.733701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.733726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.733749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.735742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.735758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.735773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.735787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.737295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.737310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.737324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.738816] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.738831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.740637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.743572] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.743598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.743615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.743638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.743693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.743715] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.743747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.760523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.760544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.760564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.760584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.760601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.760620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.760638] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.760655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.760671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.760687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.760702] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.760706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.760721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.760725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.760740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.760758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.760779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.760799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.760819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.760839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.760860] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.760881] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.760901] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.760922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.760944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.777119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.777144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.777181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.796050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.796069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.796089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.796106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.796122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.796137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.796152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.796168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.796185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.796201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.796221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.796241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.796260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.796292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.796315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.796338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.796509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.796529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.796549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.796570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.796589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.796609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.796628] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.796647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.796666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.796684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.796703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.796707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.796725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.796729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.796748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.796767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.796786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.796805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.796824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.796844] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.796872] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.796892] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.796907] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.796925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.796944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.797057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.797081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.797104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.797127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.797148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.797172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.797197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.797223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.797248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.797270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.797292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.797320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.797339] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.799322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.799339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.799353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.799368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.800871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.800886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.800900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.802397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.802412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.804224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.807167] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.807194] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.807211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.807233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.807287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.807309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.807341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.824124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.824144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.824164] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.824186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.824202] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.824221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.824239] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.824256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.824273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.824289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.824304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.824308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.824323] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.824327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.824347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.824367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.824388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.824408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.824428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.824448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.824469] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.824489] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.824510] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.824531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.824553] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.840707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.840731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.840767] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.859619] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.859638] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.859658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.859675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.859691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.859706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.859725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.859744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.859765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.859785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.859806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.859824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.859843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.859876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.859898] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.859922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.860234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.860259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.860287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.860316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.860339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.860364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.860387] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.860412] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.860434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.860457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.860478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.860484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.860506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.860512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.860536] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.860557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.860579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.860600] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.860625] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.860645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.860669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.860690] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.860712] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.860735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.860761] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.860844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.860873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.860894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.860913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.860934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.860954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.860995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.861019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.861043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.861062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.861082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.861104] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.861127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.863116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.863134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.863151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.863169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.864675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.864691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.864705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.866202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.866218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.868022] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.870954] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.870991] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.871008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.871030] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.871110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.871141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.871187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.887893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.887913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.887934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.887958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.888020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.888049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.888076] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.888102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.888127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.888143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.888157] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.888162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.888176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.888179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.888194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.888208] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.888223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.888237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.888254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.888268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.888284] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.888297] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.888312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.888328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.888347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.904534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.904558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.904603] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.923470] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.923489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.923510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.923527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.923543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.923557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.923572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.923588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.923605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.923621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.923636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.923650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.923664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.923691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.923709] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.923727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.923899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.923915] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.923932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.923951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.923966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.924016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.924041] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.924065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.924088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.924111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.924132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.924139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.924160] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.924166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.924188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.924209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.924230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.924251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.924275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.924296] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.924327] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.924346] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.924365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.924389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.924414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.924486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.924508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.924530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.924551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.924573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.924595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.924620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.924643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.924664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.924678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.924691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.924707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.924721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.926696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.926712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.926728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.926746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.928256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.928271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.928285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.929777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.929793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.931600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.934522] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.934554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.934569] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.934589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.934660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.934691] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.934736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.951431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.951451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.951471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.951492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.951509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.951527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.951545] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.951562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.951579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.951595] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.951610] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.951614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.951629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.951633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.951648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.951663] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.951678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.951693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.951710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.951725] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.951741] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.951756] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.951770] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.951791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.951813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.968076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.968100] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.968145] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.987007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.987026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.987046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.987063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.987078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.987093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.987107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.987123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.987140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.987156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.987172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.987186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.987200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.987227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.987245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.987263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.987442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.987459] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.987477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.987496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.987512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.987528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.987545] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.987560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.987576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.987590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.987604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.987608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.987621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.987625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.987639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.987653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.987667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.987680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.987696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.987710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.987724] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  315.987738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.987752] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.987768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.987793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.987840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.987854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.987867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.987880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.987893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.987906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.987921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.987935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.987948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.987961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.988013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.988037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.988058] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.990048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.990064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.990079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.990093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.991599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.991615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.991630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.993131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.993148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.994953] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.997885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.997913] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.997932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.997957] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.998078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.998110] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.998157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.014815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.014835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.014856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.014880] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.014898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.014919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.014940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.014960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.015020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.015047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.015072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.015080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.015104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.015111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.015136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.015158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.015182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.015203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.015436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.015462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.015488] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.015510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.015532] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.015558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.015585] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.031435] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.031459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.031495] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.050368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.050389] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.050411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.050430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.050450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.050469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.050488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.050507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.050528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.050548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.050569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.050587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.050606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.050639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.050661] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.050684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.050871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.050891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.050911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.050932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.050949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.050969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.051027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.051055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.051081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.051104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.051129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.051136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.051159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.051165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.051190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.051212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.051236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.051257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.051283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.051305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.051338] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.051358] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.051379] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.051404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.051430] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.051748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.051770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.051792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.051811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.051832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.051853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.051876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.051900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.051923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.051942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.051963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.052004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.052028] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.054148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.054164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.054181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.054199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.055705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.055721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.055735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.057231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.057247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.059050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.061952] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.061978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.062030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.062066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.062140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.062161] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.062191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.078883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.078904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.078924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.078945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.078962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.078981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.079040] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.079065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.079091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.079114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.079138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.079145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.079169] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.079175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.079199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.079220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.079242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.079263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.079290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.079311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.079335] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.079356] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.079378] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.079404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.079431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.095512] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.095536] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.095572] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.114454] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.114473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.114493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.114510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.114525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.114540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.114555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.114571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.114588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.114604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.114619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.114634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.114648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.114675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.114696] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.114720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.114893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.114913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.114933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.114954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.114971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.115030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.115056] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.115080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.115104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.115126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.115148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.115154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.115175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.115181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.115203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.115225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.115246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.115267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.115292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.115313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.115336] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.115359] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.115381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.115405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.115431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.115495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.115511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.115530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.115550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.115570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.115589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.115610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.115631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.115652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.115672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.115691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.115712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.115731] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.117723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.117740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.117754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.117769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.119279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.119295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.119308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.120801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.120817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.122622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.125541] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.125567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.125583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.125605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.125661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.125682] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.125714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.142444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.142466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.142488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.142511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.142531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.142552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.142572] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.142593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.142613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.142633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.142653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.142657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.142677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.142681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.142701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.142722] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.142742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.142762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.142783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.142802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.142823] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.142844] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.142864] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.142885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.142907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.159085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.159110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.159146] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.178026] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.178044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.178064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.178081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.178097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.178111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.178126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.178142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.178159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.178175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.178190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.178205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.178218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.178245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.178263] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.178282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.178457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.178473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.178491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.178510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.178525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.178541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.178558] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.178574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.178589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.178603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.178617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.178621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.178634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.178638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.178652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.178666] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.178680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.178693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.178709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.178723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.178738] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.178752] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.178766] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.178782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.178802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.178858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.178877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.178897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.178916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.178935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.178954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.178975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.179029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.179058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.179081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.179103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.179130] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.179153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.181153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.181169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.181184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.181202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.182709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.182727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.182744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.184242] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.184258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.186064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.189012] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.189038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.189055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.189077] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.189133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.189155] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.189187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.205948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.205968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.205988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.206053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.206074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.206092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.206110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.206129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.206149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.206168] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.206186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.206191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.206210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.206214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.206235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.206254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.206274] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.206293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.206313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.206331] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.206352] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.206372] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.206391] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.206411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.206432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.222575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.222600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.222636] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.241489] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.241510] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.241532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.241551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.241570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.241590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.241609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.241628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.241648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.241669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.241689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.241708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.241726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.241759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.241782] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.241805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.241970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.241989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.242049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.242079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.242102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.242127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.242152] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.242176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.242199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.242221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.242242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.242249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.242270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.242276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.242300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.242323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.242345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.242366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.242393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.242416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.242440] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.242464] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.242487] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.242513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.242540] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.242621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.242636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.242649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.242663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.242676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.242689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.242705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.242719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.242733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.242746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.242759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.242775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.242790] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.244761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.244777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.244791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.244805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.246313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.246328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.246342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.247832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.247850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.249655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.252576] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.252601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.252617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.252639] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.252695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.252716] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.252755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.269488] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.269510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.269532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.269555] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.269575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.269596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.269616] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.269636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.269657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.269677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.269697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.269701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.269721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.269725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.269745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.269765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.269785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.269805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.269826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.269846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.269867] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.269887] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.269907] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.269928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.269950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.286117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.286142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.286178] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.305033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.305052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.305072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.305089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.305107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.305127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.305146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.305165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.305186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.305206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.305227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.305245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.305264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.305297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.305319] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.305342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.305530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.305550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.305569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.305591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.305610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.305629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.305648] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.305667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.305687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.305706] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.305724] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.305728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.305747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.305750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.305770] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.305789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.305808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.305826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.305845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.305864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.305884] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.305909] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.305924] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.305941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.305958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.306048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.306070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.306091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.306112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.306132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.306153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.306177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.306199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.306222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.306242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.306261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.306285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.306306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.308295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.308311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.308325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.308340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.309844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.309859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.309872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.311368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.311384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.313187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.316133] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.316159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.316174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.316195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.316249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.316269] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.316299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.333080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.333100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.333120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.333141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.333157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.333176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.333193] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.333210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.333227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.333242] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.333257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.333262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.333276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.333280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.333295] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.333310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.333325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.333339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.333357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.333371] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.333392] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.333412] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.333433] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.333454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.333476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.349699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.349725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.349762] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.368627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.368646] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.368666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.368682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.368698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.368713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.368728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.368743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.368761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.368777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.368792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.368806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.368820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.368848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.368866] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.368884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.369125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.369148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.369175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.369205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.369227] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.369253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.369276] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.369301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.369330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.369351] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.369370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.369376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.369395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.369401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.369422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.369441] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.369461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.369480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.369502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.369521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.369543] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.369562] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.369582] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.369603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.369628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.369701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.369724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.369743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.369763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.369782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.369803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.369826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.369849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.369872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.369891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.369911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.369933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.369955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.371967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.371985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.372033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.372052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.373558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.373573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.373586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.375086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.375101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.376904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.379838] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.379865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.379881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.379903] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.379960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.379982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.380063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.396787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.396808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.396828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.396849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.396865] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.396883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.396902] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.396922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.396942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.396963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.396983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.396987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.397047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.397056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.397084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.397110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.397137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.397162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.397190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.397214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.397241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.397265] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.397287] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.397313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.397534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.413387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.413413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.413459] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.432329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.432348] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.432368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.432385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.432401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.432416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.432431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.432447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.432467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.432488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.432508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.432527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.432546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.432579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.432601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.432625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.432814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.432834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.432854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.432875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.432894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.432914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.432933] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.432952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.432971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.432990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.433052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.433060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.433086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.433094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.433120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.433143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.433168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.433190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.433216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.433238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.433264] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.433286] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.433310] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.433337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.433366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.433446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.433471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.433492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.433516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.433537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.433560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.433591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.433614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.433637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.433655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.433676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.433700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.433721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.435727] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.435744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.435758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.435773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.437279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.437294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.437309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.438803] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.438819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.440625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.443558] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.443585] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.443601] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.443623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.443680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.443702] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.443734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.460504] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.460523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.460541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.460561] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.460576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.460594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.460611] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.460627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.460643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.460658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.460672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.460676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.460690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.460693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.460708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.460721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.460735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.460749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.460765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.460779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.460793] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.460807] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.460820] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.460837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.460855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.477101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.477124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.477157] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.496003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.496039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.496059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.496077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.496092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.496108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.496123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.496138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.496155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.496172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.496188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.496202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.496216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.496243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.496261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.496280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.496454] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.496470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.496487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.496507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.496522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.496538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.496555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.496570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.496590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.496608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.496627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.496631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.496650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.496654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.496674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.496693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.496712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.496731] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.496750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.496769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.496788] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.496807] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.496826] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.496846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.496867] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.496922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.496942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.496961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.496981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.497000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.497063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.497087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.497112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.497135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.497155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.497174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.497198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.497220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.499209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.499225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.499239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.499257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.500760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.500776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.500793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.502289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.502306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.504109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.507048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.507075] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.507091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.507113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.507170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.507191] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.507231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.524031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.524050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.524069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.524090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.524109] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.524129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.524148] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.524167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.524186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.524205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.524223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.524228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.524246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.524250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.524269] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.524289] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.524308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.524327] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.524345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.524364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.524384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.524403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.524422] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.524442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.524462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.540584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.540607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.540641] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.558773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.558792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.558812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.558829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.558848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.558867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.558887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.558906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.558926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.558947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.558967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.558986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.559005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.559081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.559114] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.559147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.559530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.559554] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.559571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.559589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.559603] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.559618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.559636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.559653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.559672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.559689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.559706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.559710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.559727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.559730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.559748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.559765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.559782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.559799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.559817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.559834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.559851] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.559869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.559886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.559904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.559923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.559974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.559992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.560010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.560053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.560080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.560102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.560128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.560153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.560177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.560197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.560219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.560246] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.560268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.562484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.562500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.562514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.562529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.564066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.564082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.564096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.565606] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.565624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.567440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.570381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.570408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.570424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.570446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.570503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.570524] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.570556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.587331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.587350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.587368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.587388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.587403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.587422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.587442] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.587461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.587481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.587500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.587519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.587523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.587541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.587545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.587564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.587583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.587602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.587621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.587640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.587659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.587678] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.587697] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.587716] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.587736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.587757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.603923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.603947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.603991] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.622989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.623009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.623078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.623105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.623132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.623156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.623177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.623197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.623219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.623240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.623262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.623281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.623300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.623334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.623356] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.623380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.623566] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.623586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.623606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.623628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.623647] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.623666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.623686] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.623705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.623724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.623743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.623761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.623765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.623784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.623787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.623806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.623825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.623844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.623863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.623882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.623901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.623920] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.623939] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.623958] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.623978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.623999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.624108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.624131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.624153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.624174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.624195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.624216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.624241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.624265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.624288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.624308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.624328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.624353] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.624377] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.626368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.626385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.626402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.626420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.627924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.627940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.627955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.629453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.629468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.631272] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.634200] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.634226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.634242] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.634264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.634327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.634347] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.634377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.651136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.651154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.651173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.651193] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.651208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.651225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.651242] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.651258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.651274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.651288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.651302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.651306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.651320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.651324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.651339] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.651358] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.651377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.651396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.651415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.651434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.651454] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.651473] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.651492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.651512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.651532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.667705] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.667729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.667774] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.686650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.686669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.686689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.686705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.686720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.686739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.686758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.686777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.686798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.686819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.686839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.686858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.686877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.686910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.686932] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.686955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.687182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.687200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.687219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.687241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.687261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.687281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.687301] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.687320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.687339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.687359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.687379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.687384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.687402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.687406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.687426] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.687445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.687465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.687485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.687512] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.687530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.687546] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.687561] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.687575] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.687591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.687608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.687659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.687677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.687695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.687713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.687731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.687749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.687768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.687786] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.687806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.687823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.687841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.687859] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.687877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.689851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.689867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.689881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.689896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.691403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.691419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.691432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.692925] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.692941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.694746] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.697668] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.697693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.697709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.697739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.697791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.697810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.697840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.714576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.714596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.714616] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.714637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.714654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.714672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.714690] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.714710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.714731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.714751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.714771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.714775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.714795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.714799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.714819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.714840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.714860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.714880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.714901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.714921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.714942] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.714962] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.714982] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.715003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.715067] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.731170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.731196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.731242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.750121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.750139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.750159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.750176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.750195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.750215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.750234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.750253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.750274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.750294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.750315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.750334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.750352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.750385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.750407] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.750431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.750618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.750638] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.750658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.750679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.750698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.750718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.750737] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.750756] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.750775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.750794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.750813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.750817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.750836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.750840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.750859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.750878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.750897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.750916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.750935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.750953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.750973] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.750998] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.751013] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.751071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.751096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.751172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.751196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.751218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.751237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.751257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.751278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.751302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.751320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.751334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.751351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.751369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.751388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.751406] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.753378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.753395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.753409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.753423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.754928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.754944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.754958] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.756454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.756469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.758272] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.761221] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.761247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.761264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.761285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.761341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.761361] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.761395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.778176] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.778197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.778219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.778242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.778262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.778283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.778304] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.778324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.778344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.778365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.778384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.778389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.778408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.778412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.778433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.778453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.778473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.778493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.778514] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.778534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.778555] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.778575] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.778596] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.778617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.778638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.794746] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.794772] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.794818] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.813696] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.813715] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.813735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.813752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.813767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.813782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.813796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.813811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.813828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.813844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.813860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.813874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.813888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.813915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.813933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.813952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.814202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.814219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.814238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.814257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.814273] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.814290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.814308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.814324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.814340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.814354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.814369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.814373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.814387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.814391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.814405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.814419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.814441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.814453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.814469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.814482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.814495] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.814508] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.814521] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.814536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.814552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.814600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.814615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.814629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.814642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.814655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.814669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.814684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.814698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.814712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.814725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.814742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.814761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.814779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.816761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.816777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.816791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.816806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.818314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.818332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.818349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.819842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.819859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.821665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.824586] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.824612] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.824628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.824650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.824713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.824733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.824762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.841495] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.841517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.841538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.841562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.841582] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.841602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.841623] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.841643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.841664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.841684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.841704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.841708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.841728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.841732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.841752] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.841773] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.841793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.841813] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.841833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.841853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.841874] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.841894] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.841914] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.841936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.841957] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.858100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.858126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.858172] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.877070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.877089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.877109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.877125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.877141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.877156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.877170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.877186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.877202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.877218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.877234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.877248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.877262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.877289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.877307] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.877325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.877502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.877518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.877536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.877558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.877577] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.877596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.877616] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.877635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.877654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.877673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.877692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.877696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.877715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.877718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.877738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.877757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.877776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.877795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.877814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.877833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.877860] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.877877] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.877892] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.877909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.877926] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.877975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.877989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.878003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.878016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.878059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.878081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.878105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.878128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.878151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.878170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.878190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.878214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.878235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.880223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.880239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.880252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.880266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.881769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.881784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.881798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.883294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.883310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.885113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.888046] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.888072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.888088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.888110] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.888172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.888194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.888227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.904984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.905005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.905025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.905089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.905110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.905130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.905149] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.905169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.905188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.905209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.905227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.905232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.905251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.905255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.905275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.905294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.905314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.905333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.905353] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.905372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.905393] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.905412] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.905431] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.905452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.905473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.921587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.921612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.921658] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.940537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.940557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.940577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.940594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.940609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.940624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.940638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.940654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.940671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.940687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.940703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.940717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.940731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.940758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.940776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.940795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.940966] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.940983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.941000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.941019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.941079] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.941104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.941128] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.941152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.941174] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.941196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.941217] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.941224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.941245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.941251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.941273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.941294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.941315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.941338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.941369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.941390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.941412] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.941431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.941450] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.941475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.941494] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.941542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.941556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.941570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.941583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.941596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.941609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.941628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.941647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.941667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.941685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.941703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.941721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.941739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.943723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.943740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.943754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.943768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.945274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.945289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.945302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.946793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.946809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.948613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.951553] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.951579] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.951597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.951621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.951677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.951700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.951733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.968496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.968518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.968540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.968563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.968583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.968604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.968625] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.968645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.968666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.968686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.968706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.968710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.968730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.968733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.968754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.968774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.968794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.968814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.968835] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.968854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.968876] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.968896] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.968916] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.968937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.968958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.985138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.985162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.985198] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.004072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.004091] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.004111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.004127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.004143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.004158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.004172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.004188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.004205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.004221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.004237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.004256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.004274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.004307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.004330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.004353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.004545] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.004565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.004585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.004607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.004625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.004645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.004664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.004683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.004703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.004722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.004741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.004745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.004763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.004767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.004786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.004805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.004830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.004846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.004862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.004877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.004891] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.004905] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.004918] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.004933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.004950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.004998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.005016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.005033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.005078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.005101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.005123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.005146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.005169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.005191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.005211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.005230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.005254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.005275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.007264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.007280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.007294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.007309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.008811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.008827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.008844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.010340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.010358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.012164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.015102] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.015130] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.015146] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.015168] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.015224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.015246] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.015278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.032026] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.032064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.032085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.032108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.032128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.032149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.032169] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.032189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.032210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.032230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.032250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.032254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.032274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.032277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.032298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.032318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.032338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.032358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.032378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.032398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.032419] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.032439] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.032459] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.032480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.032501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.048676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.048701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.048736] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.067599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.067617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.067638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.067655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.067670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.067685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.067700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.067719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.067740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.067760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.067781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.067800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.067818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.067851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.067873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.067896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.068142] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.068165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.068184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.068204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.068220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.068244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.068260] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.068274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.068289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.068303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.068316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.068320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.068332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.068337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.068350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.068363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.068376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.068389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.068404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.068417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.068431] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.068444] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.068456] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.068471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.068488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.068537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.068551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.068565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.068578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.068592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.068606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.068622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.068640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.068660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.068678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.068696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.068715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.068733] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.070710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.070727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.070741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.070756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.072263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.072279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.072293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.073786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.073802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.075609] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.078530] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.078555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.078571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.078593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.078649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.078671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.078703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.095437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.095458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.095479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.095501] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.095517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.095537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.095557] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.095576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.095595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.095614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.095632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.095636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.095655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.095658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.095678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.095697] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.095716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.095735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.095753] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.095772] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.095792] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.095811] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.095830] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.095850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.095870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.112086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.112110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.112148] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.131007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.131026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.131088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.131115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.131141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.131165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.131184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.131200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.131218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.131234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.131251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.131265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.131281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.131308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.131330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.131354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.131529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.131549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.131569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.131591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.131609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.131629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.131648] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.131667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.131687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.131705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.131724] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.131736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.131753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.131756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.131774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.131791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.131808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.131825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.131843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.131860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.131878] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.131896] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.131913] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.131931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.131950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.132001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.132019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.132036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.132081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.132104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.132127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.132151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.132173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.132196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.132216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.132235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.132258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.132280] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.134270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.134286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.134300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.134315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.135818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.135834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.135848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.137343] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.137361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.139166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.142098] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.142124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.142140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.142162] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.142218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.142240] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.142272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.159040] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.159078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.159098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.159118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.159135] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.159154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.159172] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.159189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.159206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.159221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.159237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.159241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.159256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.159259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.159275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.159290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.159308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.159328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.159349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.159368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.159389] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.159410] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.159430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.159451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.159473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.175678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.175703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.175739] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.194597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.194616] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.194636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.194652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.194668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.194682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.194696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.194712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.194729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.194745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.194761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.194775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.194789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.194816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.194834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.194853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.195027] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.195044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.195105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.195133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.195156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.195181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.195205] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.195228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.195258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.195278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.195297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.195304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.195324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.195330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.195351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.195370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.195390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.195409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.195432] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.195449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.195463] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.195476] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.195489] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.195504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.195520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.195568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.195583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.195596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.195609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.195622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.195637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.195652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.195667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.195681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.195694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.195706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.195722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.195737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.197713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.197729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.197743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.197757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.199263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.199278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.199291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.200784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.200800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.202606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.205526] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.205552] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.205568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.205590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.205646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.205667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.205700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.222440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.222461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.222483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.222506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.222524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.222545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.222565] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.222586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.222606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.222626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.222646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.222650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.222670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.222674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.222695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.222715] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.222735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.222755] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.222775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.222795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.222816] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.222837] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.222857] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.222877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.222898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.239081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.239105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.239140] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.257970] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.257988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.258008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.258024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.258040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.258099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.258122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.258139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.258160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.258180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.258201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.258220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.258239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.258272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.258294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.258318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.258485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.258505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.258526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.258548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.258567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.258587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.258606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.258626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.258646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.258665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.258684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.258689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.258708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.258712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.258732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.258757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.258774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.258789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.258805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.258820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.258835] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.258849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.258862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.258877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.258894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.258943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.258961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.258979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.258997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.259015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.259032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.259051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.259093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.259117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.259139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.259159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.259184] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.259205] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.261196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.261212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.261226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.261241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.262744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.262762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.262779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.264277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.264293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.266097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.269037] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.269077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.269093] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.269114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.269167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.269187] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.269217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.285978] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.285998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.286019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.286040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.286099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.286125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.286145] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.286165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.286184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.286204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.286222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.286228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.286247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.286251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.286271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.286290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.286309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.286329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.286348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.286367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.286387] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.286407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.286426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.286447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.286467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.302573] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.302599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.302645] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.321538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.321556] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.321576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.321593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.321612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.321631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.321651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.321669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.321690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.321710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.321731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.321750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.321768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.321801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.321823] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.321847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.322035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.322055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.322119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.322148] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.322171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.322197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.322222] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.322252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.322274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.322294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.322313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.322319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.322340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.322345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.322366] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.322385] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.322405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.322424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.322448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.322469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.322492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.322513] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.322535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.322558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.322583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.322653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.322668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.322682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.322695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.322712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.322730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.322750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.322770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.322789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.322807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.322825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.322844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.322861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.324837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.324854] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.324871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.324890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.326398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.326415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.326432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.327926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.327942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.329748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.332667] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.332693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.332709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.332731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.332787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.332811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.332846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.349562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.349580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.349598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.349618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.349633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.349650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.349667] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.349683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.349701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.349725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.349742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.349746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.349760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.349763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.349778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.349792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.349805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.349819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.349836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.349849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.349864] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.349877] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.349891] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.349907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.349924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.366171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.366195] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.366239] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.385118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.385137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.385157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.385174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.385189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.385203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.385217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.385233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.385250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.385266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.385282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.385300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.385319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.385353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.385375] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.385398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.385575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.385595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.385615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.385637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.385653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.385673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.385699] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.385716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.385731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.385745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.385758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.385761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.385774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.385777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.385791] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.385803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.385816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.385828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.385843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.385856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.385869] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.385882] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.385894] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.385909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.385925] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.385973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.385988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.386001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.386014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.386027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.386041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.386059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.386116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.386140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.386160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.386180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.386204] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.386225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.388216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.388234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.388251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.388270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.389774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.389792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.389809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.391308] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.391324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.393128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.396061] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.396103] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.396120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.396145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.396205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.396229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.396264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.413010] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.413031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.413050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.413114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.413137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.413157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.413177] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.413196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.413216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.413236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.413255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.413259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.413276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.413280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.413300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.413319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.413338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.413357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.413376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.413396] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.413416] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.413436] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.413455] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.413475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.413497] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.429602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.429627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.429671] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.448550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.448569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.448589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.448605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.448621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.448636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.448650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.448666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.448683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.448699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.448715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.448729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.448743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.448770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.448788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.448807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.448983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.449000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.449017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.449036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.449052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.449113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.449138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.449161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.449190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.449210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.449230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.449236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.449255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.449260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.449280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.449299] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.449319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.449338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.449360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.449380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.449402] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.449421] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.449441] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.449466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.449491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.449565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.449588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.449610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.449632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.449653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.449673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.449689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.449704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.449718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.449731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.449744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.449760] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.449775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.451750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.451766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.451780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.451794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.453300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.453315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.453329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.454820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.454836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.456644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.459557] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.459583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.459599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.459621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.459678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.459699] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.459731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.476456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.476477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.476497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.476518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.476535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.476553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.476571] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.476589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.476606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.476621] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.476637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.476641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.476660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.476664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.476685] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.476706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.476726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.476746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.476767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.476786] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.476808] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.476828] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.476848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.476869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.476891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.493067] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.493109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.493154] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.512027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.512045] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.512065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.512126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.512147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.512163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.512177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.512194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.512211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.512227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.512243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.512258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.512272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.512299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.512318] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.512336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.512512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.512529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.512547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.512567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.512582] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.512607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.512622] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.512637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.512651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.512665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.512678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.512682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.512694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.512698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.512711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.512724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.512737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.512749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.512764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.512777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.512791] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.512803] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.512816] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.512831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.512848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.512896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.512911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.512924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.512938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.512950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.512964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.512979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.512994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.513012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.513031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.513049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.513071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.513111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.515102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.515118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.515132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.515147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.516653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.516668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.516682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.518182] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.518197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.520014] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.522937] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.522962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.522978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.523000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.523055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.523118] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.523169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.539846] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.539866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.539887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.539911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.539931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.539952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.539972] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.539992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.540013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.540033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.540053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.540096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.540123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.540130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.540155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.540179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.540203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.540226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.540252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.540270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.540285] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.540300] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.540313] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.540330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.540348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.556435] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.556462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.556508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.575386] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.575405] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.575424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.575441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.575457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.575471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.575485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.575501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.575517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.575533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.575549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.575563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.575576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.575604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.575622] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.575640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.575811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.575831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.575851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.575873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.575891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.575911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.575930] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.575949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.575969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.575987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.576012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.576016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.576031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.576035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.576049] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.576063] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.576119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.576140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.576162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.576182] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.576204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.576224] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.576244] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.576267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.576291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.576366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.576389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.576411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.576433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.576455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.576477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.576502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.576526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.576549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.576570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.576591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.576612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.576628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.578620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.578637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.578651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.578665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.580186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.580202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.580215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.581707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.581723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.583529] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.586462] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.586488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.586504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.586526] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.586582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.586603] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.586634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.603397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.603417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.603437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.603458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.603478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.603499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.603520] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.603540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.603561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.603581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.603600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.603605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.603625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.603629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.603649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.603670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.603690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.603710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.603730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.603750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.603771] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.603791] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.603811] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.603832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.603854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.620004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.620028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.620073] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.638968] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.638987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.639007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.639023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.639039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.639053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.639067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.639123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.639152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.639178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.639205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.639228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.639251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.639281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.639300] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.639318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.639498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.639514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.639530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.639549] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.639563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.639578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.639594] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.639608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.639622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.639636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.639649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.639653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.639666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.639669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.639682] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.639695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.639708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.639720] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.639735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.639748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.639762] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.639775] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.639788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.639803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.639821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.639868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.639883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.639896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.639909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.639922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.639935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.639951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.639966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.639980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.639993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.640006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.640021] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.640036] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.642026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.642043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.642060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.642110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.643623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.643639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.643653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.645154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.645171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.646974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.649895] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.649921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.649937] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.649959] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.650016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.650037] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.650069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.666810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.666831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.666851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.666875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.666895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.666916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.666936] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.666956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.666977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.666997] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.667016] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.667021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.667040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.667044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.667065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.667127] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.667151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.667174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.667200] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.667225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.667250] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.667271] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.667295] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.667478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.667499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.683399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.683423] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.683468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.702351] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.702370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.702390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.702406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.702422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.702436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.702451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.702466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.702486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.702506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.702527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.702546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.702564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.702597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.702620] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.702643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.702810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.702827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.702845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.702863] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.702878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.702894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.702913] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.702931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.702950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.702968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.702987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.702991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.703009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.703012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.703031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.703049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.703068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.703125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.703150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.703174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.703198] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.703220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.703241] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.703265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.703291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.703549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.703566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.703582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.703597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.703612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.703627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.703645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.703660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.703676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.703690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.703705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.703724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.703744] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.705733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.705750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.705764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.705779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.707285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.707300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.707314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.708805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.708820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.710626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.713560] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.713587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.713603] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.713625] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.713682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.713703] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.713736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.730505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.730527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.730548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.730572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.730592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.730613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.730633] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.730653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.730674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.730694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.730714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.730718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.730737] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.730741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.730762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.730782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.730802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.730822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.730842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.730862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.730883] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.730903] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.730923] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.730944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.730965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.747114] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.747139] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.747183] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.766056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.766077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.766132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.766216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.766236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.766256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.766276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.766295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.766317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.766337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.766358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.766377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.766397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.766429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.766452] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.766476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.766664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.766684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.766703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.766725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.766744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.766764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.766783] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.766802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.766821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.766840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.766859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.766863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.766881] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.766885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.766904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.766923] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.766941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.766960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.766979] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.767005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.767022] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.767038] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.767052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.767070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.767117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.767192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.767214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.767235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.767256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.767449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.767464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.767481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.767496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.767512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.767525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.767538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.767554] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.767569] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.769558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.769573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.769587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.769602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.771134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.771149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.771162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.772658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.772673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.774487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.777419] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.777444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.777461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.777482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.777538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.777560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.777591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.794306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.794324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.794343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.794361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.794376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.794393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.794410] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.794426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.794441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.794455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.794469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.794473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.794487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.794490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.794504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.794518] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.794532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.794545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.794561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.794575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.794589] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.794603] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.794617] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.794633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.794650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.810910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.810935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.810980] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.829870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.829889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.829909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.829926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.829942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.829957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.829976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.829995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.830016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.830036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.830056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.830075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.830136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.830184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.830209] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.830230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.830395] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.830412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.830430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.830450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.830466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.830487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.830507] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.830525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.830545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.830564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.830583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.830588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.830607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.830611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.830631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.830650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.830671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.830689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.830710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.830728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.830749] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.830769] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.830788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.830808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.830829] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.830877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.830897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.830916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.830936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.830956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.830975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.830996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.831016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.831037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.831056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.831075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.831124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.831147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.833147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.833165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.833179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.833194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.834708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.834724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.834739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.836247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.836265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.838075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.841016] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.841043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.841062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.841087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.841198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.841231] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.841282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.857982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.858001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.858019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.858039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.858055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.858071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.858132] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.858157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.858184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.858208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.858232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.858239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.858263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.858269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.858294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.858318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.858342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.858365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.858389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.858412] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.858436] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.858459] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.858480] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.858505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.858532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.874551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.874574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.874608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.893470] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.893489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.893510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.893527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.893542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.893558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.893572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.893588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.893605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.893621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.893636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.893651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.893665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.893692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.893710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.893729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.893906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.893922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.893940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.893959] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.893974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.893991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.894007] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.894023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.894038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.894053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.894067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.894071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.894085] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.894126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.894150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.894172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.894193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.894215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.894239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.894261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.894284] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.894306] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.894327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.894353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.894378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.894463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.894485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.894507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.894529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.894550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.894573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.894598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.894621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.894645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.894666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.894683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.894700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.894715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.896698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.896715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.896729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.896744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.898251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.898266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.898280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.899772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.899788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.901595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.904548] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.904575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.904594] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.904620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.904680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.904710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.904742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.921466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.921487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.921507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.921528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.921545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.921564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.921582] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.921599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.921616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.921633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.921648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.921652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.921667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.921671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.921686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.921706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.921726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.921746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.921767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.921787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.921808] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.921828] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.921848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.921870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.921891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.938121] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.938145] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.938181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.957030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.957049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.957070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.957090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.957152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.957179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.957204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.957229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.957256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.957274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.957291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.957306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.957320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.957348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.957367] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.957385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.957558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.957582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.957598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.957618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.957635] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.957653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.957671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.957689] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.957706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.957724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.957741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.957744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.957761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.957765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.957783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.957800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.957818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.957835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.957852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.957870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.957888] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.957905] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.957922] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.957941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.957960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.958012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.958030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.958048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.958065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.958083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.958125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.958150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.958173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.958196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.958217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.958237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.958261] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.958282] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.960273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.960289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.960303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.960317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.961820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.961835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.961849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.963345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.963361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.965166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.968110] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.968137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.968154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.968176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.968232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.968254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.968285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.985047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.985069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.985090] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.985152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.985184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.985212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.985240] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.985263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.985280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.985295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.985309] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.985314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.985328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.985331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.985346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.985360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.985374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.985393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.985413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.985432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.985453] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.985473] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.985493] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.985513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.985534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.001640] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.001664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.001708] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.020588] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.020609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.020631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.020650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.020670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.020689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.020708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.020727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.020748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.020768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.020788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.020807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.020825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.020858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.020880] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.020903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.021092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.021156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.021184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.021212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.021235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.021260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.021285] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.021308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.021332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.021356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.021379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.021386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.021408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.021414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.021432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.021446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.021460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.021474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.021491] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.021505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.021520] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.021534] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.021548] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.021564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.021582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.021635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.021652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.021667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.021681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.021696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.021711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.021727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.021743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.021759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.021773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.021788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.021805] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.021828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.023808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.023825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.023839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.023854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.025365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.025383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.025401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.026897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.026914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.028720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.031642] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.031668] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.031684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.031706] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.031762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.031783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.031815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.048526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.048545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.048564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.048583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.048598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.048615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.048632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.048648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.048664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.048679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.048693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.048697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.048711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.048715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.048729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.048744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.048762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.048782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.048801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.048820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.048840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.048859] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.048878] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.048898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.048918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.065146] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.065170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.065215] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.084093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.084129] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.084149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.084166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.084181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.084196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.084210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.084226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.084246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.084267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.084287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.084306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.084325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.084358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.084380] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.084404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.084590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.084610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.084630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.084652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.084671] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.084691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.084710] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.084728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.084748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.084767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.084785] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.084789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.084808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.084812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.084831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.084850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.084869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.084888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.084907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.084926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.084946] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.084965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.084984] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.085010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.085029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.085079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.085094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.085135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.085158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.085181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.085203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.085229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.085254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.085278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.085299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.085321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.085346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.085368] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.087362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.087379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.087393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.087411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.088916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.088932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.088946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.090443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.090458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.092263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.095218] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.095243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.095259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.095279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.095332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.095351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.095381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.112173] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.112193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.112212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.112231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.112247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.112264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.112281] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.112297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.112312] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.112327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.112345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.112349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.112368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.112372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.112392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.112411] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.112430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.112449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.112468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.112487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.112506] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.112525] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.112544] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.112564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.112585] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.128737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.128763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.128809] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.147688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.147707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.147727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.147744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.147759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.147775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.147789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.147805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.147822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.147839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.147859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.147878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.147897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.147929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.147952] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.147975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.148216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.148240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.148265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.148292] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.148313] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.148337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.148360] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.148383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.148404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.148426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.148445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.148451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.148471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.148477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.148498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.148518] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.148539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.148559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.148582] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.148601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.148624] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.148643] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.148664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.148686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.148710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.148786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.148809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.148829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.148850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.148870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.148892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.148916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.148939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.148963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.148983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.149003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.149026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.149049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.151060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.151076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.151090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.151136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.152646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.152662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.152676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.154185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.154203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.156012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.158950] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.158978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.158997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.159022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.159098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.159169] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.159222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.175888] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.175907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.175926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.175945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.175960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.175978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.175995] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.176010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.176026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.176040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.176054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.176058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.176072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.176076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.176095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.176153] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.176179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.176203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.176232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.176256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.176282] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.176306] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.176331] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.176358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.176387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.192492] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.192517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.192562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.211435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.211455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.211475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.211494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.211514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.211533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.211553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.211571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.211592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.211612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.211633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.211652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.211670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.211703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.211725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.211749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.211935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.211955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.211974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.211996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.212012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.212032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.212051] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.212070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.212089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.212108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.212173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.212181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.212207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.212214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.212241] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.212266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.212292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.212316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.212343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.212368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.212394] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.212418] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.212442] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.212470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.212498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.212584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.212607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.212629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.212650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.212670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.212692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.212716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.212739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.212762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.212781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.212802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.212827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.212850] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.214860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.214877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.214892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.214910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.216421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.216439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.216457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.217951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.217969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.219776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.222699] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.222726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.222742] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.222764] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.222826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.222848] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.222881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.239606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.239625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.239644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.239666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.239685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.239704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.239724] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.239743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.239762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.239781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.239800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.239804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.239822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.239826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.239846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.239865] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.239884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.239902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.239921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.239939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.239959] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.239978] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.239997] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.240017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.240038] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.256235] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.256259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.256293] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.275146] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.275165] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.275185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.275202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.275218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.275233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.275247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.275263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.275281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.275297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.275312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.275326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.275340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.275368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.275386] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.275404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.275559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.275575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.275593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.275612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.275629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.275649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.275668] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.275687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.275707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.275726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.275744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.275749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.275767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.275771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.275790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.275809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.275828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.275847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.275866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.275884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.275904] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.275923] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.275942] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.275962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.275982] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.276037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.276064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.276081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.276096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.276146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.276172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.276197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.276223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.276247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.276268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.276290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.276316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.276338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.278333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.278350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.278366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.278384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.279891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.279907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.279921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.281417] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.281434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.283241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.286168] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.286193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.286210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.286232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.286295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.286315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.286344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.303072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.303092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.303112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.303171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.303196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.303224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.303249] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.303397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.303413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.303428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.303443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.303447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.303461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.303464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.303479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.303493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.303507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.303520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.303537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.303555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.303575] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.303594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.303613] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.303633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.303653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.319704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.319728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.319763] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.337878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.337897] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.337917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.337934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.337949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.337968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.337988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.338007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.338027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.338048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.338068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.338087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.338106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.338183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.338216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.338248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.338615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.338631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.338648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.338666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.338680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.338695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.338711] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.338725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.338740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.338757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.338774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.338778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.338795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.338798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.338816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.338833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.338850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.338867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.338885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.338902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.338920] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.338937] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.338954] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.338973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.338992] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.339043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.339061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.339078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.339096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.339114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.339157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.339188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.339213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.339239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.339259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.339281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.339304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.339328] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.341543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.341560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.341574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.341588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.343169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.343185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.343198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.344700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.344716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.346542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.349476] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.349502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.349518] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.349540] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.349596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.349618] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.349649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.366419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.366439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.366459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.366483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.366503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.366524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.366544] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.366565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.366585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.366606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.366625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.366630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.366649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.366653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.366673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.366694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.366714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.366734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.366754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.366774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.366795] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.366815] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.366836] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.366857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.366878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.383054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.383079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.383115] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.402001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.402020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.402040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.402057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.402072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.402087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.402101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.402117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.402180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.402205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.402232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.402248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.402262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.402290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.402309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.402327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.402494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.402510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.402528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.402548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.402564] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.402580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.402597] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.402613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.402633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.402652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.402672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.402676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.402695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.402699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.402718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.402737] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.402757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.402776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.402795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.402814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.402834] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.402854] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.402874] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.402894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.402915] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.402974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.402990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.403005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.403019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.403036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.403054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.403073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.403092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.403111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.403149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.403172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.403196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.403218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.405208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.405226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.405243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.405261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.406766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.406782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.406796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.408292] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.408308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.410114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.413054] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.413081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.413098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.413158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.413241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.413272] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.413317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.430004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.430024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.430045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.430066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.430084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.430105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.430165] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.430190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.430216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.430233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.430248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.430252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.430267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.430270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.430285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.430300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.430314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.430328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.430347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.430367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.430386] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.430406] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.430426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.430446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.430467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.446604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.446628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.446673] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.465087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.465106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.465166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.465194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.465219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.465244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.465262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.465279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.465297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.465314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.465330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.465345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.465359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.465387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.465405] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.465424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.465604] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.465620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.465638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.465658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.465673] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.465691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.465707] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.465724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.465739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.465754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.465768] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.465773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.465787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.465791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.465806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.465820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.465835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.465848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.465866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.465880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.465896] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.465909] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.465924] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.465944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.465965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.466022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.466042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.466062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.466081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.466101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.466121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.466168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.466196] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.466222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.466244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.466266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.466292] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.466316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.468312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.468329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.468346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.468365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.469870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.469887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.469901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.471397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.471413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.473216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.476148] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.476174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.476190] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.476212] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.476269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.476293] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.476328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.493079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.493100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.493120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.493183] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.493205] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.493223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.493241] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.493257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.493273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.493288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.493302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.493306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.493320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.493324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.493338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.493353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.493367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.493380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.493397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.493411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.493426] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.493440] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.493454] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.493470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.493488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.509698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.509723] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.509767] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.528640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.528659] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.528679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.528696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.528712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.528727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.528742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.528760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.528781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.528802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.528822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.528841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.528860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.528893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.528915] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.528938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.529123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.529182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.529211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.529242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.529266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.529294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.529319] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.529345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.529369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.529394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.529415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.529423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.529445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.529451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.529475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.529497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.529520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.529789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.529819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.529842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.529863] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.529885] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.529904] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.529927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.529952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.530024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.530046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.530066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.530087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.530106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.530128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.530170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.530195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.530219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.530239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.530261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.530285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.530308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.532441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.532459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.532476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.532494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.534003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.534019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.534033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.535532] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.535548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.537354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.540291] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.540318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.540335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.540360] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.540435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.540470] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.540520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.557263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.557283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.557304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.557328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.557348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.557369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.557390] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.557410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.557430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.557450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.557470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.557475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.557494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.557498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.557519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.557539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.557559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.557579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.557599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.557619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.557640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.557660] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.557681] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.557702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.557724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.573836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.573861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.573906] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.592785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.592804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.592824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.592841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.592856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.592871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.592885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.592904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.592925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.592945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.592966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.592984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.593003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.593036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.593058] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.593081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.593393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.593416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.593441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.593468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.593488] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.593512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.593534] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.593557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.593578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.593599] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.593618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.593624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.593643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.593648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.593670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.593689] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.593709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.593728] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.593751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.593769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.593791] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.593810] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.593830] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.593851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.593875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.593950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.593972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.593992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.594013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.594032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.594054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.594077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.594100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.594123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.594160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.594182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.594206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.594229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.596218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.596234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.596248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.596262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.597773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.597788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.597801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.599298] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.599314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.601117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.604062] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.604089] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.604105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.604127] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.604250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.604283] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.604335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.620999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.621019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.621039] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.621060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.621077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.621095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.621113] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.621133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.621193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.621220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.621245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.621254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.621278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.621285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.621310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.621334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.621359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.621382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.621409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.621433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.621456] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.621478] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.621502] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.621528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.621555] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.637603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.637627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.637672] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.656541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.656559] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.656579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.656596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.656612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.656627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.656642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.656661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.656682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.656702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.656722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.656741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.656760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.656793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.656815] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.656838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.657024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.657044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.657064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.657086] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.657104] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.657124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.657185] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.657210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.657237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.657259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.657283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.657290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.657313] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.657320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.657344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.657366] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.657390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.657411] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.657437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.657459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.657485] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.657507] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.657530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.657557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.657585] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.657665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.657689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.657710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.657733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.657753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.657777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.657802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.657827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.657852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.657880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.657900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.657923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.657945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.659939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.659955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.659970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.659984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.661496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.661514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.661528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.663028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.663044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.664848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.667760] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.667787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.667806] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.667831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.667891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.667915] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.667951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.684678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.684698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.684716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.684736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.684752] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.684769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.684786] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.684802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.684817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.684832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.684845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.684849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.684863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.684866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.684881] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.684895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.684908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.684922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.684938] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.684952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.684967] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.684980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.684994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.685010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.685028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.701271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.701295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.701340] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.720209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.720228] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.720248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.720266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.720281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.720296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.720311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.720327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.720344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.720359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.720375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.720389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.720403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.720435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.720457] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.720481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.720646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.720666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.720686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.720708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.720726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.720746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.720765] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.720784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.720804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.720823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.720841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.720845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.720864] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.720867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.720887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.720906] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.720925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.720943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.720962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.720981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.721001] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.721020] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.721038] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.721058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.721079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.721134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.721197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.721223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.721249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.721272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.721298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.721326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.721353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.721380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.721402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.721425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.721454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.721484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.723481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.723496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.723510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.723524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.725040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.725057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.725072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.726569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.726585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.728388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.731313] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.731339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.731355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.731377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.731433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.731455] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.731487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.748229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.748247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.748265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.748285] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.748302] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.748322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.748341] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.748360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.748379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.748398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.748416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.748420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.748439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.748443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.748462] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.748481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.748500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.748519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.748538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.748557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.748577] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.748595] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.748614] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.748634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.748655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.764850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.764876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.764914] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.782716] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.782735] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.782755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.782775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.782794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.782814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.782833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.782852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.782872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.782893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.782913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.782932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.782951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.782984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.783006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.783029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.783310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.783338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.783364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.783394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.783416] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.783442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.783466] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.783490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.783512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.783535] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.783556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.783563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.783585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.783590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.783613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.783635] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.783657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.783678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.783702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.783723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.783747] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.783767] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.783790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.783813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.783845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.783905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.783926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.783947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.783966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.783987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.784007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.784030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.784053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.784076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.784095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.784115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.784137] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.784181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.786188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.786206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.786220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.786235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.787746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.787762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.787776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.789277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.789293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.791097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.794025] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.794049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.794065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.794085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.794140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.794198] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.794232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.810920] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.810938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.810956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.810976] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.810991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.811008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.811025] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.811041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.811056] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.811071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.811085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.811089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.811103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.811106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.811120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.811139] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.811195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.811218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.811242] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.811264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.811288] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.811309] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.811331] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.811358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.811384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.827530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.827555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.827600] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.846479] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.846498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.846519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.846535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.846551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.846566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.846580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.846596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.846614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.846630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.846646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.846661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.846675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.846703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.846721] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.846739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.846902] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.846919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.846936] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.846956] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.846971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.846988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.847006] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.847026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.847045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.847064] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.847083] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.847087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.847105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.847109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.847129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.847148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.847217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.847239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.847262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.847285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.847308] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.847328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.847348] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.847372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.847395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.847638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.847654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.847669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.847683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.847697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.847711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.847730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.847749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.847768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.847786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.847803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.847822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.847840] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.849822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.849839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.849854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.849868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.851378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.851393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.851407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.852902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.852918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.854725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.857647] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.857673] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.857689] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.857711] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.857768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.857789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.857821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.874560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.874580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.874600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.874621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.874638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.874656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.874675] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.874692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.874709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.874725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.874744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.874748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.874769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.874773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.874793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.874814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.874834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.874854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.874875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.874895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.874916] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.874936] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.874956] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.874978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.874999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.891201] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.891226] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.891262] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.910123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.910142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.910207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.910227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.910247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.910267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.910286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.910306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.910328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.910349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.910369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.910388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.910407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.910440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.910462] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.910486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.910680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.910696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.910713] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.910731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.910745] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.910760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.910776] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.910790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.910804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.910817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.910830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.910834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.910846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.910850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.910863] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.910875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.910888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.910900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.910915] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.910928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.910946] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.910963] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.910981] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.910999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.911018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.911069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.911087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.911105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.911122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.911139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.911185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.911211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.911235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.911258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.911278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.911297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.911320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.911342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.913331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.913347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.913361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.913375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.914881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.914896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.914913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.917492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.917512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.919322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.922260] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.922286] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.922303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.922326] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.922382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.922403] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.922438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.939216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.939235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.939254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.939273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.939289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.939306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.939325] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.939344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.939363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.939382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.939401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.939405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.939424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.939428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.939447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.939466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.939485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.939504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.939523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.939542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.939562] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.939581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.939600] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.939620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.939640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.955806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.955831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.955877] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.974740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.974759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.974779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.974795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.974811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.974826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.974840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.974856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.974873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.974889] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.974909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.974928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.974946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.974979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.975001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.975025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.975279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.975304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.975331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.975359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.975381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.975407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.975430] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.975454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.975476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.975499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.975519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.975525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.975547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.975552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.975575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.975595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.975617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.975637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.975661] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.975681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.975704] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.975724] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.975745] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.975768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.975794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.975872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.975893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.975915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.975935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.975957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.975978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.976002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.976026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.976050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.976070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.976091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.976115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.976145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.978183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.978200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.978214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.978229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.980816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.980832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.980845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.982342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.982360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.984180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.987093] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.987118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.987135] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.987197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.987288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.987321] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.987375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.004014] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.004034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.004054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.004075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.004092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.004110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.004129] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.004146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.004205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.004230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.004255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.004264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.004288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.004295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.004320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.004344] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.004369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.004391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.004419] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.004442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.004465] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.004487] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.004511] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.004537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.004565] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.020644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.020668] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.020703] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.039568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.039587] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.039607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.039624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.039639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.039654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.039669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.039685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.039701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.039717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.039732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.039746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.039760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.039788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.039806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.039829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.040017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.040037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.040057] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.040079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.040098] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.040117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.040136] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.040155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.040220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.040250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.040276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.040283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.040307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.040314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.040338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.040363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.040387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.040411] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.040438] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.040461] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.040487] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.040510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.040534] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.040568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.040593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.040668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.040690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.040713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.040732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.040753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.040774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.040798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.040821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.040844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.040865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.040884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.040908] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.040931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.044020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.044039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.044055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.044072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.045584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.045599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.045613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.047109] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.047125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.048930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.051852] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.051878] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.051895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.051916] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.051973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.051995] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.052027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.068746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.068766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.068786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.068809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.068830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.068851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.068871] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.068891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.068912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.068932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.068952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.068956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.068976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.068980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.069000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.069021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.069041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.069061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.069081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.069101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.069122] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.069143] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.069163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.069230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.069261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.085363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.085388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.085433] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.104312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.104331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.104351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.104368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.104383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.104398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.104413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.104428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.104445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.104461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.104477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.104491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.104505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.104532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.104550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.104568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.104744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.104761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.104778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.104800] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.104819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.104839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.104858] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.104878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.104897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.104916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.104935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.104939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.104958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.104961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.104981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.105000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.105018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.105044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.105062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.105078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.105096] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.105113] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.105130] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.105149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.105206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.105284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.105309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.105333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.105356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.105379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.105403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.105429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.105724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.105750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.105772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.105794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.105819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.105842] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.107837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.107853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.107867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.107881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.109391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.109406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.109420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.111976] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.111993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.113803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.116738] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.116765] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.116782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.116804] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.116860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.116882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.116914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.133687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.133709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.133731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.133754] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.133774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.133795] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.133815] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.133835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.133856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.133876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.133896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.133900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.133920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.133924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.133945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.133965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.133985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.134005] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.134025] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.134045] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.134066] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.134086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.134106] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.134127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.134149] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.150314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.150338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.150374] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.169237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.169256] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.169276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.169293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.169309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.169323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.169338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.169354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.169370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.169386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.169402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.169416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.169429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.169457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.169475] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.169493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.169662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.169677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.169694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.169712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.169726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.169741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.169757] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.169771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.169785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.169798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.169811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.169815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.169828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.169831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.169845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.169858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.169870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.169883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.169898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.169911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.169925] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.169942] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.169960] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.169979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.169999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.170051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.170070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.170088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.170106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.170124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.170142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.170161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.170220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.170250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.170274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.170298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.170326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.170350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.172346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.172362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.172377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.172391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.173897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.173915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.173932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.175431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.175447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.177250] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.180189] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.180216] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.180236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.180261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.180321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.180346] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.180381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.197124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.197146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.197167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.197235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.197265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.197293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.197322] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.197347] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.197372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.197396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.197419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.197426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.197448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.197454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.197478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.197502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.197525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.197548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.197572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.197595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.197620] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.197644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.197665] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.197691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.197718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.213763] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.213787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.213823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.232687] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.232706] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.232726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.232742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.232758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.232773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.232787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.232803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.232820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.232836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.232852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.232866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.232880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.232907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.232925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.232943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.233118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.233135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.233152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.233216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.233244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.233273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.233300] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.233326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.233352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.233377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.233400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.233408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.233430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.233437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.233461] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.233485] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.233509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.233532] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.233558] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.233582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.233608] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.233631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.233654] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.233680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.233708] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.233789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.233813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.233837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.233860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.233881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.233905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.233931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.233956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.233982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.234005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.234026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.234060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.234083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.236073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.236089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.236103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.236118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.237626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.237644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.237661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.239158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.239186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.240989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.243911] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.243937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.243956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.243981] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.244040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.244064] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.244100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.260839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.260858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.260877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.260897] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.260912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.260929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.260946] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.260961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.260977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.260991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.261005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.261009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.261022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.261026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.261040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.261054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.261068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.261081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.261097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.261112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.261126] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.261140] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.261153] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.261170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.261233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.277422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.277446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.277492] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.296373] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.296392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.296412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.296429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.296445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.296460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.296475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.296493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.296514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.296535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.296555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.296574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.296593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.296626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.296648] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.296672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.296837] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.296857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.296877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.296899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.296915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.296935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.296954] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.296973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.296992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.297011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.297030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.297034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.297052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.297056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.297075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.297094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.297113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.297132] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.297151] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.297170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.297239] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.297268] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.297294] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.297323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.297351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.297441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.297463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.297484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.297507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.297529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.297551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.297576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.297600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.297622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.297643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.297664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.297690] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.297713] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.299726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.299743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.299758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.299773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.301290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.301307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.301322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.302816] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.302832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.304639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.307587] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.307614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.307631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.307653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.307714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.307733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.307763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.324523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.324544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.324564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.324585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.324601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.324620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.324638] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.324655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.324672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.324687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.324707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.324711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.324731] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.324735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.324756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.324776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.324797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.324817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.324837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.324857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.324878] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.324898] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.324918] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.324939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.324961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.341123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.341147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.341292] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.360163] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.360199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.360219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.360236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.360251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.360266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.360281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.360297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.360314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.360330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.360346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.360360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.360374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.360401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.360419] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.360438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.360615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.360631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.360649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.360668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.360683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.360700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.360716] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.360732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.360747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.360762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.360776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.360780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.360793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.360797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.360811] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.360825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.360838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.360852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.360868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.360887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.360907] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.360929] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.360942] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.360958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.360974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.361022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.361037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.361050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.361063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.361080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.361097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.361116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.361135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.361153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.361171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.361217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.361242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.361264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.363260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.363276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.363290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.363305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.364813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.364828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.364841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.366341] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.366356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.368168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.371115] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.371142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.371159] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.371223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.371309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.371343] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.371395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.388090] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.388110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.388130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.388151] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.388168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.388228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.388257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.388283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.388310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.388336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.388360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.388367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.388391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.388397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.388421] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.388445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.388469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.388490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.388516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.388539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.388564] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.388587] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.388610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.388637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.388664] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.404659] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.404683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.404728] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.423594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.423613] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.423633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.423650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.423665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.423680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.423694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.423710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.423730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.423751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.423771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.423791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.423810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.423842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.423865] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.423888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.424064] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.424084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.424104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.424126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.424142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.424162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.424181] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.424248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.424273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.424298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.424321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.424328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.424350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.424356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.424379] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.424401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.424424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.424445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.424470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.424492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.424516] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.424539] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.424561] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.424586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.424612] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.424923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.424947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.424971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.424994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.425016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.425040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.425065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.425089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.425113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.425134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.425155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.425180] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.425222] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.427354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.427372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.427389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.427407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.429987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.430005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.430021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.431521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.431537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.433346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.436280] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.436306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.436323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.436345] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.436418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.436451] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.436506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.453259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.453278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.453297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.453317] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.453334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.453354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.453373] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.453392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.453412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.453430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.453449] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.453453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.453472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.453476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.453495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.453514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.453533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.453552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.453571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.453596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.453621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.453638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.453653] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.453670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.453689] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.469860] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.469884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.469920] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.488783] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.488802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.488823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.488839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.488855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.488870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.488885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.488901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.488918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.488934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.488949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.488963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.488977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.489004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.489026] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.489050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.489308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.489333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.489361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.489390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.489412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.489437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.489461] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.489485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.489507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.489530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.489551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.489557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.489578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.489584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.489607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.489635] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.489656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.489674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.489697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.489716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.489738] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.489757] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.489777] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.489798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.489822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.489894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.489915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.489936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.489955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.489975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.489996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.490018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.490041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.490064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.490083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.490103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.490125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.490147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.492157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.492173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.492217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.492244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.493826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.493844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.493861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.495359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.495377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.497181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.500120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.500148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.500167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.500226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.500317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.500340] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.500373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.517051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.517073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.517095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.517118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.517138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.517159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.517180] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.517240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.517267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.517293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.517315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.517323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.517346] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.517353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.517377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.517399] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.517422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.517446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.517470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.517492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.517514] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.517537] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.517557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.517582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.517609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.533672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.533697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.533743] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.552620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.552639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.552659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.552676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.552695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.552715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.552734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.552753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.552774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.552794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.552814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.552833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.552852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.552885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.552907] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.552930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.553115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.553134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.553154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.553176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.553236] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.553264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.553292] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.553316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.553342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.553364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.553388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.553395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.553418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.553424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.553449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.553471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.553494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.553515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.553541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.553563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.553588] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.553609] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.553634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.553658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.553958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.554043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.554064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.554086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.554106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.554127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.554147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.554171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.554212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.554237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.554257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.554279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.554305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.554326] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.556458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.556475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.556492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.556510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.558018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.558034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.558048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.559545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.559562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.561368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.564309] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.564336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.564355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.564379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.564437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.564460] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.564494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.581276] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.581295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.581314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.581333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.581349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.581366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.581383] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.581399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.581414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.581429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.581443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.581447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.581461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.581465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.581479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.581493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.581512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.581531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.581550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.581569] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.581589] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.581608] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.581627] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.581647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.581667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.597851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.597875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.597919] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.616609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.616628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.616648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.616665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.616681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.616697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.616711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.616727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.616744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.616761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.616777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.616795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.616814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.616847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.616870] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.616893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.617075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.617095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.617115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.617137] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.617156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.617175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.617195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.617257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.617284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.617310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.617332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.617340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.617364] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.617370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.617395] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.617417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.617441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.617463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.617490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.617511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.617543] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.617562] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.617584] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.617609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.617632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.617697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.617717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.617738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.617757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.617778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.617798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.617821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.617844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.617867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.617885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.617905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.617928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.617950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.619953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.619969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.619984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.619998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.621505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.621520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.621534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.623026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.623041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.624846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.627786] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.627812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.627828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.627849] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.627904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.627925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.627959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.644711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.644731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.644750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.644769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.644785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.644802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.644819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.644835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.644852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.644867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.644881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.644885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.644900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.644903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.644918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.644932] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.644951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.644970] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.644989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.645008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.645027] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.645046] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.645065] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.645085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.645106] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.661303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.661326] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.661360] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.680244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.680263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.680283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.680303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.680322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.680342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.680361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.680380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.680400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.680420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.680441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.680459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.680478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.680511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.680533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.680557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.680742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.680761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.680782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.680803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.680820] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.680839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.680859] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.680878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.680897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.680916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.680934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.680938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.680957] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.680960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.680980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.681006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.681024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.681039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.681055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.681069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.681084] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.681097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.681110] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.681126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.681142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.681190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.681232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.681257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.681278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.681300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.681321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.681346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.681371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.681395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.681415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.681436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.681462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.681484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.683478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.683496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.683513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.683531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.687227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.687247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.687265] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.688771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.688789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.690604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.693555] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.693583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.693599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.693621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.693694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.693728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.693780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.710522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.710544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.710565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.710588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.710608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.710629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.710650] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.710670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.710690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.710710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.710730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.710734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.710754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.710758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.710778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.710799] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.710819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.710839] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.710859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.710879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.710900] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.710920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.710940] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.710962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.710983] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.727084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.727108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.727151] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.745978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.745997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.746017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.746037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.746056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.746076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.746095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.746114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.746135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.746155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.746175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.746194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.746255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.746301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.746332] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.746363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.746612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.746634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.746659] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.746686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.746707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.746731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.746754] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.746776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.746797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.746818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.746837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.746843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.746863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.746868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.746890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.746910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.746931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.746950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.746973] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.746992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.747014] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.747033] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.747054] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.747078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.747103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.747178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.747200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.747245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.747267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.747290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.747311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.747336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.747360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.747385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.747406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.747435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.747461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.747482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.749476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.749491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.749508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.749526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.751043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.751060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.751075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.752572] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.752589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.754395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.757336] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.757363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.757379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.757401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.757459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.757481] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.757513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.774324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.774343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.774362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.774382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.774397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.774414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.774431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.774447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.774462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.774477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.774491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.774495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.774510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.774513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.774527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.774541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.774555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.774569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.774585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.774599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.774614] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.774628] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.774641] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.774657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.774674] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.790877] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.790901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.790946] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.808712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.808731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.808751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.808768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.808784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.808799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.808814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.808831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.808848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.808867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.808888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.808907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.808926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.808959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.808981] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.809004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.809194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.809263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.809291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.809322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.809346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.809375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.809400] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.809425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.809449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.809473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.809495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.809501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.809523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.809530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.809554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.809576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.809599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.809626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.809647] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.809667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.809687] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.809708] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.809727] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.809750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.809774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.809838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.809858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.809879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.809899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.809919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.809939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.809962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.809985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.810008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.810027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.810047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.810070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.810092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.812093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.812109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.812123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.812138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.813644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.813659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.813672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.815166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.815182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.817018] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.819953] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.819981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.819998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.820020] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.820079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.820100] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.820132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.836908] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.836928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.836948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.836969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.836985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.837004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.837022] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.837039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.837055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.837071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.837086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.837090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.837105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.837109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.837125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.837140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.837154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.837169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.837186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.837201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.837259] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.837281] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.837302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.837325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.837351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.853531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.853555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.853593] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.872457] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.872476] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.872497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.872514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.872529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.872544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.872558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.872574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.872591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.872611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.872631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.872650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.872669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.872702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.872724] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.872748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.872919] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.872939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.872959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.872981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.873000] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.873019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.873038] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.873057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.873077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.873102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.873118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.873122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.873136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.873139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.873153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.873167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.873180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.873197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.873253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.873274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.873296] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.873316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.873336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.873360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.873384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.873457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.873479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.873500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.873522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.873543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.873566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.873589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.873613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.873637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.873658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.873679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.873704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.873727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.875732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.875749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.875763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.875777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.879416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.879434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.879450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.880946] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.880962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.882771] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.885705] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.885733] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.885749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.885772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.885832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.885854] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.885886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.902642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.902662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.902682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.902705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.902723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.902743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.902763] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.902782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.902801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.902820] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.902838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.902843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.902862] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.902865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.902885] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.902904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.902923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.902942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.902961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.902979] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.902999] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.903018] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.903037] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.903057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.903077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.919292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.919316] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.919354] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.939304] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.939323] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.939343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.939360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.939376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.939391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.939405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.939421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.939438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.939454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.939469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.939484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.939497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.939525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.939543] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.939561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.939739] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.939755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.939773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.939792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.939809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.939829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.939848] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.939867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.939887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.939906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.939924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.939928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.939947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.939951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.939970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.939989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.940007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.940026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.940045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.940064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.940083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.940102] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.940121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.940141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.940162] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.940245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.940273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.940299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.940323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.940348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.940371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.940399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.940425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.940453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.940475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.940498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.940527] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.940551] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.942555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.942572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.942586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.942601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.944105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.944120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.944134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.945629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.945644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.947448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.950374] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.950400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.950417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.950438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.950497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.950521] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.950557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.967291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.967310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.967329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.967349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.967364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.967381] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.967398] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.967414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.967429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.967443] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.967457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.967461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.967475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.967479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.967493] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.967507] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.967521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.967535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.967552] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.967565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.967580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.967594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.967608] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.967624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.967641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.983911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.983936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.983972] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.002833] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.002852] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.002872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.002889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.002904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.002919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.002934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.002950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.002967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.002982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.002998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.003012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.003027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.003055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.003073] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.003091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.003339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.003356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.003374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.003393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.003409] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.003426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.003442] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.003458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.003474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.003493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.003512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.003516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.003536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.003540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.003560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.003580] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.003600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.003620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.003640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.003659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.003679] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.003698] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.003718] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.003738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.003760] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.003815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.003835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.003855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.003875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.003894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.003914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.003935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.003955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.003976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.003996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.004015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.004035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.004054] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.006035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.006051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.006065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.006080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.007586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.007601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.007615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.009106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.009124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.010931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.013852] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.013878] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.013894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.013916] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.013972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.013993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.014025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.030757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.030776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.030795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.030815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.030830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.030847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.030864] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.030880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.030899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.030918] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.030937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.030941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.030960] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.030964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.030983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.031002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.031021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.031040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.031059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.031078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.031098] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.031116] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.031135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.031155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.031176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.047392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.047416] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.047452] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.066308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.066327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.066347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.066363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.066379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.066394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.066409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.066425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.066441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.066457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.066473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.066487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.066501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.066533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.066556] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.066579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.066772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.066790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.066808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.066828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.066845] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.066863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.066881] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.066898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.066915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.066933] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.066950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.066954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.066971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.066974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.066992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.067010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.067027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.067044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.067062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.067079] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.067097] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.067114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.067131] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.067150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.067169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.067219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.067276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.067299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.067320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.067341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.067362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.067386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.067409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.067432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.067452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.067471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.067495] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.067517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.069507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.069523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.069537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.069551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.071057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.071072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.071085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.072581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.072596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.074400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.077334] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.077359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.077376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.077398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.077455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.077476] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.077508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.094285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.094303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.094322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.094341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.094357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.094374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.094391] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.094407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.094423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.094438] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.094456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.094460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.094479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.094483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.094502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.094522] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.094541] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.094559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.094579] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.094597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.094617] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.094636] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.094655] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.094674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.094695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.110884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.110910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.110956] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.129824] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.129842] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.129863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.129879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.129895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.129910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.129925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.129941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.129961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.129981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.130001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.130020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.130039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.130072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.130094] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.130118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.130393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.130418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.130445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.130475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.130498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.130524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.130547] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.130572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.130595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.130619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.130640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.130646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.130668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.130673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.130697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.130717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.130739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.130760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.130785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.130806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.130829] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.130850] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.130872] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.130896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.130922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.131001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.131025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.131046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.131069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.131089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.131119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.131143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.131166] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.131189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.131207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.131246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.131269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.131293] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.133302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.133319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.133333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.133348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.134854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.134869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.134883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.136382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.136398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.138202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.141122] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.141148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.141164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.141186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.141280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.141392] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.141437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.158036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.158057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.158079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.158102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.158122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.158143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.158164] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.158184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.158205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.158225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.158284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.158293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.158321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.158327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.158354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.158379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.158405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.158429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.158456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.158481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.158507] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.158726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.158750] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.158783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.158809] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.174636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.174660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.174705] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.193585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.193603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.193623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.193640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.193656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.193671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.193686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.193702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.193719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.193736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.193751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.193766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.193780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.193807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.193826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.193844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.194008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.194025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.194042] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.194061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.194076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.194093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.194109] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.194125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.194139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.194153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.194167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.194171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.194185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.194188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.194202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.194216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.194272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.194295] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.194323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.194347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.194373] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.194397] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.194421] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.194448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.194476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.194831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.194855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.194878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.194900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.194922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.194945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.194970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.194994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.195018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.195040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.195061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.195086] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.195109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.198191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.198208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.198223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.198268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.199779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.199795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.199809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.201327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.201345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.203179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.206112] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.206139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.206156] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.206178] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.206271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.206305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.206435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.223054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.223074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.223094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.223115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.223132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.223152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.223173] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.223194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.223215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.223273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.223299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.223308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.223333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.223340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.223366] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.223391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.223416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.223440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.223468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.223492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.223725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.223749] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.223773] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.223799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.223827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.239662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.239686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.239731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.258611] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.258630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.258650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.258667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.258682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.258701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.258721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.258740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.258760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.258781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.258801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.258820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.258839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.258872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.258894] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.258918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.259103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.259123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.259142] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.259164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.259181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.259207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.259224] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.259279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.259302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.259326] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.259349] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.259356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.259377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.259383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.259405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.259427] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.259450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.259472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.259496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.259518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.259542] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.259564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.259586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.259611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.259636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.259945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.259970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.259992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.260015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.260035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.260057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.260082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.260105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.260129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.260150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.260169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.260193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.260216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.262358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.262375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.262389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.262403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.263907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.263922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.263936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.265431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.265447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.267266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.270198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.270225] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.270283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.270321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.270409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.270430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.270459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.287153] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.287175] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.287196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.287220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.287283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.287316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.287345] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.287372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.287398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.287422] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.287447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.287454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.287477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.287484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.287509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.287533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.287556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.287579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.287603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.287626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.287650] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.287675] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.287696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.287721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.287748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.303749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.303773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.303817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.322711] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.322730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.322750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.322766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.322781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.322795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.322809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.322825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.322842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.322858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.322873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.322888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.322902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.322929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.322947] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.322966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.323121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.323136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.323154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.323173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.323189] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.323205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.323221] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.323279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.323304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.323330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.323353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.323360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.323383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.323390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.323414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.323438] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.323462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.323486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.323513] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.323536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.323562] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.323586] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.323610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.323637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.323671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.323993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.324017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.324041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.324063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.324084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.324107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.324132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.324156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.324180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.324202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.324223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.324264] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.324288] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.326421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.326439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.326456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.326474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.327980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.327996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.328010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.329507] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.329523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.331327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.334270] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.334296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.334313] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.334335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.334391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.334413] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.334445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.351209] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.351231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.351292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.351325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.351422] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.351440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.351458] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.351473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.351489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.351503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.351518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.351522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.351536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.351539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.351553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.351567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.351581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.351594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.351611] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.351625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.351640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.351654] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.351667] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.351683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.351701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.367811] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.367835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.367879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.386772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.386791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.386811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.386830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.386850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.386869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.386888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.386907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.386928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.386949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.386969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.386988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.387007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.387040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.387062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.387085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.387334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.387366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.387394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.387424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.387449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.387475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.387502] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.387527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.387552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.387575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.387599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.387605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.387628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.387634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.387657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.387681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.387704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.387727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.387753] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.387776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.387801] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.387825] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.387848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.387875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.387902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.387984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.388009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.388032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.388056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.388079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.388102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.388128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.388161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.388185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.388206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.388227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.388267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.388292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.390282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.390298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.390312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.390326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.391833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.391848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.391861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.393358] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.393374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.395187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.398115] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.398142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.398161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.398186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.398279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.398315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.398378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.415016] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.415038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.415059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.415082] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.415102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.415123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.415144] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.415164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.415184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.415204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.415224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.415228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.415289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.415298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.415326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.415352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.415378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.415403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.415431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.415455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.415482] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.415506] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.415530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.415555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.415582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.431610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.431634] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.431679] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.450557] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.450576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.450596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.450613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.450628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.450643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.450657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.450673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.450690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.450706] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.450722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.450737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.450750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.450777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.450796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.450814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.450980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.450996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.451016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.451038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.451057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.451077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.451096] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.451115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.451135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.451153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.451172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.451176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.451195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.451199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.451218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.451237] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.451297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.451323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.451352] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.451378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.451405] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.451430] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.451455] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.451483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.451512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.451836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.451860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.451883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.451905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.451927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.451948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.451973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.451996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.452020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.452042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.452063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.452088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.452111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.454102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.454118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.454132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.454147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.455656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.455671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.455684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.457187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.457203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.459008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.461929] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.461956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.461972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.461994] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.462051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.462072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.462104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.478842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.478862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.478882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.478903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.478919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.478938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.478956] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.478974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.478991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.479006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.479022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.479026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.479045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.479049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.479069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.479090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.479110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.479130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.479150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.479170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.479191] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.479211] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.479232] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.479296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.479329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.495433] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.495457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.495500] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.514380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.514400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.514422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.514442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.514461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.514480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.514499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.514518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.514539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.514560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.514580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.514599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.514618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.514651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.514673] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.514697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.514886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.514906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.514925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.514947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.514964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.514983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.515002] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.515022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.515041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.515060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.515078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.515082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.515108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.515112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.515130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.515147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.515164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.515181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.515198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.515215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.515233] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.515293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.515321] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.515348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.515375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.515451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.515473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.515495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.515517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.515540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.515563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.515588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.515611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.515636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.515657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.515677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.515702] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.515726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.517719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.517735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.517749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.517764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.519271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.519286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.519301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.520808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.520826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.522668] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.525618] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.525646] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.525662] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.525684] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.525759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.525792] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.525842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.542556] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.542576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.542597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.542617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.542634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.542653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.542671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.542688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.542705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.542720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.542735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.542739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.542754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.542757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.542773] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.542788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.542803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.542817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.542835] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.542850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.542865] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.542880] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.542900] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.542921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.542943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.559140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.559165] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.559209] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.578025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.578044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.578065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.578084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.578104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.578123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.578142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.578161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.578182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.578202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.578222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.578241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.578302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.578348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.578380] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.578411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.578703] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.578725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.578749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.578776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.578796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.578819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.578841] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.578863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.578883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.578905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.578923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.578929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.578949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.578954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.578975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.578993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.579013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.579032] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.579055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.579073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.579095] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.579114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.579134] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.579157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.579181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.579254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.579297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.579321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.579343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.579363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.579386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.579411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.579435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.579459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.579479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.579501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.579526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.579548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.581552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.581570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.581584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.581599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.583106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.583124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.583141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.584640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.584657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.586460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.589402] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.589429] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.589445] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.589467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.589525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.589547] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.589579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.606350] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.606369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.606389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.606408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.606424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.606441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.606458] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.606474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.606489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.606504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.606522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.606526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.606545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.606549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.606568] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.606587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.606606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.606625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.606644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.606663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.606682] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.606701] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.606720] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.606740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.606760] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.622974] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.622998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.623034] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.641884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.641903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.641924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.641941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.641957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.641972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.641987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.642003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.642019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.642035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.642050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.642064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.642078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.642105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.642123] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.642146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.642416] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.642442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.642470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.642499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.642523] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.642550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.642576] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.642601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.642626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.642650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.642673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.642680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.642702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.642708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.642731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.642754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.642777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.642801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.642824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.642847] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.642872] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.642895] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.642918] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.642943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.642970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.643057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.643079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.643101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.643123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.643143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.643165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.643189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.643213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.643235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.643256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.643294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.643320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.643343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.646430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.646448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.646465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.646480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.647988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.648004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.648018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.649513] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.649529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.651334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.654254] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.654295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.654310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.654330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.654381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.654401] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.654431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.671152] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.671172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.671192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.671213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.671230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.671248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.671328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.671436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.671462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.671486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.671509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.671515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.671538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.671544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.671567] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.671590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.671613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.671634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.671659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.671682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.671704] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.671726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.671746] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.671772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.671799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.687795] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.687819] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.687855] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.706684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.706703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.706723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.706740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.706756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.706771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.706786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.706802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.706819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.706835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.706851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.706866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.706880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.706907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.706925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.706943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.707117] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.707133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.707151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.707170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.707185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.707202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.707218] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.707234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.707249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.707317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.707342] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.707350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.707374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.707380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.707405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.707429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.707453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.707483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.707508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.707529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.707554] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.707575] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.707598] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.707623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.707649] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.707722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.707744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.707766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.707787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.707807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.707828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.707851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.707875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.707898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.707919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.707941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.707963] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.707986] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.709980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.709997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.710011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.710025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.711533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.711548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.711562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.714136] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.714156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.715974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.718908] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.718935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.718954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.718979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.719038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.719062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.719098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.735857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.735878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.735898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.735919] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.735935] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.735954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.735974] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.735994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.736015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.736035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.736055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.736059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.736079] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.736083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.736104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.736124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.736144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.736164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.736185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.736205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.736226] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.736246] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.736312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.736343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.736373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.752485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.752510] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.752546] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.771390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.771409] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.771429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.771446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.771462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.771477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.771491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.771507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.771524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.771540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.771556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.771570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.771584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.771612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.771630] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.771648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.771802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.771819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.771842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.771860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.771874] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.771889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.771904] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.771918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.771932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.771948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.771965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.771969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.771986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.771990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.772008] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.772025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.772042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.772059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.772077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.772094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.772112] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.772129] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.772147] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.772165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.772184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.772234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.772252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.772339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.772365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.772389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.772413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.772440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.772464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.772489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.772511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.772533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.772559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.772583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.775674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.775693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.775709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.775725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.778319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.778338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.778354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.779861] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.779879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.781691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.784638] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.784665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.784681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.784703] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.784760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.784781] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.784813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.801570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.801591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.801611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.801632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.801649] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.801668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.801686] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.801703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.801719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.801735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.801750] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.801755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.801770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.801773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.801789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.801804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.801824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.801844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.801865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.801885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.801906] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.801926] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.801946] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.801967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.801989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.818204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.818228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.818263] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.835200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.835219] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.835239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.835256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.835315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.835340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.835365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.835391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.835420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.835446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.835472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.835496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.835516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.835560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.835589] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.835619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.835846] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.835863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.835881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.835900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.835916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.835932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.835949] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.835964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.835980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.835994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.836008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.836013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.836026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.836030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.836044] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.836058] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.836072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.836085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.836102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.836115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.836137] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.836150] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.836162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.836177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.836193] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.836239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.836253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.836297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.836319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.836342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.836365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.836391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.836415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.836439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.836461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.836483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.836509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.836532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.838525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.838541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.838555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.838569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.840073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.840088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.840102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.842660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.842677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.844483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.847421] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.847445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.847461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.847482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.847538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.847558] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.847590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.864386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.864407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.864429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.864452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.864472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.864493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.864514] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.864534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.864555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.864575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.864595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.864599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.864619] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.864623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.864644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.864664] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.864684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.864704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.864724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.864744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.864765] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.864786] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.864806] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.864827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.864849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.880995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.881022] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.881060] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.899910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.899929] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.899950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.899966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.899982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.899997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.900012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.900028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.900046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.900065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.900086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.900105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.900124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.900157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.900179] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.900202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.900477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.900504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.900533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.900563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.900588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.900614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.900641] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.900672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.900695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.900717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.900739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.900745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.900766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.900771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.900793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.900815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.900837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.900858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.900882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.900903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.900925] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.900947] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.900968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.900992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.901017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.901091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.901114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.901136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.901157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.901179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.901201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.901225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.901249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.901272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.901310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.901332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.901358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.901381] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.903374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.903391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.903407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.903425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.904930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.904946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.904963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.906460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.906476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.908295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.911227] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.911254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.911270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.911332] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.911509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.911532] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.911564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.928174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.928194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.928214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.928235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.928252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.928270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.928333] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.928360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.928387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.928413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.928437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.928444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.928467] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.928599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.928623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.928647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.928670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.928691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.928717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.928740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.928765] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.928789] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.928812] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.928837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.928864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.944768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.944795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.944833] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.963705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.963724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.963744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.963761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.963777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.963792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.963806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.963822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.963839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.963855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.963871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.963886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.963900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.963927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.963945] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.963964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.964145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.964164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.964184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.964206] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.964225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.964245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.964264] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.964329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.964359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.964385] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.964411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.964418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.964442] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.964448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.964473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.964498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.964522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.964546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.964573] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.964597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.964623] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.964646] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.964670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.964698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.964726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.964809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.964834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.964856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.964880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.964903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.964925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.964951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.964976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.965001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.965024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.965045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.965071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.965096] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.967098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.967115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.967129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.967144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.968651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.968666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.968680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.970173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.970190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.971997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.974919] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.974945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.974965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.974990] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.975071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.975106] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.975154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.991814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.991833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.991853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.991875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.991894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.991913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.991932] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.991951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.991971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.991990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.992008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.992012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.992031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.992035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.992054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.992073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.992092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.992110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.992130] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.992148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.992168] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.992187] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.992206] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.992225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.992245] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.008458] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.008484] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.008530] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.027379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.027400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.027422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.027441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.027460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.027480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.027499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.027518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.027539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.027559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.027579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.027598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.027617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.027649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.027672] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.027695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.027878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.027898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.027918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.027939] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.027958] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.027978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.027997] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.028016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.028035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.028054] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.028072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.028076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.028095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.028099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.028118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.028137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.028156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.028175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.028194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.028212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.028232] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.028251] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.028270] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.028336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.028368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.028456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.028481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.028505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.028528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.028550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.028574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.028599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.028623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.028646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.028667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.028690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.028715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.028738] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.030745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.030761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.030775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.030790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.032313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.032331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.032348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.033851] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.033869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.035684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.038622] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.038655] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.038670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.038690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.038739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.038759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.038789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.055578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.055596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.055615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.055637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.055655] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.055675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.055694] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.055714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.055733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.055752] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.055771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.055775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.055794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.055797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.055817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.055836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.055855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.055874] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.055893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.055912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.055931] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.055951] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.055970] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.055989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.056010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.072157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.072182] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.072221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.091092] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.091110] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.091130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.091147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.091163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.091178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.091192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.091208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.091225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.091241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.091257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.091271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.091330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.091374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.091404] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.091434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.091727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.091745] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.091762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.091781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.091797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.091814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.091830] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.091846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.091861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.091882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.091895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.091899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.091912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.091915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.091928] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.091940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.091952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.091965] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.091980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.091992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.092010] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.092027] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.092045] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.092064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.092083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.092126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.092144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.092162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.092179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.092196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.092214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.092233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.092251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.092270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.092317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.092341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.092369] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.092393] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.094404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.094421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.094436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.094451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.095956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.095972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.095986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.097481] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.097497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.099308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.102237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.102264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.102281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.102338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.102541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.102564] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.102597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.119122] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.119142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.119162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.119183] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.119200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.119218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.119237] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.119258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.119278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.119331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.119360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.119367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.119392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.119399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.119424] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.119447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.119472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.119494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.119520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.119542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.119774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.119797] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.119821] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.119845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.119871] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.135732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.135758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.135796] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.154670] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.154689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.154709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.154726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.154741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.154756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.154771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.154786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.154807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.154827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.154848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.154866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.154885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.154918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.154940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.154964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.155150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.155169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.155189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.155218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.155234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.155251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.155267] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.155281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.155337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.155358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.155378] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.155384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.155403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.155409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.155429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.155448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.155468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.155487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.155509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.155528] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.155550] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.155569] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.155589] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.155611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.155636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.155706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.155720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.155734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.155748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.155761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.155775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.155790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.155805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.155819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.155832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.155844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.155860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.155875] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.157854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.157870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.157884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.157898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.159424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.159442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.159459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.162021] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.162040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.163848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.166784] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.166811] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.166831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.166855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.166917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.166941] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.166977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.183735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.183756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.183776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.183797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.183813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.183831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.183849] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.183867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.183883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.183899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.183915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.183918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.183934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.183937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.183953] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.183968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.183983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.183997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.184015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.184030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.184045] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.184060] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.184075] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.184092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.184110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.200377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.200403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.200441] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.219294] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.219329] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.219349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.219366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.219381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.219396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.219411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.219427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.219444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.219459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.219475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.219489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.219503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.219530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.219548] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.219566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.219734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.219749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.219766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.219784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.219799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.219814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.219830] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.219844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.219858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.219872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.219885] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.219888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.219901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.219905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.219918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.219931] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.219944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.219961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.219980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.219997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.220016] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.220034] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.220052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.220071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.220090] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.220143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.220161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.220179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.220197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.220216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.220233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.220253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.220272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.220319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.220344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.220366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.220391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.220413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.222405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.222421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.222436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.222451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.223954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.223969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.223983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.225479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.225495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.228363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.231283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.231323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.231339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.231361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.231417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.231438] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.231470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.248238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.248258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.248278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.248343] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.248364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.248382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.248400] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.248417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.248433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.248448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.248462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.248466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.248481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.248484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.248499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.248513] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.248528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.248541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.248557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.248572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.248587] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.248601] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.248614] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.248630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.248648] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.264838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.264862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.264899] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.283767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.283786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.283806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.283823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.283839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.283853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.283868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.283886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.283907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.283928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.283948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.283967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.283986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.284018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.284040] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.284064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.284251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.284271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.284291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.284358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.284384] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.284410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.284435] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.284458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.284481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.284503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.284525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.284532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.284552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.284558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.284581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.284604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.284626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.284647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.284673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.284691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.284707] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.284721] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.284734] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.284752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.284770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.284814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.284830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.284845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.284860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.284874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.284889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.284905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.284921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.284936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.284950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.284964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.284981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.284997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.286980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.286996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.287010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.287024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.288542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.288560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.288577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.291153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.291172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.292982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.295915] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.295942] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.295958] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.295981] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.296059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.296093] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.296143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.312866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.312888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.312910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.312933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.312953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.312974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.312995] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.313015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.313035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.313056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.313075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.313080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.313099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.313103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.313124] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.313144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.313163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.313183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.313204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.313224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.313244] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.313264] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.313285] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.313348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.313376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.329464] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.329488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.329524] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.348402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.348421] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.348442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.348462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.348482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.348501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.348520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.348539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.348560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.348580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.348601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.348620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.348638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.348671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.348694] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.348717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.348881] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.348901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.348921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.348942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.348961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.348981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.349000] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.349019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.349039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.349057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.349076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.349080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.349098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.349102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.349122] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.349141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.349160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.349178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.349197] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.349216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.349236] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.349255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.349274] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.349294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.349355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.349439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.349465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.349491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.349514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.349539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.349562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.349590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.349616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.349929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.349950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.349971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.349994] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.350017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.352009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.352025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.352039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.352053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.355715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.355734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.355757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.357254] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.357272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.359107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.362030] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.362057] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.362073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.362095] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.362173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.362207] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.362255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.378940] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.378960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.378980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.379001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.379018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.379036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.379055] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.379072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.379089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.379104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.379120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.379124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.379139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.379142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.379162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.379183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.379203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.379223] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.379244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.379264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.379285] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.379345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.379370] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.379399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.379429] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.395540] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.395564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.395601] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.414476] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.414495] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.414515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.414532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.414547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.414562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.414576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.414592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.414609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.414626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.414641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.414655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.414669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.414696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.414715] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.414733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.414910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.414926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.414944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.414963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.414978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.414997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.415017] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.415042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.415057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.415071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.415084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.415088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.415101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.415104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.415117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.415130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.415147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.415164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.415182] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.415199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.415217] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.415234] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.415252] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.415270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.415289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.415393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.415417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.415440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.415462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.415484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.415506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.415531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.415556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.415582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.415602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.415908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.415933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.415955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.417948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.417965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.417979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.417993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.421622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.421639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.421654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.423149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.423165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.424971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.427890] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.427916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.427932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.427954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.428032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.428065] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.428113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.444794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.444813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.444832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.444851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.444867] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.444884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.444901] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.444917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.444932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.444947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.444961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.444965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.444979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.444983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.444997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.445011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.445024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.445038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.445054] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.445068] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.445083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.445097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.445110] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.445126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.445144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.461375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.461398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.461433] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.479054] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.479074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.479097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.479116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.479136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.479155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.479175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.479194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.479215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.479235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.479255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.479274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.479293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.479376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.479410] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.479442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.479707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.479730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.479756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.479782] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.479804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.479828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.479852] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.479875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.479898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.479919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.479941] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.479946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.479967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.479973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.479994] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.480015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.480036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.480055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.480078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.480099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.480122] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.480141] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.480162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.480186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.480211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.480285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.480307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.480350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.480374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.480397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.480420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.480446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.480470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.480494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.480516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.480538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.480564] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.480587] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.482577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.482594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.482608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.482622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.484125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.484140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.484153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.486729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.486747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.488556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.491498] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.491526] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.491542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.491564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.491621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.491642] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.491674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.508451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.508472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.508492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.508515] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.508535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.508556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.508576] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.508596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.508617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.508637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.508657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.508661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.508680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.508684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.508705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.508725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.508745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.508765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.508786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.508805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.508826] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.508846] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.508866] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.508888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.508909] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.525038] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.525062] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.525107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.545049] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.545070] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.545092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.545112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.545131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.545150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.545170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.545189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.545210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.545230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.545250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.545269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.545288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.545366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.545398] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.545431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.545616] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.545633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.545652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.545672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.545688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.545705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.545722] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.545738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.545753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.545768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.545783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.545787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.545801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.545805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.545819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.545834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.545848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.545861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.545878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.545892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.545908] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.545921] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.545936] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.545952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.545971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.546024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.546039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.546054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.546069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.546083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.546098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.546118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.546142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.546157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.546170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.546183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.546199] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.546213] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.548189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.548206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.548224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.548242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.549754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.549771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.549788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.551285] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.551302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.553134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.556072] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.556100] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.556117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.556138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.556212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.556246] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.556304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.573008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.573028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.573048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.573069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.573086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.573104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.573123] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.573139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.573156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.573172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.573187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.573191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.573206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.573209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.573225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.573240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.573260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.573280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.573301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.573359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.573385] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.573407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.573430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.573454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.573480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.589614] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.589638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.589684] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.608563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.608582] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.608602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.608619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.608635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.608650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.608664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.608679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.608696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.608713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.608729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.608743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.608757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.608785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.608803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.608821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.608997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.609017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.609036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.609058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.609075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.609095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.609114] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.609133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.609152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.609171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.609189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.609193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.609212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.609216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.609235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.609254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.609273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.609292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.609311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.609372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.609399] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.609425] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.609448] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.609482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.609508] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.609584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.609604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.609626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.609647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.609669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.609689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.609712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.609735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.609759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.609779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.609799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.609821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.609844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.611859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.611876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.611890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.611905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.613432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.613451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.613468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.614965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.614982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.616789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.619724] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.619750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.619766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.619788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.619845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.619866] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.619898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.636672] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.636694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.636715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.636739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.636759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.636780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.636800] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.636820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.636841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.636861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.636881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.636885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.636905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.636909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.636929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.636949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.636969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.636989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.637010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.637030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.637050] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.637070] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.637091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.637112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.637133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.653271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.653296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.653390] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.670997] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.671015] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.671036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.671052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.671068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.671083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.671097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.671113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.671130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.671146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.671162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.671176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.671190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.671217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.671235] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.671254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.671546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.671570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.671597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.671626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.671649] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.671674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.671698] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.671722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.671745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.671767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.671788] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.671795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.671816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.671822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.671845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.671873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.671894] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.671913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.671935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.671954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.671976] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.671994] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.672015] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.672036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.672060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.672133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.672153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.672174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.672193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.672214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.672234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.672257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.672279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.672302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.672339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.672362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.672385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.672409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.675494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.675514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.675533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.675553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.678166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.678183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.678197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.679694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.679712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.681519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.684451] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.684477] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.684493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.684514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.684571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.684593] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.684624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.701404] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.701424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.701444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.701465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.701482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.701500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.701518] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.701535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.701552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.701568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.701583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.701587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.701602] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.701606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.701621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.701641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.701662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.701682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.701703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.701723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.701744] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.701764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.701785] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.701806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.701828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.718031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.718055] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.718091] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.736955] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.736974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.736994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.737010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.737026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.737041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.737056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.737072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.737089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.737105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.737121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.737139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.737158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.737191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.737214] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.737237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.737521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.737545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.737572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.737600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.737623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.737648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.737671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.737695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.737717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.737739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.737759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.737765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.737786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.737791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.737814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.737834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.737856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.737876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.737900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.737920] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.737944] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.737963] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.737985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.738008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.738033] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.738110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.738132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.738154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.738175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.738197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.738218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.738243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.738267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.738291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.738311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.738358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.738381] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.738405] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.740394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.740412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.740429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.740448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.741965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.741981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.741996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.743493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.743509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.745315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.748246] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.748272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.748288] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.748310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.748423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.748455] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.748505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.765160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.765182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.765203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.765227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.765244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.765265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.765286] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.765306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.765366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.765393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.765418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.765425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.765450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.765457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.765481] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.765504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.765529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.765551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.765576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.765598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.765622] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.765643] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.765664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.765690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.765715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.781789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.781814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.781850] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.800701] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.800720] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.800740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.800757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.800773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.800788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.800802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.800818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.800835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.800851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.800866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.800880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.800894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.800922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.800940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.800958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.801112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.801128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.801146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.801165] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.801180] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.801196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.801213] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.801228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.801242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.801256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.801270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.801274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.801287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.801291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.801305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.801318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.801407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.801429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.801456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.801478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.801504] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.801526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.801550] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.801577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.801605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.801683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.801704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.801727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.801748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.801777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.801797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.801820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.801842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.801865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.801884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.801904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.801926] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.801948] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.803951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.803969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.803986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.804005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.805521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.805539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.805554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.807048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.807064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.808871] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.811792] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.811817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.811834] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.811856] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.811919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.811939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.811968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.828687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.828705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.828723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.828743] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.828758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.828775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.828792] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.828808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.828823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.828838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.828852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.828856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.828874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.828878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.828898] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.828917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.828936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.828955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.828974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.828993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.829012] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.829031] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.829050] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.829070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.829091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.845302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.845326] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.845545] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.863255] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.863273] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.863299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.863326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.863390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.863413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.863436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.863462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.863490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.863516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.863542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.863563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.863586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.863628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.863657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.863686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.863927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.863944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.863963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.863982] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.864001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.864021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.864040] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.864059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.864078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.864097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.864116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.864120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.864138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.864142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.864168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.864184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.864199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.864213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.864229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.864242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.864256] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.864269] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.864282] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.864297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.864314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.864407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.864431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.864452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.864474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.864495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.864518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.864543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.864567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.864591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.864610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.864630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.864652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.864675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.867759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.867780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.867799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.867819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.871516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.871535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.871551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.873049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.873065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.874872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.877793] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.877818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.877835] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.877856] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.877914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.877935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.877967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.894707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.894727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.894747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.894770] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.894789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.894810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.894830] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.894850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.894871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.894891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.894911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.894915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.894935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.894939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.894959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.894980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.895000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.895020] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.895040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.895060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.895081] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.895101] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.895121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.895142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.895164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.911334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.911374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.911411] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.931380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.931399] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.931419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.931436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.931452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.931467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.931482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.931498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.931515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.931531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.931546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.931561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.931575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.931602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.931620] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.931639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.931800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.931816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.931834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.931861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.931876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.931891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.931906] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.931923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.931941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.931958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.931975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.931979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.931996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.932000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.932018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.932035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.932052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.932069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.932087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.932104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.932122] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.932139] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.932157] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.932175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.932194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.932245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.932263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.932281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.932299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.932316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.932359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.932388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.932413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.932440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.932461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.932483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.932509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.932531] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.935609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.935627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.935642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.935658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.937163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.937178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.937195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.938693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.938709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.940513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.943445] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.943471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.943487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.943509] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.943565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.943587] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.943618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.960419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.960438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.960457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.960476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.960495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.960515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.960534] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.960553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.960573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.960591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.960610] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.960614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.960632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.960636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.960655] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.960675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.960694] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.960712] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.960731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.960750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.960770] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.960789] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.960808] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.960827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.960847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.977024] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.977048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.977084] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.995947] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.995966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.995987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.996004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.996019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.996034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.996053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.996072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.996093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.996113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.996134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.996152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.996171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.996204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.996226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.996249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.996536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.996559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.996585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.996612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.996632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.996656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.996678] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.996700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.996721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.996742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.996761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.996767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.996786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.996791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.996813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.996832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.996852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.996871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.996894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.996913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.996935] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.996954] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.996974] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.996996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.997020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.997093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.997113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.997135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.997154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.997175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.997195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.997218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.997241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.997264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.997283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.997304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.997328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.997369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.999360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.999377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.999395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.999413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.000934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.000951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.000965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.002469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.002485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.004290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.007223] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.007250] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.007266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.007289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.007384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.007417] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.007468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.024160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.024182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.024204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.024227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.024245] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.024266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.024286] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.024307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.024327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.024388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.024413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.024422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.024446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.024452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.024479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.024502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.024527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.024548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.024575] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.024597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.024621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.024643] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.024666] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.024692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.024716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.040801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.040825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.040861] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.059712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.059730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.059750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.059767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.059783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.059798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.059812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.059828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.059845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.059861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.059877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.059891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.059910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.059943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.059965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.059989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.060172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.060192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.060211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.060233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.060250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.060270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.060289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.060308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.060327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.060390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.060415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.060422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.060444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.060451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.060474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.060496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.060518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.060539] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.060564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.060586] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.060609] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.060630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.060652] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.060677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.060703] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.060782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.060798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.060813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.060827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.060841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.060856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.060872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.060895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.060909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.060922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.060934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.060950] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.060965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.062942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.062958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.062973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.062987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.064499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.064515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.064528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.067089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.067106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.068924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.071859] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.071886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.071902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.071924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.071984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.072009] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.072044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.088798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.088817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.088835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.088855] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.088870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.088888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.088907] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.088926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.088946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.088965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.088983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.088987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.089006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.089010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.089029] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.089048] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.089066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.089085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.089104] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.089123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.089143] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.089162] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.089181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.089201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.089221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.105407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.105430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.105465] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.124329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.124359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.124379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.124396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.124411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.124426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.124440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.124456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.124473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.124489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.124505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.124519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.124533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.124560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.124578] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.124596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.124774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.124790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.124808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.124827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.124844] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.124864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.124883] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.124902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.124922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.124941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.124959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.124963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.124982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.124986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.125005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.125024] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.125043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.125062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.125081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.125100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.125119] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.125138] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.125157] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.125177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.125198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.125253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.125279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.125295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.125310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.125328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.125374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.125400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.125427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.125452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.125475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.125497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.125524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.125547] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.127542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.127558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.127572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.127587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.130172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.130192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.130211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.131712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.131729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.133536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.136482] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.136509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.136529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.136555] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.136618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.136639] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.136670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.153422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.153441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.153460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.153480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.153496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.153513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.153530] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.153546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.153562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.153577] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.153592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.153596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.153610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.153613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.153628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.153642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.153656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.153669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.153688] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.153707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.153727] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.153747] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.153765] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.153786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.153806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.170019] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.170044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.170081] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.188948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.188967] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.188988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.189005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.189020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.189035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.189049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.189065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.189082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.189098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.189114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.189128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.189142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.189169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.189187] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.189205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.189439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.189463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.189490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.189519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.189542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.189568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.189592] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.189616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.189638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.189661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.189682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.189688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.189710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.189715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.189738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.189759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.189781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.189801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.189833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.189851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.189873] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.189891] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.189911] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.189932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.189957] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.190030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.190049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.190070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.190089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.190110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.190130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.190153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.190175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.190198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.190217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.190237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.190259] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.190281] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.192276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.192294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.192308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.192324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.193857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.193872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.193888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.195410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.195426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.197229] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.200162] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.200189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.200205] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.200228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.200306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.200340] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.200421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.217114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.217135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.217155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.217176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.217192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.217211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.217230] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.217247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.217264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.217279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.217295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.217299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.217314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.217317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.217333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.217348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.217403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.217425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.217453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.217474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.217500] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.217521] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.217544] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.217572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.217598] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.233742] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.233766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.233811] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.252666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.252684] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.252705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.252721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.252737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.252752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.252767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.252783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.252801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.252817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.252833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.252847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.252861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.252888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.252906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.252925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.253073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.253107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.253122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.253138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.253152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.253173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.253187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.253203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.253218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.253232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.253246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.253259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.253271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.253290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.253492] [drm:drm_mode_addfb2] [FB:76]
>[  322.253529] [drm:drm_mode_addfb2] [FB:78]
>[  322.279192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  322.279270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.279321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.279413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.279427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.279501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.279524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.279550] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.279578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.279599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.279623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.279645] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.279668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.279688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.279709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.279728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.279734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.279753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.279758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.279779] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.279798] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.279818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.279837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.279861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.279879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.279900] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.279919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.279939] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.279961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.279985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.282522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.282541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.282557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.282572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.282590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.282609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.282630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.282650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.282669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.282688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.282706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.282726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.282745] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.284744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.284761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.284775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.284790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.286301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.286316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.286330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.287865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.287881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.289720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.292670] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.292698] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.292715] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.292738] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.309501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.309527] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.309563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.342960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.342979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.342998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.343017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.343033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.343050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.343067] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.343083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.343099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.343114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.343128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.343132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.343146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.343149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.343164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.343177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.343191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.343204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.343221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.343234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.343249] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.343263] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.343276] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.343292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.343310] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.359558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.359581] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.359616] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.378488] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.378507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.378527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.378544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.378559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.378575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.378589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.378605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.378623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.378639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.378655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.378669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.378683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.378710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.378728] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.378747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.378910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.378926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.378944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.378963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.378978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.378995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.379011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.379027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.379042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.379056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.379070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.379074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.379087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.379091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.379105] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.379119] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.379132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.379146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.379162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.379176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.379190] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.379204] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.379217] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.379233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.379258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.379298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.379312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.379326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.379339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.379351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.379405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.379428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.379450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.379472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.379491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.379511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.379534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.379555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.381545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.381561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.381574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.381588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.384171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.384192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.384211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.385717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.385734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.387539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.390496] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.390521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.390537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.390557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.390610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.390630] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.390660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.407439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.407458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.407477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.407496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.407512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.407529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.407546] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.407562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.407577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.407592] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.407606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.407610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.407624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.407627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.407642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.407656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.407669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.407683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.407699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.407713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.407728] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.407742] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.407760] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.407780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.407801] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.424013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.424037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.424082] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.442978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.442997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.443017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.443033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.443049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.443064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.443078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.443093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.443109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.443125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.443140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.443154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.443172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.443205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.443227] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.443251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.443601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.443620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.443639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.443659] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.443675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.443692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.443710] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.443726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.443741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.443756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.443778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.443781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.443794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.443798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.443811] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.443824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.443837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.443850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.443865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.443878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.443896] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.443914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.443932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.443951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.443970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.444022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.444041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.444059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.444077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.444095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.444112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.444132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.444151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.444171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.444188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.444206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.444225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.444242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.446216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.446234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.446251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.446270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.447779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.447795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.447809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.449311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.449327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.451133] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.454071] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.454098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.454115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.454137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.454196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.454218] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.454250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.471020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.471040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.471060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.471082] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.471099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.471117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.471135] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.471152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.471169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.471185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.471201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.471205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.471220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.471223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.471239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.471255] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.471270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.471285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.471303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.471318] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.471334] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.471348] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.471403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.471428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.471454] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.487648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.487672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.487710] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.506560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.506579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.506599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.506616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.506632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.506647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.506662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.506678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.506695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.506711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.506727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.506742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.506756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.506783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.506802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.506820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.506976] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.506997] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.507016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.507038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.507055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.507075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.507094] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.507113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.507139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.507155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.507169] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.507173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.507187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.507190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.507204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.507217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.507230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.507243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.507258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.507271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.507284] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.507297] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.507309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.507324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.507341] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.507438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.507460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.507481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.507501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.507521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.507542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.507565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.507588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.507610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.507629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.507650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.507675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.507698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.509686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.509702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.509716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.509731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.511233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.511248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.511262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.513837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.513856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.515663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.518605] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.518632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.518649] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.518671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.518728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.518750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.518782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.535545] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.535565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.535585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.535606] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.535623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.535641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.535659] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.535676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.535693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.535709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.535725] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.535729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.535744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.535747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.535767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.535788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.535808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.535828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.535848] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.535868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.535889] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.535909] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.535929] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.535951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.535972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.552136] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.552162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.552208] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.570132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.570153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.570174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.570194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.570213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.570233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.570252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.570271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.570292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.570312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.570333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.570351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.570370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.570451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.570483] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.570515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.570807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.570832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.570858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.570885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.570905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.570921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.570936] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.570950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.570964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.570978] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.570991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.570994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.571007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.571010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.571023] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.571036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.571048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.571060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.571075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.571087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.571101] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.571113] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.571125] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.571140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.571156] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.571206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.571220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.571233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.571246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.571259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.571273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.571287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.571301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.571315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.571327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.571339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.571358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.571400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.573396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.573412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.573426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.573440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.574955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.574972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.574987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.576497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.576515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.578323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.581258] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.581285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.581301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.581323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.581417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.581450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.581501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.598203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.598225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.598246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.598269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.598290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.598310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.598331] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.598351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.598372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.598435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.598465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.598473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.598498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.598505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.598531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.598556] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.598582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.598605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.598633] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.598657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.598863] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.598888] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.598912] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.598938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.598967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.614835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.614858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.614895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.633756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.633777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.633798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.633818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.633837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.633857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.633876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.633895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.633915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.633935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.633956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.633975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.633993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.634026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.634048] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.634072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.634246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.634264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.634281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.634300] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.634315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.634331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.634348] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.634363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.634423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.634449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.634475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.634481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.634504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.634511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.634535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.634558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.634582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.634605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.634631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.634654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.634680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.634703] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.634726] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.634753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.634780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.634860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.634883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.634907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.634927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.634950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.634973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.634999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.635023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.635048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.635070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.635090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.635115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.635140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.637141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.637158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.637175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.637193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.638699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.638715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.638729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.640220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.640236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.642041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.644964] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.644991] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.645007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.645029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.645091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.645112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.645148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.661874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.661894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.661914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.661936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.661954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.661973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.661992] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.662010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.662029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.662048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.662066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.662070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.662088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.662092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.662110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.662129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.662147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.662165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.662184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.662202] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.662222] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.662240] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.662259] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.662278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.662298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.678504] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.678530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.678569] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.697415] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.697434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.697455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.697472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.697487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.697502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.697517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.697533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.697550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.697566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.697581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.697595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.697609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.697636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.697658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.697681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.697874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.697894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.697914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.697936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.697954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.697974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.697993] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.698012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.698032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.698050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.698069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.698073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.698092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.698096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.698115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.698134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.698153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.698171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.698190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.698209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.698229] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.698248] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.698267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.698285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.698306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.698361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.698381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.698443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.698468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.698492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.698515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.698541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.698566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.698597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.698617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.698637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.698661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.698682] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.700672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.700688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.700702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.700717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.702224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.702239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.702253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.703748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.703763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.705567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.708508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.708535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.708554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.708579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.708639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.708664] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.708699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.725453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.725472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.725491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.725510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.725526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.725543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.725560] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.725577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.725593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.725608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.725623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.725627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.725641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.725645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.725659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.725674] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.725688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.725701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.725718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.725732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.725746] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.725760] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.725774] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.725790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.725808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.742040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.742064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.742109] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.760294] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.760314] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.760334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.760351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.760366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.760444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.760467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.760490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.760517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.760542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.760567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.760588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.760610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.760655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.760682] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.760711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.760978] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.760995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.761013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.761033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.761048] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.761065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.761089] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.761103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.761117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.761130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.761143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.761146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.761159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.761162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.761175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.761188] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.761200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.761212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.761229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.761247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.761265] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.761282] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.761300] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.761318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.761337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.761418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.761444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.761467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.761489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.761511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.761533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.761558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.761583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.761608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.761628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.761650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.761673] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.761696] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.763692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.763708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.763722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.763736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.765244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.765259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.765273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.766769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.766785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.768588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.771540] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.771567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.771583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.771605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.771662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.771685] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.771717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.788490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.788510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.788530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.788551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.788568] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.788586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.788605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.788625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.788646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.788666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.788686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.788690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.788710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.788714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.788734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.788755] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.788775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.788795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.788815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.788835] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.788856] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.788876] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.788897] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.788918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.788938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.805062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.805088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.805134] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.824013] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.824032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.824052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.824069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.824084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.824099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.824114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.824130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.824147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.824167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.824188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.824207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.824225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.824258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.824280] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.824304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.824553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.824571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.824590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.824610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.824628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.824646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.824664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.824682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.824700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.824718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.824735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.824740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.824757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.824761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.824779] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.824796] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.824814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.824829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.824847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.824864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.824883] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.824900] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.824918] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.824936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.824955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.825007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.825026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.825044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.825062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.825080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.825098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.825117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.825136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.825155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.825172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.825191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.825209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.825227] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.827200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.827218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.827236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.827254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.828763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.828779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.828793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.830286] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.830302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.832107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.835045] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.835072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.835089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.835114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.835173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.835197] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.835233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.851974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.851996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.852018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.852041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.852061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.852082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.852103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.852123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.852143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.852163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.852183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.852187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.852207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.852211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.852231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.852252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.852272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.852292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.852312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.852332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.852353] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.852373] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.852434] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.852462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.852489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.868581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.868607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.868653] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.887524] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.887543] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.887563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.887580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.887595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.887610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.887625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.887641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.887658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.887678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.887698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.887717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.887736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.887769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.887791] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.887814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.888000] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.888017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.888034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.888053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.888067] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.888083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.888099] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.888114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.888128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.888142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.888155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.888159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.888172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.888175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.888189] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.888201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.888215] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.888227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.888243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.888256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.888274] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.888292] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.888310] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.888329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.888348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.888427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.888451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.888473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.888494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.888514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.888536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.888560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.888583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.888607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.888627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.888647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.888671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.888693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.890689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.890705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.890719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.890737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.892255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.892272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.892286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.893785] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.893801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.895607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.898557] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.898584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.898601] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.898623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.898680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.898701] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.898734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.915513] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.915533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.915553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.915574] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.915591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.915609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.915628] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.915644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.915661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.915677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.915692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.915696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.915711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.915715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.915733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.915753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.915774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.915794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.915814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.915834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.915855] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.915876] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.915896] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.915917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.915938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.932081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.932105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.932149] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.951017] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.951038] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.951060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.951080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.951099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.951119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.951138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.951156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.951177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.951198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.951218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.951237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.951255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.951288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.951310] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.951333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.951601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.951627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.951653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.951679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.951700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.951724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.951745] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.951767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.951788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.951809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.951828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.951833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.951853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.951858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.951878] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.951898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.951918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.951936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.951959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.951978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.951999] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.952018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.952038] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.952062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.952087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.952161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.952181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.952202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.952221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.952242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.952262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.952285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.952307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.952330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.952350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.952370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.952392] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.952433] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.954427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.954443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.954458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.954472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.955991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.956009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.956026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.957543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.957561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.959370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.962308] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.962335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.962351] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.962374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.962480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.962503] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.962536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.979252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.979273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.979292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.979313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.979330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.979349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.979367] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.979384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.979443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.979469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.979494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.979502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.979526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.979533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.979558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.979582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.979606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.979629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.979657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.979680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.979702] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.979725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.979747] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.979773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.979800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.995851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.995875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.995920] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.014788] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.014806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.014826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.014843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.014859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.014874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.014888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.014904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.014921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.014937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.014953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.014967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.014981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.015009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.015027] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.015045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.015220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.015236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.015254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.015273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.015289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.015305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.015322] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.015338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.015353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.015368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.015382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.015419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.015444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.015450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.015476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.015498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.015522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.015543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.015569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.015591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.015616] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.015637] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.015660] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.015687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.015715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.015795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.015817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.015840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.015861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.015883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.015906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.015931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.015956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.015981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.016002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.016024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.016051] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.016074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.018079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.018095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.018109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.018124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.019639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.019656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.019671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.021165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.021181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.022989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.025912] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.025938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.025954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.025976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.026032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.026054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.026087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.042824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.042845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.042865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.042889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.042909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.042930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.042950] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.042971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.042991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.043011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.043031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.043035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.043055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.043059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.043079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.043099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.043119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.043139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.043160] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.043179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.043200] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.043221] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.043241] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.043261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.043283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.059452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.059477] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.059515] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.078366] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.078385] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.078448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.078469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.078488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.078508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.078527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.078546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.078569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.078590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.078610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.078630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.078649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.078683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.078706] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.078729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.078904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.078924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.078943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.078966] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.078984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.079004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.079024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.079043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.079062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.079081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.079099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.079103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.079122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.079126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.079145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.079164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.079182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.079201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.079220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.079239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.079259] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.079278] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.079297] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.079317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.079337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.079393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.079442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.079468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.079491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.079514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.079538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.079569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.079591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.079613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.079633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.079653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.079677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.079698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.081686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.081704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.081721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.081739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.083244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.083261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.083275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.084771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.084787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.086591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.089525] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.089551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.089567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.089589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.089646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.089669] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.089706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.106491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.106510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.106529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.106552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.106571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.106590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.106609] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.106628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.106647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.106666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.106685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.106689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.106707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.106711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.106730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.106750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.106769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.106787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.106806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.106825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.106845] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.106864] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.106883] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.106903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.106924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.123102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.123126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.123162] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.142024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.142043] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.142063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.142079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.142095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.142110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.142124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.142141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.142157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.142173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.142189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.142203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.142216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.142243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.142262] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.142280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.142538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.142565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.142593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.142622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.142638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.142655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.142672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.142688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.142703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.142718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.142732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.142736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.142754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.142758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.142778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.142798] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.142818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.142837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.142857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.142876] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.142897] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.142917] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.142936] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.142956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.142977] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.143039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.143057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.143075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.143093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.143111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.143128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.143148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.143167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.143186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.143204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.143222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.143241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.143259] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.145233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.145249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.145264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.145278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.146787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.146804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.146821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.148316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.148333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.150139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.153061] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.153087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.153103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.153125] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.153184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.153214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.153245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.169960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.169980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.170001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.170025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.170043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.170064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.170084] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.170105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.170125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.170145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.170165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.170169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.170189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.170193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.170213] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.170234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.170254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.170274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.170294] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.170314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.170335] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.170355] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.170375] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.170396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.170459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.186561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.186587] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.186633] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.205514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.205533] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.205553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.205570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.205586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.205600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.205615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.205630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.205648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.205667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.205688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.205707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.205726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.205759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.205781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.205805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.205989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.206009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.206029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.206050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.206067] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.206086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.206105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.206124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.206143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.206162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.206181] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.206185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.206204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.206207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.206227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.206246] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.206265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.206284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.206303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.206321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.206341] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.206360] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.206379] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.206406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.206461] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.206537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.206559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.206580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.206603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.206809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.206825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.206841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.206857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.206872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.206885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.206898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.206914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.206929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.208901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.208917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.208931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.208948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.210495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.210513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.210530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.212027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.212043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.213850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.216800] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.216827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.216843] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.216865] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.216921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.216943] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.216975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.233733] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.233754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.233774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.233795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.233811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.233829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.233848] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.233865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.233882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.233897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.233912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.233916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.233931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.233935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.233950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.233966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.233981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.233995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.234013] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.234028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.234043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.234058] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.234072] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.234090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.234108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.250324] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.250348] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.250392] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.268278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.268297] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.268318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.268334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.268350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.268365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.268380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.268396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.268454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.268482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.268506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.268528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.268551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.268582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.268602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.268620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.268802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.268825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.268842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.268862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.268880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.268898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.268916] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.268933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.268949] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.268966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.268984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.268988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.269005] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.269009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.269027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.269045] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.269063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.269080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.269098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.269115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.269134] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.269152] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.269170] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.269188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.269208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.269261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.269279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.269297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.269315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.269333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.269351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.269370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.269390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.269410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.269451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.269474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.269499] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.269521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.271514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.271530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.271544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.271559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.273061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.273077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.273090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.274585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.274601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.276402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.279349] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.279376] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.279393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.279457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.279637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.279660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.279693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.296276] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.296296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.296317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.296338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.296355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.296373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.296392] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.296409] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.296469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.296492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.296514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.296521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.296544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.296550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.296573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.296595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.296619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.296642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.296668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.296691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.296715] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.296739] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.296759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.296777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.296795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.312887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.312911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.312947] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.331823] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.331841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.331862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.331878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.331894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.331908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.331922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.331941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.331962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.331983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.332003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.332022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.332041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.332073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.332096] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.332119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.332302] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.332322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.332342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.332364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.332380] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.332400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.332461] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.332486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.332509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.332532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.332553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.332561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.332582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.332588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.332611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.332632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.332654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.332675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.332699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.332720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.332743] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.332764] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.332785] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.332811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.332837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.332919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.332944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.332968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.332992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.333016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.333040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.333067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.333093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.333115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.333129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.333144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.333169] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.333185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.335157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.335173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.335187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.335201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.336708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.336723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.336736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.338228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.338243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.340050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.342974] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.343000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.343016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.343038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.343095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.343116] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.343149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.359881] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.359902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.359922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.359943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.359959] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.359978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.359996] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.360013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.360030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.360046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.360065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.360069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.360089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.360093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.360114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.360134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.360154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.360174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.360194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.360214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.360235] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.360256] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.360276] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.360297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.360318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.376526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.376550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.376586] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.395471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.395490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.395509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.395526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.395542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.395557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.395572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.395588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.395605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.395621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.395637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.395651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.395665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.395692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.395710] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.395733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.395907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.395926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.395946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.395968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.395985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.396004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.396024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.396043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.396062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.396081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.396100] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.396104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.396122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.396126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.396145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.396164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.396183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.396202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.396221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.396240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.396260] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.396279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.396298] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.396318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.396338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.396394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.396413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.396464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.396490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.396514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.396537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.396563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.396588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.396612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.396634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.396655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.396682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.396705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.398705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.398721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.398735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.398750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.400253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.400268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.400281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.401778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.401794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.403597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.406539] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.406566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.406582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.406604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.406661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.406682] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.406715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.423499] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.423518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.423537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.423556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.423572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.423589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.423606] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.423622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.423638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.423653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.423667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.423671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.423685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.423688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.423707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.423727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.423746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.423765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.423784] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.423803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.423823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.423842] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.423860] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.423880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.423901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.440109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.440134] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.440170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.459032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.459050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.459071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.459088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.459103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.459118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.459132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.459148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.459165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.459181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.459197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.459211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.459225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.459253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.459271] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.459289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.459537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.459555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.459574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.459593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.459609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.459626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.459643] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.459659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.459675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.459690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.459704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.459709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.459728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.459732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.459752] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.459771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.459791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.459810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.459830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.459849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.459869] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.459889] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.459908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.459929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.459951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.460007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.460027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.460054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.460071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.460087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.460102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.460118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.460133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.460149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.460162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.460175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.460191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.460206] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.462187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.462204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.462218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.462232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.463739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.463754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.463770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.465263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.465278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.467084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.470007] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.470033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.470048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.470070] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.470127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.470149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.470181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.486919] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.486939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.486959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.486980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.486997] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.487015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.487034] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.487051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.487068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.487083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.487098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.487102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.487118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.487121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.487137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.487152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.487170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.487190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.487210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.487230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.487251] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.487272] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.487292] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.487313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.487335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.503546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.503571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.503609] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.522467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.522485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.522506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.522523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.522538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.522553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.522568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.522583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.522600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.522616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.522632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.522646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.522660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.522687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.522705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.522723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.522879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.522899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.522918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.522940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.522957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.522976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.522996] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.523014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.523034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.523052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.523071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.523075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.523094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.523098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.523117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.523136] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.523155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.523173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.523192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.523211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.523231] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.523250] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.523269] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.523289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.523310] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.523365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.523385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.523404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.523423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.523485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.523517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.523541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.523564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.523587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.523607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.523627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.523651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.523672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.525663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.525679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.525693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.525708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.527211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.527227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.527240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.528736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.528754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.530558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.533493] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.533519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.533535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.533557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.533613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.533635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.533667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.550456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.550477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.550497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.550518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.550534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.550553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.550571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.550588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.550604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.550620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.550635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.550639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.550654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.550658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.550673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.550688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.550703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.550717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.550735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.550749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.550765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.550783] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.550803] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.550825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.550847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.567070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.567096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.567135] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.585131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.585150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.585170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.585187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.585202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.585217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.585232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.585248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.585265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.585281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.585297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.585311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.585325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.585352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.585370] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.585389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.585634] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.585651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.585669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.585690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.585705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.585722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.585738] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.585754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.585769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.585785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.585799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.585803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.585817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.585821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.585836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.585850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.585865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.585879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.585896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.585914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.585937] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.585950] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.585964] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.585979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.585996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.586043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.586058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.586072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.586085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.586098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.586111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.586127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.586141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.586156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.586169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.586182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.586198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.586212] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.588190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.588207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.588221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.588236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.589744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.589760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.589777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.592334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.592352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.594161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.597097] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.597124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.597141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.597170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.597223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.597243] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.597275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.614038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.614060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.614081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.614105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.614123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.614144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.614164] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.614185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.614205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.614225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.614245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.614249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.614269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.614273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.614293] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.614313] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.614334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.614354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.614375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.614394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.614416] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.614436] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.614497] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.614524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.614551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.630673] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.630697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.630733] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.649591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.649611] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.649631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.649648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.649664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.649679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.649693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.649709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.649726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.649742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.649758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.649772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.649786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.649813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.649831] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.649850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.650017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.650033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.650050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.650073] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.650090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.650109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.650129] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.650148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.650167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.650186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.650204] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.650209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.650227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.650231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.650251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.650270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.650288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.650307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.650326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.650345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.650365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.650384] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.650410] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.650428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.650491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.650566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.650590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.650610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.650631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.650650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.650673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.650692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.650707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.650725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.650743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.650760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.650779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.650797] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.652768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.652784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.652798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.652813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.654316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.654334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.654351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.655848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.655864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.657666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.660597] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.660629] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.660645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.660665] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.660718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.660739] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.660768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.677551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.677569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.677588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.677607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.677623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.677640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.677656] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.677672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.677687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.677702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.677720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.677724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.677743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.677747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.677766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.677786] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.677805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.677823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.677843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.677861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.677881] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.677900] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.677919] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.677938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.677958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.694179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.694203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.694240] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.713101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.713120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.713140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.713157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.713173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.713188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.713202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.713218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.713235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.713251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.713266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.713281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.713294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.713322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.713340] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.713358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.713601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.713619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.713637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.713657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.713673] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.713690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.713707] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.713726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.713746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.713766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.713785] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.713790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.713809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.713814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.713833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.713853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.713873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.713899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.713917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.713932] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.713948] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.713962] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.713977] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.713992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.714010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.714057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.714073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.714087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.714105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.714123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.714141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.714161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.714179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.714198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.714216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.714233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.714252] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.714267] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.716245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.716262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.716276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.716291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.717797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.717812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.717826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.719317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.719333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.721139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.724061] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.724087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.724103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.724133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.724185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.724205] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.724235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.740948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.740969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.740989] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.741011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.741027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.741047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.741066] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.741085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.741104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.741123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.741142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.741146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.741164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.741168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.741188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.741207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.741226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.741244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.741264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.741282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.741302] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.741321] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.741340] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.741361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.741381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.757602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.757628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.757668] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.776521] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.776540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.776560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.776577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.776593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.776609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.776628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.776647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.776668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.776688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.776709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.776727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.776746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.776779] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.776801] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.776825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.777012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.777032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.777052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.777074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.777090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.777110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.777129] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.777148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.777167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.777186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.777205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.777209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.777228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.777231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.777251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.777270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.777289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.777308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.777327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.777345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.777365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.777384] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.777403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.777423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.777450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.777586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.777610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.777632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.777655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.777677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.777699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.777724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.777749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.777772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.777794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.777815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.777840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.777864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.779843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.779859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.779873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.779888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.781393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.781409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.781423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.782948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.782964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.784795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.787724] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.787750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.787766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.787788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.787846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.787868] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.787901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.804632] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.804652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.804670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.804690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.804705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.804724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.804744] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.804763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.804782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.804801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.804820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.804824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.804843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.804847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.804866] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.804885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.804904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.804923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.804942] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.804961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.804981] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.805000] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.805018] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.805038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.805058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.821217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.821242] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.821280] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.840160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.840178] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.840199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.840215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.840231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.840246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.840260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.840275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.840292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.840308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.840324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.840338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.840352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.840380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.840398] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.840417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.840777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.840795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.840814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.840834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.840853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.840873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.840892] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.840919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.840935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.840949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.840963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.840966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.840980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.840983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.840996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.841009] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.841021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.841038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.841056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.841073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.841091] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.841109] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.841126] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.841145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.841164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.841216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.841234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.841252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.841269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.841287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.841304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.841323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.841342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.841360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.841377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.841394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.841413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.841430] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.843438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.843466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.843483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.843501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.845010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.845026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.845040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.846556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.846574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.848398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.851324] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.851350] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.851367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.851392] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.851504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.851539] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.851593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.868218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.868240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.868262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.868285] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.868303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.868324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.868344] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.868364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.868385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.868405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.868425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.868429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.868449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.868488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.868520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.868548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.868575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.868602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.868629] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.868655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.868682] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.868706] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.868731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.868759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.868787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.884861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.884887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.884933] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.903788] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.903808] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.903828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.903845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.903861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.903876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.903891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.903907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.903924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.903940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.903956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.903970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.903985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.904013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.904030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.904049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.904223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.904240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.904257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.904276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.904293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.904313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.904332] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.904351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.904376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.904391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.904404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.904408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.904421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.904424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.904437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.904492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.904518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.904540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.904565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.904587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.904611] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.904632] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.904654] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.904679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.904706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.904779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.904802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.904823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.904845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.904868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.904890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.904914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.904937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.904960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.904979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.904999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.905024] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.905047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.907049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.907066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.907081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.907096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.908609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.908624] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.908637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.911238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.911255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.913069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.915996] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.916021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.916038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.916060] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.916114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.916136] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.916169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.932927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.932948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.932968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.932989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.933005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.933023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.933041] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.933059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.933076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.933092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.933107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.933111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.933126] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.933130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.933145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.933160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.933176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.933193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.933214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.933234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.933255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.933275] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.933296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.933317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.933338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.949501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.949525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.949562] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.967533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.967552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.967573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.967593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.967612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.967632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.967651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.967670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.967691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.967711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.967731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.967750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.967769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.967801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.967824] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.967847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.968011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.968031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.968051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.968073] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.968090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.968109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.968129] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.968148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.968168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.968187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.968205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.968209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.968228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.968231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.968251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.968270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.968289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.968308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.968327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.968345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.968365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.968384] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.968403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.968423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.968443] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.968560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.968588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.968615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.968640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.968666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.968692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.968721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.968748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.968775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.968800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.968831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.969130] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.969154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.971149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.971165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.971182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.971200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.972708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.972724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.972738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.974230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.974246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.976052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.978990] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.979022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.979040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.979064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.979138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.979171] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.979216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.995954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.995973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.995992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.996011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.996027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.996043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.996060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.996076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.996092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.996107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.996121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.996125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.996139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.996142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.996157] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.996171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.996184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.996198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.996214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.996228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.996243] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.996257] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.996270] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.996286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.996304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.012540] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.012564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.012610] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.031499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.031518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.031538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.031555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.031571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.031586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.031605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.031624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.031644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.031665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.031685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.031704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.031723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.031755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.031778] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.031801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.031988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.032008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.032028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.032050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.032066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.032086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.032105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.032124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.032143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.032162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.032180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.032192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.032209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.032212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.032228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.032243] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.032256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.032269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.032285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.032298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.032312] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.032325] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.032342] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.032360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.032379] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.032430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.032448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.032496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.032521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.032546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.032570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.032596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.032621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.032646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.032668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.032691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.032717] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.032741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.034734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.034751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.034765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.034779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.036283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.036300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.036317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.037817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.037833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.039636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.042572] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.042597] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.042613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.042635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.042713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.042747] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.042796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.059563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.059582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.059601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.059621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.059637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.059654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.059671] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.059687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.059703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.059717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.059732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.059736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.059749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.059753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.059772] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.059791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.059810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.059829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.059849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.059867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.059887] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.059906] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.059925] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.059945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.059966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.076119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.076145] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.076183] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.095058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.095079] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.095101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.095120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.095140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.095159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.095178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.095197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.095218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.095238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.095258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.095277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.095296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.095329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.095351] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.095375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.095785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.095811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.095837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.095864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.095887] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.095911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.095936] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.095958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.095981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.096003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.096025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.096030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.096051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.096057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.096078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.096099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.096120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.096139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.096162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.096183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.096205] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.096227] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.096246] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.096269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.096294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.096368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.096390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.096413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.096435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.096455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.096497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.096524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.096548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.096572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.096594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.096616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.096642] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.096666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.098837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.098853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.098867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.098882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.100408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.100423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.100437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.101932] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.101947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.103752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.106703] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.106730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.106746] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.106769] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.106849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.106881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.106927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.123633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.123653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.123673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.123694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.123711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.123729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.123748] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.123765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.123782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.123798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.123813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.123817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.123833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.123836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.123852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.123867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.123882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.123901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.123922] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.123942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.123963] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.123984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.124004] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.124025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.124047] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.140264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.140288] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.140333] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.159179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.159198] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.159218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.159235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.159251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.159266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.159281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.159297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.159314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.159330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.159345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.159360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.159374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.159401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.159419] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.159438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.159762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.159788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.159816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.159846] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.159870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.159896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.159923] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.159948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.159973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.159996] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.160020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.160026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.160049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.160055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.160078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.160101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.160124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.160145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.160177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.160198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.160220] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.160242] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.160263] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.160286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.160311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.160386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.160408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.160429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.160449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.160469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.160513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.160540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.160565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.160590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.160611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.160634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.160659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.160683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.162673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.162688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.162702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.162718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.164221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.164237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.164251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.165745] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.165763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.167568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.170509] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.170536] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.170555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.170582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.170671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.170707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.170754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.187439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.187459] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.187522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.187556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.187581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.187606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.187632] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.187658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.187683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.187707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.187731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.187737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.187760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.187766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.187790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.187813] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.187836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.187857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.187883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.187906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.187930] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.187952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.187975] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.188000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.188027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.204079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.204104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.204148] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.223014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.223032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.223053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.223069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.223084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.223099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.223114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.223130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.223147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.223162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.223178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.223192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.223206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.223233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.223252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.223270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.223441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.223457] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.223518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.223549] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.223574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.223602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.223628] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.223654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.223686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.223708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.223730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.223737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.223758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.223764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.223786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.223808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.223831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.223852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.223876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.223898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.223921] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.223942] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.223964] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.223989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.224014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.224087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.224109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.224131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.224150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.224172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.224193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.224218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.224241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.224264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.224286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.224305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.224329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.224352] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.226340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.226356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.226373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.226391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.228976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.228995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.229011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.230539] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.230556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.232362] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.235298] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.235325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.235342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.235363] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.235442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.235476] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.235594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.252242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.252263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.252283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.252304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.252320] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.252338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.252358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.252379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.252400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.252420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.252440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.252444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.252464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.252504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.252533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.252558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.252585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.252607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.252634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.252657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.252683] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.252705] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.252729] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.252757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.252785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.268875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.268901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.268947] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.287802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.287821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.287841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.287858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.287874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.287889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.287904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.287920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.287936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.287952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.287968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.287982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.287996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.288023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.288045] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.288069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.288259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.288279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.288299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.288321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.288337] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.288357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.288376] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.288395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.288415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.288433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.288452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.288456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.288475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.288514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.288544] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.288569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.288595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.288617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.288644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.288666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.288693] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.288715] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.288738] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.288762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.288790] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.288871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.288893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.288917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.288939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.288962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.288984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.289010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.289035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.289060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.289080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.289102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.289132] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.289154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.291147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.291163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.291177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.291191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.292698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.292712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.292725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.294217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.294233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.296038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.298960] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.298985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.299002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.299023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.299101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.299136] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.299184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.315848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.315869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.315889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.315910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.315927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.315945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.315966] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.315986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.316007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.316027] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.316047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.316051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.316071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.316075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.316096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.316116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.316136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.316156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.316176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.316196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.316217] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.316238] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.316258] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.316279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.316300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.332471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.332511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.332547] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.351414] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.351433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.351453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.351470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.351531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.351559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.351584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.351611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.351639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.351665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.351691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.351714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.351738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.351782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.351811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.351841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.352053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.352070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.352088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.352107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.352124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.352143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.352163] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.352182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.352202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.352221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.352239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.352243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.352262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.352266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.352285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.352304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.352323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.352342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.352362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.352380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.352400] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.352419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.352438] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.352459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.352479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.352590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.352617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.352641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.352664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.352687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.352711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.352737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.352761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.352786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.352808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.352829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.352855] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.352878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.354880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.354897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.354912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.354931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.356439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.356456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.356470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.358082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.358098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.359908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.362852] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.362879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.362895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.362918] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.362996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.363031] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.363080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.379793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.379813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.379834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.379857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.379875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.379896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.379917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.379937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.379958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.379978] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.379998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.380002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.380022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.380026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.380046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.380066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.380087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.380107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.380127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.380147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.380168] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.380188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.380208] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.380229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.380251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.396419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.396443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.396488] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.413427] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.413446] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.413466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.413523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.413549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.413574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.413597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.413623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.413650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.413675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.413700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.413722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.413744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.413786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.413814] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.413843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.414085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.414101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.414118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.414136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.414150] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.414165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.414181] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.414196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.414210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.414223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.414236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.414239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.414252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.414255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.414268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.414281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.414294] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.414306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.414321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.414334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.414347] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.414360] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.414372] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.414387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.414403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.414451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.414464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.414478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.414517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.414542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.414563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.414588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.414612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.414636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.414656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.414677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.414703] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.414725] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.416719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.416735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.416749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.416764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.418267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.418282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.418296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.419791] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.419807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.421610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.424551] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.424578] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.424597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.424623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.424703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.424739] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.424789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.441479] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.441515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.441534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.441554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.441570] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.441587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.441604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.441620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.441635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.441650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.441664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.441667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.441681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.441684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.441699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.441713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.441726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.441739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.441756] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.441774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.441794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.441814] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.441832] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.441852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.441872] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.458122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.458146] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.458190] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.476294] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.476313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.476334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.476351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.476366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.476382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.476396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.476412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.476429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.476445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.476460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.476479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.476535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.476579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.476609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.476768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.476999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.477016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.477034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.477054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.477073] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.477093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.477112] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.477131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.477150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.477169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.477188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.477192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.477211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.477215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.477234] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.477253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.477272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.477291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.477310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.477329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.477349] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.477368] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.477387] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.477407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.477434] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.477486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.477532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.477555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.477580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.477603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.477628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.477654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.477679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.477704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.477727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.477749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.477777] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.477800] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.480039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.480057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.480071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.480086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.481594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.481612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.481630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.483124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.483141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.484949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.487892] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.487920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.487936] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.487958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.488036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.488071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.488122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.504833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.504855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.504877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.504900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.504918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.504939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.504960] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.504980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.505001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.505021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.505040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.505045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.505065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.505068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.505089] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.505109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.505130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.505149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.505170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.505190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.505211] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.505231] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.505251] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.505272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.505294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.521461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.521485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.521658] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.540255] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.540274] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.540295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.540312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.540327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.540341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.540356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.540372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.540392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.540413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.540433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.540452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.540471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.540546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.540578] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.540611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.540865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.540883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.540902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.540924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.540941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.540968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.540985] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.541003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.541020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.541038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.541054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.541058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.541075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.541078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.541096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.541114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.541131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.541148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.541165] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.541182] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.541200] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.541218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.541235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.541253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.541272] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.541324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.541342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.541359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.541377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.541394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.541412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.541430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.541449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.541468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.541485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.541529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.541558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.541580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.543574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.543591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.543605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.543620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.546206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.546225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.546241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.547742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.547760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.549566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.552493] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.552537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.552556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.552582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.552642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.552667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.552703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.569447] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.569468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.569488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.569550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.569574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.569602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.569626] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.569651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.569673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.569697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.569718] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.569725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.569746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.569752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.569775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.569796] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.569818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.569839] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.569863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.569884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.569908] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.569928] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.569950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.569973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.570000] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.586078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.586102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.586138] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.605002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.605021] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.605041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.605058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.605073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.605089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.605103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.605119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.605136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.605152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.605168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.605182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.605196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.605223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.605241] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.605264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.605451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.605471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.605491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.605556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.605580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.605607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.605631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.605654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.605676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.605698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.605718] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.605725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.605745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.605751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.605773] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.605793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.605814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.605834] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.605857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.605877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.605900] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.605920] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.605940] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.605964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.605989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.606062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.606082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.606104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.606123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.606143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.606163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.606187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.606209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.606232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.606250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.606271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.606293] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.606315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.608306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.608322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.608339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.608357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.609865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.609881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.609895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.611387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.611403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.613208] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.616130] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.616155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.616171] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.616193] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.616249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.616270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.616302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.633033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.633054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.633074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.633094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.633111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.633130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.633148] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.633168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.633189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.633209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.633229] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.633233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.633253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.633257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.633278] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.633298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.633318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.633338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.633358] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.633378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.633399] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.633419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.633439] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.633460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.633482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.649670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.649694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.649730] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.668120] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.668139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.668159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.668176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.668192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.668207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.668221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.668245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.668281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.668298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.668314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.668328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.668342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.668369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.668387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.668405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.668671] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.668697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.668726] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.668755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.668780] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.668807] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.668833] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.668858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.668884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.668913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.668935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.668941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.668961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.668967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.668989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.669011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.669032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.669051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.669075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.669097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.669119] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.669140] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.669162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.669185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.669211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.669287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.669309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.669331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.669351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.669372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.669395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.669419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.669442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.669465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.669486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.669527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.669554] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.669576] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.671585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.671602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.671617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.671635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.673142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.673158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.673172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.674668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.674685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.676492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.679439] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.679467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.679486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.679554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.679730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.679753] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.679786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.696388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.696408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.696428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.696449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.696466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.696487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.696547] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.696572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.696599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.696621] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.696645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.696653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.696676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.696682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.696706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.696727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.696750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.696772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.696797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.696818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.696842] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.696863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.696885] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.696908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.696934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.713017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.713041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.713078] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.731927] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.731946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.731966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.731983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.731999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.732014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.732029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.732045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.732062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.732078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.732097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.732117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.732135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.732168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.732191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.732214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.732406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.732423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.732442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.732462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.732478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.732497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.732555] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.732579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.732605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.732626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.732649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.732655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.732677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.732683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.732706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.732727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.732749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.732769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.732794] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.732814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.732838] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.732858] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.732879] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.732905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.732932] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.733009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.733030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.733052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.733072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.733092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.733113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.733137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.733161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.733184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.733203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.733224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.733247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.733270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.735266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.735282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.735296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.735311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.736818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.736833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.736846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.738338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.738353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.740159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.743081] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.743106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.743122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.743144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.743199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.743221] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.743253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.759970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.759991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.760011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.760032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.760048] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.760066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.760085] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.760102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.760119] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.760136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.760155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.760160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.760180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.760183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.760204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.760224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.760245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.760265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.760285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.760305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.760326] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.760347] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.760367] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.760388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.760409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.776591] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.776616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.776653] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.795543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.795562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.795582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.795598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.795614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.795630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.795645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.795660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.795678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.795694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.795709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.795724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.795737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.795765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.795782] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.795801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.795975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.795991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.796009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.796028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.796044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.796060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.796076] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.796092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.796107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.796121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.796135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.796139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.796152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.796156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.796170] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.796184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.796198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.796211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.796227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.796241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.796255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.796269] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.796282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.796299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.796316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.796367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.796383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.796397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.796411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.796425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.796439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.796455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.796470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.796485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.796499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.796547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.796574] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.796601] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.798605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.798623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.798640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.798659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.800168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.800184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.800202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.801703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.801720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.803534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.806470] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.806497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.806548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.806586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.806669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.806692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.806724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.823427] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.823447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.823468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.823491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.823554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.823586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.823615] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.823642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.823667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.823693] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.823717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.823724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.823746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.823752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.823776] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.823800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.823823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.823846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.823870] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.823893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.823917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.823941] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.823962] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.823987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.824014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.840013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.840039] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.840077] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.858941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.858959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.858979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.858996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.859015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.859035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.859054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.859073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.859094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.859114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.859135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.859154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.859172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.859205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.859227] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.859251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.859432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.859452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.859471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.859493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.859542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.859574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.859599] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.859625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.859648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.859673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.859694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.859702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.859724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.859731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.859754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.859776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.859799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.859821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.859847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.859868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.859893] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.859915] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.859938] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.859966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.859993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.860075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.860097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.860120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.860141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.860163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.860185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.860211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.860236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.860260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.860281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.860303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.860334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.860356] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.862349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.862367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.862384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.862402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.863910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.863926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.863941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.866536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.866556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.868365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.871292] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.871318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.871335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.871357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.871435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.871470] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.871562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.888185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.888206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.888228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.888252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.888269] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.888290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.888311] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.888331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.888352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.888372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.888392] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.888396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.888416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.888420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.888440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.888461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.888481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.888501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.888561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.888588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.888616] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.888640] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.888665] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.888694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.888723] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.904826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.904852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.904898] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.923759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.923778] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.923798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.923814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.923830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.923845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.923859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.923875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.923892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.923908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.923923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.923938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.923951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.923979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.923997] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.924015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.924188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.924208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.924228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.924250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.924266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.924286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.924305] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.924324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.924343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.924362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.924381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.924385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.924403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.924407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.924426] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.924445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.924464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.924483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.924502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.924563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.924590] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.924615] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.924638] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.924667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.924696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.924775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.924799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.924822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.924845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.924873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.924895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.924919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.924942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.924964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.924983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.925003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.925026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.925048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.927060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.927076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.927091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.927105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.928624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.928642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.928657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.930155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.930171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.931982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.934932] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.934960] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.934979] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.935005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.935068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.935091] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.935124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.951876] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.951896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.951916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.951937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.951954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.951972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.951990] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.952007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.952024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.952040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.952056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.952060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.952075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.952079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.952094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.952110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.952125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.952144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.952164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.952184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.952206] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.952226] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.952246] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.952267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.952289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.968464] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.968488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.968568] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.987437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.987456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.987476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.987496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.987516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.987577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.987604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.987631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.987661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.987688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.987714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.987737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.987760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.987803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.987831] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.987861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.988076] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.988096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.988115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.988137] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.988154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.988174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.988193] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.988212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.988232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.988250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.988269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.988273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.988292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.988295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.988315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.988334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.988353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.988371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.988397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.988414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.988430] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.988445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.988458] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.988474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.988491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.988582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.988606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.988630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.988653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.988676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.988699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.988725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.988750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.988774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.988797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.988818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.988845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.988868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.990872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.990889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.990903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.990918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.992422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.992437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.992454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.993952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.993968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.995772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.998721] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.998748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.998765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.998787] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.998865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.998900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.998950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.015692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.015711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.015730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.015749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.015764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.015781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.015798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.015813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.015829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.015843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.015857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.015861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.015880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.015883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.015903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.015922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.015941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.015960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.015979] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.015997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.016017] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.016037] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.016056] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.016075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.016096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.032253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.032278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.032313] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.051188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.051207] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.051227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.051246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.051266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.051285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.051304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.051323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.051344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.051364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.051385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.051404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.051422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.051455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.051478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.051501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.051828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.051854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.051880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.051909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.051932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.051964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.051986] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.052008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.052029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.052050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.052069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.052075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.052094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.052099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.052120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.052139] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.052159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.052178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.052201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.052220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.052241] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.052260] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.052281] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.052304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.052329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.052402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.052423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.052443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.052462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.052482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.052502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.052545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.052570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.052594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.052613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.052634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.052660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.052681] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.054672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.054688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.054703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.054717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.056220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.056236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.056249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.057745] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.057761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.059564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.062477] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.062502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.062517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.062577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.062660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.062692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.062741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.079402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.079423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.079445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.079468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.079486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.079507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.079567] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.079593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.079620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.079643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.079668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.079675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.079699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.079705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.079729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.079751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.079775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.079796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.079821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.079841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.079865] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.079885] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.079907] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.079930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.079957] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.096026] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.096051] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.096096] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.114933] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.114951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.114972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.114988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.115004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.115019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.115034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.115050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.115067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.115083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.115099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.115113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.115127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.115155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.115173] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.115191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.115352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.115375] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.115391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.115409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.115426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.115444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.115462] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.115479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.115496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.115514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.115570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.115577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.115601] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.115608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.115631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.115652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.115675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.115695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.115719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.115739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.115762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.115782] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.115803] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.115829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.115855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.115928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.115950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.115970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.115991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.116010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.116031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.116055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.116078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.116100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.116119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.116140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.116164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.116184] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.118176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.118192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.118206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.118220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.119726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.119741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.119755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.121247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.121263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.123069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.125991] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.126016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.126032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.126054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.126132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.126166] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.126215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.142898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.142920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.142941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.142964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.142982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.143003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.143023] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.143044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.143064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.143084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.143104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.143108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.143128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.143132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.143153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.143173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.143193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.143213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.143234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.143253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.143274] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.143295] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.143315] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.143336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.143357] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.159530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.159570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.159615] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.178474] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.178493] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.178513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.178572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.178597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.178620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.178645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.178668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.178695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.178722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.178747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.178767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.178790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.178833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.178860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.178890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.179121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.179137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.179155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.179175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.179190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.179207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.179224] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.179239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.179255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.179269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.179283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.179287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.179300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.179304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.179318] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.179332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.179345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.179358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.179375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.179388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.179403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.179416] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.179430] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.179446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.179463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.179515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.179558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.179586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.179608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.179632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.179655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.179681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.179707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.179734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.179755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.179779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.179814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.179836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.181831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.181847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.181861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.181876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.183379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.183394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.183408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.184905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.184923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.186729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.189671] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.189698] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.189714] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.189736] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.189815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.189849] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.189900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.206616] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.206636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.206656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.206677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.206694] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.206713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.206731] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.206748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.206765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.206781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.206797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.206801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.206816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.206819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.206838] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.206858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.206878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.206898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.206919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.206939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.206960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.206980] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.207000] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.207022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.207043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.223213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.223237] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.223273] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.241305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.241325] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.241347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.241367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.241386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.241406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.241425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.241444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.241464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.241485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.241505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.241524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.241585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.241632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.241664] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.241694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.241960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.241977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.241995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.242015] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.242030] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.242047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.242064] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.242080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.242096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.242110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.242124] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.242128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.242142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.242146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.242160] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.242174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.242195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.242211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.242229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.242246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.242264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.242282] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.242299] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.242317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.242336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.242388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.242406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.242423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.242441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.242459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.242476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.242495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.242514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.242532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.242575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.242602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.242626] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.242650] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.244643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.244659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.244674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.244690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.246194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.246209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.246223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.247718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.247734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.249538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.252471] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.252497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.252513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.252572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.252663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.252697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.252750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.269409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.269428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.269448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.269470] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.269486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.269506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.269526] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.269587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.269613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.269639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.269661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.269669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.269692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.269698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.269722] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.269744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.269767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.269789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.269814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.269835] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.269859] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.269879] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.269901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.269927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.269951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.285973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.285998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.286034] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.304308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.304326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.304346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.304363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.304378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.304393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.304407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.304423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.304440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.304456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.304472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.304490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.304509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.304582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.304613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.304645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.304931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.304949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.304967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.304986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.305002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.305018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.305035] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.305051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.305066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.305080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.305094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.305098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.305112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.305115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.305130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.305144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.305158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.305171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.305187] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.305201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.305215] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.305229] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.305242] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.305258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.305275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.305327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.305342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.305357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.305371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.305385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.305400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.305416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.305431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.305447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.305461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.305474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.305491] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.305507] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.307514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.307530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.307575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.307602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.309186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.309201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.309215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.310711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.310726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.312527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.315475] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.315502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.315518] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.315582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.315673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.315708] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.315760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.332396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.332415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.332434] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.332454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.332469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.332486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.332504] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.332520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.332536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.332593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.332616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.332624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.332647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.332654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.332679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.332701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.332725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.332746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.332772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.332794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.332817] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.332838] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.332861] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.332884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.332909] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.349013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.349037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.349073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.367945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.367963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.367983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.368002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.368022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.368041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.368060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.368079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.368100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.368120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.368141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.368159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.368178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.368211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.368233] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.368256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.368442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.368462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.368482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.368504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.368521] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.368541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.368601] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.368625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.368652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.368675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.368699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.368706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.368729] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.368736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.368760] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.368782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.368806] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.368827] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.368853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.368875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.368900] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.368922] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.368945] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.368972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.368999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.369353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.369375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.369397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.369419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.369440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.369460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.369484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.369507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.369530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.369570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.369590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.369615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.369636] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.371756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.371773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.371787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.371801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.373304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.373320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.373333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.374830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.374845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.376651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.379602] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.379629] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.379645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.379668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.379746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.379781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.379831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.396536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.396575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.396597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.396620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.396638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.396659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.396679] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.396700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.396720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.396740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.396760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.396765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.396784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.396788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.396809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.396829] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.396849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.396869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.396889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.396909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.396930] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.396950] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.396971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.396992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.397013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.413125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.413148] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.413184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.432073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.432092] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.432112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.432129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.432144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.432159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.432174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.432189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.432206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.432222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.432238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.432252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.432266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.432293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.432315] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.432338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.432512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.432532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.432592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.432621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.432645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.432677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.432699] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.432721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.432742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.432762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.432782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.432788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.432809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.432953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.432968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.432983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.432997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.433010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.433027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.433040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.433055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.433068] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.433081] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.433096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.433113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.433161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.433176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.433190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.433203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.433216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.433231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.433246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.433260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.433275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.433288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.433301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.433316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.433331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.435300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.435316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.435331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.435345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.436851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.436866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.436879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.438371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.438388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.440195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.443118] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.443144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.443161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.443187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.443266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.443301] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.443349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.460013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.460033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.460051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.460071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.460086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.460103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.460120] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.460136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.460152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.460167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.460185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.460189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.460208] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.460211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.460231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.460250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.460269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.460288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.460307] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.460326] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.460346] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.460364] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.460383] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.460403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.460424] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.476657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.476682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.476726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.495593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.495612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.495632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.495649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.495665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.495680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.495695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.495711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.495731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.495751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.495772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.495791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.495809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.495842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.495865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.495888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.496075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.496095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.496121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.496140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.496155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.496170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.496186] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.496201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.496215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.496228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.496241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.496244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.496256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.496260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.496272] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.496285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.496297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.496309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.496324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.496337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.496350] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.496362] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.496379] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.496398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.496417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.496468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.496486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.496503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.496521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.496538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.496597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.496622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.496645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.496669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.496688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.496708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.496733] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.496754] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.498744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.498762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.498779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.498798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.500302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.500318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.500333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.501829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.501845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.503650] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.506587] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.506614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.506631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.506653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.506731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.506765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.506815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.523535] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.523573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.523593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.523614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.523631] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.523649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.523668] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.523684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.523705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.523725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.523745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.523749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.523769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.523773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.523793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.523814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.523834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.523854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.523874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.523894] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.523915] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.523936] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.523956] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.523977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.523998] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.540162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.540186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.540230] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.559111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.559130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.559150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.559167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.559183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.559197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.559212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.559228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.559245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.559261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.559276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.559290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.559304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.559331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.559350] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.559368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.559523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.559539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.559602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.559629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.559650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.559672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.559694] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.559716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.559737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.559757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.559777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.559783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.559802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.559807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.559829] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.559849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.559869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.559888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.559912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.559928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.559942] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.559955] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.559967] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.559983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.559999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.560047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.560062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.560079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.560098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.560115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.560134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.560153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.560172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.560192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.560209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.560227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.560246] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.560264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.562244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.562262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.562279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.562298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.563810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.563827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.563844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.565339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.565356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.567163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.570103] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.570129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.570145] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.570167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.570246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.570280] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.570328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.587044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.587065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.587084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.587105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.587121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.587140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.587158] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.587175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.587192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.587208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.587223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.587227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.587242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.587246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.587262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.587277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.587292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.587306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.587324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.587339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.587355] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.587369] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.587384] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.587401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.587419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.603676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.603701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.603747] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.622614] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.622633] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.622653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.622670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.622685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.622700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.622715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.622731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.622748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.622763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.622779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.622793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.622807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.622834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.622852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.622870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.623046] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.623062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.623080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.623099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.623114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.623131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.623147] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.623163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.623182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.623206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.623219] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.623223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.623236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.623239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.623252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.623266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.623278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.623291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.623306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.623319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.623332] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.623345] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.623357] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.623372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.623388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.623435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.623449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.623462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.623475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.623492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.623510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.623529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.623548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.623603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.623625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.623645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.623669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.623690] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.625680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.625696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.625710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.625725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.627230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.627246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.627263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.628760] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.628776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.630581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.633516] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.633543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.633592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.633629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.633723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.633758] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.633812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.650453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.650472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.650491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.650511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.650526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.650544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.650605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.650631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.650657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.650682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.650706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.650711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.650726] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.650730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.650745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.650759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.650773] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.650787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.650803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.650818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.650832] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.650847] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.650861] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.650878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.650895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.667054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.667078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.667114] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.685989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.686009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.686029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.686045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.686060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.686075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.686089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.686105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.686122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.686138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.686154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.686168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.686182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.686210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.686231] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.686255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.686433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.686453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.686473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.686495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.686511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.686531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.686551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.686625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.686652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.686676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.686700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.686706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.686728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.686734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.686757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.686779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.686802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.686824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.686849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.686871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.686895] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.686917] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.686939] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.686964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.686989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.687304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.687327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.687351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.687373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.687395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.687417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.687442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.687466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.687490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.687512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.687533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.687558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.687598] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.689719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.689736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.689750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.689764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.691267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.691283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.691297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.692794] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.692811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.694617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.697553] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.697595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.697612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.697634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.697712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.697747] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.697804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.714497] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.714518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.714538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.714559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.714618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.714643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.714662] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.714678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.714694] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.714708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.714727] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.714731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.714751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.714755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.714775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.714794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.714815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.714834] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.714854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.714873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.714893] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.714912] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.714932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.714952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.714973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.731091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.731115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.731151] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.750043] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.750062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.750082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.750098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.750114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.750129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.750143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.750158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.750175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.750191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.750207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.750221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.750235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.750263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.750284] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.750308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.750498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.750517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.750537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.750559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.750622] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.750650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.750675] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.750699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.750722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.750745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.750766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.750773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.750794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.750800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.750822] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.750843] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.750865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.750888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.750913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.750934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.750957] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.750980] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.751003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.751029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.751057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.751139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.751169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.751191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.751210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.751224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.751238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.751254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.751269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.751284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.751297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.751310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.751326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.751341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.753311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.753327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.753341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.753355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.755942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.755961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.755977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.757472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.757488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.759294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.762219] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.762244] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.762260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.762282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.762367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.762399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.762444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.779104] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.779125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.779145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.779166] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.779183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.779201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.779220] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.779237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.779254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.779270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.779285] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.779289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.779304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.779308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.779323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.779339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.779357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.779377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.779398] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.779418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.779439] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.779459] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.779480] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.779501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.779523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.795757] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.795783] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.795829] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.814697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.814715] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.814736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.814752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.814768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.814782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.814797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.814813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.814830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.814846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.814862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.814876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.814890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.814917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.814935] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.814953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.815126] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.815142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.815160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.815180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.815195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.815212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.815228] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.815244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.815259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.815274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.815288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.815292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.815305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.815309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.815323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.815337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.815351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.815364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.815381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.815395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.815409] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.815423] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.815441] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.815461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.815482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.815537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.815556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.815618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.815643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.815666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.815696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.815720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.815743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.815765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.815785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.815804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.815828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.815849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.817839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.817855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.817869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.817883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.819386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.819401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.819415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.820910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.820926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.822731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.825663] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.825688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.825704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.825726] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.825803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.825837] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.825891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.842617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.842636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.842655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.842675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.842691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.842708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.842725] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.842741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.842757] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.842771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.842786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.842790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.842804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.842807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.842821] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.842835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.842849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.842863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.842879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.842893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.842908] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.842922] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.842935] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.842951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.842968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.859205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.859229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.859266] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.878145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.878164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.878184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.878201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.878217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.878232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.878247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.878263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.878280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.878297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.878313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.878327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.878341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.878369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.878387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.878406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.878621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.878645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.878672] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.878700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.878723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.878749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.878911] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.878929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.878945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.878960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.878975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.878980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.878994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.878998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.879013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.879035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.879048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.879061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.879077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.879090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.879104] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.879121] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.879139] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.879158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.879178] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.879230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.879248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.879267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.879284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.879303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.879320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.879340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.879360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.879379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.879396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.879414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.879433] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.879451] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.881423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.881439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.881454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.881469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.882975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.882990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.883004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.884512] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.884528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.886334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.889278] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.889304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.889320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.889342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.889418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.889451] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.889500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.906201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.906223] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.906245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.906268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.906286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.906307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.906327] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.906348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.906368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.906388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.906408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.906412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.906432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.906436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.906457] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.906477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.906497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.906517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.906537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.906557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.906621] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.906646] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.906669] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.906695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.906722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.922808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.922831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.922867] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.941739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.941757] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.941778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.941795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.941810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.941825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.941840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.941858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.941879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.941899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.941919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.941938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.941957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.941990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.942012] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.942035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.942220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.942240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.942260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.942282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.942298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.942318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.942337] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.942356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.942376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.942395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.942413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.942417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.942436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.942440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.942459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.942478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.942497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.942516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.942543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.942559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.942614] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.942637] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.942659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.942682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.942706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.942781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.942969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.942985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.943000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.943014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.943028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.943045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.943060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.943076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.943090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.943104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.943122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.943141] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.945123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.945141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.945158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.945176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.946704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.946722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.946736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.948231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.948248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.950072] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.953012] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.953038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.953054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.953076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.953154] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.953189] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.953238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.969956] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.969976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.969996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.970017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.970035] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.970057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.970077] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.970098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.970118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.970138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.970158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.970163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.970182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.970186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.970207] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.970227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.970247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.970267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.970287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.970307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.970328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.970348] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.970368] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.970395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.970424] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.986600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.986624] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.986669] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.005522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.005541] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.005561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.005619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.005646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.005670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.005694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.005718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.005737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.005753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.005770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.005784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.005799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.005827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.005845] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.005864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.006024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.006038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.006055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.006073] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.006087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.006105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.006123] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.006142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.006160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.006178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.006194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.006199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.006216] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.006220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.006238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.006256] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.006274] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.006291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.006310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.006327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.006346] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.006364] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.006382] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.006400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.006419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.006470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.006489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.006507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.006526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.006543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.006562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.006602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.006629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.006652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.006673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.006693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.006718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.006739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.008729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.008746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.008760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.008775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.010278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.010293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.010306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.011802] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.011817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.013621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.016543] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.016569] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.016622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.016659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.016751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.016786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.016834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.033444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.033463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.033482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.033501] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.033517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.033534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.033553] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.033572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.033631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.033656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.033678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.033685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.033709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.033716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.033741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.033765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.033789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.033812] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.033838] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.033862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.033886] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.033903] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.033917] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.033937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.033958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.050045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.050069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.050105] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.068978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.068997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.069017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.069034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.069049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.069068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.069087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.069106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.069127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.069148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.069168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.069187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.069205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.069238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.069260] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.069284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.069471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.069491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.069511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.069533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.069549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.069569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.069630] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.069660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.069687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.069712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.069737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.069744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.069767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.069774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.069798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.069822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.069847] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.069870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.069897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.069921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.069947] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.069971] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.069995] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.070022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.070051] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.070406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.070430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.070453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.070475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.070496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.070518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.070543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.070565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.070614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.070636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.070659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.070685] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.070708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.072695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.072711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.072725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.072739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.074244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.074259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.074273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.075769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.075784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.077603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.080540] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.080567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.080625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.080663] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.080752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.080787] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.080840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.097490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.097510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.097530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.097552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.097572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.097631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.097658] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.097686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.097712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.097737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.097762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.097769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.097792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.097798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.097823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.097846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.097870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.097891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.097916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.097939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.097964] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.097984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.098007] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.098032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.098060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.114075] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.114101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.114139] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.133009] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.133028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.133048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.133065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.133080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.133095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.133109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.133125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.133142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.133158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.133173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.133187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.133201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.133228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.133247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.133265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.133425] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.133441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.133459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.133478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.133494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.133510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.133526] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.133541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.133556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.133570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.133628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.133636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.133662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.133668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.133692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.133723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.133745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.133767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.133791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.133813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.133837] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.133858] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.133880] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.133905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.133930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.134236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.134259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.134282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.134304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.134326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.134347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.134372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.134396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.134420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.134441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.134462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.134486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.134509] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.136499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.136515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.136529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.136544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.138050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.138065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.138078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.139573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.139600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.141402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.144327] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.144352] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.144368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.144390] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.144468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.144502] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.144551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.161232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.161254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.161275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.161298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.161316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.161338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.161358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.161378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.161399] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.161419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.161439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.161443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.161463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.161467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.161487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.161508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.161528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.161548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.161568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.161588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.161653] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.161683] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.161709] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.161737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.161766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.177825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.177849] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.177885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.196760] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.196779] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.196799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.196816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.196832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.196847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.196861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.196877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.196894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.196911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.196927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.196941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.196955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.196983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.197001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.197024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.197212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.197231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.197251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.197273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.197289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.197309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.197328] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.197348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.197367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.197386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.197404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.197409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.197427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.197431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.197450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.197469] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.197488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.197507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.197526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.197545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.197564] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.197583] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.197644] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.197675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.197705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.197788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.197814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.197839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.197864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.197888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.198179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.198204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.198229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.198253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.198275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.198296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.198321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.198345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.200339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.200355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.200369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.200384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.201890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.201905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.201918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.203409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.203425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.205230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.208169] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.208196] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.208212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.208234] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.208312] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.208351] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.208396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.225102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.225122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.225143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.225163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.225180] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.225199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.225217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.225237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.225258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.225278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.225298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.225302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.225322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.225326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.225346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.225367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.225387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.225407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.225428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.225447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.225469] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.225489] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.225509] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.225530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.225552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.241742] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.241766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.241810] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.260664] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.260683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.260703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.260720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.260736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.260750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.260765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.260781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.260798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.260814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.260829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.260843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.260857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.260885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.260903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.260921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.261189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.261213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.261240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.261268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.261291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.261315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.261340] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.261363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.261387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.261409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.261431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.261436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.261458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.261463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.261485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.261514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.261533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.261552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.261575] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.261595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.261650] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.261671] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.261691] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.261715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.261740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.261812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.261833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.261854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.261874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.261895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.261915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.261932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.261946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.261961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.261973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.261986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.262002] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.262016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.264002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.264019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.264034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.264052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.265575] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.265593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.265649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.267150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.267166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.268982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.271911] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.271937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.271954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.271975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.272055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.272089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.272139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.288816] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.288837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.288857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.288878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.288895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.288913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.288933] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.288954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.288974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.288994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.289014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.289019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.289039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.289042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.289063] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.289083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.289104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.289124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.289144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.289164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.289185] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.289205] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.289225] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.289246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.289268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.305441] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.305465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.305511] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.324331] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.324350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.324370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.324387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.324402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.324417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.324432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.324448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.324465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.324480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.324500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.324519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.324538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.324571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.324593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.324658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.324964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.324991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.325026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.325054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.325075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.325091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.325107] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.325121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.325135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.325148] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.325161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.325165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.325177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.325180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.325193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.325206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.325223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.325240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.325257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.325274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.325293] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.325310] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.325327] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.325346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.325364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.325416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.325434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.325452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.325470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.325487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.325505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.325523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.325542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.325561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.325578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.325595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.325639] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.325667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.327659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.327677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.327694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.327712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.329226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.329245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.329262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.330765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.330782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.332593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.335539] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.335566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.335583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.335652] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.335828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.335852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.335885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.352472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.352492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.352513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.352534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.352551] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.352569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.352587] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.352648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.352677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.352702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.352728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.352735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.352759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.352766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.352790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.352815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.352838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.352862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.352886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.352909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.352934] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.352957] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.352978] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.353004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.353031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.369085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.369111] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.369149] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.387367] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.387385] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.387406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.387423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.387439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.387454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.387469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.387485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.387502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.387517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.387533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.387547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.387565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.387598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.387658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.387691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.387986] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.388009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.388036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.388065] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.388088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.388113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.388137] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.388162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.388184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.388207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.388228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.388234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.388256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.388261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.388285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.388306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.388328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.388348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.388374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.388395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.388418] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.388438] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.388467] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.388488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.388512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.388575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.388596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.388637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.388660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.388681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.388702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.388726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.388750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.388774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.388793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.388814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.388840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.388862] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.391950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.391969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.391986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.392002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.395701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.395719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.395733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.397228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.397245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.399053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.402001] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.402028] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.402045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.402067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.402145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.402179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.402229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.418960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.418980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.418999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.419018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.419034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.419051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.419070] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.419089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.419108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.419127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.419146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.419150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.419169] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.419172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.419192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.419211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.419230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.419248] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.419267] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.419286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.419306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.419325] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.419344] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.419364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.419384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.435526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.435549] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.435592] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.454480] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.454499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.454519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.454536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.454551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.454566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.454580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.454596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.454654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.454680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.454707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.454729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.454753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.454797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.454825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.454854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.455125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.455149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.455174] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.455192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.455207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.455222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.455237] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.455251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.455265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.455278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.455290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.455294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.455306] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.455309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.455322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.455335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.455347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.455359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.455374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.455387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.455400] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.455412] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.455424] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.455439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.455455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.455503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.455517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.455530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.455547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.455565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.455583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.455602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.455645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.455672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.455693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.455715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.455742] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.455764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.457755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.457771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.457785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.457799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.459300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.459315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.459329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.460824] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.460839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.462649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.465584] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.465647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.465672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.465774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.465854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.465889] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.465940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.482547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.482566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.482584] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.482604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.482658] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.482685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.482712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.482737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.482763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.482785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.482962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.482966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.482981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.482985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.483000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.483019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.483038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.483057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.483076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.483095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.483115] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.483134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.483153] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.483173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.483194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.499124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.499149] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.499195] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.518076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.518095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.518115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.518132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.518147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.518162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.518177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.518192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.518209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.518225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.518241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.518256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.518270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.518297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.518315] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.518334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.518508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.518527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.518547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.518569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.518586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.518605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.518663] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.518688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.518712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.518735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.518757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.518764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.518785] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.518791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.518814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.518836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.518857] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.518878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.518903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.518925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.518948] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.518969] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.518991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.519017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.519044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.519118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.519134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.519148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.519163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.519177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.519192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.519209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.519225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.519240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.519254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.519268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.519286] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.519302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.521280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.521298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.521315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.521333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.522844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.522861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.522875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.524368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.524384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.526189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.529112] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.529138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.529154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.529176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.529253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.529288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.529336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.546045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.546065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.546083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.546103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.546119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.546136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.546153] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.546169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.546184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.546199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.546214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.546218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.546232] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.546236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.546251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.546265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.546279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.546292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.546309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.546323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.546338] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.546352] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.546365] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.546381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.546399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.562611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.562650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.562694] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.581559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.581578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.581598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.581658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.581684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.581708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.581733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.581755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.581774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.581790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.581807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.581825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.581845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.581878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.581900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.581924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.582091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.582111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.582131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.582153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.582169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.582189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.582208] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.582227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.582247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.582266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.582284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.582288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.582307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.582310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.582330] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.582349] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.582368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.582387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.582406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.582424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.582444] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.582463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.582482] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.582502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.582522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.582578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.582598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.582647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.582672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.582695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.582719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.582746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.582771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.582802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.582822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.582842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.582865] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.582887] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.584877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.584893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.584907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.584922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.586424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.586440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.586453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.587949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.587965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.589770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.592711] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.592737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.592754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.592776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.592854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.592888] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.592938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.609693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.609712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.609731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.609750] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.609766] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.609783] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.609800] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.609816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.609831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.609846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.609860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.609864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.609878] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.609882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.609896] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.609910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.609923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.609936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.609953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.609967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.609982] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.609996] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.610009] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.610026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.610043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.626243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.626266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.626310] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.645163] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.645181] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.645201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.645218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.645234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.645249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.645264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.645280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.645297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.645313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.645329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.645343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.645358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.645385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.645403] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.645422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.645596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.645612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.645674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.645702] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.645725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.645751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.645775] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.645798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.645820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.645843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.645864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.645871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.645893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.645899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.645922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.645943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.645965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.645986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.646012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.646035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.646059] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.646082] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.646105] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.646132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.646159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.646238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.646253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.646266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.646279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.646292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.646306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.646322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.646336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.646351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.646364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.646377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.646393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.646407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.648379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.648395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.648409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.648423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.649930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.649946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.649960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.651452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.651469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.653276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.656199] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.656224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.656240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.656262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.656339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.656374] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.656428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.673127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.673146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.673165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.673184] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.673200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.673217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.673234] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.673250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.673266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.673280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.673299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.673303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.673322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.673326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.673345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.673364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.673383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.673402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.673421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.673440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.673460] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.673479] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.673498] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.673517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.673537] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.689699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.689722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.689767] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.708645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.708664] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.708684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.708701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.708717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.708732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.708747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.708763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.708779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.708795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.708811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.708825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.708839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.708871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.708893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.708916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.709094] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.709114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.709134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.709156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.709173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.709192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.709212] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.709231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.709250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.709269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.709288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.709292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.709310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.709314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.709333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.709352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.709371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.709390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.709409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.709427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.709447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.709466] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.709485] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.709505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.709526] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.709581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.709601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.709620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.709674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.709698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.709720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.709743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.709767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.709790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.709810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.709829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.709853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.709875] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.711866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.711882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.711896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.711910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.713413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.713429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.713446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.714944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.714960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.717868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.720812] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.720839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.720856] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.720883] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.720956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.720988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.721033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.737779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.737798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.737817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.737836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.737852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.737869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.737886] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.737901] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.737917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.737931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.737945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.737949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.737963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.737966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.737981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.737995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.738008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.738026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.738046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.738065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.738084] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.738104] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.738123] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.738143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.738163] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.754342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.754366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.754402] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.772334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.772353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.772373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.772390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.772405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.772420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.772434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.772450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.772467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.772484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.772499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.772514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.772528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.772555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.772573] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.772592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.772937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.772955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.772974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.772994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.773010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.773027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.773044] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.773067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.773081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.773095] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.773108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.773112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.773125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.773128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.773142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.773155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.773168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.773180] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.773196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.773213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.773232] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.773250] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.773268] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.773287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.773307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.773359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.773378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.773396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.773415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.773433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.773451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.773471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.773489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.773509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.773526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.773545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.773563] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.773582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.775573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.775589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.775604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.775620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.777224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.777241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.777259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.778763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.778781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.780583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.783519] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.783547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.783563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.783585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.783697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.783732] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.783785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.800445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.800466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.800486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.800507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.800525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.800546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.800567] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.800587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.800608] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.800628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.800688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.800697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.800724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.800731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.800757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.800783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.800808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.800833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.800861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.800885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.800911] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.800935] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.800960] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.800987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.801014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.817056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.817080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.817116] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.835992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.836011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.836031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.836048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.836064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.836079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.836093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.836109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.836126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.836142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.836158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.836172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.836186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.836213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.836231] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.836250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.836423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.836439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.836457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.836476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.836491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.836507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.836530] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.836544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.836558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.836571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.836584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.836587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.836600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.836603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.836616] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.836668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.836690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.836713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.836737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.836760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.836784] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.836806] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.836828] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.836853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.836878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.836952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.836975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.836998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.837020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.837042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.837064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.837088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.837112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.837135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.837154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.837175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.837198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.837220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.839227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.839243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.839258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.839272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.840780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.840795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.840808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.842299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.842315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.844136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.847079] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.847104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.847120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.847142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.847220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.847254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.847302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.864019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.864040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.864060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.864081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.864097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.864116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.864134] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.864151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.864168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.864184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.864199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.864203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.864218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.864221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.864237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.864252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.864267] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.864282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.864299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.864314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.864330] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.864345] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.864360] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.864377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.864396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.880665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.880691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.880738] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.899602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.899623] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.899689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.899720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.899746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.899772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.899796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.899822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.899849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.899875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.899901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.899925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.899948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.899992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.900027] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.900056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.900233] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.900248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.900265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.900284] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.900298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.900314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.900329] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.900344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.900358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.900371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.900384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.900388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.900401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.900405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.900418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.900432] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.900444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.900457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.900472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.900485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.900499] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.900512] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.900524] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.900539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.900556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.900604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.900618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.900663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.900685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.900709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.900732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.900758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.900783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.900809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.900831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.900855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.900881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.900905] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.902899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.902915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.902929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.902944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.904446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.904462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.904475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.905970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.905987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.907793] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.910730] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.910758] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.910777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.910803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.910884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.910920] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.910969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.927685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.927704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.927722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.927742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.927757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.927775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.927792] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.927808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.927824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.927839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.927853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.927857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.927871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.927874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.927889] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.927903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.927917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.927931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.927947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.927961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.927976] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.927990] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.928004] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.928020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.928037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.944267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.944291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.944326] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.963203] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.963222] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.963242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.963259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.963274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.963289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.963303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.963319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.963336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.963353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.963372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.963392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.963411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.963444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.963466] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.963489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.963868] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.963896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.963924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.963953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.963978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.964004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.964031] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.964056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.964081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.964105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.964128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.964135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.964157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.964164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.964188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.964211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.964234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.964257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.964283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.964307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.964332] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.964355] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.964376] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.964401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.964434] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.964508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.964530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.964552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.964573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.964594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.964616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.964662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.964686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.964711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.964733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.964755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.964781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.964805] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.967016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.967032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.967046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.967061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.968582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.968597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.968611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.970136] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.970152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.971986] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.974932] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.974958] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.974975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.974997] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.975076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.975110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.975160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.991872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.991894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.991915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.991939] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.991957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.991978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.991999] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.992019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.992040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.992060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.992080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.992084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.992104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.992107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.992128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.992148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.992168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.992188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.992209] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.992229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.992250] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.992270] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.992290] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.992311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.992333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.008498] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.008523] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.008567] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.027411] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.027430] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.027450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.027467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.027483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.027498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.027513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.027529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.027546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.027561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.027577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.027591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.027605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.027632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.027692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.027724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.028086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.028105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.028125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.028146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.028162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.028182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.028200] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.028219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.028238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.028256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.028274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.028278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.028296] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.028300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.028319] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.028337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.028355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.028373] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.028392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.028410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.028429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.028448] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.028466] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.028485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.028505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.028559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.028578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.028597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.028616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.028634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.028679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.028711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.028737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.028764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.028785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.028808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.028840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.028863] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.031104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.031120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.031134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.031149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.032676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.032692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.032706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.035329] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.035347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.037156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.040098] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.040123] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.040139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.040163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.040239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.040273] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.040321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.057026] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.057046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.057065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.057085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.057104] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.057124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.057143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.057162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.057181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.057200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.057219] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.057223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.057242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.057245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.057265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.057284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.057303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.057321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.057341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.057359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.057379] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.057398] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.057417] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.057437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.057457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.073683] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.073707] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.073752] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.092618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.092637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.092696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.092721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.092747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.092770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.092903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.092920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.092938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.092954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.092970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.092985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.092999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.093030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.093053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.093076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.093263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.093282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.093303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.093332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.093348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.093365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.093381] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.093396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.093410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.093423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.093436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.093439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.093452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.093455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.093473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.093490] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.093508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.093525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.093542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.093559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.093577] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.093595] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.093612] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.093630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.093675] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.093753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.093778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.093800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.093822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.094053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.094075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.094100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.094124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.094147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.094167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.094187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.094210] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.094232] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.096232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.096248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.096262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.096276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.097796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.097815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.097832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.099331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.099349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.101163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.104100] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.104127] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.104144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.104166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.104220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.104242] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.104275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.121072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.121094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.121116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.121139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.121157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.121178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.121199] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.121219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.121240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.121260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.121280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.121284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.121304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.121307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.121328] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.121348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.121369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.121388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.121409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.121429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.121450] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.121470] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.121490] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.121511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.121533] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.137636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.137676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.137712] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.156579] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.156598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.156618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.156636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.156696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.156721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.156748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.156773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.156802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.156828] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.156854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.156878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.156901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.156945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.156974] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.157004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.157219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.157239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.157259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.157281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.157297] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.157317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.157336] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.157355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.157375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.157393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.157412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.157416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.157435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.157439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.157458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.157477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.157496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.157515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.157534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.157552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.157572] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.157591] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.157610] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.157630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.157684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.157770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.157795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.157820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.157842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.157865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.157888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.157913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.157937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.157961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.157982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.158002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.158026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.158049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.160047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.160064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.160082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.160100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.161609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.161626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.161640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.163184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.163203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.165098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.168037] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.168063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.168080] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.168101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.168155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.168176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.168209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.185012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.185034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.185055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.185079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.185097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.185118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.185138] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.185158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.185179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.185199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.185218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.185223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.185243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.185246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.185267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.185287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.185308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.185328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.185348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.185368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.185389] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.185409] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.185429] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.185451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.185472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.201579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.201605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.201643] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.220555] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.220574] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.220594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.220611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.220627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.220641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.220694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.220720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.220747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.220776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.220802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.220823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.220847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.220892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.220920] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.220949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.221231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.221247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.221264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.221281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.221295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.221310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.221326] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.221340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.221354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.221367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.221380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.221383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.221396] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.221399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.221412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.221424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.221437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.221449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.221464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.221477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.221490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.221503] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.221515] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.221530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.221546] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.221594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.221608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.221622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.221637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.221677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.221702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.221726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.221751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.221775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.221795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.221817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.221843] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.221864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.223857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.223874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.223888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.223903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.225406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.225421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.225435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.226931] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.226946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.228752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.231697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.231725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.231744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.231770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.231851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.231887] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.231936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.248637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.248673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.248693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.248715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.248731] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.248751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.248771] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.248790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.248809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.248828] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.248847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.248851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.248869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.248873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.248892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.248911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.248930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.248949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.248968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.248986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.249006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.249025] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.249044] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.249064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.249084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.265234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.265258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.265294] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.283456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.283475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.283495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.283511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.283527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.283541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.283556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.283572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.283592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.283612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.283633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.283652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.283706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.283756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.283928] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.283960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.284168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.284185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.284203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.284223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.284238] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.284255] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.284272] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.284287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.284303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.284317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.284331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.284335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.284349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.284353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.284372] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.284391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.284410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.284429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.284448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.284467] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.284486] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.284511] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.284526] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.284542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.284561] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.284613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.284631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.284648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.284691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.284718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.284740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.284765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.284790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.284814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.284834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.284855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.284882] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.284904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.287131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.287147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.287161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.287176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.288709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.288725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.288742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.290248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.290267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.292082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.295032] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.295059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.295076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.295098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.295152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.295175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.295207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.311993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.312014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.312034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.312056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.312076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.312097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.312118] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.312138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.312159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.312180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.312199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.312204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.312224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.312227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.312248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.312268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.312288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.312308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.312329] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.312348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.312370] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.312390] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.312410] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.312432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.312453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.328563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.328587] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.328623] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.347510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.347530] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.347550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.347566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.347582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.347597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.347612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.347628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.347648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.347711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.347742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.347767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.347792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.347837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.347866] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.347896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.348144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.348160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.348176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.348195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.348209] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.348225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.348241] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.348255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.348269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.348283] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.348296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.348299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.348312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.348315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.348328] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.348341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.348354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.348366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.348382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.348395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.348413] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.348431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.348449] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.348467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.348487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.348540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.348559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.348577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.348595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.348613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.348631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.348651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.348701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.348731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.348755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.348780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.348808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.348833] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.350833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.350849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.350864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.350878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.352385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.352401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.352414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.353913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.353928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.355735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.358655] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.358690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.358706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.358728] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.358783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.358805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.358837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.375579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.375601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.375623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.375646] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.375710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.375743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.375773] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.375799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.375825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.375849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.375873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.375879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.375902] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.375908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.375932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.375955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.375978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.376001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.376025] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.376048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.376072] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.376095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.376116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.376141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.376169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.392164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.392188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.392225] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.410435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.410453] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.410473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.410490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.410509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.410529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.410548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.410567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.410588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.410608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.410628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.410647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.410708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.410756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.410787] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.410819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.411029] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.411046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.411065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.411085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.411101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.411118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.411135] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.411151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.411166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.411181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.411195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.411200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.411218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.411222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.411242] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.411261] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.411281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.411300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.411319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.411338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.411366] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.411383] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.411399] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.411415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.411433] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.411483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.411498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.411512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.411530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.411548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.411566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.411585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.411603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.411623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.411640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.411659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.411701] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.411725] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.413716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.413732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.413746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.413761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.415268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.415285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.415303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.416805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.416821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.418667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.421610] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.421638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.421657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.421721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.421816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.421851] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.421905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.438558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.438579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.438598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.438619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.438636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.438654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.438713] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.438738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.438764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.438786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.438811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.438818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.438841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.438848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.438871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.438892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.438916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.438937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.438963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.438984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.439008] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.439029] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.439051] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.439074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.439100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.455157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.455183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.455221] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.473610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.473628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.473649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.473665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.473720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.473746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.473769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.473795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.473823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.473996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.474014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.474028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.474043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.474070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.474089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.474108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.474270] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.474287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.474305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.474324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.474340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.474356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.474372] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.474387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.474402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.474416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.474430] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.474434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.474447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.474451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.474465] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.474479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.474493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.474506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.474522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.474536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.474550] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.474564] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.474577] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.474593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.474611] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.474663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.474712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.474738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.474758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.474780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.474801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.474825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.474849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.474874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.474893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.474915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.474941] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.474962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.477228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.477247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.477264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.477282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.478795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.478811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.478828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.480322] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.480338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.482160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.485116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.485144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.485163] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.485189] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.485270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.485306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.485356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.502028] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.502048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.502067] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.502089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.502106] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.502126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.502145] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.502164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.502183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.502202] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.502221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.502225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.502244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.502247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.502267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.502286] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.502305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.502323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.502342] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.502361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.502381] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.502400] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.502419] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.502439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.502459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.518642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.518667] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.518776] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.537652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.537670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.537729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.537755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.537780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.537803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.537826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.537849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.537875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.537900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.537925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.537946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.537969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.538012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.538040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.538069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.538285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.538300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.538317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.538335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.538349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.538364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.538379] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.538393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.538406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.538419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.538432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.538435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.538447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.538451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.538463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.538476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.538488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.538500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.538515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.538528] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.538541] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.538554] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.538566] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.538580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.538596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.538644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.538658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.538697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.538721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.538741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.538764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.538789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.538814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.538838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.538857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.538878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.538904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.538926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.540916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.540932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.540946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.540960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.542463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.542479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.542492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.543988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.544004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.545806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.548756] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.548783] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.548800] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.548822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.548880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.548902] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.548935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.565710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.565731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.565753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.565776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.565794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.565815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.565836] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.565856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.565877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.565897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.565917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.565921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.565941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.565945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.565966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.565986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.566006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.566026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.566046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.566066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.566087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.566108] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.566128] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.566149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.566170] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.582289] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.582313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.582350] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.601213] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.601232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.601252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.601269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.601285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.601304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.601323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.601342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.601363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.601384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.601404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.601423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.601441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.601474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.601497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.601520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.601727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.601756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.601786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.601815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.601840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.601868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.601894] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.601920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.601944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.601969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.601992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.601999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.602022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.602029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.602051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.602073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.602097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.602120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.602145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.602168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.602192] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.602214] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.602234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.602259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.602285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.602363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.602387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.602408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.602431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.602453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.602477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.602503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.602528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.602553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.602576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.602606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.602631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.602654] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.604666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.604695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.604712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.604730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.606254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.606271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.606285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.607788] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.607806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.609621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.612556] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.612583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.612600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.612622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.612727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.612770] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.612909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.629503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.629523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.629543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.629564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.629581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.629599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.629617] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.629635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.629651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.629667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.629720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.629730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.629754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.629760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.629785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.629807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.629831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.629853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.629879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.629902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.629926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.630182] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.630203] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.630230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.630258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.646133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.646158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.646202] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.665054] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.665073] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.665093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.665110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.665125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.665141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.665155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.665171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.665192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.665213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.665233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.665252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.665271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.665304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.665326] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.665350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.665537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.665557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.665576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.665598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.665615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.665634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.665654] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.665673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.665735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.665761] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.665787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.665794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.665818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.665824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.665849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.665871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.665895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.665924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.665949] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.665969] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.665992] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.666012] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.666033] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.666058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.666084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.666159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.666179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.666200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.666219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.666239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.666259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.666282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.666306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.666329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.666348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.666368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.666392] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.666413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.669505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.669525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.669544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.669564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.671075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.671091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.671108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.672625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.672643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.674451] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.677388] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.677416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.677432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.677454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.677532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.677567] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.677617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.694329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.694349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.694370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.694390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.694407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.694426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.694444] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.694461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.694478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.694494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.694509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.694513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.694528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.694531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.694547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.694563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.694578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.694592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.694610] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.694625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.694641] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.694655] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.694670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.694728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.694754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.710934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.710958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.710995] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.729867] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.729887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.729909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.729929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.729948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.729967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.729986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.730005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.730026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.730046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.730067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.730085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.730104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.730137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.730159] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.730182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.730357] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.730377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.730397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.730426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.730443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.730460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.730476] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.730492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.730506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.730519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.730532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.730535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.730548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.730551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.730564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.730576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.730589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.730601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.730616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.730629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.730642] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.730655] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.730667] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.730718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.730744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.730818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.730841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.730862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.730884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.730905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.730927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.730951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.731232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.731257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.731277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.731298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.731321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.731343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.733333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.733349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.733364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.733378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.734885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.734900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.734913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.736404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.736420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.738227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.741151] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.741176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.741193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.741214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.741293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.741327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.741376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.758058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.758078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.758098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.758118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.758135] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.758153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.758171] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.758191] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.758212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.758232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.758252] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.758256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.758276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.758280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.758301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.758321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.758341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.758361] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.758381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.758401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.758422] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.758443] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.758463] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.758484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.758505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.774687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.774729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.774776] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.793629] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.793648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.793668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.793685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.793741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.793766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.793791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.793814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.793842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.793867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.793894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.793915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.793938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.793980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.794008] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.794037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.794262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.794279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.794296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.794315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.794331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.794347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.794364] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.794380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.794395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.794409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.794423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.794427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.794441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.794444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.794459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.794477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.794497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.794516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.794535] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.794554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.794573] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.794592] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.794611] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.794632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.794652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.794743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.794771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.794795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.794828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.794849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.794872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.794897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.794921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.794945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.794965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.794987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.795013] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.795035] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.797026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.797043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.797058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.797076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.798583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.798598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.798613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.800108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.800124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.801927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.804867] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.804894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.804911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.804933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.805011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.805052] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.805098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.821808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.821828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.821848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.821869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.821886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.821904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.821923] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.821940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.821957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.821973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.821989] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.821992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.822008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.822011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.822031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.822052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.822072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.822092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.822113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.822133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.822154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.822175] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.822195] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.822216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.822238] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.838441] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.838467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.838513] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.857379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.857398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.857418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.857435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.857450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.857465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.857479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.857495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.857512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.857528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.857544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.857558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.857572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.857600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.857618] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.857636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.857933] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.857959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.857984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.858013] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.858036] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.858061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.858084] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.858108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.858130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.858153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.858174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.858180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.858201] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.858207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.858230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.858250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.858273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.858293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.858324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.858343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.858364] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.858383] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.858402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.858424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.858447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.858519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.858540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.858560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.858579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.858600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.858619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.858642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.858665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.858688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.858727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.858747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.858772] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.858794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.860783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.860799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.860813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.860828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.862338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.862353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.862367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.863865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.863881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.865687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.868621] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.868648] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.868667] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.868728] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.868907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.868931] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.868966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.885532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.885553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.885574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.885598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.885616] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.885637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.885657] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.885678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.885729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.885759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.885782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.885791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.885814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.885821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.885846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.885868] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.885892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.885913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.885940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.885962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.885987] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.886008] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.886030] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.886053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.886079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.902132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.902158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.902196] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.921064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.921082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.921103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.921119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.921135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.921149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.921168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.921187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.921208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.921228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.921249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.921267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.921286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.921319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.921341] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.921365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.921546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.921565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.921585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.921607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.921623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.921650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.921668] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.921684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.921736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.921760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.921782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.921789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.921810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.921816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.921840] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.921860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.921882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.921901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.921925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.921945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.921968] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.921987] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.922009] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.922034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.922060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.922406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.922428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.922449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.922469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.922491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.922511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.922534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.922557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.922580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.922599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.922619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.922641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.922664] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.924670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.924686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.924731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.924756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.926265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.926280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.926293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.927790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.927806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.929636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.932572] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.932600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.932617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.932639] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.932735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.932770] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.932828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.949506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.949526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.949546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.949567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.949584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.949602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.949620] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.949638] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.949654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.949670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.949686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.949725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.949750] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.949756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.949781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.949804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.949828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.949850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.949876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.949898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.949923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.949945] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.949968] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.949994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.950020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.966118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.966142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.966179] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.984620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.984639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.984660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.984680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.984736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.984763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.984789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.984814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.984842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.985024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.985041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.985056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.985074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.985106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.985127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.985150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.985329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.985348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.985367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.985388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.985404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.985423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.985442] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.985461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.985479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.985497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.985515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.985519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.985537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.985541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.985560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.985578] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.985596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.985614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.985633] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.985651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.985670] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.985688] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.985736] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.985768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.985794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.985875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.986127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.986149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.986170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.986191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.986211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.986235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.986258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.986282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.986301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.986322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.986345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.986367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.988365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.988382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.988397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.988412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.991003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.991021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.991036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.992536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.992553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.994359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.997291] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.997316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.997332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.997353] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.997428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.997461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.997510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.014239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.014258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.014277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.014298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.014316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.014336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.014355] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.014374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.014394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.014412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.014431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.014435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.014453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.014457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.014476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.014496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.014514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.014533] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.014552] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.014571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.014591] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.014610] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.014629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.014649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.014669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.030842] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.030866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.030901] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.049777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.049796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.049816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.049833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.049849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.049864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.049878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.049894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.049911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.049927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.049943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.049957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.049971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.049998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.050016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.050035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.050189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.050205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.050223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.050242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.050257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.050273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.050289] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.050304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.050319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.050334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.050347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.050351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.050365] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.050368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.050387] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.050406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.050425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.050444] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.050464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.050483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.050502] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.050528] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.050545] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.050561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.050580] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.050631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.050649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.050667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.050684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.050734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.050762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.050788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.050814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.050839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.050859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.050881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.050907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.050929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.052923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.052939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.052954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.052968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.054471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.054487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.054500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.055996] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.056013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.057817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.060753] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.060778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.060795] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.060816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.060894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.060929] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.060977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.077699] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.077738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.077759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.077783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.077801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.077821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.077842] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.077862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.077883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.077903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.077923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.077927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.077947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.077951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.077971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.077992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.078012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.078032] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.078052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.078072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.078093] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.078113] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.078133] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.078155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.078176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.094329] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.094353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.094398] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.113265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.113284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.113304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.113323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.113343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.113362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.113381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.113400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.113421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.113441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.113461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.113480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.113499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.113532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.113554] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.113577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.113842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.113870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.113898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.113928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.113953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.113984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.114008] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.114029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.114051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.114070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.114091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.114096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.114116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.114121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.114142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.114161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.114182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.114201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.114224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.114243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.114264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.114283] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.114303] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.114324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.114348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.114420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.114441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.114461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.114481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.114500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.114522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.114545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.114567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.114590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.114609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.114629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.114651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.114673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.116683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.116699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.116743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.116770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.118278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.118293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.118307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.119807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.119824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.121657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.124593] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.124620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.124637] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.124659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.124770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.124805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.124857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.141543] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.141563] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.141583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.141607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.141625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.141646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.141667] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.141687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.141707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.141768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.141793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.141801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.141825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.141832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.141858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.141882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.141906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.141928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.141955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.141977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.142001] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.142023] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.142046] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.142072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.142099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.158139] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.158163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.158199] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.176793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.176813] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.176833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.176850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.176866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.176881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.176896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.176912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.176930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.176946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.176961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.176976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.176990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.177017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.177035] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.177054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.177216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.177232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.177250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.177272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.177289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.177309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.177328] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.177348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.177367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.177386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.177404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.177408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.177427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.177431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.177456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.177472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.177486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.177499] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.177516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.177533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.177551] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.177568] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.177586] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.177604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.177623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.177674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.177692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.177737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.177765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.177787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.177811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.177837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.177863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.177887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.177908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.177929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.177955] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.177977] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.179970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.179987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.180001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.180019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.181523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.181539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.181553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.183048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.183064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.184868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.187818] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.187845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.187865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.187891] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.187971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.188007] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.188057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.204774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.204793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.204812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.204832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.204847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.204864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.204881] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.204897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.204913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.204927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.204941] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.204945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.204959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.204962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.204977] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.204991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.205004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.205018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.205034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.205048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.205063] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.205076] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.205090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.205106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.205123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.221380] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.221406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.221452] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.240317] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.240336] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.240358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.240378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.240397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.240416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.240436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.240455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.240475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.240495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.240516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.240534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.240553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.240586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.240608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.240632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.240925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.240948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.240973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.241000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.241021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.241044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.241066] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.241088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.241109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.241129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.241148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.241154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.241174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.241179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.241201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.241220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.241241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.241260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.241282] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.241301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.241323] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.241342] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.241362] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.241383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.241407] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.241479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.241500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.241520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.241540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.241560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.241580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.241603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.241625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.241648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.241667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.241687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.241709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.241749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.243740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.243756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.243770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.243784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.245289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.245307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.245324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.246822] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.246839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.248657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.251587] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.251614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.251633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.251659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.251763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.251802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.251971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.268477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.268499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.268520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.268544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.268562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.268583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.268603] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.268624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.268644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.268664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.268684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.268688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.268708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.268747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.268777] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.268802] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.268828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.268851] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.268878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.268901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.268927] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.268949] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.268974] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.268999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.269025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.285118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.285143] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.285187] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.304054] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.304075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.304097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.304117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.304136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.304156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.304175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.304194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.304215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.304235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.304255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.304274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.304293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.304326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.304348] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.304371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.304553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.304570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.304586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.304604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.304618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.304633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.304649] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.304663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.304677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.304691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.304704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.304740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.304762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.304768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.304791] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.304811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.304833] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.304852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.304877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.304897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.304919] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.304939] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.304960] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.304985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.305010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.305084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.305106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.305129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.305152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.305173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.305196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.305220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.305244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.305267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.305288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.305309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.305333] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.305356] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.307349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.307367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.307385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.307403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.308912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.308928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.308942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.310436] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.310453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.312259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.315182] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.315207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.315224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.315246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.315324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.315358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.315407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.332091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.332113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.332135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.332158] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.332176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.332197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.332217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.332237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.332258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.332278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.332298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.332302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.332322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.332326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.332347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.332367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.332387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.332407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.332428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.332447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.332468] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.332489] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.332509] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.332530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.332551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.348721] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.348761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.348806] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.367666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.367686] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.367709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.367769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.367795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.367822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.367845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.367870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.367898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.367923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.367949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.367970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.367992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.368035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.368064] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.368093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.368313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.368330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.368348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.368367] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.368383] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.368400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.368417] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.368433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.368448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.368463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.368477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.368480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.368494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.368498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.368512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.368531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.368550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.368569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.368588] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.368607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.368627] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.368646] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.368665] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.368685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.368705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.368808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.368833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.368859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.368883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.368906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.368930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.368963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.368988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.369012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.369031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.369052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.369075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.369098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.371087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.371103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.371117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.371131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.372662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.372677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.372691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.374185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.374201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.376006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.378937] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.378962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.378978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.379000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.379078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.379113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.379170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.395834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.395854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.395874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.395895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.395912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.395930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.395948] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.395965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.395982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.395998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.396017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.396021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.396042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.396045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.396066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.396086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.396107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.396126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.396147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.396167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.396188] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.396208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.396229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.396250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.396271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.412468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.412492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.412537] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.431413] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.431432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.431452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.431469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.431484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.431499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.431513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.431532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.431553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.431574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.431594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.431613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.431631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.431664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.431687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.431710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.432036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.432061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.432089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.432118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.432140] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.432166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.432190] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.432214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.432237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.432260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.432281] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.432287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.432309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.432314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.432337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.432358] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.432381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.432401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.432425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.432453] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.432475] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.432494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.432514] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.432535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.432559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.432631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.432651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.432672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.432691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.432711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.432752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.432777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.432800] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.432824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.432844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.432865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.432890] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.432912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.434901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.434917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.434930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.434945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.436448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.436464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.436482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.437979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.437995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.439798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.442720] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.442760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.442776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.442798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.442877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.442911] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.442960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.459676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.459695] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.459714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.459776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.459800] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.459829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.459853] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.459878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.459901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.459923] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.459944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.459951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.459972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.459977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.460000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.460021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.460043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.460064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.460088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.460109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.460133] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.460153] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.460176] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.460199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.460225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.476310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.476335] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.476380] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.495233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.495252] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.495274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.495293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.495313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.495332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.495351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.495370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.495391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.495411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.495431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.495450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.495469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.495501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.495524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.495547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.495722] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.495778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.495803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.495832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.495854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.495879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.495903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.495926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.495948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.495970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.495990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.495997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.496017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.496023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.496045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.496065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.496086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.496105] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.496130] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.496149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.496172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.496191] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.496211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.496232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.496255] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.496330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.496350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.496371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.496390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.496410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.496430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.496454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.496477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.496499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.496519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.496539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.496562] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.496584] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.498577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.498595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.498613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.498631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.500139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.500155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.500169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.501674] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.501690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.503495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.506419] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.506444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.506460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.506482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.506560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.506595] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.506644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.523319] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.523339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.523359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.523380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.523397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.523415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.523435] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.523456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.523476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.523496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.523516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.523520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.523540] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.523544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.523565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.523585] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.523605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.523625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.523646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.523666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.523687] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.523707] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.523727] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.523789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.523817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.539957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.539983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.540029] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.558881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.558900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.558920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.558937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.558952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.558967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.558981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.559000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.559021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.559042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.559062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.559081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.559099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.559132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.559155] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.559178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.559364] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.559384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.559403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.559425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.559442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.559462] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.559481] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.559500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.559519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.559538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.559557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.559561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.559579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.559583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.559602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.559621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.559640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.559659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.559678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.559696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.559716] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.559778] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.559804] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.559833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.559862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.559942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.559967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.559990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.560014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.560037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.560067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.560093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.560118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.560142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.560163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.560184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.560209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.560232] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.562227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.562243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.562257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.562272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.563818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.563836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.563850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.565344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.565360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.567167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.570102] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.570128] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.570144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.570167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.570250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.570282] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.570327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.587053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.587075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.587096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.587120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.587138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.587158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.587179] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.587199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.587220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.587240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.587259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.587264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.587284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.587288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.587308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.587328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.587348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.587368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.587388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.587409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.587430] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.587450] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.587470] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.587491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.587513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.603680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.603704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.603786] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.622623] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.622642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.622662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.622678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.622694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.622710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.622725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.622782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.622810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.622838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.622865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.623044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.623060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.623088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.623110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.623133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.623297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.623316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.623336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.623358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.623374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.623394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.623414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.623433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.623452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.623471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.623489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.623493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.623518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.623521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.623537] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.623551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.623565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.623578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.623593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.623607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.623621] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.623634] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.623646] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.623662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.623680] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.623731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.623773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.623799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.623820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.623842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.623864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.623888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.623912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.623937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.623957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.623978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.624004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.624025] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.626293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.626309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.626323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.626338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.627859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.627876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.627891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.629387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.629403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.631226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.634180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.634207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.634223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.634245] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.634325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.634360] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.634410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.651102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.651121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.651140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.651159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.651176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.651196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.651216] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.651235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.651254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.651273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.651292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.651296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.651314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.651318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.651337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.651357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.651376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.651394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.651414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.651432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.651452] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.651471] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.651490] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.651510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.651531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.667739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.667779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.667823] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.686655] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.686673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.686694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.686711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.686726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.686786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.686803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.686819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.686837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.686853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.686869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.686883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.686898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.686925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.686944] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.686962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.687141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.687157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.687175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.687194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.687210] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.687227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.687243] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.687260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.687275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.687290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.687304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.687309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.687322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.687326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.687341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.687360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.687380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.687399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.687418] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.687437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.687458] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.687477] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.687497] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.687518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.687538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.687595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.687615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.687634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.687653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.687673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.687692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.687713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.687734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.687786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.687811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.687834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.687861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.687892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.689881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.689896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.689910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.689924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.691426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.691441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.691458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.692954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.692970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.694773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.697703] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.697728] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.697779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.697806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.697886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.697920] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.697969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.714595] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.714614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.714633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.714652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.714668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.714685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.714702] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.714719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.714734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.714793] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.714817] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.714824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.714841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.714845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.714860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.714874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.714889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.714903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.714920] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.714934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.714949] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.714963] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.714977] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.714993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.715011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.731234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.731260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.731306] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.750090] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.750109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.750129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.750146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.750162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.750177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.750192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.750208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.750225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.750241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.750257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.750271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.750290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.750322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.750345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.750368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.750544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.750564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.750583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.750605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.750622] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.750641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.750661] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.750680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.750699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.750718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.750736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.750778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.750805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.750811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.750837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.750861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.750883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.750905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.750930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.750952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.750975] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.750997] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.751018] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.751043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.751069] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.751148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.751164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.751179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.751194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.751208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.751224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.751242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.751258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.751281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.751294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.751307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.751322] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.751337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.753308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.753326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.753343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.753361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.754869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.754885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.754899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.756389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.756404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.758210] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.761161] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.761187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.761203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.761225] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.761303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.761337] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.761388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.778093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.778113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.778133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.778157] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.778175] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.778196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.778217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.778237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.778258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.778278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.778298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.778302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.778322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.778326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.778346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.778367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.778387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.778407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.778427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.778447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.778468] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.778489] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.778509] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.778530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.778551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.794686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.794710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.794747] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.813547] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.813566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.813586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.813603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.813619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.813634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.813649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.813665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.813682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.813698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.813714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.813732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.813790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.813837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.813867] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.813898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.814192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.814209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.814227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.814247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.814262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.814279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.814295] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.814311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.814326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.814341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.814355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.814359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.814373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.814376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.814391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.814405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.814418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.814432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.814448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.814462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.814477] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.814490] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.814504] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.814523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.814544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.814592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.814611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.814631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.814650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.814670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.814689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.814709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.814730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.814788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.814813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.814836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.814863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.814887] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.816884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.816902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.816919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.816937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.818445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.818461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.818476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.819973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.819989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.821797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.824721] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.824747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.824803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.824841] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.825011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.825033] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.825067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.841641] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.841662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.841681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.841702] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.841719] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.841737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.841799] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.841828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.841856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.841881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.841905] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.841912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.841935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.841941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.841964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.841988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.842013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.842034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.842060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.842082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.842107] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.842128] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.842150] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.842176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.842203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.858228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.858252] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.858289] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.877184] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.877203] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.877223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.877240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.877255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.877270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.877285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.877300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.877318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.877334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.877350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.877364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.877378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.877406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.877424] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.877443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.877617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.877633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.877651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.877673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.877691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.877711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.877730] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.877749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.877804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.877830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.877857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.877864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.877887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.877894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.877919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.877943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.877968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.877991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.878019] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.878043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.878068] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.878092] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.878116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.878143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.878171] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.878257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.878279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.878301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.878323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.878342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.878364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.878389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.878412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.878436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.878457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.878478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.878501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.878524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.880518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.880535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.880549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.880563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.882069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.882085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.882098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.883591] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.883607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.885413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.888359] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.888384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.888402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.888426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.888501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.888534] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.888579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.905291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.905310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.905329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.905349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.905367] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.905387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.905407] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.905426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.905445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.905464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.905483] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.905487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.905505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.905509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.905529] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.905548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.905566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.905585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.905604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.905623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.905643] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.905662] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.905681] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.905700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.905721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.921895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.921921] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.921959] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.940835] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.940853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.940873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.940892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.940912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.940931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.940951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.940970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.940990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.941011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.941031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.941050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.941069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.941102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.941124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.941147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.941328] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.941348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.941368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.941390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.941407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.941426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.941445] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.941464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.941484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.941503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.941521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.941526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.941544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.941548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.941568] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.941586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.941613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.941630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.941646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.941662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.941677] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.941690] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.941703] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.941719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.941735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.941836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.941858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.941879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.941899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.941920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.941940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.941963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.941987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.942189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.942204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.942218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.942235] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.942251] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.944223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.944239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.944253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.944268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.945786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.945802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.945815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.947314] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.947330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.949143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.952078] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.952104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.952120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.952142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.952219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.952253] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.952303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.969006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.969027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.969047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.969069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.969086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.969105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.969125] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.969144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.969163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.969182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.969200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.969205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.969223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.969227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.969246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.969265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.969284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.969303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.969322] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.969340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.969360] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  328.969379] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.969398] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.969418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.969438] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.985626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.985651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.985687] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.004573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.004592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.004612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.004629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.004644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.004659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.004673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.004688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.004706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.004722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.004737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.004752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.004809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.004854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.004883] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.004913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.005096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.005129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.005144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.005159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.005172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.005184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.005199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.005219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.005237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.005256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.005275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.005293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.005312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.005336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.007562] [IGT] kms_flip: exiting, ret=0
>[  329.031207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.031227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.031247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.031268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.031283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.031301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.031321] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.031341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.031361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.031380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.031400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.031404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.031424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.031427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.031447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.031466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.031486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.031505] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.031526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.031545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.031564] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.031584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.031604] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.031624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.031647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.031721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.031741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.031761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.031793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.031813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.031833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.031855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.031876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.031897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.031917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.031937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.031958] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.031978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.033969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.033985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.033998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.034013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.035519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.035532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.035545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.038152] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.038168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.039975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.042759] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.042801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.042816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.042837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.042887] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.042909] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.059580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.059605] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.059642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.059783] Console: switching to colour frame buffer device 240x75
>[  329.187774] Console: switching to colour dummy device 80x25
>[  329.187869] [IGT] kms_flip: executing
>[  329.197080] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  329.197110] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  329.198826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  329.198848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  329.200831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  329.200838] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  329.202826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  329.202846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  329.204826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  329.204832] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  329.204836] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  329.204852] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  329.204875] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  329.205913] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  329.206813] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  329.206839] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  329.206860] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  329.206883] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  329.207877] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  329.207901] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  329.208951] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  329.208954] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  329.209034] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  329.209037] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  329.209041] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  329.209042] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  329.209046] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  329.209048] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  329.209055] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  329.209058] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.209061] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.209063] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.209066] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  329.209068] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  329.209071] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  329.209073] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  329.209075] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.209078] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.209080] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  329.209083] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  329.209085] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  329.209087] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  329.209090] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  329.209092] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  329.209095] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  329.209097] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  329.209100] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  329.209102] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  329.209104] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  329.209107] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  329.209109] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  329.209112] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  329.209114] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  329.209116] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  329.209119] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  329.209121] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  329.209124] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  329.209126] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  329.209128] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  329.209158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  329.209175] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  329.210840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  329.210859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  329.212833] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  329.212838] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  329.214826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  329.214846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  329.216837] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  329.216842] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  329.216846] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  329.217051] [IGT] kms_flip: starting subtest basic-flip-vs-modeset
>[  329.217449] [drm:drm_mode_addfb2] [FB:58]
>[  329.217471] [drm:drm_mode_addfb2] [FB:79]
>[  329.259876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.259929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.276469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.276495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.276536] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.295404] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.295428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.295448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.295471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.295491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.295512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.295532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.295551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.295570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.295592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.295612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.295633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.295653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.295672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.295690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.295729] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.295820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  329.295938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.296031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.296040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.296082] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.296099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.296116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.296135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.296149] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.296166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.296182] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.296197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.296212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.296226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.296239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.296244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.296256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.296260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.296274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.296288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.296301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.296314] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.296329] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.296343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.296356] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.296369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.296382] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.296397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.296413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.299037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.299057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.299076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.299095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.299113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.299132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.299152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.299171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.299191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.299209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.299227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.299247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.299265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.301258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.301274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.301289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.301304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.302837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.302852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.302866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.304360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.304376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.306187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.309120] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.309146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.309162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.309184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.309237] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.309261] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.325940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.325965] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.325999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.342625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.342635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.359402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.359447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.392729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.392768] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.393078] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.411623] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.411651] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.411673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.411699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.411721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.411745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.411765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.411784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.411866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.411910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.411947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.411983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.412017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.412050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.412082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.412149] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.412301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.412319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.412413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.412447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.412484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.412524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.412557] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.412591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.412623] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.412655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.412689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.412720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.412751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.412759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.412790] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.412834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.412871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.412903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.412936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.412968] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.413005] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.413037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.413066] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.413097] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.413129] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.413166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.413203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.413309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.413342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.413374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.413403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.413434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.413467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.413503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.413537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.413572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.413603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.413634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.413670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.413703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.415817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.415844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.415869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.415896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.417473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.417498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.417519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.419063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.419089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.420940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.424007] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.424042] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.424063] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.424091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.424140] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.424161] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.440811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.440836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.440872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.440974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.441016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.474183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.474208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.474254] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.493122] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.493144] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.493160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.493179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.493196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.493214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.493229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.493244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.493259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.493277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.493293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.493309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.493325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.493339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.493353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.493385] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.493458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.493466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.493508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.493523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.493541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.493560] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.493583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.493598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.493613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.493626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.493640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.493653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.493665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.493669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.493681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.493684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.493697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.493709] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.493722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.493734] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.493749] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.493761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.493774] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.493825] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.493847] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.493871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.493897] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.493959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.493980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.494002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.494022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.494043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.494064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.494089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.494112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.494135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.494154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.494174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.494197] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.494220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.496215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.496232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.496250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.496268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.497779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.497807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.497821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.499333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.499351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.501173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.504117] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.504146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.504165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.504190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.504241] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.504267] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.520955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.520980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.521014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.521114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.521153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.554314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.554341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.554387] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.573266] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.573289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.573309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.573330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.573350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.573371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.573391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.573410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.573429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.573451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.573471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.573492] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.573512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.573531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.573549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.573586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.573652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.573661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.573707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.573726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.573746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.573768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.573787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.573847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.573873] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.573896] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.573920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.573943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.573964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.573971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.573992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.573998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.574020] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.574041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.574063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.574084] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.574108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.574129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.574151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.574171] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.574192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.574217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.574244] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.574308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.574324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.574339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.574353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.574367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.574382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.574407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.574421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.574435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.574448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.574460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.574476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.574491] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.576471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.576488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.576502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.576516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.578029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.578044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.578058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.579554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.579570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.581379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.584301] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.584326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.584342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.584365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.584406] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.584425] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.601088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.601114] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.601151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.601245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.601287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.634469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.634493] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.634529] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.653394] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.653416] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.653432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.653452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.653468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.653486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.653502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.653517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.653533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.653551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.653568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.653584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.653600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.653614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.653628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.653660] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.653731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.653739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.653781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.653840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.653867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.653898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.653921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.653948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.653972] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.653997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.654020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.654044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.654066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.654073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.654095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.654102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.654125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.654147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.654177] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.654196] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.654220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.654240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.654261] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.654279] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.654301] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.654325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.654349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.654419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.654439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.654460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.654479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.654499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.654519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.654542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.654565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.654587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.654606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.654627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.654649] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.654671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.656668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.656686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.656704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.656722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.658236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.658252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.658266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.659764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.659782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.661616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.664540] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.664566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.664583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.664605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.664643] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.664659] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.681326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.681350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.681384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.681484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.681523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.714707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.714730] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.714766] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.733649] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.733671] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.733688] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.733707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.733724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.733742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.733757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.733773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.733788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.733876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.733904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.733930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.733956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.733979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.734002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.734052] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.734169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.734183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.734250] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.734275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.734303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.734332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.734356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.734382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.734408] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.734433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.734457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.734480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.734501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.734507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.734529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.734535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.734558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.734581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.734602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.734624] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.734650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.734674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.734695] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.734717] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.734741] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.734767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.734794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.734891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.734916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.734947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.734969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.734991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.735015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.735040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.735065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.735089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.735110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.735131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.735157] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.735181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.737177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.737193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.737207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.737222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.738747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.738765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.738782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.740313] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.740329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.742168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.745116] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.745141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.745156] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.745176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.745212] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.745227] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.761928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.761953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.761987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.762086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.762126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.795342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.795385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.795452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.814403] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.814431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.814452] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.814478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.814499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.814522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.814542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.814560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.814581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.814603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.814625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.814645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.814665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.814683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.814700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.814741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.814875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.814894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.814983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.815013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.815047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.815084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.815113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.815146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.815176] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.815207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.815236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.815265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.815292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.815299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.815327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.815334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.815364] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.815390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.815419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.815445] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.815478] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.815504] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.815533] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.815559] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.815588] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.815619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.815652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.815737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.815766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.815795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.815849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.815874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.815897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.815923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.815949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.815974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.815996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.816020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.816045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.816071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.818069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.818084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.818098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.818113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.819618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.819633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.819646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.821142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.821157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.822960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.825915] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.825940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.825956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.825976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.826014] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.826029] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.842714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.842739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.842776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.842974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.843014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.876070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.876094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.876129] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.894984] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.895006] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.895022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.895041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.895058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.895076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.895091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.895106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.895122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.895139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.895156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.895172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.895188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.895202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.895216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.895247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.895319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.895327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.895369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.895384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.895402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.895421] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.895436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.895453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.895469] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.895484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.895498] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.895520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.895532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.895536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.895549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.895552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.895565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.895577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.895590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.895602] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.895617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.895629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.895641] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.895658] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.895676] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.895694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.895713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.895762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.895781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.895798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.895855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.895877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.895899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.895924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.895947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.895970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.895990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.896009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.896033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.896054] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.898048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.898064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.898078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.898096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.899600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.899616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.899629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.901126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.901142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.902945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.905879] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.905906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.905923] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.905946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.905983] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.906000] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.922697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.922722] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.922756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.922967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.923014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.956054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.956078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.956112] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.974974] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.974996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.975012] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.975032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.975049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.975067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.975082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.975097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.975113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.975131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.975148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.975163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.975179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.975193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.975211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.975248] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.975322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.975331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.975377] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.975397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.975416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.975445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.975460] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.975477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.975493] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.975508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.975522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.975536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.975549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.975552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.975565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.975568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.975581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.975594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.975607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.975619] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.975634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.975647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.975659] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.975672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.975684] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.975699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.975715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.975763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.975781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.975799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.975817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.975868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.975892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.975916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.975939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.975961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.975980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.976000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.976023] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.976045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.978035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.978052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.978066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.978080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.979584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.979599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.979613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.981108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.981125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.982931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.985870] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.985897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.985916] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.985940] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.985981] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.986001] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.002683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.002709] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.002743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.002895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.002954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.036041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.036065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.036100] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.055022] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.055046] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.055067] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.055090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.055111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.055134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.055154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.055175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.055196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.055218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.055240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.055262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.055283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.055303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.055323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.055362] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.055443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.055452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.055502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.055523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.055544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.055568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.055588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.055609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.055630] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.055650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.055670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.055690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.055710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.055715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.055734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.055738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.055759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.055779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.055799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.055819] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.055885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.055912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.055937] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.055962] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.055985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.056012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.056040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.056123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.056149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.056175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.056200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.056225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.056251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.056279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.056307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.056335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.056359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.056384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.056413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.056440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.058442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.058459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.058475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.058491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.060014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.060031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.060046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.061559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.061586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.063414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.066347] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.066375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.066394] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.066420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.066461] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.066481] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.083167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.083193] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.083227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.083319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.083358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.116524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.116550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.116586] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.135446] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.135468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.135484] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.135504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.135520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.135538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.135553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.135568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.135584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.135601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.135617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.135637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.135658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.135677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.135696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.135733] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.135806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.135852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.135925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.135953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.135981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.136017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.136040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.136065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.136087] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.136103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.136117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.136131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.136144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.136148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.136165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.136169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.136187] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.136204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.136221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.136238] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.136256] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.136274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.136290] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.136308] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.136326] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.136345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.136364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.136413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.136431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.136449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.136467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.136485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.136502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.136522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.136541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.136560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.136578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.136595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.136614] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.136630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.138612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.138629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.138643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.138657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.140164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.140179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.140193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.141684] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.141702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.143511] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.146446] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.146473] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.146490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.146512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.146550] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.146566] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.163260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.163284] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.163317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.163419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.163471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.196649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.196684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.196737] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.215657] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.215678] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.215695] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.215715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.215731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.215749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.215764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.215778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.215794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.215812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.215827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.215888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.215913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.215935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.215958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.216009] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.216122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.216132] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.216176] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.216192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.216211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.216230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.216246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.216263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.216280] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.216299] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.216319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.216339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.216358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.216363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.216381] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.216386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.216405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.216425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.216444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.216463] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.216483] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.216501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.216520] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.216540] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.216559] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.216579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.216601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.216656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.216683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.216700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.216714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.216729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.216744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.216760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.216775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.216790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.216803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.216816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.216855] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.216878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.218877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.218893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.218907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.218925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.220434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.220452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.220469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.221970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.221987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.223798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.226732] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.226759] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.226776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.226798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.226882] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.226904] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.243552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.243577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.243611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.243711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.243751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.276941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.276965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.277001] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.295879] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.295900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.295916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.295936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.295952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.295969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.295984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.295999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.296015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.296033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.296049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.296064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.296080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.296094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.296108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.296140] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.296213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.296221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.296263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.296278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.296296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.296315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.296330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.296346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.296363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.296378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.296393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.296407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.296421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.296425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.296438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.296442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.296456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.296470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.296491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.296503] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.296518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.296535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.296552] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.296570] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.296587] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.296605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.296624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.296674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.296692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.296710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.296727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.296745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.296762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.296781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.296799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.296818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.296835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.296891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.296917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.296942] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.298935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.298951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.298966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.298980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.300484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.300499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.300516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.302013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.302029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.303831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.306771] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.306798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.306815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.306878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.306937] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.306960] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.323591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.323616] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.323650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.323740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.323779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.356948] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.356974] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.357010] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.375870] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.375892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.375908] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.375928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.375945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.375962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.375978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.375993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.376009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.376026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.376043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.376058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.376074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.376092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.376112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.376148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.376215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.376223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.376270] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.376290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.376309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.376331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.376350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.376370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.376389] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.376408] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.376427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.376453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.376470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.376473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.376488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.376491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.376506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.376519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.376532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.376545] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.376560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.376573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.376586] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.376598] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.376611] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.376626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.376642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.376688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.376702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.376715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.376728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.376741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.376754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.376769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.376783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.376797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.376810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.376826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.376881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.376904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.378901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.378918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.378933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.378952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.380457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.380473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.380488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.381984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.381999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.383803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.386736] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.386762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.386779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.386801] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.386840] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.386895] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.403556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.403581] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.403615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.403713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.403754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.436946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.436971] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.437015] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.455885] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.455907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.455924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.455944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.455960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.455978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.455993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.456008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.456024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.456042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.456059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.456075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.456090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.456109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.456128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.456164] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.456238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.456247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.456293] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.456312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.456332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.456354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.456373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.456392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.456412] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.456437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.456454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.456468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.456481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.456485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.456498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.456501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.456514] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.456528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.456541] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.456553] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.456568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.456581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.456594] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.456607] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.456619] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.456634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.456650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.456688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.456703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.456716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.456730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.456743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.456756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.456771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.456785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.456799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.456811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.456823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.456838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.456893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.458891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.458909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.458927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.458945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.460463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.460480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.460496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.462002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.462026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.463836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.466780] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.466807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.466824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.466888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.466948] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.466973] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.483599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.483625] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.483662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.483765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.483807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.516956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.516982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.517027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.535882] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.535903] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.535919] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.535938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.535955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.535972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.535987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.536002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.536017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.536034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.536050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.536066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.536082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.536096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.536109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.536141] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.536214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.536222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.536264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.536279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.536304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.536322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.536336] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.536350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.536365] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.536379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.536393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.536406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.536418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.536422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.536434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.536437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.536450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.536463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.536475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.536487] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.536502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.536519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.536536] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.536554] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.536571] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.536590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.536609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.536658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.536676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.536693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.536711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.536728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.536746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.536764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.536783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.536801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.536818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.536835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.536895] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.536923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.538922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.538939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.538953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.538971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.540476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.540494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.540511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.542008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.542025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.543830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.546781] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.546808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.546825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.546847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.546936] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.546962] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.563581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.563607] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.563644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.563746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.563788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.596971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.596996] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.597032] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.615908] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.615929] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.615945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.615964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.615981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.615999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.616014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.616028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.616045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.616065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.616086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.616106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.616127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.616146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.616164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.616201] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.616268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.616276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.616322] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.616342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.616362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.616383] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.616402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.616422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.616441] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.616460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.616479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.616498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.616517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.616521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.616539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.616543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.616562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.616581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.616600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.616619] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.616638] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.616657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.616676] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.616695] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.616713] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.616733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.616754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.616808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.616828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.616847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.616907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.616936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.616965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.616994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.617021] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.617048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.617072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.617097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.617125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.617151] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.619156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.619172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.619186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.619201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.620704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.620719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.620733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.622228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.622244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.624047] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.626995] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.627022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.627039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.627061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.627110] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.627135] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.643799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.643825] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.643905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.644046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.644093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.677156] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.677180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.677224] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.694634] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.694656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.694673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.694692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.694709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.694726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.694741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.694756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.694772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.694793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.694814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.694834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.694854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.694913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.694937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.694991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.695108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.695122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.695193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.695216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.695242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.695271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.695294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.695319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.695342] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.695366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.695388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.695411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.695431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.695437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.695459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.695464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.695487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.695508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.695530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.695550] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.695575] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.695596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.695618] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.695639] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.695661] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.695684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.695710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.695788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.695810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.695833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.695854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.695896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.695919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.695946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.695973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.696000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.696028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.696049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.696075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.696096] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.698096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.698114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.698131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.698149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.699657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.699673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.699688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.702266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.702284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.704100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.707049] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.707076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.707092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.707115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.707163] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.707188] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.723850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.723890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.723925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.724042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.724090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.757209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.757235] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.757281] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.776130] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.776152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.776168] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.776187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.776204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.776221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.776237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.776252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.776267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.776285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.776301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.776317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.776333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.776347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.776365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.776402] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.776476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.776485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.776532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.776551] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.776571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.776593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.776610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.776630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.776649] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.776668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.776688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.776707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.776725] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.776729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.776748] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.776751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.776771] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.776790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.776808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.776827] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.776845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.776864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.776935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.776963] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.776987] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.777014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.777040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.777112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.777136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.777159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.777182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.777204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.777227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.777252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.777276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.777300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.777321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.777342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.777368] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.777390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.779401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.779417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.779431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.779446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.780967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.780984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.780998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.782497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.782513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.784325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.787274] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.787301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.787318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.787340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.787379] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.787395] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.804087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.804111] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.804145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.804248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.804287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.837466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.837491] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.837527] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.856402] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.856423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.856439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.856458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.856475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.856493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.856508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.856522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.856538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.856556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.856572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.856587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.856603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.856617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.856630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.856662] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.856727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.856735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.856776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.856792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.856811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.856834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.856853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.856927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.856955] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.856978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.857003] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.857025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.857048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.857054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.857075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.857081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.857104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.857126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.857148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.857170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.857194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.857216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.857239] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.857260] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.857282] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.857307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.857333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.857407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.857429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.857449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.857471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.857492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.857513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.857536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.857560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.857583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.857602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.857623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.857648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.857670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.859665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.859681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.859695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.859710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.861217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.861240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.861261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.862761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.862777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.864584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.867518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.867545] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.867562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.867583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.867632] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.867657] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.884335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.884360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.884396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.884500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.884553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.917693] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.917719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.917763] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.936605] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.936627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  330.936644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  330.936663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.936680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.936698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.936714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.936729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.936744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.936762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.936779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.936794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.936810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.936824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.936838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.936870] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.937015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.937029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  330.937098] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  330.937121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.937147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  330.937176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  330.937198] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  330.937223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.937246] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  330.937270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.937292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  330.937315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.937336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.937342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.937363] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.937369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  330.937392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  330.937413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  330.937435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.937456] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  330.937481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  330.937502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.937524] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  330.937545] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  330.937567] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  330.937591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.937617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  330.937699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  330.937719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  330.937740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  330.937759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  330.937780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  330.937799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  330.937822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  330.937845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  330.937868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.937910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  330.937929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  330.937955] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  330.937976] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  330.939965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.939983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.940001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.940019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.941525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  330.941542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.941556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.943053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.943069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.944881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.947823] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.947850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  330.947874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.947934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.948111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.948129] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.964644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  330.964669] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  330.964703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  330.964813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  330.964862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.998033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.998073] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  330.998129] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.017117] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.017147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.017170] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.017197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.017220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.017244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.017271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.017299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.017326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.017356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.017385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.017414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.017442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.017469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.017495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.017546] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.017651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.017663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.017728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.017756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.017783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.017814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.017840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.017868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.017953] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.017989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.018027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.018059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.018092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.018102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.018135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.018145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.018178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.018209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.018243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.018273] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.018310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.018341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.018374] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.018405] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.018437] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.018476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.018516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.018624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.018658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.018681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.018702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.018725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.018747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.018772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.018797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.018822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.018843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.018865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.018912] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.018936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.020937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.020953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.020967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.020982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.022497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.022513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.022526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.024025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.024041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.025847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.028779] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.028806] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.028823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.028852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.028917] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.028939] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.045599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.045624] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.045658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.045773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.045821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.078991] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.079015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.079052] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.097919] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.097940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.097956] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.097976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.097992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.098010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.098025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.098040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.098056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.098074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.098090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.098106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.098122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.098140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.098159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.098196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.098264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.098273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.098319] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.098338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.098358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.098380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.098399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.098418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.098438] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.098457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.098476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.098495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.098514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.098518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.098543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.098547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.098564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.098579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.098593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.098606] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.098621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.098635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.098648] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.098661] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.098673] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.098688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.098705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.098753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.098767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.098784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.098802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.098819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.098837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.098855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.098874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.098932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.098960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.098984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.099011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.099035] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.101035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.101053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.101070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.101088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.102597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.102615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.102632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.104134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.104150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.105960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.108906] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.108933] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.108950] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.108972] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.109011] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.109027] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.125711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.125736] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.125770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.125861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.126009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.159069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.159094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.159137] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.177989] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.178011] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.178028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.178047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.178064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.178081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.178096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.178111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.178127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.178145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.178161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.178177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.178193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.178207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.178221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.178253] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.178324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.178332] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.178381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.178396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.178413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.178431] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.178446] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.178461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.178477] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.178491] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.178506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.178520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.178534] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.178538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.178551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.178554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.178568] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.178582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.178595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.178608] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.178623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.178637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.178650] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.178663] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.178676] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.178692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.178709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.178757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.178772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.178786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.178799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.178813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.178827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.178847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.178867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.178887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.178944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.178966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.178992] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.179014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.181007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.181024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.181038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.181052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.182556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.182571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.182585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.184080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.184098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.185918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.188851] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.188878] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.188927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.188964] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.189027] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.189053] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.205670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.205695] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.205729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.205826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.205866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.239027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.239053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.239099] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.257964] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.257986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.258002] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.258023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.258043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.258064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.258084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.258103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.258122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.258143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.258164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.258184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.258204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.258223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.258242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.258278] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.258353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.258361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.258407] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.258427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.258447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.258469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.258488] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.258508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.258527] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.258546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.258565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.258584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.258602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.258606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.258625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.258629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.258648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.258667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.258686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.258705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.258724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.258742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.258761] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.258780] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.258799] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.258819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.258839] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.258893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.258956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.258981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.259005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.259028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.259052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.259078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.259103] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.259127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.259156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.259176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.259200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.259221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.261210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.261227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.261241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.261263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.262775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.262790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.262804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.265402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.265422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.267265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.270205] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.270232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.270248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.270270] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.270324] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.270347] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.287017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.287042] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.287077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.287176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.287215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.320375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.320400] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.320445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.339296] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.339319] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.339339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.339360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.339380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.339401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.339421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.339440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.339458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.339480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.339500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.339521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.339541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.339560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.339579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.339615] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.339691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.339699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.339746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.339765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.339785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.339807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.339823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.339843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.339862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.339881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.339900] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.339969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.339992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.339998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.340019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.340024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.340045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.340065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.340085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.340105] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.340128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.340147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.340167] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.340187] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.340206] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.340229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.340253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.340323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.340347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.340368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.340390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.340411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.340434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.340458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.340482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.340505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.340526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.340544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.340561] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.340578] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.342555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.342571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.342586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.342600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.344107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.344121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.344135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.345626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.345642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.347449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.350371] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.350396] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.350413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.350435] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.350482] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.350507] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.367146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.367170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.367203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.367292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.367330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.400508] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.400534] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.400578] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.419515] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.419539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.419557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.419579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.419600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.419623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.419645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.419666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.419687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.419711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.419734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.419756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.419778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.419799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.419820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.419860] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.420005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.420021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.420101] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.420132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.420158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.420180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.420202] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.420225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.420246] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.420268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.420289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.420311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.420332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.420338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.420358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.420363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.420384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.420405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.420428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.420449] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.420470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.420491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.420513] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.420534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.420555] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.420577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.420601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.420661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.420683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.420705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.420726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.420749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.420770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.420794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.420817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.420841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.420861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.420883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.420916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.420959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.422950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.422967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.422981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.422996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.424503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.424518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.424532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.426043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.426062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.427885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.430848] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.430875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.430892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.430960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.431009] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.431040] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.447638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.447663] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.447697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.447794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.447833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.481027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.481053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.481091] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.499959] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.499981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.499997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.500016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.500033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.500051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.500066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.500081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.500097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.500114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.500131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.500147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.500162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.500177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.500191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.500223] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.500294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.500303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.500344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.500359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.500377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.500397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.500412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.500428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.500444] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.500460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.500475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.500489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.500503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.500507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.500521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.500525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.500539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.500553] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.500567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.500580] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.500603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.500616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.500628] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.500640] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.500653] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.500667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.500684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.500731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.500748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.500766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.500784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.500801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.500819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.500838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.500856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.500875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.500892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.500946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.500976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.500998] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.502996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.503013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.503027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.503042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.504549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.504564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.504578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.506079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.506095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.507902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.510848] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.510881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.510896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.510952] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.511103] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.511119] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.527694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.527719] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.527754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.527854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.527894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.561023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.561047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.561081] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.579959] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.579981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.579997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.580016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.580033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.580060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.580085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.580105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.580121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.580139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.580156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.580171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.580187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.580201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.580214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.580250] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.580326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.580335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.580381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.580401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.580421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.580443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.580461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.580481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.580500] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.580519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.580545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.580562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.580576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.580580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.580593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.580597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.580611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.580624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.580637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.580650] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.580665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.580678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.580691] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.580704] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.580716] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.580731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.580747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.580794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.580809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.580822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.580835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.580848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.580861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.580876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.580890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.580904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.580949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.580971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.580998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.581022] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.583019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.583037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.583054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.583072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.584577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.584594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.584608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.586103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.586119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.587940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.590872] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.590900] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.590952] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.590991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.591145] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.591165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.607693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.607718] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.607752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.607842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.607882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.641098] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.641144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.641211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.660070] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.660091] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.660108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.660127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.660143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.660161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.660176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.660191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.660207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.660224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.660241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.660256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.660276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.660295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.660314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.660351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.660418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.660426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.660472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.660492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.660511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.660533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.660552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.660572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.660591] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.660610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.660630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.660649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.660667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.660671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.660690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.660693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.660713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.660732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.660751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.660769] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.660788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.660807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.660826] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.660845] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.660864] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.660884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.660904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.661021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.661049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.661075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.661101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.661126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.661152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.661180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.661208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.661235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.661260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.661284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.661312] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.661337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.663340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.663356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.663370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.663385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.664891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.664905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.664952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.666462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.666477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.668307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.671246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.671274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.671290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.671312] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.671350] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.671367] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.688061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.688086] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.688120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.688220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.688259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.721416] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.721442] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.721479] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.740335] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.740356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.740372] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.740391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.740408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.740425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.740441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.740455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.740471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.740489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.740505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.740521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.740537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.740551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.740565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.740596] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.740668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.740677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.740718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.740734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.740751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.740771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.740786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.740802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.740818] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.740833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.740847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.740862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.740875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.740879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.740893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.740896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.740910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.740970] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.740997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.741021] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.741048] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.741072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.741097] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.741120] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.741144] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.741171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.741199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.741276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.741301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.741326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.741355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.741377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.741399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.741423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.741446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.741469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.741488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.741508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.741532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.741554] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.743558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.743576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.743590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.743606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.745118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.745133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.745147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.746652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.746669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.748481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.751414] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.751441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.751458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.751480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.751519] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.751536] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.768233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.768258] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.768294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.768394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.768435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.801638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.801688] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.801759] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.818708] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.818730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.818746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.818766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.818782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.818800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.818816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.818835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.818854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.818875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.818896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.818917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.818983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.819009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.819035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.819089] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.819207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.819221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.819295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.819318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.819343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.819371] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.819393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.819417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.819440] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.819463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.819486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.819507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.819529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.819534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.819555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.819560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.819582] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.819603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.819624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.819644] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.819666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.819687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.819708] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.819728] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.819747] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.819770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.819795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.819867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.819889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.819911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.819953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.819976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.820000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.820025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.820049] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.820073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.820095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.820117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.820143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.820166] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.822157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.822173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.822187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.822202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.823708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.823723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.823737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.825233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.825248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.827055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.829989] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.830017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.830036] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.830061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.830102] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.830122] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.846808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.846833] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.846867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.847039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.847100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.880164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.880188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.880223] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.901250] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.901272] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.901288] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.901308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.901324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.901342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.901357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.901372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.901388] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.901405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.901422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.901437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.901453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.901467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.901481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.901512] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.901578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.901586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.901627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.901643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.901661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.901679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.901695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.901711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.901727] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.901746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.901765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.901785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.901803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.901807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.901826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.901829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.901849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.901868] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.901887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.901906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.901925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.901988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.902019] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.902045] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.902071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.902106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.902133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.902204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.902228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.902250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.902272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.902294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.902317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.902342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.902365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.902389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.902410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.902431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.902456] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.902479] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.904548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.904564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.904578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.904593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.906100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.906115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.906132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.907626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.907642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.909448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.912389] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.912415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.912431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.912453] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.912491] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.912510] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.929201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.929227] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.929263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.929361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.929403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.962558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.962583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  331.962620] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.981465] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.981486] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  331.981503] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  331.981522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.981538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.981556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.981571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.981586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.981605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  331.981626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.981647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.981667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.981688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.981707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.981726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.981762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.981836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  331.981844] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  331.981891] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  331.981911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.981930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  331.981995] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  331.982026] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  331.982061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.982086] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.982111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.982134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  331.982157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.982179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.982186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.982207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.982213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  331.982235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  331.982257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  331.982279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.982300] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  331.982325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  331.982347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.982370] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  331.982391] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  331.982413] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  331.982438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.982463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  331.982534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.982556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  331.982577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  331.982599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  331.982620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  331.982640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  331.982664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  331.982688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  331.982711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  331.982733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  331.982754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  331.982779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  331.982802] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  331.984796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.984812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.984826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.984840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.986347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.986365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.986382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.987879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.987896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  331.989701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.992629] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.992656] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  331.992673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  331.992695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.992733] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.992753] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.009402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.009428] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.009462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.009559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.009598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.042761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.042786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.042820] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.061676] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.061707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.061730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.061758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.061782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.061808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.061830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.061852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.061876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.061903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.061928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.062209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.062235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.062258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.062276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.062313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.062389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.062398] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.062444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.062463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.062483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.062505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.062524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.062543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.062563] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.062582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.062601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.062620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.062639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.062643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.062661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.062665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.062684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.062704] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.062723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.062742] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.062761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.062779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.062798] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.062817] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.062836] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.062856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.062877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.062937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.062980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.063007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.063028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.063051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.063073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.063099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.063124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.063148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.063168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.063190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.063216] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.063237] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.065228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.065246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.065263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.065281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.066787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.066804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.066818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.068316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.068332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.070137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.073072] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.073099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.073116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.073138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.073176] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.073200] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.089889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.089915] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.089989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.090147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.090192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.123244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.123268] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.123303] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.142144] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.142166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.142182] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.142201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.142221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.142242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.142262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.142281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.142300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.142322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.142342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.142363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.142383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.142402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.142421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.142457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.142524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.142533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.142579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.142599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.142618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.142641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.142659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.142679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.142698] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.142717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.142736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.142755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.142774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.142778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.142796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.142800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.142819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.142838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.142864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.142880] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.142896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.142911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.142925] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.142939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.142990] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.143015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.143040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.143111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.143132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.143155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.143175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.143197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.143218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.143244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.143267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.143290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.143309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.143331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.143356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.143376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.145370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.145386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.145401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.145415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.146920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.146935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.146978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.148475] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.148490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.150313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.154344] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.154372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.154389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.154411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.154451] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.154468] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.171124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.171148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.171181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.171265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.171302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.204482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.204507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.204543] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.223424] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.223445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.223461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.223480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.223497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.223514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.223530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.223548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.223568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.223589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.223610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.223630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.223650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.223669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.223688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.223725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.223800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.223809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.223855] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.223881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.223899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.223917] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.223931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.223947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.223999] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.224023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.224047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.224069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.224091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.224097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.224118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.224124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.224147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.224167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.224189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.224209] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.224233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.224253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.224274] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.224294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.224316] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.224341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.224366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.224724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.224747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.224769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.224789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.224810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.224831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.224854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.224877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.224900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.224920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.224940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.224983] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.225006] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.227142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.227158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.227173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.227187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.228692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.228707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.228721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.230217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.230234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.232041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.234985] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.235012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.235029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.235051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.235090] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.235107] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.251793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.251818] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.251852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.251986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.252165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.285150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.285176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.285213] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.304064] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.304085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.304104] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.304126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.304145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.304167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.304186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.304205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.304224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.304246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.304266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.304286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.304306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.304325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.304344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.304381] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.304457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.304466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.304512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.304532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.304552] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.304574] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.304590] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.304610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.304629] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.304648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.304667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.304686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.304704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.304708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.304727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.304730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.304750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.304769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.304788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.304806] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.304826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.304851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.304868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.304883] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.304896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.304912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.304930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.305026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.305048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.305070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.305091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.305113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.305134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.305158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.305182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.305206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.305226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.305247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.305273] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.305295] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.307288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.307304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.307319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.307334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.308839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.308857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.308874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.310372] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.310389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.312194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.315126] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.315151] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.315168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.315190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.315228] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.315244] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.331947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.331990] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.332026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.332128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.332169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.365303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.365328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.365363] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.384225] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.384246] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.384263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.384282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.384299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.384317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.384332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.384347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.384364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.384381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.384397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.384413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.384429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.384443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.384457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.384488] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.384553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.384561] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.384602] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.384618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.384635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.384654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.384670] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.384686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.384703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.384718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.384733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.384747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.384761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.384765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.384778] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.384782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.384801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.384820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.384839] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.384866] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.384882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.384897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.384911] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.384925] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.384937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.384953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.385007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.385078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.385099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.385122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.385142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.385163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.385184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.385209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.385233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.385258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.385278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.385298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.385323] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.385346] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.387338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.387354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.387368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.387382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.388906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.388923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.388941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.390467] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.390484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.392317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.395256] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.395282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.395299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.395321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.395359] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.395378] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.412069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.412094] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.412128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.412218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.412258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.445426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.445452] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.445488] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.464431] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.464453] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.464469] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.464488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.464505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.464523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.464538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.464553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.464571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.464593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.464614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.464634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.464654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.464673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.464692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.464728] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.464802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.464810] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.464857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.464877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.464896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.464919] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.464936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.464955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.465013] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.465040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.465066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.465090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.465114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.465121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.465144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.465150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.465175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.465196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.465220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.465241] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.465267] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.465289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.465313] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.465334] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.465357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.465384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.465413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.465489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.465514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.465538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.465562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.465586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.465610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.465637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.465662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.465688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.465711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.465734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.465761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.465792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.467784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.467800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.467815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.467830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.469336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.469351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.469364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.470855] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.470871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.472676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.475595] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.475621] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.475637] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.475659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.475696] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.475713] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.492378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.492403] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.492439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.492539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.492580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.525767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.525790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.525827] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.544789] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.544818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.544840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.544866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.544888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.544912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.544932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.544952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.544973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.545062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.545100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.545137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.545173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.545203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.545237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.545311] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.545463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.545481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.545574] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.545600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.545629] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.545660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.545686] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.545713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.545741] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.545767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.545793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.545818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.545842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.545849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.545873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.545879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.545904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.545928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.545953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.545976] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.546034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.546060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.546084] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.546110] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.546135] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.546161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.546192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.546264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.546290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.546316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.546341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.546365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.546392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.546419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.546446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.546473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.546498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.546522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.546550] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.546577] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.548601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.548621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.548639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.548656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.550181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.550199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.550215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.551723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.551744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.553571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.556515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.556541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.556558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.556580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.556629] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.556655] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.573327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.573351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.573384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.573481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.573518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.606689] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.606714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.606759] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.625611] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.625632] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.625649] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.625668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.625685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.625702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.625718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.625732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.625748] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.625766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.625782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.625798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.625814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.625828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.625842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.625874] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.625947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.625955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.626050] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.626074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.626102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.626132] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.626156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.626182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.626210] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.626235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.626260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.626285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.626308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.626314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.626337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.626343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.626367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.626388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.626410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.626431] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.626456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.626477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.626499] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.626520] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.626541] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.626565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.626591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.626668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.626689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.626709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.626729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.626748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.626769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.626793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.626816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.626839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.626858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.626878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.626900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.626922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.628935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.628951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.628965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.629011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.630520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.630535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.630549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.632116] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.632133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.633938] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.636871] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.636898] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.636915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.636937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.637016] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.637045] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.653689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.653714] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.653750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.653843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.653885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.687048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.687074] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.687119] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.705976] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.706014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.706031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.706050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.706066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.706083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.706099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.706113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.706129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.706146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.706163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.706179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.706194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.706208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.706222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.706254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.706326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.706334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.706375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.706390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.706408] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.706428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.706447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.706467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.706486] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.706512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.706527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.706541] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.706554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.706558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.706571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.706574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.706587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.706600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.706612] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.706629] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.706647] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.706664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.706681] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.706699] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.706717] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.706735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.706754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.706804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.706822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.706840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.706857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.706875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.706892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.706911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.706929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.706948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.706965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.707010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.707039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.707061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.709055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.709072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.709086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.709104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.710619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.710636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.710650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.712151] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.712168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.713977] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.716924] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.716951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.716967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.717037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.717097] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.717123] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.733770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.733795] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.733829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.733921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.733960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.767130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.767155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.767190] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.788235] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.788257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.788273] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.788292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.788309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.788327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.788342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.788357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.788373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.788391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.788407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.788422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.788437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.788451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.788465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.788497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.788568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.788576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.788617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.788633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.788650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.788669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.788684] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.788700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.788716] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.788731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.788746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.788764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.788783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.788787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.788806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.788810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.788829] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.788848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.788868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.788887] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.788906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.788924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.788943] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.788963] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.788982] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.789045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.789073] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.789153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.789180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.789203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.789228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.789250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.789276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.789304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.789331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.789357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.789378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.789400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.789427] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.789451] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.791464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.791481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.791495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.791510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.793460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.793477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.793492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.795024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.795040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.796840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.798907] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.798935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.798955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.798979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.799133] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.799160] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.815683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.815708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.815743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.815862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.815911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.849071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.849097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.849135] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.868034] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.868056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.868072] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.868093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.868113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.868135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.868155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.868174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.868193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.868214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.868235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.868255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.868275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.868294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.868313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.868350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.868426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.868435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.868482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.868501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.868521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.868543] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.868562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.868588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.868605] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.868620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.868634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.868648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.868660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.868664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.868677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.868680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.868693] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.868706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.868718] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.868730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.868747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.868764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.868782] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.868799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.868817] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.868835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.868854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.868897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.868915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.868932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.868950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.868967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.868985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.869046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.869075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.869102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.869125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.869148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.869174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.869198] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.871195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.871211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.871225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.871240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.872746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.872761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.872776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.874277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.874293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.876098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.879042] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.879069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.879086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.879107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.879146] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.879163] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.895859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.895884] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.895920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.896071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.896129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.929207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  332.929231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  332.929274] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  332.948136] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  332.948158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  332.948178] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  332.948199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.948219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.948240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.948259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.948278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.948297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.948319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.948340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.948360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.948380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.948399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.948417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.948454] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.948520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.948529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  332.948580] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  332.948597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.948614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  332.948632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.948646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  332.948661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.948676] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  332.948691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  332.948706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  332.948719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.948736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.948739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.948756] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.948760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  332.948778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  332.948795] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  332.948812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.948830] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  332.948847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  332.948864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.948881] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  332.948899] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  332.948916] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  332.948934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.948953] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  332.949041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  332.949065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  332.949089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  332.949111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  332.949133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  332.949155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  332.949180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  332.949206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  332.949231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.949251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  332.949273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  332.949299] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  332.949321] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  332.951314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.951330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.951344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.951359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.952862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  332.952877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.952891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.954387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.954403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  332.956207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.959140] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  332.959167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  332.959184] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  332.959206] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.959254] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  332.959279] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  332.975951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  332.975975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  332.976048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  332.976221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  332.976261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.009317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.009341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.009385] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.028321] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.028346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.028363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.028385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.028403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.028422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.028440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.028456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.028474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.028493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.028512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.028529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.028551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.028572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.028593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.028633] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.028715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.028725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.028775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.028797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.028819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.028843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.028861] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.028883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.028904] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.028925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.028947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.028968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.028997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.029044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.029074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.029081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.029111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.029137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.029165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.029189] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.029220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.029244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.029271] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.029295] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.029321] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.029352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.029383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.029469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.029493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.029520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.029545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.029570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.029595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.029622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.029650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.029678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.029701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.029727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.029756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.029782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.031803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.031822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.031839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.031856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.033378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.033395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.033411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.034920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.034940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.036765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.039711] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.039738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.039756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.039779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.039829] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.039856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.056530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.056556] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.056591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.056691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.056732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.089883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.089908] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.089953] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.108774] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.108797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.108817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.108838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.108858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.108879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.108898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.108918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.108937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.108958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.108979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.108999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.109063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.109088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.109114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.109166] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.109285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.109298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.109361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.109383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.109407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.109433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.109454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.109477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.109499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.109521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.109541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.109562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.109581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.109586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.109606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.109611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.109632] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.109651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.109672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.109691] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.109714] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.109732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.109753] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.109772] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.109792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.109813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.109837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.109907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.109927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.109948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.109968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.109988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.110026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.110050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.110075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.110099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.110118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.110140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.110165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.110187] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.112175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.112190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.112204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.112219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.113723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.113738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.113752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.116375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.116393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.118198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.121140] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.121166] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.121182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.121204] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.121252] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.121278] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.137950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.137975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.138050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.138207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.138252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.171307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.171333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.171378] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.190297] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.190319] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.190338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.190360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.190380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.190401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.190421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.190440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.190459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.190480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.190501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.190521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.190541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.190560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.190579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.190616] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.190683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.190692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.190738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.190757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.190777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.190799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.190818] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.190837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.190857] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.190876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.190895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.190914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.190933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.190936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.190955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.190959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.190978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.190997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.191059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.191085] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.191113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.191143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.191166] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.191187] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.191208] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.191234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.191259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.191330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.191350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.191372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.191392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.191413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.191433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.191456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.191479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.191502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.191522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.191543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.191567] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.191588] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.193590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.193607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.193622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.193637] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.195157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.195174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.195188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.196682] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.196700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.198525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.201459] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.201486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.201502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.201524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.201573] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.201598] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.218274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.218297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.218330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.218425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.218464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.251635] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.251661] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.251707] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.270548] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.270570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.270586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.270606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.270622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.270640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.270659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.270678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.270698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.270719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.270740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.270760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.270780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.270799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.270818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.270855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.270927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.270936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.270982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.271001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.271064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.271096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.271120] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.271149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.271180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.271204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.271225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.271247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.271267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.271274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.271295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.271301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.271323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.271343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.271365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.271384] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.271409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.271428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.271450] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.271471] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.271492] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.271517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.271543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.271615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.271638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.271660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.271682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.271703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.271725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.271749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.271772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.271795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.271814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.271835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.271857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.271880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.273872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.273889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.273906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.273925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.275432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.275448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.275462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.276959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.276975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.278780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.281714] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.281741] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.281758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.281780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.281829] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.281855] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.298532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.298557] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.298591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.298688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.298728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.331889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.331916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.331961] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.350787] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.350808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.350825] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.350844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.350861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.350878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.350893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.350908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.350927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.350949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.350969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.350990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.351010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.351070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.351095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.351148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.351263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.351277] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.351347] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.351370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.351397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.351426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.351448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.351473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.351497] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.351521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.351543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.351565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.351586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.351592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.351613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.351619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.351642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.351663] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.351685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.351705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.351730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.351751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.351773] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.351794] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.351816] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.351839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.351865] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.351941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.351963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.351986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.352007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.352049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.352077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.352102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.352126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.352150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.352170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.352192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.352214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.352237] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.354225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.354240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.354254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.354268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.355771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.355789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.355806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.357303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.357319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.359124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.362064] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.362091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.362110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.362135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.362184] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.362210] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.378873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.378897] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.378930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.379069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.379129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.412233] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.412258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.412301] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.431164] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.431187] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.431207] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.431228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.431248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.431269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.431288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.431307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.431327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.431348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.431369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.431389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.431409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.431428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.431447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.431483] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.431550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.431558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.431604] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.431624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.431644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.431666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.431682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.431702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.431721] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.431740] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.431760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.431778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.431797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.431801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.431819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.431823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.431843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.431862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.431880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.431899] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.431918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.431937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.431955] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.431974] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.431993] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.432021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.432077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.432150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.432173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.432196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.432217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.432239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.432261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.432286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.432310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.432335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.432355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.432376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.432402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.432424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.434416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.434432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.434446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.434460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.435969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.435987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.436004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.437530] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.437546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.439380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.442318] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.442345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.442361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.442383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.442431] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.442457] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.459128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.459151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.459184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.459275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.459312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.492522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.492548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.492585] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.511460] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.511482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.511498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.511517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.511534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.511552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.511567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.511581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.511597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.511615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.511631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.511646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.511661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.511675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.511689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.511721] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.511794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.511802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.511844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.511860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.511877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.511896] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.511912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.511928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.511945] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.511960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.511975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.511989] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.512003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.512007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.512020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.512067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.512090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.512110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.512132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.512152] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.512176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.512196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.512217] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.512237] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.512258] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.512283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.512309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.512646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.512668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.512690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.512710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.512731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.512752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.512775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.512798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.512822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.512840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.512861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.512883] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.512905] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.514892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.514910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.514928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.514946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.516454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.516470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.516484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.517979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.517995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.519802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.522736] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.522764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.522783] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.522808] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.522858] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.522884] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.539554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.539578] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.539612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.539709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.539748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.572901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.572926] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.572971] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.591800] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.591821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.591838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.591858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.591874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.591892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.591907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.591922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.591941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.591963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.591983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.592004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.592024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.592081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.592107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.592159] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.592273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.592287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.592356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.592381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.592407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.592435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.592458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.592483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.592506] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.592530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.592552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.592576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.592597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.592603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.592624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.592630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.592653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.592673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.592695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.592716] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.592741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.592761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.592783] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.592804] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.592825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.592849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.592875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.592957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.592977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.592998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.593017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.593056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.593077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.593103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.593127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.593152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.593172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.593193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.593219] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.593240] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.595233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.595249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.595263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.595281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.596784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.596800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.596814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.598309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.598325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.600129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.603060] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.603087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.603106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.603131] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.603187] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.603211] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.619826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.619849] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.619882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.619980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.620018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.653188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.653213] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.653256] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.672216] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.672244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.672264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.672289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.672310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.672333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.672352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.672371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.672391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.672414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.672435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.672455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.672475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.672493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.672517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.672564] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.672651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.672662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.672721] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.672747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.672772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.672801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.672825] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.672851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.672875] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.672900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.672925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.672949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.672973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.672978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.673003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.673007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.673032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.673112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.673145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.673179] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.673212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.673244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.673273] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.673305] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.673333] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.673367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.673403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.673504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.673533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.673564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.673593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.673623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.673651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.673684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.673716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.673748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.673775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.673803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.673834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.673866] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.675913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.675935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.675954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.675974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.677485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.677499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.677513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.679006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.679021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.680850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.683795] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.683821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.683838] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.683860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.683908] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.683933] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.700603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.700628] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.700662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.700753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.700793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.733959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.733983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.734026] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.752918] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.752940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.752956] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.752976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.752993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.753010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.753026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.753041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.753128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.753159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.753187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.753213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.753239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.753261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.753284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.753334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.753449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.753462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.753527] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.753544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.753562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.753582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.753598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.753614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.753631] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.753646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.753661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.753676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.753690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.753694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.753708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.753711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.753726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.753740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.753754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.753767] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.753783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.753797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.753811] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.753825] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.753849] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.753864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.753881] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.753926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.753940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.753954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.753967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.753980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.753993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.754008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.754022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.754036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.754075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.754099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.754122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.754145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.756137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.756153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.756167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.756182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.757685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.757700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.757714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.759208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.759224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.761027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.763969] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.763994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.764010] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.764032] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.764116] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.764148] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.780749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.780774] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.780808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.780905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.780945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.814138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.814163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.814198] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.832869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.832899] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.832922] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.832949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.832975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.833005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.833031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.833057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.833124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.833167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.833205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.833242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.833278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.833552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.833573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.833621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.833729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.833741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.833802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.833823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.833848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.833874] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.833895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.833917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.833939] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.833960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.833980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.833999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.834018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.834023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.834041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.834079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.834112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.834144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.834176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.834205] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.834240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.834269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.834302] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.834331] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.834363] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.834400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.834437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.834829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.834860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.834892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.834922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.834952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.834982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.835017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.835051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.835329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.835359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.835389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.835426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.835457] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.837545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.837568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.837590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.837616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.839186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.839209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.839231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.840767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.840790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.842639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.845665] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.845699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.845720] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.845748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.845812] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.845844] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.862433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.862461] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.862501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.862621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.862668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.895820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.895850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.895904] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.914785] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.914807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.914823] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.914842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.914859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.914877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.914892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.914907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.914923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.914940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.914956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.914972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.914988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.915002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.915016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.915048] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.915198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.915212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.915283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.915306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.915332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.915361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.915382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.915408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.915431] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.915454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.915476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.915499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.915520] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.915526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.915548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.915553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.915576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.915597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.915619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.915639] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.915664] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.915685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.915713] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.915732] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.915752] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.915774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.915798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.915867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.915886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.915907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.915926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.915947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.915966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.915989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.916012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.916035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.916055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.916095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.916120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.916142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.918132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.918148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.918163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.918177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.919681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.919697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.919710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.921205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.921221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.923024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.925949] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.925974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.925990] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  333.926011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.926057] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  333.926116] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  333.942715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.942739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.942775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.942866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.942906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.976083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.976105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.976148] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.994978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.994999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.995016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.995035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.995052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.995113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.995136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.995160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.995185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.995213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.995239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.995264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.995289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.995309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.995331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.995381] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.995497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.995520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.995579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.995594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.995612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.995632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.995650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.995668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.995685] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  333.995703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  333.995720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.995738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.995755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.995758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.995775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.995779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.995797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.995814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.995831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.995848] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  333.995866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.995883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.995901] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  333.995918] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  333.995936] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  333.995954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.995973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  333.996025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.996043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.996086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.996113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.996134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.996158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.996184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.996207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.996230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.996249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.996270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.996295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  333.996316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.998308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.998325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.998339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.998354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.999856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.999871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.999886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.001382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.001398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.003201] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.006128] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.006154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.006170] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.006192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.006242] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.006266] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.022901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.022924] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.022957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.023130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.023191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.056260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.056285] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.056330] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.075193] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.075215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.075231] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.075251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.075267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.075285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.075300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.075319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.075338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.075360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.075381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.075401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.075421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.075440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.075459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.075496] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.075571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.075580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.075626] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.075646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.075666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.075688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.075707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.075726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.075746] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.075765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.075784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.075803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.075821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.075825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.075844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.075847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.075867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.075886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.075905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.075924] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.075942] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.075961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.075980] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.075999] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.076018] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.076038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.076058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.076170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.076198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.076222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.076247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.076270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.076295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.076330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.076355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.076380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.076400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.076422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.076447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.076468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.078459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.078474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.078488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.078503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.080009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.080024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.080038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.081533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.081550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.083355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.086290] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.086316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.086332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.086354] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.086403] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.086429] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.103108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.103133] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.103170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.103273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.103315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.136497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.136523] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.136561] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.155436] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.155458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.155474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.155494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.155511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.155528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.155543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.155557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.155573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.155590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.155606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.155622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.155637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.155652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.155665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.155697] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.155770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.155778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.155821] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.155840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.155860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.155882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.155901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.155921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.155940] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.155959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.155978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.155997] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.156016] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.156019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.156038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.156042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.156062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.156123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.156149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.156175] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.156207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.156230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.156251] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.156273] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.156293] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.156318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.156343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.156415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.156694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.156716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.156738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.156758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.156780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.156804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.156827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.156849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.156868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.156888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.156911] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.156933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.158923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.158939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.158953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.158968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.160473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.160491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.160508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.162014] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.162031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.163840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.166775] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.166802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.166819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.166841] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.166889] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.166915] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.183584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.183608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.183641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.183730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.183769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.216949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.216976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.217021] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.235888] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.235910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.235926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.235945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.235962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.235979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.235994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.236009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.236024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.236042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.236058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.236119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.236144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.236167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.236190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.236242] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.236339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.236348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.236391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.236408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.236427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.236446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.236462] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.236479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.236496] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.236512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.236527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.236542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.236556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.236561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.236574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.236578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.236593] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.236606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.236620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.236634] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.236651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.236665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.236679] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.236693] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.236706] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.236723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.236741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.236792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.236808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.236823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.236838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.236851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.236867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.236883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.236900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.236915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.236930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.236944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.236962] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.236978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.238954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.238970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.238984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.238998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.240509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.240524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.240538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.242032] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.242048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.243889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.246822] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.246849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.246866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.246888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.246937] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.246963] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.263642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.263667] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.263701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.263799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.263839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.296988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.297012] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.297056] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.315931] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.315952] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.315969] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.315988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.316005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.316022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.316037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.316052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.316068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.316127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.316155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.316183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.316210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.316232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.316255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.316304] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.316419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.316434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.316503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.316526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.316552] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.316580] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.316602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.316627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.316651] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.316675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.316697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.316720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.316741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.316747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.316768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.316774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.316797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.316818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.316840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.316861] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.316886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.316906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.316928] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.316956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.316976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.316998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.317022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.317113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.317134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.317156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.317177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.317198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.317219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.317243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.317266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.317290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.317309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.317329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.317352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.317374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.319362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.319378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.319392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.319406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.320909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.320925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.320938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.322434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.322449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.324253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.327181] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.327214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.327229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.327250] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.327294] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.327317] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.343955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.343980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.344014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.344226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.344266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.377312] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.377336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.377380] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.396283] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.396304] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.396320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.396340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.396356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.396374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.396389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.396404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.396420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.396438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.396455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.396471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.396487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.396501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.396514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.396546] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.396619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.396627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.396669] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.396684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.396702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.396722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.396741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.396761] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.396780] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.396800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.396819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.396838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.396856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.396860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.396879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.396883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.396902] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.396921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.396947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.396963] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.396980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.396997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.397014] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.397032] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.397049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.397067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.397125] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.397198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.397220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.397243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.397264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.397287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.397309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.397334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.397358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.397383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.397403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.397425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.397448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.397471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.399464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.399481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.399498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.399517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.401027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.401044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.401058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.402599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.402614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.404440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.407379] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.407405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.407422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.407444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.407491] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.407516] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.424193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.424219] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.424256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.424358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.424399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.457586] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.457627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.457701] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.476657] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.476687] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.476710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.476738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.476761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.476785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.476807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.476827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.476849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.476874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.476897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.476919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.476941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.476961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.476980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.477025] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.477180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.477200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.477296] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.477328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.477365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.477405] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.477436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.477473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.477506] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.477540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.477571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.477603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.477632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.477640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.477670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.477678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.477710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.477740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.477771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.477799] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.477834] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.477863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.477895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.477924] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.477955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.477987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.478023] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.478162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.478193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.478226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.478256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.478287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.478318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.478354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.478390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.478424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.478453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.478485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.478521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.478552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.480617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.480640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.480661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.480682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.482331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.482354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.482374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.483914] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.483938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.485795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.488865] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.488899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.488919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.488947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.489009] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.489042] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.505665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.505696] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.505738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.505858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.505908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.539028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.539060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.539165] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.558066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.558089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.558152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.558186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.558212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.558240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.558265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.558289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.558314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.558343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.558370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.558395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.558421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.558444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.558467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.558517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.558606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.558614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.558656] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.558679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.558695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.558712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.558726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.558741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.558756] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.558770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.558783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.558796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.558809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.558812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.558825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.558828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.558841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.558853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.558866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.558878] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.558893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.558905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.558917] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.558930] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.558942] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.558956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.558973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.559018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.559032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.559046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.559059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.559072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.559085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.559131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.559157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.559182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.559204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.559226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.559253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.559276] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.561270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.561287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.561301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.561317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.562821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.562837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.562851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.564346] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.564362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.566165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.569090] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.569131] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.569148] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.569170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.569218] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.569244] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.585916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.585941] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.585975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.586074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.586165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.619264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.619290] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.619335] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.638248] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.638269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.638285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.638304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.638321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.638338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.638353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.638367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.638383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.638401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.638418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.638433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.638449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.638463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.638477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.638509] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.638581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.638589] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.638631] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.638650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.638677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.638695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.638709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.638725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.638740] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.638754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.638768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.638787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.638808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.638812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.638825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.638828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.638841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.638853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.638866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.638878] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.638893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.638906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.638918] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.638931] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.638943] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.638958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.638974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.639020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.639033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.639046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.639060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.639072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.639085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.639142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.639169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.639194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.639216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.639238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.639264] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.639288] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.641283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.641299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.641313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.641327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.642830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.642845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.642859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.644354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.644369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.646172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.649114] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.649141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.649161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.649185] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.649236] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.649263] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.665925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.665949] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.665983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.666082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.666267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.699281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.699305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.699349] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.718207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.718229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.718245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.718264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.718284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.718305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.718325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.718344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.718363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.718384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.718405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.718426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.718446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.718465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.718483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.718520] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.718587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.718596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.718642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.718661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.718681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.718703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.718722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.718742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.718761] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.718780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.718800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.718818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.718837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.718841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.718859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.718863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.718882] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.718902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.718920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.718939] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.718959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.718977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.718997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.719016] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.719034] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.719054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.719075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.719186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.719214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.719241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.719266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.719292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.719318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.719346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.719373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.719400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.719424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.719448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.719477] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.719502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.721507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.721525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.721542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.721560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.723068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.723084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.723098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.724638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.724656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.726479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.729409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.729435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.729452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.729474] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.729522] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.729548] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.746181] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.746206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.746242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.746335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.746377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.779538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.779562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.779605] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.798497] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.798518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.798535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.798556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.798576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.798597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.798616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.798636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.798655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.798677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.798697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.798717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.798738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.798756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.798775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.798811] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.798887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.798896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.798942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.798962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.798981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.799003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.799020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.799040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.799059] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.799078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.799097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.799160] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.799189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.799197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.799222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.799229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.799254] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.799280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.799305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.799329] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.799357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.799381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.799406] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.799430] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.799455] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.799482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.799516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.799587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.799610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.799632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.799653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.799673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.799694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.799718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.799742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.799765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.799786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.799806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.799830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.799853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.801847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.801863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.801881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.801899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.803406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.803422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.803436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.804928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.804943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.806748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.809666] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.809692] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.809708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.809735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.809779] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.809802] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.826446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.826470] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.826506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.826605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.826645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.859806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.859830] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.859874] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.878714] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.878736] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.878752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.878771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.878788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.878805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.878821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.878836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.878852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.878870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.878886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.878902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.878918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.878932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.878946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.878978] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.879049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.879057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.879099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.879160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.879189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.879221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.879246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.879273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.879300] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.879326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.879351] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.879376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.879400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.879408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.879430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.879437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.879461] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.879485] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.879515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.879536] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.879560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.879581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.879602] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.879623] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.879645] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.879669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.879694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.879764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.879786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.879809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.879828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.879849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.879868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.879892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.879916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.879939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.879960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.879979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.880003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.880026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.882018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.882034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.882049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.882063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.883569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.883583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.883597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.885090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.885105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.886938] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.889858] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.889884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.889900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.889922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.889969] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.889995] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.906639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.906664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.906698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.906796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.906835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.939995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  334.940021] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  334.940066] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.958942] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  334.958966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  334.958987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  334.959009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.959029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.959051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.959071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.959091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.959110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.959177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.959208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.959237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.959265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.959288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.959313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.959541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.959607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.959616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  334.959661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  334.959678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.959697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  334.959717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  334.959732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  334.959750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.959767] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  334.959783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  334.959799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  334.959814] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.959828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.959832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.959846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.959850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  334.959864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  334.959879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  334.959893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.959907] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  334.959924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  334.959943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.959963] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  334.959982] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  334.960002] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  334.960023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.960044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  334.960100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  334.960148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  334.960175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  334.960202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  334.960226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  334.960253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  334.960282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  334.960309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  334.960336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.960359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  334.960384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  334.960414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  334.960438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  334.962699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.962715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.962729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.962744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.964251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  334.964268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.964286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.965778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.965795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  334.967616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.970550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  334.970576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  334.970592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  334.970613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.970661] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  334.970686] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  334.987369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  334.987395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  334.987432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  334.987524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  334.987566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.020726] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.020750] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.020794] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.039657] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.039679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.039695] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.039715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.039731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.039749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.039765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.039779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.039795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.039813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.039829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.039845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.039861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.039874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.039888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.039920] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.039992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.040000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.040041] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.040057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.040075] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.040094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.040110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.040158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.040186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.040209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.040232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.040256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.040278] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.040285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.040307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.040314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.040338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.040359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.040383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.040404] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.040430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.040451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.040474] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.040495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.040525] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.040550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.040575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.040646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.040669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.040691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.040712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.040733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.040756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.040780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.040804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.040827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.040848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.040868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.040890] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.040913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.042906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.042924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.042941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.042960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.044468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.044484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.044498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.045990] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.046006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.047810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.050730] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.050762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.050777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.050798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.050843] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.050868] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.067511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.067538] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.067574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.067674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.067716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.100869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.100893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.100937] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.119815] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.119837] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.119854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.119873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.119890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.119907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.119923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.119938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.119954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.119971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.119988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.120004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.120020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.120034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.120048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.120080] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.120205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.120219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.120288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.120312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.120339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.120374] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.120395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.120417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.120439] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.120461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.120481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.120503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.120522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.120528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.120547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.120552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.120573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.120592] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.120613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.120631] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.120654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.120673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.120693] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.120712] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.120732] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.120753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.120777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.120847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.120868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.120889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.120908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.120928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.120948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.120972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.120995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.121018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.121037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.121057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.121081] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.121102] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.123110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.123139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.123153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.123168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.124744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.124760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.124774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.126281] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.126298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.128118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.131062] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.131089] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.131106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.131164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.131354] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.131371] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.147883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.147908] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.147945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.148046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.148088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.181271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.181295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.181331] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.200211] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.200232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.200249] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.200268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.200285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.200302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.200317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.200332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.200348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.200365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.200382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.200397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.200417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.200436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.200455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.200492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.200568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.200576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.200622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.200642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.200662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.200684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.200701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.200721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.200740] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.200759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.200778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.200797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.200815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.200819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.200838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.200841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.200861] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.200880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.200899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.200917] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.200937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.200955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.200974] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.200993] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.201012] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.201032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.201053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.201107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.201126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.201184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.201211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.201243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.201265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.201291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.201316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.201341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.201361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.201383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.201409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.201431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.203424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.203441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.203457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.203475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.206073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.206092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.206107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.207640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.207658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.209493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.212441] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.212468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.212492] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.212515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.212555] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.212572] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.229247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.229272] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.229306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.229396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.229436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.262602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.262626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.262662] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.281522] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.281543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.281562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.281584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.281604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.281625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.281644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.281663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.281682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.281704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.281725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.281745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.281765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.281784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.281803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.281840] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.281913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.281922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.281968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.281988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.282007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.282029] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.282046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.282065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.282085] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.282104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.282130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.282186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.282209] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.282217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.282238] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.282245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.282268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.282289] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.282311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.282331] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.282355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.282375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.282397] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.282417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.282438] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.282463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.282489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.282560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.282581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.282603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.282622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.282643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.282662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.282686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.282709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.282732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.282751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.282771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.282795] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.282816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.284810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.284826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.284840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.284854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.286360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.286375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.286388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.287882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.287898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.289702] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.292622] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.292648] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.292664] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.292686] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.292723] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.292739] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.309403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.309428] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.309462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.309560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.309600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.342761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.342785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.342820] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.361764] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.361788] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.361807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.361829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.361848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.361868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.361885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.361902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.361920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.361940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.361959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.361977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.361994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.362016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.362038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.362079] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.362219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.362235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.362316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.362344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.362375] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.362408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.362433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.362463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.362490] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.362519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.362545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.362570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.362594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.362601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.362625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.362631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.362658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.362682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.362707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.362730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.362759] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.362782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.362808] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.362831] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.362856] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.362883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.362913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.362999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.363025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.363051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.363075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.363101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.363126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.363181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.363206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.363231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.363252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.363274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.363300] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.363322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.365313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.365329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.365343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.365358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.366860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.366878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.366895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.368393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.368410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.370212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.373130] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.373170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.373187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.373209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.373246] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.373262] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.389965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.389990] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.390024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.390123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.390211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.423320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.423344] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.423379] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.442240] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.442263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.442282] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.442304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.442324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.442345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.442364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.442384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.442402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.442424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.442444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.442465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.442485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.442504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.442523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.442559] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.442634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.442643] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.442689] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.442709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.442729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.442751] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.442769] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.442789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.442808] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.442827] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.442847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.442866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.442884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.442888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.442907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.442911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.442930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.442949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.442968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.442987] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.443006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.443025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.443044] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.443069] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.443084] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.443101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.443119] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.443215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.443238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.443261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.443282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.443304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.443325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.443350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.443374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.443399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.443419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.443441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.443464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.443488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.445481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.445497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.445511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.445526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.447028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.447043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.447057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.448551] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.448567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.450369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.453308] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.453333] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.453348] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.453369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.453407] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.453422] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.470122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.470147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.470231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.470340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.470379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.503478] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.503504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.503541] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.522396] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.522417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.522434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.522453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.522469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.522487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.522502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.522517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.522533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.522550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.522567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.522582] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.522598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.522612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.522625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.522657] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.522722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.522730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.522771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.522787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.522805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.522824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.522839] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.522855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.522871] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.522886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.522905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.522924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.522948] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.522951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.522965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.522968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.522982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.522995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.523008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.523021] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.523035] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.523048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.523061] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.523074] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.523086] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.523101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.523117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.523202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.523224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.523246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.523266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.523288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.523309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.523334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.523358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.523382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.523402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.523424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.523448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.523471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.525463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.525481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.525498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.525516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.528100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.528118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.528135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.529672] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.529689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.531510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.534457] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.534484] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.534501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.534523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.534562] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.534579] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.551263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.551288] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.551322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.551420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.551459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.584620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.584644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.584679] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.603597] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.603620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.603637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.603657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.603674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.603692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.603708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.603723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.603740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.603758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.603775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.603792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.603808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.603823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.603837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.603870] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.603944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.603952] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.603995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.604011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.604029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.604049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.604065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.604081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.604098] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.604113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.604129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.604143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.604197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.604206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.604228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.604235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.604259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.604282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.604307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.604329] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.604356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.604378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.604402] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.604424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.604449] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.604475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.604503] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.604583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.604606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.604630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.604652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.604675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.604698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.604723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.604749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.604775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.604796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.604818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.604844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.604868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.606868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.606886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.606903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.606921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.608431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.608448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.608462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.609953] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.609969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.611773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.614692] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.614717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.614734] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.614755] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.614793] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.614809] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.631476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.631501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.631535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.631633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.631672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.664832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.664856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.664891] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.683758] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.683779] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.683795] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.683815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.683832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.683849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.683865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.683880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.683896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.683914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.683930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.683946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.683962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.683976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.683990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.684022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.684094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.684103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.684144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.684200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.684229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.684258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.684282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.684310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.684334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.684359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.684383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.684408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.684429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.684437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.684459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.684465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.684490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.684511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.684535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.684556] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.684581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.684602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.684625] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.684647] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.684670] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.684695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.684722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.684798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.684825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.684847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.684867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.684888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.684908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.684931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.684954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.684976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.684995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.685015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.685038] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.685060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.687063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.687079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.687092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.687107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.688614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.688629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.688643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.690136] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.690151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.691983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.694901] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.694927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.694943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.694964] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.695002] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.695026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.711685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.711710] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.711745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.711849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.711891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.745042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.745068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.745105] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.763969] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.763991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.764007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.764027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.764043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.764060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.764075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.764090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.764106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.764124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.764140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.764156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.764218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.764245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.764270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.764321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.764422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.764435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.764505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.764530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.764557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.764587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.764611] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.764637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.764663] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.764688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.764713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.764737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.764760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.764767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.764796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.764802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.764823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.764844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.764866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.764885] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.764908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.764929] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.764950] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.764969] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.764990] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.765013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.765039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.765110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.765133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.765155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.765193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.765217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.765238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.765264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.765287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.765312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.765333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.765355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.765381] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.765405] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.767395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.767411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.767426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.767440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.768943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.768958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.768971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.770466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.770481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.772283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.775215] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.775240] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.775256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.775278] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.775316] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.775332] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.791984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.792009] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.792044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.792140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.792227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.825377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.825418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.825478] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.844429] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.844450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.844467] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.844486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.844503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.844520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.844536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.844554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.844574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.844595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.844616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.844636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.844657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.844675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.844694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.844730] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.844806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.844814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.844861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.844880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.844900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.844922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.844941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.844961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.844980] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.844999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.845018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.845037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.845055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.845059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.845078] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.845081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.845101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.845120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.845139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.845157] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.845222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.845252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.845280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.845306] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.845331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.845359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.845388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.845465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.845491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.845514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.845539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.845570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.845593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.845617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.845641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.845664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.845685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.845706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.845729] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.845751] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.848858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.848876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.848892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.848909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.850420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.850435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.850449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.851941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.851957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.853762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.856696] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.856725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.856744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.856770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.856811] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.856837] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.873514] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.873540] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.873576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.873677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.873719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.906870] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.906895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.906929] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  335.925781] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  335.925803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  335.925822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  335.925844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.925863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.925885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.925904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.925923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.925942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.925963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.925984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.926004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.926024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.926043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.926061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.926098] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.926213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.926227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  335.926299] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  335.926326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.926354] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  335.926384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  335.926408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  335.926435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.926462] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  335.926487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  335.926512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  335.926535] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.926565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.926571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.926591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.926597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  335.926618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  335.926639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  335.926660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.926681] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  335.926705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  335.926727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.926748] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  335.926768] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  335.926789] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  335.926813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.926837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  335.926909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  335.926931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  335.926953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  335.926975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  335.926994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  335.927016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  335.927040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  335.927064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  335.927088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.927109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  335.927130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  335.927155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  335.927178] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  335.929200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.929216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.929230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.929245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.930750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  335.930768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.930786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.932284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.932301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.934122] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.937056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.937083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  335.937100] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  335.937122] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.937160] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  335.937303] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  335.953875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  335.953901] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  335.953938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  335.954038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  335.954080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  335.987231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  335.987256] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  335.987290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  336.006277] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  336.006305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  336.006326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.006351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.006372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.006394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.006414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.006433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.006453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.006476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.006497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.006517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.006536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.006555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.006573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.006614] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  336.006698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  336.006708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.006761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.006782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.006807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.006836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.006860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.006886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.006910] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  336.006935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  336.006960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.006984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.007008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.007013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.007037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.007042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.007067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.007092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.007115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.007140] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  336.007164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.007243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.007275] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  336.007305] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  336.007335] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  336.007369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.007403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  336.007503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.007535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.007564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.007595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.007618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.007638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.007661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.007681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.007702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.007720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.007739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.007765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  336.007791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.009777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.009795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.009812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.009830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.011339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.011355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.011369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.012862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.012878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.014683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.017629] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  336.017654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.017669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  336.017691] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.017728] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  336.017744] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  336.034437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.034462] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  336.034496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.034586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  336.034625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.067793] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  336.067817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.067852] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  336.086711] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  336.086732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  336.086748] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.086770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.086789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.086811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.086830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.086849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.086868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.086890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.086911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.086931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.086952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.086970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.086989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.087026] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  336.087243] [drm:drm_mode_addfb2] [FB:58]
>[  336.087291] [drm:drm_mode_addfb2] [FB:78]
>[  336.112898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  336.112983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.113040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  336.113094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.113103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.113152] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.113168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.113223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.113252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.113274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.113299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.113323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.113346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.113368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.113392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.113412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.113418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.113437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.113442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.113464] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.113483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.113504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.113523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.113547] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.113567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.113588] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.113607] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.113627] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.113649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.113673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.116207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.116227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.116246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.116265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.116284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.116302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.116323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.116343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.116362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.116381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.116399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.116419] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.116438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.118442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.118459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.118474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.118492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.119997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.120013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.120027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.121518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.121535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.123339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.126275] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.126303] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.126320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.126343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.143091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.143116] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.143151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.159768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.159777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.176520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.176562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.193134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.193160] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.193234] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.212094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.212115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.212137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.212156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.212178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.212242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.212264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.212281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.212300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.212317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.212333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.212348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.212362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.212377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.212413] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.212481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.212490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.212536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.212556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.212577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.212599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.212618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.212639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.212659] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.212678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.212698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.212717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.212737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.212741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.212761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.212765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.212785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.212804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.212824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.212843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.212863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.212882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.212902] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.212921] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.212942] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.212962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.212984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.213030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.213050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.213070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.213090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.213109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.213128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.213156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.213174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.213213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.213234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.213256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.213280] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.213302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.215292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.215308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.215323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.215337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.216839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.216857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.216874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.218370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.218387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.221269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.224215] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.224243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.224259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.224281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.241019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.241045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.241080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.241169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.241258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.257721] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.257745] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.257781] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.276673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.276692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.276712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.276728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.276746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.276761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.276779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.276799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.276821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.276841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.276862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.276882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.276901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.276920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.276957] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.277030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.277039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.277085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.277105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.277124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.277146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.277165] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.277184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.277243] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.277271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.277296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.277319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.277343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.277350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.277373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.277379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.277404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.277426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.277449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.277470] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.277497] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.277518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.277542] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.277563] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.277586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.277614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.277642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.278002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.278024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.278046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.278066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.278086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.278107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.278130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.278153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.278176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.278194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.278231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.278255] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.278279] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.280391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.280407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.280421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.280436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.281938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.281954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.281967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.283462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.283478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.285282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.288216] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.288241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.288258] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.288280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.305032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.305058] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.305093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.305232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.305292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.321734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.321758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.321794] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.340685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.340704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.340724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.340741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.340758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.340773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.340787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.340803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.340821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.340837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.340852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.340868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.340882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.340895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.340927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.340999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.341007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.341049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.341065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.341082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.341102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.341117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.341133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.341150] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.341165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.341180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.341194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.341247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.341256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.341286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.341292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.341315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.341335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.341357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.341376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.341400] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.341420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.341441] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.341461] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.341482] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.341507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.341532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.341842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.341864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.341886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.341906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.341927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.341948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.341971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.341994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.342017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.342036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.342057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.342080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.342103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.344102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.344118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.344132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.344147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.345652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.345670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.345687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.347184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.347213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.349016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.351950] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.351977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.351997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.352023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.368766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.368792] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.368826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.368925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.368964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.385447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.385471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.385515] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.404379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.404398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.404418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.404435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.404452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.404468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.404482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.404498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.404515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.404531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.404547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.404562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.404576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.404590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.404622] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.404686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.404695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.404736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.404751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.404769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.404788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.404803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.404819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.404836] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.404851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.404866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.404881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.404894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.404898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.404911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.404915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.404929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.404943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.404957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.404970] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.404989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.405008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.405028] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.405047] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.405066] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.405086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.405107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.405160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.405180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.405199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.405262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.405288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.405315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.405343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.405371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.405398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.405420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.405444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.405473] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.405497] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.407496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.407512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.407526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.407541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.409043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.409058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.409071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.410566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.410582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.412387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.415321] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.415348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.415365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.415387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.432138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.432163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.432197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.432363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.432413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.448838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.448863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.448899] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.467772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.467792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.467814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.467834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.467855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.467875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.467894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.467913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.467935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.467955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.467976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.467996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.468015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.468033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.468070] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.468142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.468151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.468197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.468263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.468289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.468316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.468338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.468365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.468388] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.468411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.468433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.468455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.468474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.468481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.468502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.468508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.468530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.468550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.468571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.468590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.468841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.468862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.468884] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.468904] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.468925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.468947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.468971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.469041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.469062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.469083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.469103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.469123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.469143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.469167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.469190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.469230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.469252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.469272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.469297] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.469319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.471490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.471507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.471521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.471537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.473040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.473056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.473069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.474563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.474579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.476382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.479330] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.479356] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.479373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.479395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.496131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.496156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.496190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.496367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.496412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.512832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.512857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.512893] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.531781] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.531800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.531820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.531837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.531854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.531869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.531884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.531900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.531920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.531941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.531962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.531982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.532001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.532020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.532056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.532131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.532140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.532186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.532206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.532267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.532298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.532322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.532350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.532376] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.532401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.532425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.532450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.532472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.532479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.532501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.532508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.532532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.532555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.532578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.532600] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.532626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.532648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.532672] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.532965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.532985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.533009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.533035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.533104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.533125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.533146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.533166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.533186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.533207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.533247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.533272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.533296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.533316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.533338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.533364] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.533385] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.535527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.535543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.535557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.535571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.537074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.537089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.537102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.538597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.538615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.540419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.543375] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.543402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.543421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.543446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.560169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.560194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.560275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.560396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.560434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.576870] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.576894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.576931] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.595112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.595131] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.595151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.595168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.595185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.595201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.595254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.595280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.595310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.595338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.595516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.595534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.595549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.595564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.595596] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.595668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.595676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.595718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.595734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.595752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.595771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.595786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.595802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.595819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.595834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.595849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.595863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.595877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.595881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.595894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.595898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.595912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.595926] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.595939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.595952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.595968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.595982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.595997] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.596010] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.596023] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.596039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.596057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.596107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.596123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.596137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.596151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.596164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.596179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.596195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.596210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.596255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.596289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.596309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.596334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.596355] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.598347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.598364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.598378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.598393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.599895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.599910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.599927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.601423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.601439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.603241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.606172] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.606200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.606257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.606297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.622987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.623011] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.623045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.623134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.623173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.639672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.639696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.639739] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.658605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.658624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.658644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.658661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.658678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.658693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.658708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.658724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.658741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.658758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.658773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.658789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.658803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.658817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.658849] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.658919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.658927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.658969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.658984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.659002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.659021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.659036] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.659053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.659069] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.659084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.659099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.659114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.659127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.659131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.659145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.659148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.659162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.659176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.659190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.659208] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.659268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.659292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.659317] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.659340] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.659365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.659390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.659418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.659494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.659517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.659540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.659562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.659585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.659608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.659634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.659658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.659683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.659704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.659726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.659752] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.659775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.661797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.661821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.661843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.661865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.663382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.663398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.663411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.664903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.664921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.666728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.670764] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.670791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.670808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.670830] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.687530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.687554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.687587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.687682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.687719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.704259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.704283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.704319] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.723194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.723213] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.723276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.723300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.723328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.723352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.723376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.723400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.723429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.723455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.723480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.723506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.723528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.723550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.723599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.723712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.723725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.723791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.723808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.723826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.723847] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.723866] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.723886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.723905] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.723924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.723944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.723963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.723981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.723985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.724004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.724008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.724027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.724046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.724065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.724084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.724103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.724122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.724140] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.724159] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.724178] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.724198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.724219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.724321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.724353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.724377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.724399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.724421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.724443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.724468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.724493] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.724517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.724538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.724559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.724582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.724604] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.726596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.726612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.726627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.726641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.728161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.728176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.728190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.729685] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.729700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.731502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.734449] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.734476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.734496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.734520] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.751253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.751278] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.751313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.751409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.751449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.767953] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.767979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.768017] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.786891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.786909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.786929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.786946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.786963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.786982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.787001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.787021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.787042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.787063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.787083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.787103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.787122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.787141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.787177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.787301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.787315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.787387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.787412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.787439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.787468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.787491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.787516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.787540] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.787564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.787587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.787609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.787630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.787636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.787658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.787663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.787692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.787711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.787732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.787750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.787773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.787792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.787812] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.787832] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.787852] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.787873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.787897] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.787967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.787987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.788007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.788027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.788047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.788067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.788089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.788112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.788135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.788154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.788174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.788197] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.788219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.790229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.790257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.790271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.790289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.791796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.791813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.791830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.793333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.793349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.795174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.798097] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.798123] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.798139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.798161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.814874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.814901] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.814938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.815031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.815072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.831575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.831600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.831638] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.849673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.849691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.849711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.849728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.849746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.849761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.849776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.849792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.849810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.849826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.849842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.849858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.849872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.849886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.849917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.849982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.849990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.850031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.850047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.850065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.850084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.850099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.850116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.850132] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.850150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.850170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.850195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.850209] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.850213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.850226] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.850255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.850278] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.850298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.850320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.850339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.850362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.850381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.850401] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.850420] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.850440] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.850462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.850486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.850556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.850577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.850598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.850619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.850641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.850663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.850686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.850710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.850734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.850755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.850776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.850800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.850824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.852811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.852827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.852844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.852862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.854371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.854387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.854401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.855892] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.855908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.857729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.860664] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.860690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.860706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.860728] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.877479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.877504] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.877539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.877637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.877677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.894160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.894185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.894229] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.913110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.913129] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.913149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.913166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.913183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.913198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.913213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.913229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.913288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.913317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.913344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.913371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.913393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.913416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.913468] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.913580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.913594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.913662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.913685] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.913711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.913746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.913767] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.913789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.913811] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.913833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.913853] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.913874] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.913892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.913898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.913917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.913922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.913943] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.913962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.913982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.914000] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.914023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.914041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.914061] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.914080] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.914099] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.914123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.914147] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.914216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.914256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.914280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.914300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.914321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.914342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.914367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.914390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.914414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.914434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.914455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.914481] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.914502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.916497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.916513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.916530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.916549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.918054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.918070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.918085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.919582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.919598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.921402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.924342] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.924369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.924386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.924408] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.941152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.941178] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.941213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.941393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.941451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.957853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  336.957878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  336.957916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  336.976791] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  336.976809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  336.976829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.976846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.976863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.976877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.976892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.976907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  336.976925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.976941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.976956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.976972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.976986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.977000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.977035] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  336.977109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  336.977117] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  336.977163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  336.977183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.977203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  336.977225] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  336.977291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  336.977316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.977342] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  336.977364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  336.977387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  336.977407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.977429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.977435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.977457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.977463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  336.977485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  336.977505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  336.977527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.977547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.977571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  336.977590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.977612] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  336.977632] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  336.977653] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  336.977678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.977704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  336.977775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  336.977799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  336.977821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  336.977842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  336.977863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  336.977885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  336.977909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  336.977933] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  336.977956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  336.977977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  336.977997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  336.978020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  336.978042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  336.980036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.980052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.980066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.980080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.981586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  336.981601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.981614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.983106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.983122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  336.984926] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.987860] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  336.987888] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  336.987907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  336.987931] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.004677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.004703] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.004737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.004836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.004875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.021377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.021402] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.021441] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.040314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.040333] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.040352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.040369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.040386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.040401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.040415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.040431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.040448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.040465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.040484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.040505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.040524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.040543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.040580] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.040645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.040654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.040700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.040727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.040746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.040765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.040780] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.040797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.040814] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.040829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.040844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.040858] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.040871] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.040875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.040888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.040892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.040906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.040920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.040933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.040946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.040962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.040976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.040990] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.041003] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.041016] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.041032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.041049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.041097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.041112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.041126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.041140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.041153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.041167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.041183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.041197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.041212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.041225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.041277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.041304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.041328] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.043326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.043342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.043356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.043370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.044877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.044894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.044912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.046410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.046426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.048232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.051164] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.051190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.051206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.051227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.067943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.067969] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.068003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.068101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.068140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.084624] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.084648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.084692] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.103544] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.103563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.103583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.103600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.103618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.103637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.103657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.103676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.103697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.103718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.103738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.103758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.103777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.103796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.103832] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.103905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.103914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.103960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.103980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.104000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.104022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.104041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.104060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.104080] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.104099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.104118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.104137] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.104155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.104159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.104185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.104188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.104205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.104221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.104235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.104287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.104312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.104334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.104356] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.104379] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.104399] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.104424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.104450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.104523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.104545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.104567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.104589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.104611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.104634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.104659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.104682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.104705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.104726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.104747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.104772] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.104795] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.106790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.106806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.106820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.106838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.108358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.108375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.108389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.109888] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.109904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.111712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.114656] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.114683] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.114702] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.114727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.131470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.131495] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.131530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.131634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.131686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.148183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.148208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.148243] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.167145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.167164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.167184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.167200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.167218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.167233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.167290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.167317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.167346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.167374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.167400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.167426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.167449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.167471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.167520] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.167642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.167654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.167717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.167740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.167765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.167792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.167814] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.167838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.167862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.167885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.167907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.167928] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.167947] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.167953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.167973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.167978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.167999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.168020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.168039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.168059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.168082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.168104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.168123] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.168143] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.168162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.168185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.168209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.168300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.168324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.168347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.168369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.168392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.168415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.168441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.168465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.168490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.168511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.168534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.168559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.168582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.170590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.170607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.170622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.170637] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.172140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.172156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.172170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.173665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.173681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.175487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.178415] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.178441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.178458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.178479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.195187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.195213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.195247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.195463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.195502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.211867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.211891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.211935] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.230818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.230836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.230858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.230878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.230899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.230919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.230938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.230957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.230978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.230999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.231019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.231040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.231059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.231077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.231113] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.231180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.231189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.231235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.231255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.231315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.231347] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.231371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.231398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.231423] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.231449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.231473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.231497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.231519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.231526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.231548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.231555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.231579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.231601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.231625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.231646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.231673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.231694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.231718] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.231739] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.231762] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.231789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.231817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.231896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.231921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.231945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.231968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.231991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.232015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.232041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.232074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.232097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.232116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.232137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.232159] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.232181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.234173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.234189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.234203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.234217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.235722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.235737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.235750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.238347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.238364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.240191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.243120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.243146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.243163] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.243184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.259891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.259918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.259955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.260047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.260088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.276571] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.276597] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.276642] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.295507] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.295526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.295546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.295562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.295580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.295595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.295609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.295625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.295642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.295658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.295673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.295688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.295702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.295716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.295747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.295819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.295828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.295869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.295884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.295902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.295921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.295936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.295952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.295968] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.295983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.295998] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.296012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.296026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.296030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.296043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.296047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.296061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.296075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.296089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.296102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.296119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.296133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.296146] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.296160] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.296174] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.296190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.296207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.296296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.296322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.296346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.296368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.296392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.296415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.296441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.296468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.296495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.296523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.296544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.296570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.296592] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.298586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.298603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.298621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.298639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.300143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.300159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.300174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.301686] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.301710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.303532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.306469] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.306495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.306512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.306534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.323284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.323309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.323344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.323443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.323482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.339984] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.340008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.340044] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.358033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.358052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.358072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.358089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.358107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.358122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.358137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.358153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.358170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.358187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.358206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.358227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.358245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.358305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.358358] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.358472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.358486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.358538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.358555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.358575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.358597] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.358617] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.358637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.358657] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.358677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.358697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.358717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.358736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.358740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.358759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.358763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.358783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.358802] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.358822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.358841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.358861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.358879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.358905] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.358922] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.358937] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.358953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.358971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.359019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.359033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.359047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.359060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.359073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.359087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.359103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.359117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.359131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.359145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.359157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.359174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.359188] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.361163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.361179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.361194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.361209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.362714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.362729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.362742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.364237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.364253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.366083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.369017] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.369045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.369064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.369089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.385833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.385859] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.385893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.385992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.386032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.402514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.402539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.402582] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.421450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.421471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.421493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.421512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.421534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.421553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.421572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.421591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.421612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.421633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.421653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.421674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.421692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.421711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.421748] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.421814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.421823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.421868] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.421888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.421908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.421930] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.421949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.421968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.421987] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.422007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.422026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.422045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.422063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.422067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.422086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.422089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.422109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.422128] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.422146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.422164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.422184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.422202] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.422221] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.422240] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.422259] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.422326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.422352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.422423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.422444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.422467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.422488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.422509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.422530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.422555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.422580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.422604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.422625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.422646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.422671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.422695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.424685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.424701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.424715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.424729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.426234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.426250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.426296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.427804] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.427823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.429647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.432589] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.432617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.432633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.432655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.449389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.449415] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.449451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.449543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.449583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.466078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.466102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.466145] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.484996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.485015] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.485036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.485056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.485078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.485097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.485116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.485135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.485157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.485177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.485197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.485218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.485237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.485256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.485347] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.485459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.485473] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.485542] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.485568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.485596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.485626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.485650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.485677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.485703] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.485727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.485753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.485782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.485804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.485809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.485830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.485836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.485857] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.485878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.485900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.485921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.485945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.485967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.485988] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.486010] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.486029] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.486052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.486077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.486148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.486171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.486193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.486214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.486235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.486258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.486298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.486323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.486345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.486367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.486390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.486416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.486439] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.488431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.488447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.488461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.488476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.489979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.489995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.490012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.491509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.491526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.493329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.496248] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.496310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.496339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.496375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.513030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.513056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.513093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.513193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.513235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.529730] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.529755] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.529793] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.548673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.548691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.548711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.548728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.548745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.548760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.548774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.548791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.548811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.548832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.548853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.548873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.548892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.548911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.548947] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.549023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.549031] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.549077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.549097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.549117] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.549139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.549157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.549177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.549196] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.549215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.549235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.549253] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.549279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.549314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.549339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.549348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.549372] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.549396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.549420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.549442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.549467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.549490] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.549513] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.549536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.549558] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.549584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.549610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.549907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.549931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.549954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.549976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.549999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.550021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.550046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.550070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.550094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.550116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.550137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.550162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.550185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.552173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.552189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.552203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.552221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.553728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.553744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.553758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.556349] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.556366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.559234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.562153] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.562178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.562194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.562216] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.578934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.578959] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.578994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.579092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.579131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.595615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.595639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.595683] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.614536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.614555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.614576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.614596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.614617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.614637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.614656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.614675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.614697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.614717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.614738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.614758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.614777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.614796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.614832] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.614909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.614918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.614964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.614983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.615003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.615025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.615044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.615064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.615083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.615102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.615121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.615140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.615159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.615163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.615181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.615185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.615204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.615223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.615242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.615261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.615323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.615350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.615377] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.615400] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.615426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.615452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.615480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.615558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.615581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.615605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.615627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.615651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.615681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.615704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.615728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.615750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.615770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.615790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.615812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.615835] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.617911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.617927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.617942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.617956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.619473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.619491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.619505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.621010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.621027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.622835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.625767] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.625794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.625811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.625833] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.642585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.642611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.642645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.642735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.642775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.659280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.659321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.659357] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.678230] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.678250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.678270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.678325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.678354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.678379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.678402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.678575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.678594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.678611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.678631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.678652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.678671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.678689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.678725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.678798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.678807] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.678853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.678872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.678892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.678913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.678932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.678952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.678971] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.678990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.679010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.679028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.679047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.679051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.679070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.679073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.679093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.679118] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.679134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.679149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.679165] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.679180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.679193] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.679207] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.679220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.679235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.679251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.679333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.679354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.679377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.679397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.679419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.679440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.679465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.679489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.679513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.679532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.679554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.679579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.679601] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.681860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.681876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.681891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.681905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.683413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.683429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.683442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.684934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.684949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.686754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.689701] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.689728] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.689744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.689767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.706505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.706531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.706565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.706664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.706703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.723206] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.723232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.723270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.742187] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.742206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.742226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.742242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.742260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.742274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.742330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.742354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.742384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.742411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.742437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.742463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.742484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.742506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.742555] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.742669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.742683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.742749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.742774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.742799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.742827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.742849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.742874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.742897] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.742921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.742943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.742965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.742986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.742992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.743013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.743019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.743041] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.743062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.743083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.743103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.743128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.743149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.743171] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.743191] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.743213] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.743238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.743264] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.743362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.743386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.743411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.743432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.743464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.743485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.743509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.743533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.743556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.743578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.743597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.743621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.743642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.745633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.745649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.745663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.745677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.747179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.747194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.747208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.748703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.748718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.750521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.753469] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.753495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.753512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.753534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.770271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.770314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.770350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.770451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.770493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.786952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.786977] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.787019] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.805893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.805911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.805931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.805948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.805965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.805980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.805995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.806011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.806028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.806045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.806060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.806075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.806090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.806103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.806139] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.806214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.806223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.806269] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.806288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.806349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.806382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.806406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.806433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.806459] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.806484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.806507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.806532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.806554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.806561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.806583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.806590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.806615] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.806637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.806661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.806682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.806708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.806730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.806754] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.806774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.806797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.806824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.806851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.806928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.806950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.806973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.807001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.807022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.807042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.807065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.807088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.807112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.807131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.807151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.807174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.807196] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.809193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.809209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.809227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.809245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.810753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.810768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.810783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.812277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.812305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.814107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.817041] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.817068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.817084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.817107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.833858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.833883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.833918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.834008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.834047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.850538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.850563] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.850606] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.869466] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.869485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.869505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.869522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.869539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.869554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.869573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.869593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.869614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.869635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.869655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.869676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.869694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.869713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.869750] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.869817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.869826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.869872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.869892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.869911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.869933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.869952] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.869971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.869991] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.870010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.870029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.870048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.870066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.870070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.870089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.870092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.870112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.870131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.870150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.870169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.870188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.870207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.870225] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.870244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.870263] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.870283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.870344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.870425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.870447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.870471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.870492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.870514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.870536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.870561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.870586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.870610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.870629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.870650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.870676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.870698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.872691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.872707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.872722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.872736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.874243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.874258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.874272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.875797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.875813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.877640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.880585] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.880610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.880625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.880645] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.897389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.897416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.897453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.897554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.897595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.914071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.914094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.914137] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.933014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.933033] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.933053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.933073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.933094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.933114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.933133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.933152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.933174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.933194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.933214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.933235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.933254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.933272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.933353] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.933656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.933666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.933711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.933729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.933747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.933767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.933782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.933799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.933816] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.933832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.933851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.933870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.933889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.933893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.933918] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.933921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.933936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.933950] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.933967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.933984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.934002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.934019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.934037] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.934054] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.934071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.934090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.934108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.934158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.934176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.934194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.934211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.934228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.934246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.934265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.934283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.934329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.934356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.934378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.934404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.934426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.936422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.936438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.936452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.936467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.937970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.937985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.938000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.939497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.939513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.941325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.944256] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  337.944283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.944332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  337.944370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.961025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.961051] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.961085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.961182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.961222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.977706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.977730] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.977774] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.996634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.996653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.996673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.996690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.996708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.996723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.996737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.996753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.996770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.996787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.996802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.996818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.996832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.996845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.996877] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.996949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.996957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.996999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.997014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.997033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.997056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.997075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.997094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.997114] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  337.997133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  337.997152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.997171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.997189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.997193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.997212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.997215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.997235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.997254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.997272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.997291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.997359] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.997383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.997408] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  337.997429] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  337.997452] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  337.997478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.997504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  337.997576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.997597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.997618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.997639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.997660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.997682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.997705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.997729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.997752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.997771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.997792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.997815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  337.997838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.999858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.999876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.999890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.999905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.001417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.001432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.001446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.002938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.002956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.004763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.007709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.007736] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.007752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.007774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.024513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.024539] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.024573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.024672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.024711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.041213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.041237] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.041273] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.060067] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.060087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.060109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.060128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.060150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.060169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.060188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.060207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.060228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.060249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.060269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.060290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.060350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.060375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.060430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.060532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.060545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.060615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.060638] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.060665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.060694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.060716] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.060742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.060765] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.060797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.060817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.060838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.060858] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.060863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.060883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.060888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.060910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.060929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.060950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.060969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.060992] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.061011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.061032] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.061051] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.061071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.061092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.061116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.061186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.061206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.061227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.061246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.061267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.061287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.061329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.061354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.061378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.061398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.061419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.061445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.061466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.063455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.063471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.063486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.063503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.065007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.065023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.065037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.066531] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.066547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.068349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.071281] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.071339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.071367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.071404] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.088100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.088125] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.088160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.088255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.088295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.104800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.104826] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.104864] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.123738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.123756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.123776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.123792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.123814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.123833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.123852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.123871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.123893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.123914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.123934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.123954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.123973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.123992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.124028] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.124102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.124111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.124157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.124177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.124196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.124225] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.124240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.124257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.124273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.124288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.124302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.124348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.124371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.124378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.124400] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.124406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.124429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.124451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.124473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.124495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.124520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.124542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.124564] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.124585] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.124607] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.124633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.124658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.124938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.124961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.124984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.125006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.125028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.125048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.125073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.125096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.125120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.125142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.125161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.125186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.125209] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.127205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.127221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.127235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.127249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.128756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.128771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.128784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.130278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.130293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.132126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.135059] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.135085] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.135102] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.135124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.151876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.151901] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.151936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.152034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.152074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.168557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.168583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.168619] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.187468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.187487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.187507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.187524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.187542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.187557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.187571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.187587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.187605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.187621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.187637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.187652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.187666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.187680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.187713] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.187785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.187793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.187834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.187850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.187867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.187886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.187901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.187917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.187933] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.187948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.187963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.187977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.187991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.187995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.188008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.188011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.188026] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.188039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.188053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.188066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.188082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.188096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.188110] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.188123] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.188137] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.188153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.188170] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.188219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.188234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.188249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.188263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.188277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.188292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.188308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.188369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.188399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.188422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.188447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.188475] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.188501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.190499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.190515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.190529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.190544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.193129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.193148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.193167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.194669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.194687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.197573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.200522] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.200549] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.200568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.200593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.217340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.217365] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.217400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.217500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.217541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.234004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.234028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.234062] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.252919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.252940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.252962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.252981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.253003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.253022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.253042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.253061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.253082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.253103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.253123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.253144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.253163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.253181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.253218] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.253285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.253293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.253397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.253424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.253453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.253484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.253510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.253537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.253564] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.253589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.253614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.253638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.253661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.253667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.253689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.253695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.253718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.253742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.253765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.253788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.253814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.253837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.253860] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.253884] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.253904] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.253930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.253957] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.254035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.254059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.254082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.254105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.254129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.254153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.254180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.254205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.254231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.254255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.254282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.254307] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.254351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.256342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.256360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.256377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.256395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.257902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.257918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.257933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.259431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.259447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.261262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.264194] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.264221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.264240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.264265] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.281012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.281039] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.281076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.281168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.281210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.297693] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.297719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.297755] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.316618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.316637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.316657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.316674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.316692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.316708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.316722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.316738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.316755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.316771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.316787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.316807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.316826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.316845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.316882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.316956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.316965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.317010] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.317030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.317050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.317072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.317091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.317110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.317130] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.317149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.317168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.317187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.317205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.317209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.317227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.317231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.317250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.317269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.317288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.317307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.317372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.317403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.317430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.317456] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.317481] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.317509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.317538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.317616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.317641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.317665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.317689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.317720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.317742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.317766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.317789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.317813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.317834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.317855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.317878] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.317901] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.319913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.319931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.319945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.319960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.321470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.321485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.321499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.322991] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.323006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.324822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.327769] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.327797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.327814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.327836] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.344573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.344599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.344635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.344734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.344776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.361273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.361297] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.361382] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.380261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.380280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.380300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.380317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.380380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.380408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.380433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.380460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.380489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.380515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.380540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.380565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.380589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.380611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.380661] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.380762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.380771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.380813] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.380832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.380852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.380875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.380893] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.380913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.380932] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.380951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.380971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.380990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.381008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.381012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.381031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.381034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.381054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.381073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.381091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.381110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.381129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.381148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.381173] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.381189] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.381204] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.381220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.381237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.381283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.381297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.381311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.381354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.381375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.381399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.381425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.381449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.381474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.381496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.381518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.381544] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.381568] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.383563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.383578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.383594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.383612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.385116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.385132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.385146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.386641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.386657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.389563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.392510] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.392537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.392553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.392575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.409314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.409357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.409391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.409491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.409530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.426014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.426037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.426073] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.444938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.444957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.444977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.444994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.445012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.445027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.445041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.445060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.445082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.445103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.445123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.445143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.445162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.445181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.445218] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.445285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.445293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.445388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.445413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.445440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.445470] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.445493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.445521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.445540] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.445557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.445573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.445588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.445603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.445607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.445621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.445625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.445639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.445654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.445668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.445681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.445698] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.445713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.445727] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.445748] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.445761] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.445776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.445793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.445842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.445856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.445869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.445882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.445895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.445909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.445924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.445939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.445954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.445967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.445980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.445996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.446010] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.448003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.448020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.448035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.448050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.449557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.449573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.449587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.451079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.451095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.452901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.455835] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.455862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.455878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.455900] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.472652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.472677] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.472711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.472803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.472842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.489364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.489388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.489424] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.508289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.508308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.508328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.508388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.508417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.508441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.508466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.508488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.508507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.508523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.508539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.508555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.508570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.508584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.508617] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.508690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.508699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.508741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.508758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.508776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.508796] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.508811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.508829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.508845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.508861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.508876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.508892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.508911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.508916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.508934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.508938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.508958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.508977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.508997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.509016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.509037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.509056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.509076] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.509095] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.509114] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.509141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.509160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.509210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.509226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.509240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.509258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.509275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.509293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.509313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.509353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.509379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.509400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.509421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.509445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.509467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.512560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.512578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.512595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.512611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.514120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.514138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.514155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.515652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.515669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.517473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.520428] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.520452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.520467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.520488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.537223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.537248] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.537283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.537480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.537519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.553923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.553947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.553984] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.572860] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.572878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.572898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.572915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.572932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.572947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.572961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.572976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.572994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.573011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.573026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.573042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.573056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.573070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.573105] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.573179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.573188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.573234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.573253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.573273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.573295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.573314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.573333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.573395] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.573424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.573453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.573478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.573503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.573509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.573533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.573540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.573564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.573596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.573618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.573640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.573665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.573687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.573709] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.573731] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.573753] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.573779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.573805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.574130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.574154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.574177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.574199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.574221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.574244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.574268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.574292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.574315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.574336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.574374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.574401] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.574424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.576544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.576560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.576574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.576589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.578092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.578107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.578120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.579615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.579631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.581436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.584383] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.584410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.584427] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.584448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.601187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.601213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.601247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.601397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.601456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.617888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.617913] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.617951] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.636077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.636096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.636116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.636133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.636151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.636166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.636180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.636196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.636214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.636234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.636254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.636275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.636294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.636312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.636397] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.636515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.636529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.636600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.636626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.636654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.636684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.636709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.636736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.636762] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.636787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.636812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.636836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.636859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.636865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.636888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.636895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.636925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.636946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.636967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.636988] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.637012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.637034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.637056] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.637077] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.637098] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.637120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.637144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.637215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.637238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.637260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.637281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.637303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.637325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.637367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.637390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.637415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.637437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.637459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.637485] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.637508] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.639498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.639514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.639528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.639543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.641046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.641064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.641081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.643658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.643677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.645484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.648431] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.648458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.648475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.648497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.665230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.665254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.665288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.665479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.665519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.681935] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.681958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.681994] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.700868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.700887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.700907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.700926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.700948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.700967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.700986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.701006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.701027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.701047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.701068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.701088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.701107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.701125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.701162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.701236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.701244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.701291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.701310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.701330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.701395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.701425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.701454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.701483] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.701509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.701535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.701560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.701584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.701591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.701614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.701620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.701644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.701668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.701692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.701716] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.701744] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.701767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.701792] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.701816] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.701840] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.701867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.702130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.702209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.702235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.702267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.702289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.702311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.702334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.702379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.702403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.702428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.702450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.702472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.702604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.702627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.704618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.704634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.704648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.704663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.706166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.706183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.706200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.707697] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.707714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.709517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.712464] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.712491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.712508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.712530] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.729267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.729294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.729330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.729514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.729561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.745968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.745993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.746031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.764918] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.764937] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.764957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.764974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.764991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.765007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.765021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.765039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.765061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.765082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.765102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.765123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.765142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.765160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.765197] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.765270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.765278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.765324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.765344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.765407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.765440] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.765466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.765495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.765523] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.765549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.765575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.765600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.765624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.765631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.765654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.765661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.765686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.765715] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.765738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.765759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.765784] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.765806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.765838] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.766084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.766106] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.766131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.766156] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.766227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.766250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.766272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.766294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.766315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.766337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.766383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.766407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.766432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.766454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.766476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.766502] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.766645] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.768636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.768652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.768666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.768681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.770186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.770201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.770214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.771709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.771724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.773528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.776476] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.776502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.776521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.776547] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.793277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.793304] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.793341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.793527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.793573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.809979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.810004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.810042] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.828917] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.828936] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.828957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.828977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.828998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.829018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.829037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.829056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.829077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.829098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.829118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.829138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.829157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.829176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.829213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.829288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.829297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.829343] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.829404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.829435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.829467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.829493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.829521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.829548] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.829574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.829600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.829624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.829648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.829656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.829679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.829685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.829710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.829734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.829758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.829781] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.830037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.830064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.830095] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.830118] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.830140] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.830164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.830189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.830260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.830282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.830304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.830326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.830347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.830386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.830411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.830436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.830460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.830482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.830504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.830529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.830553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.832707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.832723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.832736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.832751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.834253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.834268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.834281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.835777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.835795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.837600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.840543] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.840570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.840587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.840609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.857351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.857392] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.857427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.857516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.857556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.874031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.874057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.874102] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.892953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.892972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.892993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.893010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.893027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.893043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.893058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.893074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.893092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.893108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.893124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.893140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.893154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.893168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.893200] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.893265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.893273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.893315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.893331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.893348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.893415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.893443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.893471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.893498] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.893524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.893556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.893579] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.893601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.893607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.893628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.893634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.893656] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.893678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.893701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.893722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.893747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.893769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.893791] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.893813] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.893835] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.893859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.893883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.893955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.893978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.893999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.894021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.894043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.894063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.894087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.894111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.894134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.894156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.894177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.894202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.894225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.896216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.896232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.896246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.896261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.898862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.898881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.898900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.900423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.900441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.902245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.905167] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.905193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.905209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.905231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.921945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.921971] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.922008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.922107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.922148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.938628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  338.938654] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  338.938700] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  338.957553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  338.957572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  338.957592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.957609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.957626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.957641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.957656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.957672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.957689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.957706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.957721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.957736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.957750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.957764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.957796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.957870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.957879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  338.957921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  338.957937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.957955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  338.957974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.957989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.958006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.958029] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  338.958043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.958056] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.958069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.958082] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.958085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.958097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.958100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  338.958113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  338.958126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.958139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.958151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.958166] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  338.958178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.958191] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  338.958203] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  338.958216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  338.958230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.958246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  338.958292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  338.958306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  338.958320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  338.958333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  338.958345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  338.958398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  338.958421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  338.958446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  338.958470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.958489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  338.958510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  338.958536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  338.958558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  338.960552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.960568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.960583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.960597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.962101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  338.962116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.962130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.963626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.963642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  338.965447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.968390] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.968416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  338.968433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.968455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.985197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  338.985222] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  338.985257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  338.985479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  338.985526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.001899] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.001924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.001962] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.020839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.020857] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.020877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.020894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.020912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.020926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.020941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.020957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.020974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.020991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.021007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.021023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.021037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.021051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.021084] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.021156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.021165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.021206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.021222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.021240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.021259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.021274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.021291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.021307] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.021323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.021338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.021353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.021411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.021418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.021448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.021454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.021476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.021496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.021518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.021537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.021561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.021580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.021602] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.021622] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.021643] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.021668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.021693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.021765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.021786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.021806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.021826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.021846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.021866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.021889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.021912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.021935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.021954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.021974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.021996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.022018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.024011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.024027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.024042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.024056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.026641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.026658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.026673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.028168] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.028184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.031054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.033990] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.034017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.034034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.034056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.050805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.050830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.050865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.050963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.051004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.067486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.067510] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.067553] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.086409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.086427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.086449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.086469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.086490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.086509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.086529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.086548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.086569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.086590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.086610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.086631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.086649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.086668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.086705] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.086770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.086779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.086825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.086845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.086864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.086893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.086910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.086927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.086943] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.086957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.086971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.086984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.086997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.087000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.087017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.087020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.087038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.087055] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.087073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.087090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.087107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.087125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.087142] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.087159] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.087176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.087195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.087213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.087263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.087281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.087298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.087316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.087333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.087350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.087407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.087435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.087461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.087482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.087504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.087531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.087553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.089547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.089563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.089577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.089592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.092176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.092195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.092211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.093712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.093728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.095533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.098466] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.098492] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.098508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.098529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.115279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.115303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.115336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.115513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.115559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.131976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.132000] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.132043] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.150907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.150926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.150946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.150963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.150980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.150994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.151009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.151025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.151042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.151058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.151074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.151089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.151103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.151117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.151149] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.151220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.151229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.151271] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.151287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.151311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.151329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.151344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.151360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.151404] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.151431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.151453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.151477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.151497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.151504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.151525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.151531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.151554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.151574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.151596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.151616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.151641] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.151661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.151684] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.151704] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.151726] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.151751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.151777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.151849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.151869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.151890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.151910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.151931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.151951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.151975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.151998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.152021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.152040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.152060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.152083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.152106] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.154111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.154128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.154143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.154157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.155675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.155693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.155708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.157201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.157218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.159024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.161957] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.161984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.162000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.162022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.178774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.178799] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.178834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.178946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.178995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.195467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.195491] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.195535] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.214422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.214441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.214461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.214477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.214495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.214510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.214525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.214541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.214562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.214582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.214603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.214623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.214642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.214661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.214697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.214773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.214782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.214828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.214848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.214867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.214890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.214909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.214928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.214948] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.214967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.214986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.215005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.215023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.215027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.215046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.215050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.215069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.215088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.215107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.215126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.215145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.215163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.215182] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.215201] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.215220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.215240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.215261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.215315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.215334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.215353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.215373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.215421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.215451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.215477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.215505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.215533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.215555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.215579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.215605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.215631] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.217628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.217644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.217659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.217673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.220263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.220281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.220298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.221797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.221814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.223617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.226541] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.226567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.226583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.226604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.243317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.243342] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.243419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.243543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.243586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.260014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.260038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.260082] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.280021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.280040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.280060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.280076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.280093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.280108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.280122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.280138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.280155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.280171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.280187] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.280202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.280216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.280230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.280261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.280326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.280334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.280375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.280435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.280461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.280489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.280511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.280535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.280559] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.280582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.280604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.280626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.280649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.280655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.280677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.280683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.280706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.280728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.280749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.280769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.280793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.280815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.280834] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.280854] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.280873] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.280894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.280915] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.280969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.280989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.281009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.281029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.281049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.281068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.281089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.281109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.281131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.281150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.281170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.281191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.281210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.283193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.283209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.283223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.283238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.285847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.285862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.285876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.287372] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.287396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.289198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.292119] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.292145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.292164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.292190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.308899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.308924] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.308959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.309061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.309114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.325599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.325623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.325660] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.344527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.344546] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.344566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.344583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.344601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.344616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.344631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.344649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.344671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.344692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.344712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.344732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.344751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.344770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.344806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.344882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.344890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.344936] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.344956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.344976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.344997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.345016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.345036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.345055] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.345074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.345093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.345112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.345131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.345135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.345153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.345157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.345177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.345196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.345214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.345233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.345252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.345271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.345289] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.345308] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.345327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.345347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.345368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.345485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.345510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.345533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.345556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.345578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.345601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.345629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.345662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.345685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.345705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.345725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.345749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.345767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.347757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.347775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.347790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.347805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.349334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.349352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.349370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.350910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.350927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.352766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.355707] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.355734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.355751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.355776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.372517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.372542] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.372576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.372675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.372716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.389198] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.389222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.389265] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.408118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.408137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.408157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.408174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.408191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.408206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.408220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.408236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.408253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.408270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.408285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.408300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.408315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.408328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.408360] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.408502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.408511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.408555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.408571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.408590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.408609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.408625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.408643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.408659] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.408675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.408691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.408706] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.408721] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.408725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.408739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.408743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.408758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.408772] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.408786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.408800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.408817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.408832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.408847] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.408860] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.408875] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.408892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.408910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.408960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.408975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.408991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.409005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.409019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.409034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.409050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.409066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.409082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.409095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.409110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.409127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.409144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.411124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.411140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.411154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.411168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.412675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.412690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.412703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.414195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.414211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.416016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.418936] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.418961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.418977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.418999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.435716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.435741] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.435776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.435873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.435913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.452386] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.452431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.452474] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.471324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.471343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.471363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.471380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.471442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.471468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.471492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.471518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.471547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.471571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.471588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.471604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.471619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.471633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.471667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.471733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.471741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.471783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.471800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.471817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.471837] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.471853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.471870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.471886] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.471902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.471917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.471931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.471946] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.471950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.471963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.471967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.471982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.471995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.472009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.472023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.472040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.472053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.472068] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.472082] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.472095] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.472112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.472130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.472180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.472196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.472210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.472225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.472239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.472254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.472275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.472296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.472317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.472336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.472356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.472376] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.472420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.474413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.474429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.474444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.474459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.475967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.475982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.475996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.477494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.477510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.479340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.482273] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.482300] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.482319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.482343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.499090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.499115] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.499149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.499241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.499280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.515770] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.515795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.515838] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.534694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.534712] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.534732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.534749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.534767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.534782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.534796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.534812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.534830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.534846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.534862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.534878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.534892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.534906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.534938] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.535009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.535017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.535059] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.535074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.535092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.535111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.535127] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.535147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.535166] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.535185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.535205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.535224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.535243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.535247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.535265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.535269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.535288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.535308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.535326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.535345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.535364] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.535383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.535445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.535471] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.535497] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.535526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.535555] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.535633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.535656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.535681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.535705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.535729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.535754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.535781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.535807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.535833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.535856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.535878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.535906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.535931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.537945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.537962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.537976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.537991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.539502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.539518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.539531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.541027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.541043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.542854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.545804] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.545831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.545848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.545870] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.562605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.562632] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.562669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.562769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.562811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.579306] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.579331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.579369] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.598259] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.598280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.598302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.598321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.598343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.598362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.598381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.598440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.598472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.598500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.598527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.598553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.598575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.598598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.598650] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.598765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.598780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.598846] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.598863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.598882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.598904] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.598923] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.598943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.598962] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.598982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.599001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.599020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.599038] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.599042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.599061] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.599064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.599084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.599103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.599122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.599141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.599160] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.599179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.599197] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.599216] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.599235] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.599255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.599276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.599330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.599350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.599369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.599395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.599437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.599464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.599489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.599514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.599538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.599558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.599580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.599607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.599629] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.601620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.601635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.601649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.601664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.603166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.603181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.603195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.604690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.604705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.606507] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.609456] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.609483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.609499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.609522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.626256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.626282] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.626317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.626466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.626526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.642938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.642962] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.643006] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.661873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.661892] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.661912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.661929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.661946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.661961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.661976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.661992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.662009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.662025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.662040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.662055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.662069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.662082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.662118] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.662194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.662202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.662249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.662269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.662289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.662311] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.662327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.662347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.662366] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.662386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.662445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.662470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.662492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.662499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.662521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.662527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.662550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.662572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.662593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.662614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.662639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.662660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.662681] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.662702] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.662723] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.662748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.662773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.662853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.662874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.662895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.662916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.662932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.662945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.662961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.662975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.662990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.663003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.663015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.663033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.663051] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.665035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.665052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.665066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.665080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.666586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.666604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.666621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.668115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.668132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.671006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.673926] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.673951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.673967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.673989] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.690696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.690718] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.690752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.690838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.690875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.707387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.707434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.707477] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.726342] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.726361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.726382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.726402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.726467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.726489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.726505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.726521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.726542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.726563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.726585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.726605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.726625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.726645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.726682] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.726756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.726765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.726813] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.726833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.726854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.726876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.726896] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.726915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.726935] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.726954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.726974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.726993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.727012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.727016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.727035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.727039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.727059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.727079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.727098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.727117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.727136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.727155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.727175] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.727195] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.727221] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.727240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.727258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.727306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.727321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.727335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.727348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.727362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.727377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.727392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.727431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.727454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.727474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.727494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.727518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.727539] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.729528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.729545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.729559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.729574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.731076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.731091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.731105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.732600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.732617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.734440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.737372] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.737406] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.737458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.737492] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.754191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.754216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.754251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.754348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.754387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.770872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.770896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.770940] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.789802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.789820] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.789840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.789857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.789874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.789888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.789903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.789918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.789936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.789952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.789968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.789984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.789998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.790012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.790044] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.790116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.790124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.790166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.790182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.790199] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.790219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.790234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.790250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.790269] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.790288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.790308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.790327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.790345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.790349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.790368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.790372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.790391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.790453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.790482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.790508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.790536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.790562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.790588] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.790620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.790642] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.790668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.790694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.790765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.791035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.791058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.791081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.791103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.791126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.791150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.791174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.791198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.791220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.791242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.791267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.791290] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.793278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.793294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.793308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.793326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.794833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.794848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.794863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.797427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.797445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.799246] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.802177] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.802204] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.802221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.802243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.818947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.818973] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.819011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.819115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.819157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.835648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.835674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.835713] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.854573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.854592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.854612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.854629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.854647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.854662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.854676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.854695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.854717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.854737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.854757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.854778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.854796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.854815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.854852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.854930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.854938] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.854985] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.855012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.855030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.855048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.855062] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.855078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.855094] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.855108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.855122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.855136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.855149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.855152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.855165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.855168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.855181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.855194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.855207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.855219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.855234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.855247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.855259] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.855272] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.855285] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.855300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.855316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.855363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.855378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.855391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.855404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.855459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.855480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.855503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.855526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.855548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.855568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.855587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.855611] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.855632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.857628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.857644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.857659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.857673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.859190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.859207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.859221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.861798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.861817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.863624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.866569] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.866597] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.866614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.866636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.883375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.883400] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.883489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.883602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.883640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.900055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.900080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.900123] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.918976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.918995] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.919015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.919032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.919049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.919064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.919078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.919094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.919112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.919128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.919143] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.919163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.919182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.919200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.919237] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.919304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.919313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.919359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.919379] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.919398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.919468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.919494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.919521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.919547] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.919571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.919595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.919617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.919639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.919646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.919667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.919673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.919695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.919717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.919739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.919760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.919785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.919806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.919829] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.919850] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.919872] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.919897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.919922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.919993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.920015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.920037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.920059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.920080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.920100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.920125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.920148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.920171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.920193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.920214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.920236] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.920259] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.922253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.922269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.922283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.922298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.923805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.923820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.923834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.925326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.925342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.927147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.930074] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.930102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.930118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.930140] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  339.946847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.946872] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.946907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.947003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.947043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.963547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.963571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  339.963608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.982484] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  339.982503] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  339.982523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.982540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.982557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.982572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.982586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.982601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  339.982619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.982636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.982651] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.982671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.982690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.982709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.982745] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  339.982820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  339.982829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  339.982875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  339.982894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.982914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  339.982936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.982955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.982975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.982994] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  339.983013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  339.983032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.983051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  339.983070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.983074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.983093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.983096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  339.983116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  339.983135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.983154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.983173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.983192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  339.983210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.983229] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  339.983248] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  339.983267] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  339.983287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.983307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  339.983361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  339.983381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  339.983400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  339.983419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  339.983480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  339.983507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  339.983537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  339.983565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  339.983593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  339.983617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  339.983642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  339.983671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  339.983703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  339.985698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.985714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.985728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.985744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.987248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  339.987263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  339.987277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.988772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.988787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  339.990590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.993538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  339.993565] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  339.993581] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  339.993603] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.010341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.010366] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.010401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.010586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.010630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.027034] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.027057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.027101] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.045981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.046000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.046020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.046037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.046055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.046070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.046084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.046100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.046118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.046134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.046150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.046166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.046180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.046194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.046225] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.046297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.046305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.046347] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.046362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.046380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.046399] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.046414] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.046474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.046500] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.046527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.046553] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.046577] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.046601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.046608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.046631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.046637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.046661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.046685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.046709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.046733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.046759] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.046783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.046807] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.046831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.046855] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.046882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.046909] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.046988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.047012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.047036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.047060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.047083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.047107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.047133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.047157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.047188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.047209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.047230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.047253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.047275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.049269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.049285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.049300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.049314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.050820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.050836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.050849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.052370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.052385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.054191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.057111] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.057137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.057153] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.057175] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.073891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.073917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.073954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.074071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.074120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.090591] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.090615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.090652] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.109530] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.109549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.109569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.109586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.109604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.109619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.109633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.109649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.109666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.109682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.109698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.109714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.109728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.109742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.109777] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.109845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.109853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.109899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.109919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.109939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.109961] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.109980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.110000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.110019] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.110038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.110057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.110076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.110095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.110099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.110117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.110121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.110140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.110159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.110178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.110197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.110216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.110235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.110253] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.110272] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.110291] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.110311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.110332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.110386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.110405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.110424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.110485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.110511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.110539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.110568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.110601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.110626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.110648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.110671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.110697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.110721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.112715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.112731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.112746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.112760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.114264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.114279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.114292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.115789] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.115805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.117608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.120556] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.120583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.120600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.120622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.137359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.137385] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.137422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.137592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.137632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.154055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.154079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.154115] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.172994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.173013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.173033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.173049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.173067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.173081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.173096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.173111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.173129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.173146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.173161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.173177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.173195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.173214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.173251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.173325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.173334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.173380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.173400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.173419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.173489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.173518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.173547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.173575] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.173601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.173627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.173652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.173676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.173683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.173706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.173713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.173737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.173761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.173785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.173808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.173835] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.173859] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.173883] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.173907] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.173931] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.173957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.173984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.174065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.174087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.174108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.174130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.174150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.174172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.174196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.174219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.174243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.174265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.174284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.174308] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.174331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.176333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.176351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.176368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.176386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.179016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.179035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.179051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.180552] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.180568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.182379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.185319] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.185345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.185361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.185382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.202129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.202155] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.202189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.202287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.202327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.218810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.218834] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.218878] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.237730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.237749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.237769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.237786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.237804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.237819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.237834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.237850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.237867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.237887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.237908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.237928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.237947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.237966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.238003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.238078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.238086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.238132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.238152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.238172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.238194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.238211] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.238230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.238250] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.238269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.238288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.238307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.238326] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.238330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.238348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.238352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.238371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.238390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.238409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.238428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.238492] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.238517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.238542] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.238563] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.238586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.238612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.238638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.238709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.238730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.238752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.238772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.238794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.238815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.238838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.238861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.238884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.238903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.238923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.238946] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.238968] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.240981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.240998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.241012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.241027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.242544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.242561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.242576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.244072] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.244088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.245896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.248830] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.248856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.248872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.248894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.265675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.265701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.265735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.265837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.265877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.282344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.282369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.282408] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.301298] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.301316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.301336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.301353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.301370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.301385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.301404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.301423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.301487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.301516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.301544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.301571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.301592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.301616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.301667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.301770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.301784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.301852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.301882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.301907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.301934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.301954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.301977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.301999] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.302020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.302041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.302062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.302081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.302086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.302106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.302111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.302132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.302151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.302171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.302189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.302212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.302230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.302251] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.302270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.302290] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.302313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.302337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.302407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.302427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.302469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.302491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.302513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.302534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.302559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.302583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.302608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.302628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.302649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.302675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.302696] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.304684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.304699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.304713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.304727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.306230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.306245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.306259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.307755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.307770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.309573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.312521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.312548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.312564] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.312587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.329323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.329349] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.329386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.329538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.329598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.346016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.346040] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.346083] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.364949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.364968] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.364988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.365005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.365023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.365038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.365053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.365069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.365087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.365103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.365119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.365134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.365148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.365162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.365194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.365265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.365274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.365315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.365331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.365348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.365367] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.365382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.365398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.365415] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.365430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.365485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.365510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.365533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.365540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.365563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.365570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.365594] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.365616] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.365639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.365661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.365687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.365709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.365732] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.365754] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.365777] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.365805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.365833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.365910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.365932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.365955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.365977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.366000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.366022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.366048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.366073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.366098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.366118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.366141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.366168] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.366190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.368186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.368202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.368216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.368230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.369738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.369753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.369766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.371257] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.371274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.373080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.376001] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.376026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.376042] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.376064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.392780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.392806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.392841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.392952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.393000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.409490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.409514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.409548] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.428418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.428437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.428500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.428530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.428559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.428583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.428607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.428633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.428662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.428689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.428714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.428740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.428764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.428787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.428844] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.428927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.428935] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.428975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.428990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.429007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.429025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.429040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.429056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.429071] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.429085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.429100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.429113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.429126] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.429130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.429143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.429146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.429159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.429172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.429185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.429202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.429221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.429238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.429256] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.429275] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.429293] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.429311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.429331] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.429383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.429401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.429420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.429438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.429487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.429515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.429543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.429570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.429596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.429619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.429642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.429669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.429694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.431700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.431719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.431736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.431755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.433259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.433275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.433289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.434785] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.434801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.436604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.439542] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.439569] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.439588] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.439613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.456354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.456379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.456414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.456592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.456633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.473047] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.473070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.473114] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.491967] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.491987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.492007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.492024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.492041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.492055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.492070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.492086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.492104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.492120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.492136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.492151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.492165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.492179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.492211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.492276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.492284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.492325] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.492341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.492358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.492377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.492393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.492409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.492425] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.492440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.492499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.492522] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.492544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.492552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.492575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.492581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.492605] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.492627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.492651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.492672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.492699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.492721] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.492745] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.492767] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.492790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.492817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.492845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.492922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.492944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.492967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.492988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.493010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.493032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.493057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.493082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.493107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.493128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.493157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.493180] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.493202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.495194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.495211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.495225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.495239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.496747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.496765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.496782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.498275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.498292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.500099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.503018] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.503044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.503060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.503081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.519799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.519826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.519863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.519966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.520020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.536500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.536524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.536560] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.555424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.555443] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.555511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.555540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.555569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.555593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.555617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.555643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.555672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.555699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.555725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.555750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.555774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.555796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.555847] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.555946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.555954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.555997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.556013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.556031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.556050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.556065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.556082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.556098] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.556113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.556128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.556143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.556156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.556160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.556174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.556177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.556192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.556205] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.556219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.556232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.556248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.556262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.556280] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.556300] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.556319] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.556339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.556359] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.556405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.556425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.556445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.556503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.556529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.556555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.556581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.556606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.556631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.556653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.556676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.556702] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.556726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.558724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.558742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.558759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.558777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.561354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.561372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.561387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.562888] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.562904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.564715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.567665] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.567698] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.567713] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.567734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.584490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.584515] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.584550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.584648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.584688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.601199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.601238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.601296] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.620261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.620284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.620309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.620329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.620351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.620370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.620388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.620408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.620430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.620450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.620509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.620545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.620572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.620603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.620666] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.620811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.620829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.620915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.620944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.620976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.621012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.621040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.621071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.621100] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.621129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.621156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.621184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.621210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.621218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.621244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.621251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.621279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.621305] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.621333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.621359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.621390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.621415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.621443] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.621504] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.621528] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.621556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.621586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.621670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.621694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.621719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.621745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.621768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.621792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.621820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.621847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.621874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.621896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.621920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.621946] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.621972] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.624022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.624041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.624058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.624075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.625600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.625618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.625634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.627143] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.627161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.628984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.631945] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.631974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.631991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.632015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.648735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.648761] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.648798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.648898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.648939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.665431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.665457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.665545] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.684412] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.684431] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.684451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.684512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.684543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.684569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.684594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.684620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.684649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.684675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.684701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.684727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.684749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.684772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.684822] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.684928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.684936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.684979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.684995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.685013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.685032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.685051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.685071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.685090] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.685109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.685128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.685147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.685166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.685169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.685188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.685192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.685211] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.685231] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.685257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.685273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.685289] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.685304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.685318] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.685332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.685349] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.685367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.685386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.685428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.685446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.685493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.685517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.685542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.685566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.685592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.685617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.685642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.685664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.685687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.685713] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.685737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.687734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.687750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.687764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.687779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.689285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.689302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.689319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.690819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.690836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.692644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.695574] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.695600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.695616] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.695637] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.712373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.712399] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.712433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.712601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.712640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.729041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.729065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.729102] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.747975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.747993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.748013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.748030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.748048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.748063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.748077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.748093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.748110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.748127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.748142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.748157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.748172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.748190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.748227] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.748300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.748310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.748355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.748375] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.748395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.748417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.748435] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.748455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.748517] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.748543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.748570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.748593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.748617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.748624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.748646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.748653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.748677] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.748699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.748722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.748743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.748770] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.748797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.748819] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.748839] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.748860] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.748885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.748911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.748972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.748992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.749013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.749032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.749053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.749073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.749096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.749118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.749141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.749160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.749180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.749203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.749225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.751220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.751236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.751253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.751271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.752780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.752796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.752810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.754302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.754318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.756123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.759058] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.759085] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.759101] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.759123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.775874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.775899] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.775934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.776030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.776070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.792555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.792579] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.792623] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.811493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.811512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.811532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.811549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.811566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.811582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.811596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.811612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.811629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.811646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.811661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.811677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.811691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.811705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.811737] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.811808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.811817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.811858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.811873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.811891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.811910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.811926] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.811946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.811965] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.811984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.812004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.812022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.812041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.812045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.812064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.812067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.812087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.812106] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.812125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.812144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.812170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.812187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.812202] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.812220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.812237] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.812255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.812274] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.812323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.812341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.812359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.812376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.812394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.812411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.812429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.812448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.812466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.812510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.812534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.812561] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.812583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.814576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.814593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.814608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.814626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.816130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.816146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.816161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.817660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.817677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.819497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.822429] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.822456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.822512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.822550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.839248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.839274] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.839308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.839405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.839444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.855928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.855952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.855995] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.874844] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.874862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.874882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.874899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.874917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.874932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.874946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.874962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.874980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.874996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.875012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.875028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.875042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.875056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.875088] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.875161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.875169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.875211] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.875227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.875244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.875264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.875279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.875295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.875312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.875327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.875342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.875356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.875370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.875374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.875387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.875391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.875405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.875419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.875432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.875446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.875462] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.875515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.875539] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.875568] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.875588] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.875613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.875639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.875709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.875730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.876011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.876032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.876054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.876075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.876099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.876122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.876145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.876164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.876185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.876208] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.876230] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.878221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.878238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.878255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.878273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.879782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.879799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.879813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.881305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.881320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.883125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.886044] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.886069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.886085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.886107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.902825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.902852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.902889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.902982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.903023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.919506] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.919532] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.919577] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.938423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  340.938442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.938462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.938520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.938549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.938573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.938597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.938620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.938650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.938676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.938701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.938726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.938747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.938769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.938818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.938919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.938931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  340.938980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.938995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.939011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.939029] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.939043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.939058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.939073] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  340.939088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  340.939102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.939118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.939135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.939139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.939156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.939159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.939177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.939194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.939212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.939229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.939246] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.939263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.939280] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  340.939298] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  340.939315] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  340.939333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.939352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  340.939402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.939420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.939437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.939455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.939472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.939515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.939544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.939569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.939595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.939616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.939638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.939665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  340.939687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.941677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.941693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.941707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.941722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.943224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.943239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.943253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.944748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.944764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.946567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.949498] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  340.949524] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.949540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  340.949562] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.966317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.966343] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  340.966377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.966513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  340.966575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.982998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.983023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.983068] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.001948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.001966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.001986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.002003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.002021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.002036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.002051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.002067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.002084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.002101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.002117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.002133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.002147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.002165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.002202] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.002276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.002284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.002330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.002350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.002369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.002392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.002408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.002434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.002451] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.002466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.002514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.002539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.002560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.002566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.002588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.002594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.002616] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.002637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.002658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.002678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.002702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.002722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.002744] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.002764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.002785] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.002810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.002836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.002906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.002928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.002951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.002972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.002993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.003016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.003042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.003065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.003088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.003110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.003130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.003155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.003178] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.005171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.005188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.005202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.005216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.007806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.007825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.007841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.009336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.009353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.011159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.014080] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.014106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.014125] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.014150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.030859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.030884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.030919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.031016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.031056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.047541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.047565] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.047608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.066455] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.066474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.066538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.066563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.066591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.066613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.066637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.066660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.066687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.066713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.066739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.066764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.066785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.066807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.066857] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.066974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.066982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.067021] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.067036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.067052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.067070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.067084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.067099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.067114] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.067128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.067142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.067159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.067176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.067180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.067197] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.067200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.067218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.067235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.067253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.067270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.067288] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.067304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.067322] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.067339] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.067356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.067375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.067394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.067443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.067461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.067479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.067522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.067549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.067571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.067597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.067622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.067647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.067667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.067689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.067716] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.067739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.070824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.070843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.070862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.070881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.072393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.072409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.072424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.073920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.073936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.075740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.078687] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.078714] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.078731] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.078752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.095490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.095532] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.095569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.095669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.095711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.112172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.112197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.112242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.131104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.131123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.131143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.131163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.131184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.131203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.131222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.131241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.131263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.131283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.131304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.131324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.131343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.131362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.131398] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.131466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.131507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.131579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.131604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.131631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.131660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.131683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.131709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.131733] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.131757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.131780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.131803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.131824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.131830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.131851] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.131857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.131880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.131902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.131924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.131945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.131969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.131990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.132013] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.132034] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.132056] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.132079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.132105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.132181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.132202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.132225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.132246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.132268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.132297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.132321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.132343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.132366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.132385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.132405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.132427] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.132449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.135554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.135573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.135589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.135605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.137113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.137128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.137145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.138642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.138658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.140462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.143398] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.143425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.143441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.143463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.160213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.160239] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.160274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.160370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.160408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.176894] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.176918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.176961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.195813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.195832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.195852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.195869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.195886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.195901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.195916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.195935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.195956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.195977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.195997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.196017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.196036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.196055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.196091] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.196165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.196174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.196220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.196240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.196259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.196281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.196300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.196320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.196339] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.196358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.196377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.196396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.196414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.196418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.196437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.196441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.196460] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.196479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.196542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.196567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.196596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.196620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.196645] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.196668] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.196692] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.196719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.196747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.196829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.196849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.196871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.196891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.196913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.196933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.196956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.196979] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.197002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.197021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.197041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.197065] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.197086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.199085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.199101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.199116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.199130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.200636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.200651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.200665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.202156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.202174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.203992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.206925] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.206950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.206966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.206988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.223741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.223768] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.223805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.223907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.223949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.240443] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.240467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.240547] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.259416] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.259436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.259458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.259478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.259543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.259572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.259599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.259626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.259656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.259682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.259708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.259734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.259757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.259779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.259830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.259935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.259944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.259988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.260007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.260027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.260049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.260068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.260087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.260107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.260126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.260145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.260164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.260182] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.260186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.260205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.260216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.260233] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.260249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.260263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.260277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.260292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.260306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.260319] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.260333] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.260345] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.260361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.260377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.260416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.260431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.260444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.260457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.260470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.260484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.260529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.260556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.260581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.260604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.260626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.260651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.260675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.262679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.262703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.262724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.262746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.264257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.264272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.264286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.265786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.265801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.267610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.270552] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.270580] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.270596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.270618] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.287361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.287386] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.287421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.287620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.287680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.304061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.304086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.304124] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.322272] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.322291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.322311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.322328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.322345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.322360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.322375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.322391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.322408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.322424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.322440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.322455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.322469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.322483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.322568] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.322671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.322684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.322753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.322783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.322807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.322834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.322854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.322877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.322899] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.322921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.322942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.322963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.322982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.322987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.323007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.323012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.323033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.323053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.323073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.323092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.323115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.323134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.323155] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.323174] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.323194] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.323215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.323239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.323309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.323329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.323351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.323370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.323390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.323411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.323434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.323457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.323479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.323498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.323535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.323558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.323581] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.325571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.325587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.325601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.325616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.327118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.327133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.327147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.328642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.328657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.330461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.333395] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.333422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.333438] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.333463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.350211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.350236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.350272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.350364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.350406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.366892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.366916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.366959] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.385825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.385844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.385864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.385881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.385899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.385914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.385929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.385945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.385963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.385983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.386004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.386024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.386043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.386062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.386099] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.386172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.386181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.386227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.386247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.386273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.386292] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.386307] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.386324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.386340] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.386354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.386368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.386382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.386395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.386398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.386411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.386414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.386427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.386440] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.386452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.386464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.386482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.386499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.386549] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.386573] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.386594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.386618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.386643] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.386715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.386736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.386759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.386779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.386799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.386820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.386844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.386868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.386890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.386909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.386930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.386954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.386975] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.388983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.388998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.389012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.389026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.390556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.390570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.390586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.392082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.392098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.393905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.396842] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.396869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.396889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.396913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.413656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.413681] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.413716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.413813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.413852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.430356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.430382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.430420] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.449292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.449311] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.449331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.449348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.449365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.449380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.449395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.449411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.449429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.449445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.449461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.449476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.449490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.449548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.449599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.449718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.449732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.449802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.449827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.449854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.449884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.449908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.449934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.449960] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.449984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.450009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.450033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.450056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.450062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.450085] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.450091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.450115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.450138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.450161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.450184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.450210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.450234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.450258] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.450281] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.450302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.450327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.450355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.450420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.450444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.450468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.450491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.450537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.450561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.450589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.450616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.450643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.450672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.450695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.450720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.450743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.452739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.452755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.452769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.452783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.454289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.454304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.454318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.455818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.455833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.457642] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.460577] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.460603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.460621] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.460646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.477400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.477426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.477463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.477634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.477675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.494090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.494114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.494151] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.512280] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.512299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.512320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.512336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.512354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.512369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.512383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.512399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.512416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.512432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.512448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.512464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.512478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.512492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.512570] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.512673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.512687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.512756] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.512782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.512809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.512838] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.512861] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.512887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.512910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.512935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.512964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.512985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.513005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.513010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.513030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.513035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.513057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.513076] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.513096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.513115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.513138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.513157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.513177] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.513196] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.513216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.513237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.513261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.513333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.513353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.513374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.513394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.513414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.513434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.513458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.513481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.513505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.513545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.513565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.513591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.513612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.515605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.515621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.515635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.515650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.517152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.517167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.517181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.518677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.518692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.520498] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.523442] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.523469] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.523486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.523508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.540260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.540285] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.540320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.540409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.540449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.556941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.556966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.557004] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.575865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.575884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.575905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.575921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.575939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.575954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.575969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.575985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.576003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.576020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.576036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.576051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.576066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.576080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.576112] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.576182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.576191] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.576233] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.576249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.576268] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.576290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.576307] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.576327] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.576346] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.576365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.576385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.576403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.576422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.576426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.576452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.576455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.576471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.576486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.576500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.576552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.576577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.576600] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.576621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.576644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.576664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.576689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.576715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.576785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.576806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.576828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.576849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.576870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.576891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.576915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.576938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.576961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.576980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.577000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.577024] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.577045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.579056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.579072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.579086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.579100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.580628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.580645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.580661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.582157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.582173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.583978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.586925] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.586951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.586968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.586990] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.603729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.603755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.603789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.603887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.603926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.620410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.620436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.620472] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.639324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.639342] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.639363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.639379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.639396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.639411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.639425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.639441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.639459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.639475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.639490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.639506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.639563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.639586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.639637] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.639752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.639766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.639834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.639857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.639883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.639912] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.639941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.639964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.639985] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.640007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.640028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.640048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.640067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.640073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.640092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.640097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.640118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.640137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.640158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.640177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.640200] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.640218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.640239] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.640258] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.640278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.640299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.640324] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.640394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.640414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.640435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.640455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.640475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.640495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.640519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.640559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.640584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.640604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.640626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.640651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.640672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.642661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.642676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.642690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.642704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.644206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.644221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.644235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.645729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.645745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.647547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.650478] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.650505] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.650561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.650598] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.667247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.667272] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.667306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.667405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.667444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.683949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.683973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.684010] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.702527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.702562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.702582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.702599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.702617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.702632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.702647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.702663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.702681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.702697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.702713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.702728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.702742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.702756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.702788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.702861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.702870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.702912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.702927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.702946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.702969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.702988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.703007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.703027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.703046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.703065] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.703084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.703103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.703107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.703125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.703129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.703149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.703168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.703187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.703206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.703225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.703243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.703262] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.703282] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.703301] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.703321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.703341] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.703395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.703414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.703434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.703453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.703479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.703495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.703511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.703553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.703580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.703600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.703622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.703649] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.703671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.705664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.705680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.705694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.705709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.707212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.707227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.707240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.708738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.708754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.710556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.713490] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.713517] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.713572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.713610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.730307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.730332] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.730367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.730457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.730497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.746988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.747013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.747058] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.765910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.765929] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.765949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.765966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.765984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.765999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.766014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.766030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.766048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.766064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.766079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.766095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.766109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.766127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.766164] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.766237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.766246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.766292] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.766312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.766331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.766353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.766369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.766389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.766408] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.766427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.766447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.766465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.766484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.766488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.766507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.766510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.766604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.766633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.766657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.766682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.766708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.766733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.766755] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.766780] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.766801] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.766828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.766856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.766939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.766959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.766980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.766999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.767020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.767040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.767064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.767088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.767110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.767131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.767150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.767174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.767195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.769188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.769204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.769219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.769233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.770741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.770756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.770770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.772260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.772276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.774080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.777001] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.777027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.777046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.777072] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.793780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.793806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.793843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.793942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.793984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.810476] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.810501] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.810583] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.829462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.829481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.829500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.829517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.829578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.829601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.829627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.829652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.829681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.829708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.829734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.829759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.829780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.829802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.829852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.829964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.829978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.830039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.830056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.830074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.830093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.830110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.830130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.830149] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.830169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.830188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.830207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.830225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.830229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.830248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.830251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.830271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.830290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.830308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.830327] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.830346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.830365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.830384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.830403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.830428] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.830446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.830463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.830511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.830526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.830565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.830590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.830611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.830634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.830659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.830683] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.830708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.830728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.830750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.830776] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.830798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.832791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.832809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.832826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.832844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.834348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.834365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.834379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.835874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.835891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.837694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.840640] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.840665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.840681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.840701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.857445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.857470] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.857505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.857683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.857727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.874146] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.874170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.874207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.893082] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.893101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.893121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.893137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.893155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.893170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.893184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.893199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.893217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.893234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.893249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.893265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.893280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.893298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.893335] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.893410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.893418] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.893465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.893484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.893504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.893526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.893584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.893614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.893641] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.893666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.893691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.893714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.893743] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.893749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.893771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.893777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.893799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.893820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.893841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.893861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.893885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.893905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.893927] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.893946] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.893968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.893992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.894016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.894338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.894360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.894382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.894402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.894423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.894443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.894468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.894490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.894513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.894532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.894571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.894597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.894618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.896723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.896739] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.896756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.896774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.898279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.898296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.898314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.899812] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.899830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.901636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.904580] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.904607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.904623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.904646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.921387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.921413] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.921449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.921589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.921648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.938087] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  341.938111] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.938147] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  341.956312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  341.956331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.956351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.956368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.956385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.956400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.956414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.956429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.956447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.956463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.956478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.956494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.956507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.956521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.956603] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.956851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.956865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.956935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.956961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.956988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.957018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.957043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.957070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.957096] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  341.957128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  341.957151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.957172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.957193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.957199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.957220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.957225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.957246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.957267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.957288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.957307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.957330] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.957351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.957370] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  341.957390] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  341.957409] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  341.957432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.957457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  341.957527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.957571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.957592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.957616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.957638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.957661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.957686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.957711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.957735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.957757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.957779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.957805] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  341.957828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.960018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.960034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.960048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.960062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.961595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.961611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.961624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.963119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.963135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.964941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.967888] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  341.967915] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.967932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  341.967954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.984692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.984717] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  341.984752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.984850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.984890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.001393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.001418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.001455] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.020289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.020308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.020327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.020344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.020361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.020376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.020390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.020406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.020423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.020444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.020464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.020485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.020503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.020522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.020603] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.020715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.020729] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.020801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.020827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.020853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.020883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.020905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.020931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.020955] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.020980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.021002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.021025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.021046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.021052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.021074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.021080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.021103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.021124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.021146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.021167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.021191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.021212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.021235] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.021256] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.021278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.021301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.021327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.021404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.021426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.021449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.021470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.021499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.021519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.021543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.021583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.021607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.021627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.021648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.021674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.021695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.023689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.023705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.023720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.023735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.025239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.025254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.025267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.026763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.026780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.028583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.031517] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.031572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.031598] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.031634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.048333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.048360] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.048397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.048498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.048539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.065033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.065059] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.065097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.083973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.083991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.084011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.084028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.084045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.084060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.084075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.084090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.084108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.084124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.084140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.084156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.084170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.084184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.084216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.084288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.084296] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.084338] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.084354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.084371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.084391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.084406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.084422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.084439] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.084454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.084470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.084484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.084498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.084502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.084515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.084519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.084533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.084587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.084611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.084634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.084658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.084682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.084704] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.084728] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.084749] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.084775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.084803] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.084879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.085172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.085193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.085215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.085235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.085257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.085281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.085304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.085327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.085346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.085366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.085391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.085412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.087400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.087416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.087433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.087452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.088959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.088975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.088989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.090490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.090506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.092311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.095245] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.095272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.095291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.095315] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.112062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.112087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.112122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.112221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.112261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.128762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.128787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.128823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.147693] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.147712] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.147732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.147749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.147766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.147781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.147795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.147811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.147829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.147845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.147861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.147876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.147890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.147904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.147936] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.148000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.148008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.148049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.148065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.148083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.148102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.148119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.148139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.148158] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.148177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.148196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.148215] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.148234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.148238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.148256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.148260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.148279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.148299] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.148318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.148337] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.148356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.148375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.148400] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.148415] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.148429] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.148445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.148464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.148513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.148531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.148549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.148600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.148625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.148649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.148675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.148701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.148726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.148746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.148768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.148794] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.148816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.150811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.150827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.150843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.150861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.152366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.152381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.152395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.153890] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.153907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.155713] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.158667] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.158693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.158711] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.158737] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.175463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.175489] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.175526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.175701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.175746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.192157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.192180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.192223] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.211075] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.211094] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.211114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.211131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.211148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.211163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.211178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.211194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.211211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.211227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.211243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.211258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.211272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.211286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.211318] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.211388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.211396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.211438] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.211454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.211471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.211493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.211512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.211532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.211551] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.211613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.211639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.211665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.211687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.211695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.211717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.211724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.211748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.211770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.211794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.211815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.211842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.211870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.211891] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.211911] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.211932] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.211957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.211983] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.212054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.212075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.212096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.212115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.212135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.212155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.212179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.212202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.212225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.212244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.212264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.212289] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.212309] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.214302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.214318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.214332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.214346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.215852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.215866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.215880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.217371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.217388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.219194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.222114] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.222139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.222155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.222177] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.238894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.238920] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.238958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.239071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.239121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.255589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.255613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.255649] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.274521] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.274540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.274601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.274626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.274656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.274763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.274783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.274802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.274824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.274845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.274865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.274886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.274905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.274923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.274959] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.275034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.275042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.275088] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.275108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.275128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.275150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.275168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.275188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.275208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.275227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.275246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.275271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.275286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.275290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.275304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.275307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.275321] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.275334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.275347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.275364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.275381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.275398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.275415] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.275433] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.275450] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.275469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.275488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.275537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.275555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.275599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.275626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.275647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.275672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.275698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.275722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.275746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.275767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.275789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.275815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.275836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.277831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.277847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.277861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.277876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.279378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.279393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.279409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.280905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.280921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.282725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.285664] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.285691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.285708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.285730] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.302475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.302501] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.302537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.302754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.302793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.319156] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.319180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.319223] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.338077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.338096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.338116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.338133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.338151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.338166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.338181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.338197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.338214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.338231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.338250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.338271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.338290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.338309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.338345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.338411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.338420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.338466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.338485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.338505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.338527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.338552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.338608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.338632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.338656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.338678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.338700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.338720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.338727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.338749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.338755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.338777] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.338797] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.338818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.338838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.338862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.338882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.338904] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.338924] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.338945] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.338970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.338996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.339067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.339089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.339111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.339133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.339153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.339176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.339200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.339224] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.339248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.339268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.339287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.339311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.339332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.341326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.341342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.341356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.341371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.342878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.342893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.342907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.344399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.344414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.346219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.349140] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.349167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.349186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.349210] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.365919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.365945] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.365979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.366068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.366108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.382600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.382624] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.382667] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.401525] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.401543] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.401564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.401621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.401650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.401674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.401698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.401723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.401753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.401780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.401805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.401831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.401854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.401876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.401925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.402040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.402053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.402114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.402135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.402159] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.402185] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.402206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.402229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.402250] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.402272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.402293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.402314] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.402333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.402338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.402358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.402363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.402384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.402403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.402423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.402442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.402465] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.402483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.402504] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.402523] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.402543] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.402567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.402615] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.402685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.402706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.402729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.402751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.402772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.402794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.402819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.402842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.402866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.402887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.402907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.402932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.402955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.404946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.404962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.404976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.404991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.406509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.406524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.406538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.408031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.408047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.409851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.412785] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.412812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.412829] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.412851] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.429602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.429628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.429663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.429760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.429799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.446302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.446328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.446366] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.465221] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.465240] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.465260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.465277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.465295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.465310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.465324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.465340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.465357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.465374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.465389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.465405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.465419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.465433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.465464] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.465537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.465545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.465641] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.465665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.465692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.465901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.465925] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.465951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.465975] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.466000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.466023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.466046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.466067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.466073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.466094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.466100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.466123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.466144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.466167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.466187] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.466213] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.466233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.466263] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.466282] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.466303] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.466324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.466348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.466418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.466438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.466459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.466478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.466499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.466519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.466542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.466565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.466606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.466626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.466647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.466674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.466695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.468685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.468701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.468715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.468730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.470232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.470247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.470260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.471755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.471771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.473588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.476523] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.476551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.476567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.476633] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.493338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.493364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.493401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.493501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.493543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.510039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.510065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.510103] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.528977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.528996] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.529016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.529032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.529050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.529065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.529083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.529103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.529124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.529145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.529165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.529186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.529204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.529223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.529260] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.529328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.529337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.529383] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.529403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.529423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.529445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.529463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.529483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.529502] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.529521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.529541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.529560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.529617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.529626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.529651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.529658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.529683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.529706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.529738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.529759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.529783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.529803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.529825] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.529846] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.529867] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.529892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.529918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.530217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.530239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.530261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.530281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.530302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.530323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.530346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.530369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.530392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.530411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.530432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.530454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.530476] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.532475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.532491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.532506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.532520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.534026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.534041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.534054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.535547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.535563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.537391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.540324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.540351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.540370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.540395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.557141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.557166] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.557202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.557293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.557332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.573821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.573847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.573892] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.592745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.592764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.592784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.592801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.592819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.592834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.592848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.592864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.592882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.592899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.592915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.592930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.592944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.592958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.592990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.593061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.593070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.593111] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.593127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.593145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.593163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.593178] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.593195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.593211] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.593233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.593247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.593260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.593273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.593276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.593289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.593292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.593305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.593318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.593330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.593342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.593357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.593370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.593383] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.593395] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.593408] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.593422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.593438] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.593484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.593498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.593512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.593525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.593537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.593551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.593565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.593617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.593642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.593662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.593684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.593710] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.593731] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.595725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.595741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.595755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.595770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.597272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.597287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.597300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.598796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.598813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.600622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.603553] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.603611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.603638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.603668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.620318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.620342] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.620376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.620475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.620513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.637022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.637047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.637083] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.655955] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.655975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.655997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.656017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.656038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.656057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.656076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.656096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.656117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.656138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.656158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.656178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.656197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.656216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.656252] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.656327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.656336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.656381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.656401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.656421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.656443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.656459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.656479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.656498] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.656517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.656536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.656555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.656581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.656620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.656644] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.656649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.656672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.656693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.656714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.656734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.656757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.656778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.656798] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.656818] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.656838] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.656860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.656884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.656955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.656978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.657000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.657022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.657043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.657066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.657091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.657114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.657138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.657160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.657181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.657202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.657220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.659196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.659212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.659226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.659240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.660746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.660761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.660774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.662265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.662281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.664087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.667028] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.667054] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.667070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.667092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.683837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.683863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.683898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.683995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.684034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.700536] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.700560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.700643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.719518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.719537] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.719557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.719574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.719632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.719656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.719681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.719705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.719734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.719760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.719786] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.719811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.719832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.719854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.719904] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.720025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.720038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.720093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.720108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.720125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.720142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.720158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.720176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.720194] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.720211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.720229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.720246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.720263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.720266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.720283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.720287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.720305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.720322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.720339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.720356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.720374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.720391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.720408] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.720426] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.720443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.720461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.720480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.720530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.720548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.720566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.720583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.720626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.720654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.720679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.720704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.720730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.720750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.720772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.720798] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.720820] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.722811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.722827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.722841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.722855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.724358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.724373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.724387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.725881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.725899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.727703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.730637] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.730662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.730679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.730700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.747450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.747474] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.747507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.747642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.747702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.764155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.764179] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.764215] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.783087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.783106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.783126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.783143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.783161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.783175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.783190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.783206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.783223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.783240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.783255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.783271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.783285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.783299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.783330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.783401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.783409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.783450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.783466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.783483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.783503] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.783518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.783535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.783551] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  342.783566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.783581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.783669] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.783692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.783700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.783724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.783731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.783755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.783778] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.783801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.783823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.783849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.783871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.783895] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  342.783916] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  342.784196] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  342.784222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.784250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  342.784325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.784347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.784371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.784392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.784414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.784436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.784468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.784492] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.784515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.784534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.784555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.784577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  342.784618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.786744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.786760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.786774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.786788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.788292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.788308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.788326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.789822] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.789839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.791642] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.794576] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.794619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.794635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  342.794657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.811392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.811418] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.811453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.811551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.811591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.828093] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  342.828117] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.828153] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  342.847027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  342.847046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.847066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.847085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.847107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.847126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.847145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.847164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.847186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.847206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.847227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.847247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.847266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.847285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.847321] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  342.847495] [drm:drm_mode_addfb2] [FB:58]
>[  342.847520] [drm:drm_mode_addfb2] [FB:78]
>[  342.873178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  342.873264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  342.873321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  342.873375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  342.873384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.873433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.873450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.873468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.873487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.873501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.873517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.873533] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  342.873548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  342.873562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.873576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.873621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.873628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.873648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.873654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.873675] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.873696] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.873717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.873738] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.873761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.873783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.873803] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  342.873825] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  342.873844] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  342.873867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.873894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  342.876416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.876433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.876447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.876461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.876474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.876488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.876504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.876518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.876533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.876546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.876559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.876575] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  342.876593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.878616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.878631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.878645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.878660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.880165] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.880180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.880193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.881688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.881704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.883540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.886475] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  342.886505] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.886524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  342.886549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  342.903292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.903318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  342.903356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.920015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  342.920028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.936731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  342.936788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.953376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  342.953401] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  342.953437] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  342.972384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  342.972403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  342.972425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.972444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.972466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.972485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.972504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.972523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  342.972545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.972565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.972586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.972646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.972671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.972698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.972751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  342.972997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  342.973005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  342.973049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  342.973069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.973089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  342.973111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.973130] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.973149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.973169] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  342.973188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  342.973207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.973226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  342.973244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.973248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.973267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.973271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  342.973290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  342.973309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.973328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.973347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.973366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  342.973385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.973403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  342.973423] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  342.973442] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  342.973462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.973482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  342.973536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  342.973555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  342.973575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  342.973594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  342.973642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  342.973672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  342.973700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  342.973734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  342.973760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  342.973781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  342.973803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  342.973830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  342.973851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  342.975844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.975860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.975874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.975889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.977393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  342.977407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  342.977421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.978918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.978933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.980737] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.983678] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  342.983705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  342.983724] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  342.983750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.000485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.000511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.000546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.000708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.000748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.017188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.017213] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.017252] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.036127] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.036146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.036166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.036183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.036200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.036215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.036230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.036246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.036263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.036279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.036295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.036311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.036325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.036339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.036371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.036442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.036451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.036492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.036508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.036526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.036545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.036560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.036576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.036593] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.036650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.036674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.036699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.036721] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.036728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.036751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.036757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.036781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.036803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.036827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.036848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.036875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.036896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.036919] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.036941] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.036964] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.036991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.037018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.037352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.037373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.037395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.037415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.037436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.037456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.037480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.037503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.037527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.037546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.037566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.037589] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.037630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.039770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.039786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.039800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.039815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.041318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.041334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.041347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.042842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.042858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.044661] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.047598] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.047641] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.047657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.047679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.064412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.064438] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.064476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.064578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.064663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.081113] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.081139] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.081177] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.100049] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.100069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.100089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.100106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.100123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.100138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.100152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.100168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.100185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.100202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.100217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.100233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.100251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.100270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.100307] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.100382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.100391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.100437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.100463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.100482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.100502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.100517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.100534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.100552] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.100570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.100589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.100607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.100666] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.100673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.100699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.100706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.100731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.100754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.100778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.100799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.100824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.100846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.100869] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.100890] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.100913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.100940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.100967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.101043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.101066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.101090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.101113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.101136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.101160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.101186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.101211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.101235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.101258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.101280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.101306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.101329] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.103325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.103341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.103355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.103369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.104876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.104891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.104904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.106398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.106414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.108221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.111146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.111171] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.111187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.111209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.127921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.127947] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.127983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.128073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.128113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.144592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.144636] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.144680] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.163538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.163557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.163577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.163593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.163651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.163676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.163700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.163724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.163753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.163780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.163805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.163831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.163855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.163877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.163927] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.164032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.164044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.164106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.164127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.164151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.164177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.164197] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.164221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.164242] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.164265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.164285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.164305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.164324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.164330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.164349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.164354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.164375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.164394] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.164414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.164432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.164455] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.164474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.164494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.164513] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.164533] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.164557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.164581] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.164672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.164693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.164716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.164737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.164758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.164780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.164804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.164828] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.164852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.164872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.164893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.164919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.164941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.166932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.166949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.166963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.166978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.168481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.168498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.168516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.170013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.170029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.171834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.174771] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.174798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.174815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.174837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.191584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.191610] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.191691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.191808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.191847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.208285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.208309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.208345] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.226384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.226403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.226423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.226440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.226457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.226472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.226487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.226503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.226520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.226537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.226552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.226568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.226582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.226596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.226673] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.226790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.226804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.226872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.226896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.226922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.226951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.226973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.226998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.227021] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.227045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.227067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.227090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.227111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.227116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.227138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.227143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.227166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.227187] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.227209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.227229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.227254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.227274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.227297] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.227318] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.227340] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.227368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.227392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.227462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.227482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.227503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.227523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.227543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.227562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.227585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.227608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.227649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.227669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.227691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.227714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.227738] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.229728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.229744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.229758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.229773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.231277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.231292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.231309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.232806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.232822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.234645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.237588] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.237614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.237657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.237693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.254387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.254412] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.254446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.254543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.254581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.271076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.271102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.271147] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.290014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.290033] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.290053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.290069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.290087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.290102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.290116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.290133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.290150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.290166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.290181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.290197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.290211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.290224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.290256] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.290328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.290337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.290378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.290394] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.290411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.290430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.290445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.290462] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.290480] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.290499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.290519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.290538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.290556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.290560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.290579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.290582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.290602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.290659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.290686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.290712] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.290737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.290762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.290785] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.290809] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.290837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.290862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.290889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.290960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.291242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.291263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.291285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.291305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.291327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.291351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.291375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.291398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.291417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.291438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.291460] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.291482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.293473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.293489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.293504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.293518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.295025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.295040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.295054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.296557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.296573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.298378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.301300] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.301325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.301342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.301363] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.318078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.318104] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.318140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.318241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.318283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.334758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.334782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.334825] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.353684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.353703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.353723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.353740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.353758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.353774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.353788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.353804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.353822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.353839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.353854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.353870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.353884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.353898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.353930] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.353994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.354002] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.354044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.354060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.354077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.354096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.354111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.354127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.354143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.354158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.354173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.354187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.354201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.354212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.354225] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.354228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.354241] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.354253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.354266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.354278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.354293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.354305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.354322] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.354340] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.354357] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.354375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.354394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.354443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.354462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.354479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.354497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.354514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.354531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.354550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.354568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.354587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.354604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.354621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.354678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.354702] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.356697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.356713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.356728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.356744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.358259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.358277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.358291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.359793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.359809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.361623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.364571] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.364598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.364614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.364672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.381392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.381419] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.381456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.381551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.381592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.398082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.398108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.398146] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.415305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.415326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.415348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.415368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.415389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.415408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.415427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.415447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.415468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.415489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.415509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.415529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.415548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.415567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.415603] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.415920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.415934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.416006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.416033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.416060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.416090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.416115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.416141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.416168] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.416193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.416218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.416242] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.416265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.416271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.416294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.416299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.416323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.416346] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.416367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.416389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.416415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.416438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.416459] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.416482] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.416505] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.416531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.416559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.416668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.416693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.416717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.416739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.416761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.416784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.416810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.416835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.416859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.416881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.416903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.416929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.416952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.419109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.419126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.419140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.419154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.420696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.420711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.420725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.422219] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.422234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.424040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.426983] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.427010] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.427027] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.427049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.443791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.443816] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.443851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.443964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.444013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.460483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.460507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.460550] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.479363] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.479382] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.479402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.479419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.479436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.479451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.479465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.479481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.479499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.479515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.479531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.479546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.479560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.479574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.479606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.479747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.479761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.479832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.479857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.479882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.479911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.479934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.479959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.479983] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.480006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.480028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.480051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.480071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.480077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.480098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.480104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.480127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.480148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.480170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.480190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.480215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.480242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.480264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.480283] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.480303] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.480324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.480348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.480418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.480438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.480459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.480478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.480499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.480519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.480542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.480565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.480588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.480607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.480627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.480668] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.480691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.482684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.482700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.482715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.482729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.484244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.484262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.484279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.485782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.485799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.487612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.490557] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.490584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.490600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.490622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.507380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.507405] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.507440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.507533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.507572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.524070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.524094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.524131] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.543002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.543022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.543044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.543064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.543086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.543105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.543125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.543144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.543165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.543186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.543206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.543226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.543245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.543264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.543300] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.543367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.543376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.543422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.543441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.543461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.543483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.543502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.543522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.543541] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.543560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.543579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.543598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.543617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.543659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.543688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.543696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.543729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.543753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.543776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.543799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.543824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.543847] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.543870] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.543893] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.543915] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.543941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.543967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.544038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.544061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.544083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.544104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.544124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.544146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.544170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.544193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.544216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.544235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.544256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.544281] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.544304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.546301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.546317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.546331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.546345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.547863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.547880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.547895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.549389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.549405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.551212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.554148] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.554175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.554192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.554213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.570962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.570988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.571024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.571125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.571178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.587667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.587689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.587732] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.606587] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.606606] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.606626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.606684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.606714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.606737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.606762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.606786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.606816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.606843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.606869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.606895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.606917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.606938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.606987] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.607103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.607116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.607181] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.607203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.607228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.607255] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.607276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.607300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.607322] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.607345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.607365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.607386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.607405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.607411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.607431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.607436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.607458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.607477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.607498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.607517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.607540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.607559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.607580] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.607599] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.607620] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.607665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.607694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.607766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.607787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.607810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.607832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.607854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.607877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.607903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.607927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.607951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.607973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.607994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.608019] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.608050] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.610038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.610055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.610069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.610083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.611590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.611606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.611619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.613140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.613155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.614989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.617930] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.617957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.617974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.617999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.634739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.634765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.634800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.634911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.634961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.651432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.651457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.651502] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.670365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.670384] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.670404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.670424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.670445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.670464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.670483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.670503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.670524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.670545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.670565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.670586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.670605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.670624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.670708] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.670823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.670837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.670907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.670931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.670957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.670987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.671010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.671035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.671059] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.671083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.671106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.671129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.671149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.671156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.671178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.671183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.671207] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.671228] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.671250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.671271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.671296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.671317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.671339] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.671360] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.671381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.671404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.671431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.671514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.671534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.671555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.671574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.671594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.671614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.671637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.671680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.671704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.671724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.671746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.671772] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.671794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.673781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.673798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.673816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.673834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.675339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.675355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.675369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.676865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.676880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.678684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.681619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.681683] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.681716] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.681749] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.698434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.698461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.698498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.698613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.698706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.715135] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.715158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.715195] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.733418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.733437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.733457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.733473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.733491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.733506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.733521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.733537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.733554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.733571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.733587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.733602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.733616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.733630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.733713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.733816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.733830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.733897] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.733923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.733948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.733976] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.733999] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.734024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.734054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.734076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.734097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.734118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.734137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.734142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.734161] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.734167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.734188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.734207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.734227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.734245] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.734268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.734288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.734308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.734327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.734347] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.734368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.734392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.734463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.734483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.734505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.734524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.734545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.734565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.734588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.734610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.734633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.734672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.734692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.734718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.734740] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.736731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.736747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.736761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.736776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.738289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.738305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.738319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.739816] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.739833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.741635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.744581] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.744608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.744625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.744688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.761396] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.761422] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.761459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.761551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.761593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.778097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.778121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.778157] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.797035] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.797054] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.797074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.797091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.797108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.797123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.797137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.797153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.797170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.797187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.797203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.797218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.797233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.797246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.797282] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.797356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.797364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.797411] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.797431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.797450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.797472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.797489] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.797509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.797528] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.797553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.797571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.797588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.797605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.797608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.797625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.797629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.797646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.797700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.797725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.797748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.797771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.797794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.797815] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.797838] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.797858] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.797883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.797909] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.797981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.798264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.798285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.798307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.798327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.798349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.798374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.798397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.798421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.798440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.798461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.798483] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.798506] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.800495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.800513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.800530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.800548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.802058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.802074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.802088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.803594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.803610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.805416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.808341] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.808367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.808384] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.808405] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.825107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.825133] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.825169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.825270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.825310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.841818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.841842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.841880] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.860742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.860760] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.860780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.860797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.860814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.860830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.860844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.860860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.860877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.860894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.860909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.860925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.860939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.860952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.860984] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.861057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.861066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.861107] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.861126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.861146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.861168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.861187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.861207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.861226] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.861245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.861265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.861284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.861302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.861307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.861325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.861329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.861348] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.861367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.861386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.861404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.861424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.861442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.861461] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.861481] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.861499] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.861519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.861540] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.861586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.861605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.861624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.861643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.861707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.861736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.861766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.861794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.861821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.861845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.861870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.861899] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.861925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.863941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.863959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.863973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.863989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.865497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.865513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.865526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.867023] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.867038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.868844] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.871789] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.871816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.871833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.871855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.888594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.888620] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.888689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.888877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.888915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.905276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.905300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.905343] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.924210] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.924228] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.924248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.924265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.924282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.924298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.924312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.924328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.924345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.924361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.924377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.924392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.924406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.924420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.924452] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.924526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.924534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.924576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.924595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.924615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.924638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.924657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.924717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.924743] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.924769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.924793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.924817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.924839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.924846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.924868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.924874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.924898] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.924920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.924944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.924965] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.924991] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.925012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.925036] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.925057] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.925080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.925108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.925136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.925213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.925237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.925261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.925284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.925307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.925337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.925361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.925385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.925408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.925428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.925447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.925472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.925493] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.927487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.927504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.927522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.927540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.929048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.929064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.929077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.930600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.930618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.932426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.935357] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.935384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.935401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.935423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  343.952171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.952196] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.952230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.952319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.952357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.968857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  343.968883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.968928] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  343.987790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  343.987809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  343.987830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.987847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.987864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.987880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.987899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.987918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  343.987939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.987960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.987980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.988000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.988019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.988038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.988074] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  343.988147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  343.988156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  343.988202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  343.988222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.988241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  343.988264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.988282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.988302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.988321] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  343.988340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  343.988360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.988379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  343.988397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.988401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.988420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.988423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  343.988443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  343.988462] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.988481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.988500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.988519] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  343.988537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.988556] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  343.988575] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  343.988594] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  343.988614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.988635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  343.988740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  343.988763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  343.988787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  343.988808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  343.988830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  343.988852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  343.988877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  343.988903] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  343.988928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  343.988948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  343.988970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  343.988996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  343.989018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  343.991011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.991027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.991041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.991056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.992559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  343.992574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  343.992588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.994083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.994099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.995902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.998837] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  343.998870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  343.998884] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  343.998904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.015653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.015697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.015735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.015837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.015879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.032335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.032359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.032402] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.051269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.051287] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.051307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.051324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.051342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.051361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.051380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.051400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.051421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.051442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.051463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.051483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.051502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.051520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.051557] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.051632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.051641] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.051738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.051768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.051794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.051824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.051848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.051875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.051898] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.051923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.051945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.051968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.051989] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.051995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.052017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.052022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.052045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.052066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.052088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.052116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.052139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.052157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.052178] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.052197] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.052217] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.052238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.052262] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.052331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.052352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.052373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.052392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.052413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.052433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.052456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.052479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.052502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.052521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.052541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.052564] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.052586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.054579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.054595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.054609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.054624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.056129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.056144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.056157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.057652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.057675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.059479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.062403] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.062429] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.062448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.062474] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.079179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.079205] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.079240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.079338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.079377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.095860] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.095885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.095928] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.114789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.114808] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.114828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.114847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.114868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.114888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.114907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.114926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.114947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.114968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.114989] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.115008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.115027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.115046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.115083] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.115159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.115168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.115214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.115234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.115253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.115276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.115294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.115314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.115333] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.115352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.115372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.115390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.115409] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.115413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.115431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.115435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.115454] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.115474] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.115492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.115511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.115530] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.115549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.115568] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.115587] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.115613] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.115632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.115649] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.115749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.115771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.115792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.115812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.115833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.115854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.115878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.115902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.115925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.115945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.115965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.115991] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.116009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.117983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.118000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.118014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.118028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.119531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.119546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.119560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.121056] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.121072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.122877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.125819] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.125843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.125859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.125879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.142623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.142649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.142731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.142844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.142883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.159308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.159334] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.159379] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.178244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.178263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.178284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.178304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.178326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.178345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.178364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.178383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.178405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.178425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.178446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.178466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.178485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.178503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.178540] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.178606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.178615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.178661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.178723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.178751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.178781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.178804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.178833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.178858] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.178883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.178906] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.178932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.178953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.178961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.178983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.178990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.179014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.179044] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.179066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.179085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.179109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.179127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.179150] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.179170] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.179191] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.179215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.179240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.179309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.179330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.179351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.179370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.179391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.179411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.179435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.179458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.179480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.179499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.179519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.179542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.179564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.181554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.181570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.181585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.181599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.183105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.183120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.183134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.184628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.184644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.186448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.189371] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.189397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.189413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.189435] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.206144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.206168] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.206202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.206299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.206337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.222829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.222853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.222896] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.241757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.241776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.241796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.241813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.241831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.241846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.241861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.241878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.241895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.241912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.241927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.241943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.241957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.241971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.242003] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.242075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.242084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.242125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.242140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.242158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.242177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.242192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.242208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.242224] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.242239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.242254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.242269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.242282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.242286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.242299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.242303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.242317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.242331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.242344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.242358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.242374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.242388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.242406] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.242425] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.242444] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.242469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.242486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.242533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.242547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.242561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.242574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.242586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.242600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.242615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.242630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.242644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.242656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.242669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.242723] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.242746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.244737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.244753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.244766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.244781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.246285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.246302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.246320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.247819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.247836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.249640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.252595] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.252622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.252639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.252668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.269390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.269417] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.269454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.269553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.269595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.286071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.286095] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.286130] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.304991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.305011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.305031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.305047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.305065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.305080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.305095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.305111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.305129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.305145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.305161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.305177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.305191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.305205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.305240] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.305315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.305323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.305369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.305389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.305408] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.305430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.305447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.305466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.305486] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.305505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.305524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.305543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.305562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.305566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.305584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.305588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.305607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.305626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.305645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.305664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.305725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.305752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.305780] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.305803] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.305828] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.305856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.305890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.305961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.305981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.306004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.306024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.306045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.306065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.306088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.306111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.306134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.306153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.306173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.306195] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.306217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.308238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.308255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.308270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.308285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.309795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.309811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.309824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.311317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.311333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.313139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.316089] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.316114] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.316132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.316155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.332890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.332916] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.332951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.333049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.333088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.349571] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.349594] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.349629] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.368490] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.368509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.368529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.368546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.368563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.368578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.368592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.368611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.368632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.368653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.368673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.368736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.368760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.368786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.368838] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.368940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.368954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.369022] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.369045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.369071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.369100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.369123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.369148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.369171] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.369195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.369217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.369240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.369260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.369266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.369287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.369293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.369315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.369343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.369363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.369382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.369404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.369422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.369443] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.369461] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.369482] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.369505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.369529] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.369598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.369618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.369639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.369658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.369678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.369722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.369747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.369772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.369796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.369816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.369838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.369863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.369885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.371873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.371889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.371903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.371917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.373420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.373435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.373452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.374949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.374966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.376769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.379704] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.379729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.379745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.379767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.396521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.396547] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.396582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.396718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.396779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.413200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.413225] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.413260] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.432122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.432141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.432162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.432179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.432196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.432212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.432226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.432242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.432260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.432276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.432292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.432307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.432322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.432335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.432367] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.432441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.432450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.432492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.432507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.432525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.432544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.432559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.432575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.432592] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.432607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.432622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.432636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.432650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.432653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.432667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.432670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.432726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.432754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.432775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.432794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.432816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.432835] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.432855] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.432875] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.432894] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.432916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.432940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.433010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.433032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.433052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.433074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.433091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.433105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.433121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.433135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.433149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.433163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.433180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.433199] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.433216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.435215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.435231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.435245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.435260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.436831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.436847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.436860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.438352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.438368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.440185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.443116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.443142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.443158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.443180] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.459885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.459911] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.459946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.460043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.460083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.476565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.476589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.476624] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.495493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.495511] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.495531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.495549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.495566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.495581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.495596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.495612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.495629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.495646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.495661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.495677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.495736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.495760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.495813] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.495927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.495941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.496009] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.496034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.496061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.496091] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.496115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.496141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.496167] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.496192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.496217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.496247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.496269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.496274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.496295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.496300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.496322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.496343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.496364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.496385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.496407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.496428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.496449] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.496470] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.496489] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.496512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.496537] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.496608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.496630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.496652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.496673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.496712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.496735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.496760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.496785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.496809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.496831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.496853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.496878] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.496902] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.498891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.498907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.498921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.498935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.500438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.500453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.500466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.501962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.501977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.503781] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.506714] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.506740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.506756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.506778] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.523531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.523558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.523593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.523734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.523794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.540211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.540236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.540270] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.559134] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.559153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.559172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.559189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.559207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.559226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.559246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.559265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.559286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.559307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.559327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.559347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.559366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.559385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.559421] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.559488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.559497] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.559543] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.559562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.559582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.559604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.559623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.559642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.559661] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.559688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.559743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.559767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.559792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.559798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.559820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.559827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.559849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.559872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.559895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.559916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.559941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.559963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.559986] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.560007] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.560029] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.560054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.560080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.560151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.560173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.560195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.560217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.560236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.560258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.560282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.560303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.560326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.560347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.560366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.560391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.560414] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.562407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.562425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.562442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.562460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.563968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.563986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.564003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.565497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.565513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.567320] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.570242] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.570268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.570284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.570306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.587020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.587046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.587081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.587171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.587210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.603690] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.603727] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.603760] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.622621] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.622639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.622659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.622676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.622694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.622753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.622778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.622805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.622835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.622861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.622887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.622913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.622936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.622959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.623009] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.623125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.623142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.623181] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.623196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.623212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.623232] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.623250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.623268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.623285] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.623303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.623320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.623337] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.623354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.623358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.623375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.623378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.623396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.623414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.623431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.623448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.623466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.623483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.623500] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.623518] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.623535] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.623553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.623572] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.623621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.623639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.623657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.623674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.623692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.623740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.623768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.623794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.623820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.623843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.623865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.623892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.623915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.625907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.625923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.625937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.625952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.627455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.627470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.627483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.628979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.628994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.630797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.633730] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.633756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.633772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.633794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.650547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.650573] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.650608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.650752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.650812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.667228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.667254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.667290] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.686167] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.686186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.686207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.686227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.686248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.686268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.686287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.686306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.686327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.686348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.686368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.686388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.686407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.686426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.686462] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.686537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.686546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.686592] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.686612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.686631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.686653] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.686672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.686699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.686754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.686778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.686804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.686827] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.686849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.686856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.686877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.686883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.686906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.686928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.686950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.686972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.686996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.687018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.687041] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.687062] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.687085] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.687110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.687135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.687206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.687228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.687251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.687270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.687292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.687314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.687338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.687361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.687384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.687405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.687424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.687449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.687472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.689463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.689479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.689493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.689507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.691012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.691027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.691042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.692535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.692550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.694355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.697278] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.697305] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.697321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.697343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.714058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.714084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.714120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.714231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.714273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.730736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.730762] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.730799] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.749654] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.749673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.749693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.749754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.749785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.749812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.749837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.749862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.749892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.749918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.749944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.749969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.749992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.750016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.750066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.750153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.750162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.750205] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.750221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.750239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.750259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.750277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.750303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.750320] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.750338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.750355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.750373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.750390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.750393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.750410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.750414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.750432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.750449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.750466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.750484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.750501] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.750518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.750536] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.750553] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.750571] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.750589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.750608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.750657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.750675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.750693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.750741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.750767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.750793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.750819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.750844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.750869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.750891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.750913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.750940] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.750964] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.752957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.752973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.752988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.753002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.754505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.754522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.754539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.756036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.756053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.757856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.760798] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.760824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.760841] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.760863] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.777606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.777632] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.777666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.777824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.777864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.794307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.794331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.794368] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.813232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.813251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.813271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.813288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.813305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.813325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.813344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.813363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.813385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.813405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.813426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.813446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.813465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.813483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.813520] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.813594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.813603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.813649] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.813669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.813688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.813710] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.813776] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.813801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.813824] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.813846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.813867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.813887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.813906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.813913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.813932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.813938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.813958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.813977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.813997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.814016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.814039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.814060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.814080] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.814099] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.814118] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.814142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.814161] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.814201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.814215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.814229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.814242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.814256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.814269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.814285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.814303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.814322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.814340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.814357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.814376] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.814394] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.816377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.816394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.816408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.816422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.817934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.817949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.817963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.819469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.819486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.821295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.824233] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.824260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.824276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.824298] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.841045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.841071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.841106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.841203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.841243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.857743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.857767] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.857803] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.876672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.876690] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.876710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.876762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.876790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.876816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.876841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.876992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.877011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.877027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.877043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.877058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.877072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.877086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.877127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.877195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.877203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.877246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.877265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.877284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.877305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.877322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.877341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.877359] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.877377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.877395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.877413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.877430] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.877434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.877451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.877454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.877473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.877491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.877509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.877527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.877545] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.877563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.877581] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.877599] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.877617] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.877635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.877654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.877705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.877754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.877779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.877805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.877829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.877854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.877880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.877906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.877931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.877954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.877978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.878004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.878029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.880279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.880297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.880314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.880332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.881845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.881861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.881875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.883368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.883384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.885188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.888136] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.888163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.888180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.888202] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.904934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.904959] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.904993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.905091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.905130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.921619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.921644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.921689] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  344.940533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  344.940552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.940572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.940589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.940606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.940621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.940635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.940652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.940669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.940686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.940701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.940762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.940784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.940808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.940859] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.940976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.940989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.941057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.941080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.941106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.941134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.941157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.941183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.941206] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  344.941230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  344.941252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.941275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.941296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.941302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.941323] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.941328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.941351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.941371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.941393] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.941413] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.941437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.941458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.941480] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  344.941500] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  344.941522] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  344.941545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.941578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  344.941649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.941668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.941689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.941709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.941747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.941768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.941792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.941816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.941839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.941858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.941879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.941905] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  344.941926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.943917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.943932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.943946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.943961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.945463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.945479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.945492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.946988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.947003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.948807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.951749] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  344.951781] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.951796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  344.951816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.968557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.968584] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  344.968619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.968743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.968802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.985238] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  344.985264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.985309] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.004191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.004210] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.004230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.004247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.004264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.004279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.004294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.004310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.004327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.004344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.004360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.004376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.004390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.004404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.004436] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.004506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.004514] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.004555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.004571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.004588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.004607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.004622] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.004638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.004657] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.004676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.004696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.004715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.004765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.004773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.004797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.004803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.004826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.004848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.004871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.004892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.004917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.004938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.004961] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.004982] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.005003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.005028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.005060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.005130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.005150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.005163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.005176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.005194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.005212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.005232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.005252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.005270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.005288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.005306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.005325] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.005343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.007323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.007340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.007354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.007368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.008877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.008893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.008906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.010398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.010414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.012237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.015178] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.015203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.015219] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.015241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.031988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.032014] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.032052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.032150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.032192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.048661] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.048684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.048727] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.067592] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.067611] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.067631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.067648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.067665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.067680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.067694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.067710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.067772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.067800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.067827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.067854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.067876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.067899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.067950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.068063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.068076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.068144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.068168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.068194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.068222] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.068244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.068269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.068292] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.068317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.068339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.068361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.068381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.068387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.068408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.068414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.068436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.068463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.068483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.068501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.068524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.068542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.068562] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.068581] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.068601] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.068624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.068648] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.068718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.068759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.068782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.068802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.068824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.068845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.068869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.068893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.068916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.068936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.068957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.068982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.069004] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.070997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.071013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.071027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.071044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.072548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.072563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.072577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.074073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.074088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.075891] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.078832] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.078859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.078876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.078898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.095637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.095662] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.095695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.095869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.095914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.112334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.112357] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.112401] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.131265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.131284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.131304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.131321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.131338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.131353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.131367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.131382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.131400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.131416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.131435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.131456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.131475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.131494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.131530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.131606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.131615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.131661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.131681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.131700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.131722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.131783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.131810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.131838] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.131862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.131894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.131915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.131936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.131942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.131963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.131969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.131991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.132011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.132034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.132053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.132077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.132097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.132120] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.132140] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.132161] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.132185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.132211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.132281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.132301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.132322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.132342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.132362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.132382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.132405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.132427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.132450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.132469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.132489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.132511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.132532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.134525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.134543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.134560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.134578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.136087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.136103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.136120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.137613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.137630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.139438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.142360] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.142385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.142401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.142423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.159137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.159165] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.159202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.159305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.159359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.175839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.175863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.175899] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.194774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.194793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.194813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.194830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.194848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.194862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.194877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.194892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.194910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.194927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.194943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.194958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.194972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.194986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.195018] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.195082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.195090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.195132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.195148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.195165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.195184] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.195200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.195216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.195232] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.195248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.195263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.195278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.195292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.195295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.195313] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.195317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.195337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.195356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.195375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.195394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.195413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.195439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.195454] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.195469] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.195482] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.195498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.195515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.195561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.195576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.195590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.195603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.195616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.195630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.195645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.195659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.195673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.195686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.195698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.195714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.195729] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.197764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.197781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.197795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.197810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.199315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.199331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.199345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.200840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.200856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.202677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.205613] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.205647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.205664] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.205685] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.222427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.222454] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.222492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.222592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.222634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.239108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.239132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.239175] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.258039] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.258058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.258078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.258094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.258112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.258127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.258142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.258158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.258175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.258192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.258208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.258223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.258237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.258251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.258283] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.258354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.258362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.258404] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.258420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.258437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.258456] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.258472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.258488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.258504] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.258519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.258534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.258553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.258572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.258576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.258595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.258598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.258618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.258637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.258656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.258675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.258694] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.258713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.258732] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.258789] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.258817] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.258845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.258875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.258959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.258982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.259003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.259025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.259045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.259067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.259369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.259393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.259417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.259436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.259457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.259479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.259501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.261492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.261508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.261522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.261537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.263041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.263059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.263076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.264570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.264587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.266392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.269314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.269339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.269355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.269377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.286092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.286117] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.286152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.286250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.286289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.302773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.302797] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.302840] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.321696] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.321715] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.321735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.321794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.321823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.321846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.321870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.321893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.321923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.321948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.321973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.321998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.322018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.322041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.322090] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.322197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.322206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.322249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.322265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.322282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.322302] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.322317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.322334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.322350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.322368] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.322388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.322407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.322426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.322430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.322448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.322452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.322472] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.322491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.322509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.322534] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.322551] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.322568] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.322585] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.322602] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.322619] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.322638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.322657] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.322707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.322725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.322768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.322794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.322816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.322840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.322866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.322890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.322915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.322935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.322956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.322982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.323004] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.324992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.325008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.325022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.325036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.326538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.326553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.326567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.328062] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.328077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.329880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.332822] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.332849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.332866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.332888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.349630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.349656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.349693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.349851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.349891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.366330] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.366356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.366394] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.385270] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.385289] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.385309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.385328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.385349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.385368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.385388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.385407] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.385428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.385449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.385469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.385489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.385507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.385526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.385562] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.385629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.385637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.385683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.385702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.385722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.385744] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.385803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.385831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.385858] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.385882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.385907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.385935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.385957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.385963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.385984] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.385990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.386012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.386032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.386054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.386073] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.386097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.386116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.386138] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.386157] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.386178] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.386203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.386228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.386536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.386558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.386581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.386601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.386621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.386642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.386666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.386688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.386711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.386730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.386769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.386792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.386816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.388952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.388969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.388983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.388998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.390504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.390519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.390533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.392028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.392044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.393847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.396797] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.396824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.396841] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.396862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.413596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.413622] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.413656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.413794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.413854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.430277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.430301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.430345] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.449217] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.449237] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.449257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.449273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.449291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.449305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.449320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.449336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.449353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.449369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.449385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.449400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.449415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.449428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.449460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.449530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.449538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.449580] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.449596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.449614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.449633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.449648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.449664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.449681] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.449696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.449711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.449725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.449739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.449773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.449799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.449806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.449830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.449853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.449876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.449898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.449924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.449945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.449968] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.449990] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.450013] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.450038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.450066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.450144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.450169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.450193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.450217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.450240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.450272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.450297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.450320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.450344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.450366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.450386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.450411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.450432] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.452424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.452442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.452459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.452477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.453985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.454002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.454016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.455508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.455523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.457328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.460249] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.460281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.460297] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.460322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.477027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.477053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.477088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.477185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.477225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.493724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.493748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.493839] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.512716] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.512735] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.512799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.512824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.512852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.512875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.512897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.512920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.512948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.512973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.512998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.513023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.513043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.513065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.513115] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.513223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.513231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.513274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.513290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.513308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.513327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.513343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.513359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.513376] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.513390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.513405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.513419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.513438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.513442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.513461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.513464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.513484] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.513503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.513522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.513540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.513559] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.513578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.513597] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.513623] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.513638] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.513654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.513672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.513719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.513734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.513748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.513787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.513811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.513832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.513857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.513881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.513905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.513926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.513947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.513970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.513993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.515983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.516000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.516017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.516035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.517540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.517556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.517570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.519066] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.519081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.520885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.523833] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.523859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.523874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.523895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.540635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.540660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.540696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.540885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.540925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.557335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.557359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.557396] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.576286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.576305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.576325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.576341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.576359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.576373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.576388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.576403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.576421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.576437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.576453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.576468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.576482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.576496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.576528] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.576591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.576599] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.576640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.576656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.576675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.576698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.576715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.576735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.576754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.576813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.576840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.576865] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.576887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.576894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.576917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.576923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.576947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.576969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.576994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.577024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.577047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.577069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.577089] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.577110] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.577130] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.577154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.577180] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.577479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.577501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.577523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.577543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.577563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.577584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.577607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.577630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.577653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.577672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.577692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.577714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.577736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.579744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.579771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.579785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.579800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.581317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.581332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.581346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.582863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.582879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.584699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.587637] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.587664] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.587681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.587703] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.604448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.604474] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.604509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.604597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.604636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.621131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.621157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.621202] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.640069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.640087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.640107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.640124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.640142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.640157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.640172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.640188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.640205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.640222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.640238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.640253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.640272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.640291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.640328] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.640402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.640410] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.640457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.640476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.640496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.640518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.640534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.640554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.640573] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.640592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.640611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.640630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.640649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.640653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.640671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.640675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.640694] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.640714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.640732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.640751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.640812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.640839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.640865] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.640889] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.640913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.640941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.640969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.641047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.641070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.641093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.641117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.641141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.641166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.641194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.641220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.641245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.641268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.641292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.641326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.641349] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.643350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.643367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.643382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.643397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.644911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.644926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.644939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.646435] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.646451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.648262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.651218] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.651246] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.651265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.651290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.668038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.668065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.668102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.668197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.668239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.684711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.684734] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.684815] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.703683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.703702] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.703722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.703739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.703756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.703815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.703840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.703866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.703896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.703923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.703949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.703975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.703998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.704020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.704070] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.704187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.704197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.704240] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.704256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.704274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.704293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.704309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.704325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.704342] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.704358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.704373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.704392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.704410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.704415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.704433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.704437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.704456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.704476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.704494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.704513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.704532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.704551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.704570] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.704589] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.704608] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.704628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.704649] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.704703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.704723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.704742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.704761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.704814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.704844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.704879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.704905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.704929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.704952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.704974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.705074] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.705098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.707101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.707118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.707132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.707150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.708656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.708672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.708686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.710183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.710199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.712004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.714954] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.714981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.714998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.715027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.731756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.731811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.731846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.731952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.732002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.748448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.748472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.748515] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.767369] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.767388] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.767408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.767425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.767446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.767465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.767485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.767504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.767525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.767546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.767566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.767586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.767605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.767624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.767660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.767727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.767736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.767829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.767856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.767886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.767916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.767940] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.767966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.767991] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.768016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.768039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.768063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.768087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.768094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.768117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.768123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.768146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.768170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.768193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.768216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.768240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.768262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.768290] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.768310] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.768329] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.768351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.768376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.768446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.768467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.768487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.768507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.768526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.768547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.768570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.768593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.768616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.768635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.768655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.768677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.768699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.770690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.770706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.770720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.770735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.772241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.772257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.772270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.773768] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.773795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.775599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.778542] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.778569] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.778585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.778606] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.795349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.795376] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.795414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.795516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.795570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.812043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.812067] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.812111] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.830973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.830992] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.831012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.831029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.831050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.831069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.831089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.831108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.831129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.831150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.831170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.831190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.831209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.831228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.831264] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.831338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.831347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.831393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.831413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.831432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.831454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.831473] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.831493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.831512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.831531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.831550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.831569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.831588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.831592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.831610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.831614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.831633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.831652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.831671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.831697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.831715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.831731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.831746] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.831760] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.831811] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.831836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.831862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.831933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.831955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.831977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.831997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.832019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.832040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.832065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.832088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.832112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.832134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.832156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.832181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.832204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.834199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.834215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.834230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.834244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.835752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.835767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.835805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.837306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.837322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.839136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.842086] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.842113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.842130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.842152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.858883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.858908] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.858941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.859034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.859073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.875579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.875603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.875638] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.894478] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.894498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.894519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.894539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.894560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.894580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.894599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.894618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.894640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.894660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.894681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.894701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.894720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.894739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.894775] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.894912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.894926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.894997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.895022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.895049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.895078] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.895101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.895128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.895159] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.895181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.895201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.895222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.895241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.895246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.895266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.895271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.895292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.895311] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.895332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.895351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.895373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.895392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.895413] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.895431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.895451] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.895472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.895496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.895566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.895588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.895608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.895629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.895648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.895669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.895693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.895716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.895739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.895758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.895801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.895827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.895848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.897842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.897859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.897876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.897894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.899400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.899416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.899430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.900927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.900945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.902754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.905721] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.905747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.905763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.905824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.922504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.922530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.922567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.922668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.922710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.939185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  345.939210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  345.939245] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  345.958103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  345.958122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  345.958142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.958159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.958177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.958192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.958210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.958230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.958251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.958272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.958292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.958312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.958331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.958349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.958386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.958462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.958471] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  345.958517] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  345.958537] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.958556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  345.958578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.958597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.958623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.958649] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  345.958665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  345.958679] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.958692] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  345.958705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.958708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.958725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.958728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  345.958746] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  345.958763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.958818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.958841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.958866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  345.958887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.958910] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  345.958930] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  345.958952] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  345.958977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.959003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  345.959074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  345.959096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  345.959118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  345.959140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  345.959162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  345.959185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  345.959210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  345.959233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  345.959257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.959278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  345.959299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  345.959324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  345.959347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  345.961422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.961440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.961458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.961476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.962985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  345.963002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  345.963016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.964508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.964524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  345.966330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.969253] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  345.969279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  345.969295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  345.969317] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  345.986030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  345.986056] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  345.986091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  345.986181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  345.986221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.002703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.002727] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.002760] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.021722] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.021741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.021761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.021777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.021839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.021865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.021888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.021914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.021943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.021968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.021985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.022002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.022017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.022031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.022065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.022136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.022145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.022188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.022205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.022223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.022242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.022258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.022275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.022292] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.022308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.022323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.022338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.022352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.022357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.022375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.022379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.022399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.022418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.022439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.022457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.022477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.022496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.022516] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.022535] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.022555] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.022576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.022597] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.022651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.022672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.022691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.022711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.022731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.022750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.022771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.022818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.022845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.022868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.022891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.022917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.022941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.024934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.024951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.024965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.024979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.026481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.026496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.026510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.028006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.028021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.029826] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.032762] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.032821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.032853] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.032890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.049576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.049602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.049638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.049734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.049774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.066277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.066301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.066337] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.085212] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.085233] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.085255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.085274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.085296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.085316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.085335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.085354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.085376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.085396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.085416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.085436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.085455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.085474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.085510] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.085584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.085593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.085638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.085658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.085678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.085700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.085718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.085738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.085757] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.085776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.085836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.085861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.085884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.085891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.085912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.085919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.085941] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.085963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.085985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.086006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.086031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.086053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.086074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.086095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.086117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.086142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.086167] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.086408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.086433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.086448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.086462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.086475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.086490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.086506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.086521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.086536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.086549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.086562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.086578] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.086593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.088564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.088580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.088595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.088611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.090119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.090134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.090147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.091639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.091654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.093460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.096383] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.096409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.096425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.096446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.113160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.113186] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.113220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.113319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.113359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.129840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.129864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.129907] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.148767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.148786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.148850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.148869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.148888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.148904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.148919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.148935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.148954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.148971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.148987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.149004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.149018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.149033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.149065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.149139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.149147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.149191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.149207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.149225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.149244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.149260] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.149276] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.149292] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.149308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.149323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.149337] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.149352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.149356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.149370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.149374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.149388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.149402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.149416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.149430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.149447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.149461] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.149476] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.149490] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.149504] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.149520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.149539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.149588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.149604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.149618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.149633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.149647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.149662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.149678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.149694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.149710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.149724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.149738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.149754] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.149770] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.151777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.151805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.151819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.151834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.153400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.153415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.153432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.154929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.154945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.156751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.159673] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.159699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.159715] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.159737] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.176446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.176470] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.176504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.176592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.176630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.193131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.193157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.193201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.212064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.212083] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.212103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.212121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.212138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.212154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.212168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.212184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.212201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.212218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.212233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.212249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.212263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.212277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.212309] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.212373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.212381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.212423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.212438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.212455] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.212477] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.212497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.212516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.212536] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.212555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.212574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.212593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.212612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.212616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.212635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.212638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.212658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.212677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.212696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.212715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.212734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.212753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.212772] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.212791] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.212853] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.212880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.212911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.212990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.213015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.213038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.213062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.213084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.213109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.213136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.213161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.213187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.213209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.213233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.213260] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.213283] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.215286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.215303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.215317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.215332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.216861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.216876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.216890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.218385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.218402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.220214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.223163] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.223191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.223210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.223235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.239965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.239991] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.240026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.240123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.240162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.256645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.256669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.256704] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.275533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.275552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.275572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.275589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.275606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.275621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.275636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.275652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.275669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.275686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.275702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.275718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.275732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.275746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.275778] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.275921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.275935] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.276004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.276028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.276054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.276083] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.276105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.276130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.276154] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.276177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.276200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.276222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.276243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.276249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.276270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.276275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.276299] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.276320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.276342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.276362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.276387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.276407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.276429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.276450] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.276472] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.276495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.276521] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.276596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.276619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.276640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.276662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.276683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.276706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.276731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.276756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.276781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.276827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.276849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.276873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.276896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.278885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.278901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.278915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.278930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.280433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.280449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.280463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.281960] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.281977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.283822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.286746] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.286772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.286792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.286849] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.303517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.303542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.303576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.303672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.303710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.320203] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.320227] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.320262] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.339119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.339138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.339158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.339175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.339192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.339208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.339222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.339238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.339256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.339272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.339288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.339303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.339317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.339331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.339363] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.339435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.339443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.339485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.339500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.339518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.339537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.339552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.339568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.339584] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.339602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.339622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.339641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.339660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.339664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.339682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.339686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.339705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.339724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.339743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.339762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.339782] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.339800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.339862] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.339888] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.339914] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.339940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.339968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.340046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.340069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.340094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.340116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.340139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.340161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.340188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.340220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.340243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.340262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.340282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.340304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.340326] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.342336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.342353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.342367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.342382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.343977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.343995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.344011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.345509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.345525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.347337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.350276] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.350303] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.350319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.350341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.367096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.367122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.367157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.367250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.367290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.383787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.383828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.383873] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.402742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.402761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.402781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.402798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.402860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.402881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.402896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.402913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.402931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.402948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.402964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.402984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.403004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.403024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.403061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.403129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.403138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.403185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.403206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.403226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.403249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.403268] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.403288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.403307] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.403326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.403346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.403365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.403384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.403388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.403407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.403411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.403431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.403450] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.403470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.403490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.403509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.403527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.403547] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.403574] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.403591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.403609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.403626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.403667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.403682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.403697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.403710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.403724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.403738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.403755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.403769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.403784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.403797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.403833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.403856] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.403878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.405879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.405897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.405914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.405933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.407440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.407457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.407472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.408968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.408985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.410789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.413737] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.413763] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.413780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.413809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.430551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.430577] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.430612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.430710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.430750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.447232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.447256] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.447291] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.466152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.466171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.466191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.466208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.466225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.466241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.466256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.466272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.466290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.466310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.466331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.466351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.466370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.466389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.466425] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.466499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.466507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.466553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.466573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.466593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.466614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.466633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.466653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.466672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.466691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.466710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.466729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.466748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.466752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.466770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.466774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.466793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.466858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.466888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.466914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.466942] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.466968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.466994] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.467018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.467043] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.467076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.467102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.467173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.467195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.467219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.467241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.467262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.467285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.467309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.467333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.467356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.467377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.467397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.467421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.467444] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.469436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.469453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.469467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.469482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.470989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.471004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.471017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.472509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.472525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.474330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.477254] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.477279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.477295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.477323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.494030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.494057] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.494095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.494194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.494236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.510711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.510735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.510770] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.529621] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.529640] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.529659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.529676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.529693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.529708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.529722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.529738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.529756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.529772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.529787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.529803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.529862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.529885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.529938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.530053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.530067] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.530136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.530162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.530189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.530219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.530243] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.530268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.530294] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.530319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.530343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.530367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.530390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.530396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.530418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.530424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.530448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.530471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.530493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.530516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.530542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.530565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.530586] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.530608] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.530638] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.530661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.530686] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.530757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.530779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.530801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.530843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.530864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.530888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.530914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.530938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.530962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.530984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.531007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.531033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.531056] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.533051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.533067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.533082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.533096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.534599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.534614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.534628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.536124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.536139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.537943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.540884] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.540911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.540928] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.540951] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.557694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.557721] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.557758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.557927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.557968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.574394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.574418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.574455] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.593345] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.593364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.593384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.593400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.593418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.593432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.593446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.593462] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.593480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.593496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.593516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.593537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.593556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.593575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.593611] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.593678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.593686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.593733] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.593752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.593772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.593794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.593813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.593876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.593905] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.593933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.593959] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.593984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.594009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.594016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.594039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.594046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.594071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.594095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.594120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.594144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.594178] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.594200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.594223] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.594245] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.594267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.594292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.594318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.594658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.594681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.594704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.594726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.594748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.594771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.594796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.594819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.594865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.594888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.594910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.594936] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.594960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.597069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.597085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.597099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.597114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.598616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.598630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.598644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.600141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.600156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.601959] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.604891] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.604917] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.604933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.604955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.621709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.621735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.621770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.621961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.622002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.638409] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.638434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.638470] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.657347] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.657366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.657385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.657405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.657427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.657446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.657465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.657484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.657506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.657526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.657547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.657567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.657586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.657605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.657641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.657716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.657724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.657770] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.657789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.657809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.657875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.657905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.657934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.657963] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.657989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.658015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.658039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.658064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.658071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.658094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.658100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.658125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.658148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.658173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.658196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.658224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.658247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.658272] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.658296] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.658320] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.658346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.658610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.658696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.658720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.658743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.658765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.658786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.658809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.658856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.658881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.658906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.658928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.658950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.658976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.659078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.661069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.661085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.661099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.661117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.662622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.662638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.662652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.664150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.664166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.665969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.668921] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.668946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.668961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.668982] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.685720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.685746] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.685780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.685946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.685985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.702420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.702446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.702483] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.721360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.721378] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.721398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.721415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.721432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.721451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.721471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.721490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.721511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.721532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.721552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.721573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.721592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.721610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.721647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.721722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.721731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.721777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.721796] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.721816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.721882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.721912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.721941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.721969] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.721995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.722021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.722046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.722070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.722077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.722100] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.722107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.722137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.722159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.722182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.722203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.722228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.722249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.722272] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.722293] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.722315] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.722340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.722564] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.722636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.722660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.722682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.722704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.722726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.722749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.722773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.722797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.722821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.722860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.722882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.722906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.722930] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.725056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.725072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.725086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.725101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.726603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.726618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.726631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.728127] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.728143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.729950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.732895] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.732922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.732938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.732960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.749701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.749727] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.749765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.749955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.749995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.766401] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.766425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.766460] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.785334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.785353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.785372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.785389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.785406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.785421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.785435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.785451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.785472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.785492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.785513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.785533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.785552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.785571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.785608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.785674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.785683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.785729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.785749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.785769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.785791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.785809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.785829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.785892] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.785922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.785949] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.785975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.786000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.786007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.786031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.786037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.786062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.786086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.786111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.786135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.786162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.786186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.786210] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.786234] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.786258] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.786285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.786313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.786392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.786416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.786440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.786461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.786485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.786508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.786535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.786560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.786591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.786611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.786632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.786656] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.786679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.788675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.788691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.788705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.788719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.790226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.790241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.790255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.791770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.791786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.793591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.796515] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.796541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.796557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.796579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.813291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.813317] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.813353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.813446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.813488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.829971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.829997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.830043] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.848907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.848926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.848946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.848963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.848980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.848995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.849010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.849025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.849043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.849059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.849075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.849090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.849104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.849118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.849150] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.849222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.849230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.849271] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.849287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.849304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.849323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.849338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.849355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.849371] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.849386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.849401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.849415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.849429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.849432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.849446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.849449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.849463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.849477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.849491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.849504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.849520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.849534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.849547] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.849561] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.849574] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.849590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.849607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.849657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.849676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.849695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.849715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.849734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.849753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.849774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.849794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.849815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.849876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.849902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.849932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.849958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.851956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.851973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.851987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.852002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.853505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.853521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.853534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.855030] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.855046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.856859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.859794] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.859821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.859873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.859911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.876610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.876636] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.876671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.876767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.876807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.893310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.893335] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.893372] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.912247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.912265] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.912285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.912302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.912319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.912334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.912349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.912364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.912382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.912398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.912414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.912429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.912443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.912457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.912489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.912561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.912569] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.912611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.912626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.912644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.912663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.912678] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.912694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.912710] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.912726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.912740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.912755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.912769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.912772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.912786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.912790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.912804] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.912818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.912831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.912887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.912913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.912938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.912962] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.912984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.913008] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.913035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.913063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.913141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.913427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.913452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.913477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.913501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.913525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.913559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.913583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.913607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.913628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.913648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.913672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.913695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.915689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.915706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.915719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.915734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.917240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.917254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.917267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.918783] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.918799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.920606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.923544] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.923571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.923588] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.923610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  346.940357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.940383] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.940421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.940522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.940564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.957056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  346.957080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  346.957117] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.975985] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  346.976006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  346.976028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.976047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.976069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.976088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.976108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.976127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  346.976148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.976169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.976189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.976209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.976228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.976246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.976283] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  346.976359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  346.976367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  346.976413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  346.976433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  346.976452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  346.976474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.976493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.976512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.976532] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  346.976551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.976570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.976589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  346.976607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.976611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.976630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.976633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  346.976653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  346.976672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.976691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.976710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.976728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  346.976747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.976766] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  346.976785] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  346.976804] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  346.976824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.976888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  346.976959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  346.976983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  346.977009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  346.977039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  346.977061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  346.977083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  346.977108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  346.977132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  346.977156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  346.977176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  346.977198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  346.977222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  346.977245] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  346.981440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.981459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.981475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.981491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.984090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  346.984108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  346.984124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.986688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.986706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.989584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.992508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.992534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  346.992550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  346.992572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.009284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.009309] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.009345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.009438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.009478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.025964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.025989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.026032] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.044898] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.044917] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.044938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.044954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.044972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.044987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.045002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.045018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.045036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.045052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.045068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.045083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.045097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.045111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.045146] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.045219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.045228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.045274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.045294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.045314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.045336] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.045355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.045375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.045394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.045413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.045432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.045451] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.045470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.045474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.045492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.045496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.045515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.045534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.045553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.045572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.045591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.045610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.045635] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.045651] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.045665] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.045681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.045698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.045744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.045758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.045772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.045785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.045798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.045812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.045827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.045881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.045905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.045925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.045945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.045969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.045990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.049077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.049097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.049116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.049136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.051705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.051722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.051745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.054318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.054336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.057212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.060162] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.060189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.060206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.060228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.076962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.076988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.077023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.077119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.077158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.093642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.093666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.093709] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.112573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.112592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.112612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.112629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.112646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.112665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.112684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.112704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.112725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.112746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.112766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.112786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.112805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.112824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.112909] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.113003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.113011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.113056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.113074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.113092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.113112] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.113129] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.113146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.113163] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.113179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.113194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.113217] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.113230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.113235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.113247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.113250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.113264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.113280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.113301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.113319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.113335] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.113351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.113370] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.113387] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.113406] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.113424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.113444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.113495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.113513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.113531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.113549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.113567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.113585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.113605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.113624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.113643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.113660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.113678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.113697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.113715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.116786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.116805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.116820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.116836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.120474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.120494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.120513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.123080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.123099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.125996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.128936] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.128963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.128980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.129002] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.145745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.145770] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.145804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.145954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.145993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.162428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.162451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.162485] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.181339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.181358] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.181377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.181394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.181412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.181427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.181441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.181457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.181475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.181491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.181506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.181522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.181536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.181550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.181582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.181653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.181662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.181703] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.181719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.181736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.181755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.181771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.181787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.181803] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.181818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.181833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.181855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.181907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.181914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.181936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.181942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.181965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.181985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.182006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.182026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.182049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.182069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.182090] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.182110] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.182131] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.182156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.182182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.182252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.182274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.182294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.182315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.182335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.182356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.182380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.182403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.182426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.182445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.182465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.182490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.182511] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.185611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.185630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.185646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.185662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.189381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.189399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.189415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.192015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.192034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.194926] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.197850] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.197891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.197908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.197930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.214677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.214702] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.214737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.214829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.214918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.231358] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.231382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.231417] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.250273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.250292] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.250312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.250329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.250347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.250362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.250377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.250393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.250414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.250435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.250455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.250476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.250494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.250513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.250550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.250616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.250625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.250671] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.250691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.250710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.250732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.250751] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.250770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.250790] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.250809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.250828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.250847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.250911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.250921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.250948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.250955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.250980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.251006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.251032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.251057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.251084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.251109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.251134] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.251158] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.251183] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.251210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.251238] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.251316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.251340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.251364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.251396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.251417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.251439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.251461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.251483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.251506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.251525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.251546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.251571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.251593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.255780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.255799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.255815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.255832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.258452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.258470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.258484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.261055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.261073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.263931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.266881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.266908] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.266928] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.266952] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.283681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.283707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.283742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.283838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.283929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.300362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.300388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.300425] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.319288] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.319307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.319327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.319344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.319362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.319377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.319393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.319409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.319427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.319443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.319458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.319474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.319488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.319502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.319535] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.319607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.319615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.319657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.319672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.319690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.319709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.319724] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.319741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.319757] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.319772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.319787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.319806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.319825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.319829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.319848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.319897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.319924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.319948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.319972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.319994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.320019] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.320042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.320064] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.320087] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.320109] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.320134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.320159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.320230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.320252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.320274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.320296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.320318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.320339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.320363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.320386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.320409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.320428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.320449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.320474] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.320497] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.323587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.323606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.323622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.323638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.326214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.326232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.326247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.328809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.328826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.331704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.334630] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.334657] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.334676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.334701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.351403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.351430] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.351465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.351562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.351602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.368104] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.368129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.368173] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.387041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.387059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.387079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.387096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.387117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.387137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.387156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.387175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.387197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.387217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.387238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.387258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.387277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.387296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.387332] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.387407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.387415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.387461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.387487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.387505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.387523] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.387537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.387553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.387569] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.387584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.387598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.387611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.387624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.387628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.387640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.387643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.387657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.387670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.387687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.387704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.387722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.387739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.387756] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.387774] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.387791] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.387809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.387828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.387910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.387932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.387954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.387974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.387995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.388016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.388040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.388062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.388084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.388104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.388123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.388147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.388168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.391271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.391290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.391306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.391325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.395020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.395039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.395055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.397622] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.397640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.400516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.403454] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.403481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.403497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.403519] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.420266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.420291] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.420326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.420427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.420467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.436946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.436971] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.437005] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.455860] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.455895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.455916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.455933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.455950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.455965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.455981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.455997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.456014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.456031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.456047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.456062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.456077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.456090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.456122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.456187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.456195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.456237] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.456256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.456276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.456298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.456317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.456337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.456356] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.456375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.456395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.456414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.456432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.456436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.456455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.456458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.456478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.456497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.456516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.456535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.456554] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.456572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.456591] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.456610] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.456629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.456649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.456670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.456724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.456743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.456763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.456782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.456802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.456821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.456841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.456861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.456918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.456944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.456971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.457000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.457032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.460129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.460147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.460163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.460183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.462759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.462776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.462792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.465376] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.465394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.468303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.471253] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.471279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.471296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.471318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.488042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.488065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.488098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.488193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.488231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.504735] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.504761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.504796] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.523675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.523694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.523714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.523730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.523747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.523762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.523776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.523792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.523810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.523826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.523842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.523857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.523916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.523940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.523992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.524104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.524118] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.524186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.524211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.524238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.524268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.524292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.524318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.524345] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.524369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.524394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.524417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.524438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.524445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.524467] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.524473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.524497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.524520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.524550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.524571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.524595] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.524617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.524638] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.524660] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.524679] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.524702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.524727] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.524798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.524820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.524842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.524863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.524901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.524924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.524950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.524975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.524999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.525021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.525043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.525069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.525093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.527084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.527100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.527114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.527131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.528637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.528654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.528672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.530170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.530187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.531991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.534935] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.534962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.534978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.535000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.551741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.551767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.551802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.551960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.552017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.568422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.568446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.568480] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.587355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.587374] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.587394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.587411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.587429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.587444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.587459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.587474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.587492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.587512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.587533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.587553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.587572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.587591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.587628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.587703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.587712] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.587758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.587777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.587797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.587819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.587838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.587857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.587876] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.587935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.587968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.587993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.588016] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.588023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.588044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.588051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.588073] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.588095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.588118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.588140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.588164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.588184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.588207] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.588228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.588250] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.588275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.588301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.588373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.588395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.588417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.588438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.588457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.588478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.588502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.588526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.588549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.588568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.588589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.588613] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.588636] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.590630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.590646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.590660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.590678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.592186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.592202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.592216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.593708] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.593723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.595528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.598453] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.598480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.598499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.598523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.615229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.615255] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.615289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.615389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.615429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.631909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.631933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.631968] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.650822] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.650841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.650861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.650878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.650950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.650976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.651000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.651025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.651054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.651080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.651107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.651132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.651156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.651179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.651228] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.651328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.651336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.651375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.651390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.651407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.651424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.651439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.651454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.651469] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.651483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.651497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.651510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.651523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.651526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.651539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.651542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.651555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.651567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.651579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.651591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.651606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.651619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.651631] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.651644] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.651656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.651670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.651687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.651732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.651746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.651759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.651772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.651785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.651798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.651812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.651826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.651840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.651852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.651865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.651911] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.651936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.653931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.653947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.653961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.653976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.655491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.655508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.655524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.657026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.657045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.658854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.661779] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.661805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.661821] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.661843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.678558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.678583] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.678617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.678704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.678742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.695252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.695278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.695325] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.714195] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.714214] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.714234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.714251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.714268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.714283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.714298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.714317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.714339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.714359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.714380] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.714400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.714419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.714438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.714475] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.714549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.714558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.714604] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.714623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.714643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.714665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.714684] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.714703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.714723] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.714741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.714761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.714780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.714798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.714802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.714820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.714824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.714850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.714866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.714881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.714936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.714959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.714980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.715001] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.715021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.715041] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.715065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.715088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.715148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.715170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.715191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.715213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.715229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.715244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.715260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.715274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.715289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.715302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.715315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.715331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.715346] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.717351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.717368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.717382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.717397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.718909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.718925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.718939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.720502] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.720518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.722326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.725270] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.725298] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.725314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.725336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.742076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.742103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.742140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.742254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.742304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.758767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.758791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.758824] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.777684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.777702] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.777723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.777739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.777757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.777772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.777787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.777803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.777820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.777836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.777851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.777871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.777964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.777988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.778039] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.778155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.778169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.778238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.778270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.778294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.778321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.778343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.778367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.778391] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.778414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.778436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.778458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.778479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.778485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.778505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.778510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.778531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.778552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.778571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.778592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.778615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.778636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.778655] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.778676] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.778696] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.778718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.778743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.778813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.778835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.778856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.778877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.778919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.778943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.778968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.778994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.779018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.779040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.779062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.779088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.779111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.781101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.781117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.781131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.781145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.782650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.782665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.782678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.784175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.784192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.785997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.788932] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.788958] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.788974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.788996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.805746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.805772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.805806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.805958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.806017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.822449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.822473] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.822518] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.841380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.841399] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.841418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.841435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.841452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.841467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.841481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.841497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.841515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.841531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.841547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.841563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.841577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.841590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.841623] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.841688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.841697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.841738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.841754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.841771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.841790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.841806] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.841822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.841838] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.841856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.841876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.841922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.841951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.841957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.841981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.841988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.842013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.842035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.842059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.842080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.842106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.842128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.842151] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.842172] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.842195] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.842222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.842251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.842617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.842639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.842661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.842681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.842702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.842723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.842746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.842769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.842793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.842812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.842832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.842854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.842877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.845013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.845029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.845043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.845058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.846563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.846578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.846592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.848088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.848104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.849923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.852844] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.852870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.852886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.852947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.869622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.869649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.869687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.869781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.869823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.886304] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.886327] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.886362] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.905226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.905245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.905265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.905282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.905300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.905316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.905331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.905347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.905365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.905381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.905397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.905412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.905427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.905445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.905482] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.905555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.905564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.905610] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.905629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.905649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.905671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.905690] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.905709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.905729] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.905748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.905767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.905786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.905804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.905808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.905826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.905830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.905849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.905869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.905888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.905950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.905977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.906004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.906035] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.906058] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.906078] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.906103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.906129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.906200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.906220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.906241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.906262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.906284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.906305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.906328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.906351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.906374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.906393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.906413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.906438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.906458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.908460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.908479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.908496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.908514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.910032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.910048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.910063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.911560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.911576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.913397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.916353] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.916381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.916401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.916425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.933177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.933203] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.933238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.933339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.933378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.949845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  347.949869] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.949952] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.968821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  347.968840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.968861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.968877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.968895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.968952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.968976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.969002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.969031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.969057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.969083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.969108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.969129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.969151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.969201] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.969315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.969329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.969387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.969403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.969421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.969440] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.969455] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.969479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.969494] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.969508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.969522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.969536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.969549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.969552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.969565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.969568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.969581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.969598] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.969616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.969633] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.969651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.969668] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.969685] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.969703] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.969720] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.969739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.969758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.969807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.969825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.969843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.969861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.969878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.969895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.969941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.969971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.969996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.970018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.970040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.970067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.970089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.972085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.972101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.972115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.972129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.973637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.973652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.973666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.975167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.975182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.976993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.979926] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.979952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.979968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.979990] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.996745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.996772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.996809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.996963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.997024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.013444] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.013468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.013513] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.032395] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.032414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.032434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.032451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.032468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.032483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.032498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.032513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.032531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.032547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.032563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.032579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.032593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.032607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.032638] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.032711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.032719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.032761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.032776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.032794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.032814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.032829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.032846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.032862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.032877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.032892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.032951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.032973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.032980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.033008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.033013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.033033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.033053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.033073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.033092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.033113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.033133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.033153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.033172] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.033191] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.033214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.033237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.033307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.033329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.033349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.033370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.033386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.033399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.033418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.033434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.033449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.033461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.033474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.033490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.033505] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.035494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.035511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.035525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.035540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.037060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.037075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.037089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.038582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.038598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.040404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.043361] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.043387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.043404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.043426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.060149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.060174] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.060207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.060297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.060335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.076856] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.076880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.076963] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.095844] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.095862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.095882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.095899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.095959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.095981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.095997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.096013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.096034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.096055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.096077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.096098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.096118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.096138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.096174] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.096249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.096258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.096305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.096325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.096345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.096368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.096394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.096412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.096429] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.096444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.096459] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.096472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.096485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.096489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.096501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.096504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.096518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.096531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.096544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.096557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.096573] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.096586] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.096600] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.096613] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.096625] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.096640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.096658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.096704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.096718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.096732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.096745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.096758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.096772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.096787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.096801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.096815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.096828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.096841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.096857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.096871] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.098864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.098880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.098894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.098941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.100510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.100525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.100539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.102040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.102056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.103860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.106783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.106808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.106825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.106847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.123559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.123585] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.123623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.123723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.123765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.140260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.140286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.140332] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.158529] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.158548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.158568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.158584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.158601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.158616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.158631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.158646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.158664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.158680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.158696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.158711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.158725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.158739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.158771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.158843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.158851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.158893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.158912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.158975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.159004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.159027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.159053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.159076] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.159100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.159122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.159144] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.159167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.159173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.159195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.159201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.159225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.159246] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.159267] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.159288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.159315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.159335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.159349] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.159363] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.159377] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.159393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.159411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.159462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.159477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.159493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.159507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.159522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.159536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.159553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.159569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.159585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.159599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.159614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.159631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.159647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.161629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.161647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.161664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.161683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.163194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.163211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.163225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.164718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.164735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.166544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.169482] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.169509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.169525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.169547] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.186295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.186321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.186356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.186454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.186493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.202989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.203013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.203058] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.221910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.221947] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.221967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.221984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.222001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.222016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.222030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.222046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.222064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.222080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.222100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.222120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.222139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.222158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.222195] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.222272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.222280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.222333] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.222350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.222368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.222387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.222402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.222418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.222434] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.222449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.222464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.222478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.222491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.222495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.222508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.222512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.222526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.222539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.222552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.222565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.222580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.222598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.222617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.222636] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.222654] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.222673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.222693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.222746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.222765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.222784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.222803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.222822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.222840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.222860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.222880] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.222900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.222945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.222970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.222998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.223021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.225017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.225034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.225050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.225068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.226574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.226590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.226604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.228102] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.228120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.229941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.232877] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.232904] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.232959] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.232996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.249688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.249712] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.249746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.249837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.249875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.266393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.266417] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.266461] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.285342] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.285361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.285380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.285397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.285415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.285429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.285444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.285459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.285477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.285493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.285513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.285534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.285553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.285571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.285608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.285674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.285683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.285728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.285748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.285768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.285790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.285809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.285828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.285847] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.285867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.285886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.285905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.285963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.285972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.285998] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.286004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.286031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.286054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.286078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.286100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.286126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.286148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.286172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.286194] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.286218] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.286246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.286274] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.286614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.286644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.286666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.286686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.286707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.286727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.286750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.286774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.286797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.286816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.286836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.286859] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.286881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.288888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.288904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.288949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.288976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.290557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.290573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.290587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.292084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.292100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.293903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.296844] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.296869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.296885] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.296906] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.313614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.313640] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.313675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.313772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.313812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.330315] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.330340] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.330385] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.349269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.349288] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.349308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.349325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.349342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.349357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.349372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.349387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.349408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.349429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.349449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.349469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.349488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.349507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.349544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.349617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.349626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.349673] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.349692] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.349712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.349734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.349753] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.349773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.349792] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.349811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.349830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.349849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.349868] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.349872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.349890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.349894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.349913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.349977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.350003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.350036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.350059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.350081] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.350102] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.350124] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.350144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.350169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.350194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.350265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.350287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.350310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.350331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.350352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.350374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.350398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.350422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.350445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.350466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.350486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.350510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.350534] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.352537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.352555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.352572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.352590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.354106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.354124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.354142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.355639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.355656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.357463] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.360401] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.360429] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.360445] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.360468] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.377214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.377240] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.377274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.377373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.377412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.393914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.393957] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.394002] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.412881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.412900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.412920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.412977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.413078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.413095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.413110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.413126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.413144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.413160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.413176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.413191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.413206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.413219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.413251] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.413324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.413332] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.413374] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.413390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.413407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.413427] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.413442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.413458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.413475] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.413490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.413505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.413520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.413541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.413544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.413557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.413560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.413573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.413586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.413602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.413620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.413638] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.413655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.413672] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.413690] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.413707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.413725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.413744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.413793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.413811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.413829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.413847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.413864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.413881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.413900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.413919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.413967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.413990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.414011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.414034] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.414056] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.416049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.416065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.416080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.416098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.417603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.417618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.417632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.419128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.419144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.420948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.423884] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.423911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.423970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.423999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.440699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.440726] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.440763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.440865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.440907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.457399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.457423] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.457459] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.475686] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.475705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.475727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.475747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.475768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.475788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.475807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.475826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.475847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.475868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.475888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.475909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.475927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.475986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.476040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.476145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.476156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.476202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.476219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.476238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.476258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.476274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.476293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.476313] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.476333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.476353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.476373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.476392] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.476397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.476416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.476420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.476440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.476459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.476478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.476497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.476517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.476536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.476555] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.476575] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.476594] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.476614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.476636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.476690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.476710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.476730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.476751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.476770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.476790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.476811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.476831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.476853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.476872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.476892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.476912] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.476956] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.478965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.478982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.478996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.479011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.480523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.480539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.480552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.482055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.482071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.483876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.486811] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.486837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.486853] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.486875] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.503623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.503647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.503681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.503777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.503815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.520328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.520352] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.520388] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.539258] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.539277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.539297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.539314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.539335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.539355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.539374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.539393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.539415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.539435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.539456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.539476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.539495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.539514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.539550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.539625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.539634] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.539680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.539699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.539719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.539741] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.539759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.539779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.539798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.539818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.539837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.539856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.539874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.539878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.539897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.539900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.539920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.539983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.540008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.540031] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.540055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.540078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.540101] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.540123] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.540144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.540169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.540195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.540263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.540287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.540310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.540333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.540351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.540366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.540383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.540399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.540415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.540430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.540443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.540461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.540477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.542470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.542487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.542504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.542522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.544042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.544058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.544073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.545567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.545584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.547393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.550341] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.550368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.550384] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.550406] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.567152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.567179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.567216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.567311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.567353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.583842] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.583866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.583903] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.602462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.602483] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.602505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.602524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.602546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.602565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.602584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.602603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.602625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.602645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.602665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.602685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.602704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.602723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.602759] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.602834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.602843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.602889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.602909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.602928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.602986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.603012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.603038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.603069] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.603091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.603112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.603133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.603152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.603159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.603178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.603184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.603204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.603223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.603243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.603261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.603284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.603303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.603324] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.603344] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.603364] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.603387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.603412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.603460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.603474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.603488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.603501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.603514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.603531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.603551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.603570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.603589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.603606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.603623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.603641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.603659] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.605654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.605672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.605689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.605707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.607218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.607235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.607249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.608743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.608759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.610569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.613506] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.613534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.613550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.613572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.630320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.630345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.630380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.630481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.630521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.647021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.647047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.647085] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.665475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.665493] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.665513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.665529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.665547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.665562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.665577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.665592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.665610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.665626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.665642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.665658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.665672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.665686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.665718] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.665782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.665791] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.665832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.665847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.665864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.665883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.665898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.665914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.665930] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.665988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.666011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.666034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.666055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.666062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.666083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.666089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.666112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.666133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.666155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.666177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.666201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.666223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.666245] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.666266] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.666287] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.666313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.666338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.666608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.666624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.666639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.666652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.666666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.666680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.666696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.666711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.666725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.666738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.666751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.666767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.666782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.668754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.668769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.668783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.668798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.670305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.670319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.670333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.671827] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.671842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.673648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.676585] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.676612] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.676628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.676650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.693398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.693425] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.693463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.693554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.693596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.710094] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.710117] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.710152] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.729028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.729047] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.729066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.729083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.729101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.729115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.729130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.729145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.729163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.729179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.729194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.729210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.729228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.729248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.729284] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.729359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.729367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.729414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.729433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.729453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.729475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.729494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.729513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.729533] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.729552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.729571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.729590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.729608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.729612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.729631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.729634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.729654] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.729673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.729692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.729711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.729730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.729749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.729768] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.729787] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.729806] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.729825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.729846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.729900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.729920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.729939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.729996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.730028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.730050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.730074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.730097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.730120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.730139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.730159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.730183] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.730204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.732195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.732211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.732225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.732243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.733748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.733763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.733777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.735274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.735292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.737098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.740048] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.740075] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.740091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.740113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.756845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.756869] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.756903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.757062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.757109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.773542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.773565] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.773609] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.792460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.792478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.792499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.792515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.792533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.792548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.792562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.792579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.792596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.792612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.792628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.792644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.792658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.792671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.792703] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.792775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.792783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.792825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.792840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.792858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.792879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.792898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.792918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.792937] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.792999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.793023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.793045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.793067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.793074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.793095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.793101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.793123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.793144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.793166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.793187] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.793212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.793233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.793254] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.793275] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.793296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.793321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.793348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.793428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.793449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.793470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.793486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.793499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.793513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.793529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.793544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.793558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.793570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.793582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.793598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.793613] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.795597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.795614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.795631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.795649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.797159] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.797175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.797189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.798682] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.798698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.800505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.803441] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.803468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.803485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.803507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.820255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.820281] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.820316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.820431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.820478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.836950] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.836992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.837029] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.855904] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.855923] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.855943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.855999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.856082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.856098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.856117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.856136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.856159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.856180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.856201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.856222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.856241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.856261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.856298] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.856366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.856374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.856421] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.856441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.856461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.856484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.856503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.856523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.856542] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.856561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.856581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.856600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.856619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.856623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.856642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.856646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.856666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.856685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.856705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.856724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.856744] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.856762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.856782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.856808] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.856824] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.856841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.856859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.856906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.856924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.856942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.856980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.857002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.857024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.857048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.857070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.857093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.857112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.857132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.857155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.857176] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.859168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.859184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.859198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.859212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.860715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.860730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.860744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.862240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.862255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.864060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.866998] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.867031] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.867046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.867067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.883811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.883837] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.883872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.884006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.884065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.900511] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.900535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.900571] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.919437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.919458] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.919480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.919499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.919521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.919540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.919559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.919578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.919600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.919620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.919640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.919661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.919680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.919698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.919735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.919810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.919818] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.919864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.919884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.919904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.919926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.919945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.920007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.920034] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.920060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.920084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.920109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.920131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.920138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.920161] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.920167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.920191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.920213] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.920242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.920262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.920287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.920307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.920328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.920348] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.920370] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.920394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.920420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.920752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.920774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.920796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.920817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.920837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.920858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.920883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.920906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.920929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.920948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.920986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.921010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.921033] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.923163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.923179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.923193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.923208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.924712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.924727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.924741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.926238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.926254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.928059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.931010] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.931037] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.931054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.931076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  348.947805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.947830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.947864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.948003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.948063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.964510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  348.964534] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  348.964570] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.983445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  348.983464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  348.983483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.983500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.983518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.983533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.983547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.983563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  348.983581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.983597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.983613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.983629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.983643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.983657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.983689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  348.983761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  348.983769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  348.983810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  348.983826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  348.983843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  348.983862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.983878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.983894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.983910] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  348.983926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.983941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.983955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  348.984013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.984021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.984044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.984051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  348.984075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  348.984097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.984120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.984141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.984167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  348.984188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.984212] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  348.984233] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  348.984256] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  348.984283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.984312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  348.984389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  348.984413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  348.984435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  348.984457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  348.984478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  348.984501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  348.984527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  348.984551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  348.984576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  348.984597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  348.984624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  348.984646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  348.984669] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  348.986666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.986682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.986696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.986711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.988219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  348.988234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  348.988248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.989742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.989757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.991565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.994490] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.994516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  348.994532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  348.994554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.011264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.011290] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.011325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.011424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.011463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.027936] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.027958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.028129] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.046729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.046748] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.046768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.046785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.046802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.046818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.046832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.046848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.046866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.046886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.046907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.046927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.046946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.046964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.047049] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.047168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.047182] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.047252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.047276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.047303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.047331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.047354] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.047379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.047403] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.047428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.047450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.047472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.047493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.047499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.047520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.047525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.047548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.047569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.047591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.047612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.047636] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.047657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.047679] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.047700] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.047721] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.047744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.047770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.047846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.047868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.047891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.047912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.047934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.047956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.048003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.048030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.048056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.048083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.048105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.048131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.048152] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.050142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.050158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.050172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.050188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.051694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.051710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.051724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.053220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.053236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.055040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.057962] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.058003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.058019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.058040] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.074791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.074818] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.074855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.074946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.075041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.091491] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.091516] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.091552] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.110446] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.110465] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.110485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.110502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.110519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.110534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.110549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.110565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.110593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.110620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.110637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.110653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.110667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.110681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.110713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.110783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.110792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.110833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.110849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.110866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.110885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.110902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.110922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.110941] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.110960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.111022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.111047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.111072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.111079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.111103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.111109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.111134] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.111157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.111180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.111202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.111228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.111250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.111273] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.111295] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.111318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.111346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.111374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.111457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.111478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.111499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.111518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.111538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.111558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.111581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.111604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.111626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.111645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.111665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.111687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.111709] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.114799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.114818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.114837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.114857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.116372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.116389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.116403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.117910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.117926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.119735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.122660] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.122692] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.122709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.122732] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.139435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.139460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.139495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.139593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.139632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.156115] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.156140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.156183] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.175018] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.175037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.175057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.175074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.175092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.175107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.175122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.175138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.175156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.175172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.175188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.175203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.175217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.175231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.175263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.175334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.175342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.175384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.175399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.175417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.175436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.175451] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.175467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.175483] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.175498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.175514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.175528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.175542] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.175545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.175559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.175562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.175577] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.175590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.175604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.175622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.175641] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.175660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.175679] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.175698] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.175717] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.175737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.175758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.175812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.175832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.175851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.175870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.175890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.175908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.175929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.175949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.175969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.176037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.176061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.176088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.176110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.178103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.178119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.178134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.178148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.179652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.179670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.179687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.181186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.181204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.183011] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.185946] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.185973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.186028] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.186066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.202761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.202787] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.202822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.202919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.202958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.219462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.219486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.219531] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.238408] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.238427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.238447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.238463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.238480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.238495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.238509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.238525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.238542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.238558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.238574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.238589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.238603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.238617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.238650] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.238724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.238732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.238774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.238790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.238807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.238827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.238846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.238866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.238885] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.238904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.238923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.238942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.238961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.238991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.239018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.239027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.239054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.239080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.239105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.239130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.239156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.239180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.239204] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.239228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.239253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.239278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.239306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.239389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.239409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.239431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.239451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.239472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.239492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.239515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.239538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.239560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.239578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.239598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.239620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.239642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.241639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.241655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.241669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.241683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.243189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.243204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.243217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.244707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.244724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.246530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.249449] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.249474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.249493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.249525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.266230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.266256] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.266291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.266382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.266421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.282906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.282928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.282961] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.301829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.301848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.301867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.301884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.301901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.301916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.301931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.301947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.301965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.302023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.302050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.302068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.302083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.302097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.302129] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.302195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.302203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.302245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.302261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.302278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.302298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.302314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.302331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.302348] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.302363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.302379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.302393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.302408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.302412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.302426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.302430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.302445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.302459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.302474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.302487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.302505] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.302519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.302533] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.302552] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.302572] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.302592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.302613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.302668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.302688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.302708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.302728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.302747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.302768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.302794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.302811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.302827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.302841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.302855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.302871] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.302887] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.304856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.304872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.304886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.304903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.306412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.306427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.306441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.307933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.307949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.309753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.312671] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.312697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.312713] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.312734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.329452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.329478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.329514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.329610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.329649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.346153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.346179] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.346225] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.365105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.365124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.365144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.365161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.365178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.365193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.365207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.365226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.365247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.365268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.365289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.365309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.365328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.365346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.365383] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.365457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.365466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.365512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.365531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.365551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.365573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.365592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.365611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.365630] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.365649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.365669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.365688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.365706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.365710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.365728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.365732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.365751] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.365770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.365790] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.365808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.365828] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.365846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.365865] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.365884] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.365903] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.365923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.365944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.366035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.366060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.366084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.366107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.366129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.366153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.366178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.366203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.366227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.366249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.366278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.366301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.366322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.368315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.368330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.368344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.368359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.369863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.369881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.369898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.371396] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.371412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.373216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.376153] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.376178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.376194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.376216] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.392954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.392976] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.393047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.393142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.393179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.409667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.409691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.409736] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.428591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.428610] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.428630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.428647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.428664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.428679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.428693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.428709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.428727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.428743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.428759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.428774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.428788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.428802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.428835] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.428912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.428921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.428963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.428978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.429036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.429064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.429087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.429113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.429136] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.429159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.429182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.429203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.429225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.429232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.429252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.429258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.429282] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.429460] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.429479] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.429498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.429518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.429537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.429556] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.429576] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.429595] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.429623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.429642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.429692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.429707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.429721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.429735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.429749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.429764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.429780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.429795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.429809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.429826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.429845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.429863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.429882] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.431854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.431870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.431887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.431905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.433414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.433432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.433449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.434945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.434962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.436801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.439737] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.439764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.439781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.439810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.456552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.456578] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.456613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.456714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.456754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.473251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.473277] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.473324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.492204] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.492222] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.492242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.492259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.492276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.492292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.492306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.492322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.492339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.492356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.492371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.492387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.492401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.492415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.492447] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.492512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.492520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.492562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.492577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.492595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.492614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.492630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.492646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.492663] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.492678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.492693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.492708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.492726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.492730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.492749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.492752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.492772] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.492791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.492810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.492829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.492848] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.492867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.492886] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.492905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.492924] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.492944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.492965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.493072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.493094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.493116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.493137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.493157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.493178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.493202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.493225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.493249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.493471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.493488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.493508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.493525] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.495523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.495539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.495554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.495568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.497084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.497099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.497112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.498605] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.498621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.500428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.503364] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.503391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.503410] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.503434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.520178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.520204] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.520239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.520336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.520376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.536878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.536903] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.536948] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.555780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.555799] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.555819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.555836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.555853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.555868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.555883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.555899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.555917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.555933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.555949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.555964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.555979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.556036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.556088] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.556177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.556186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.556229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.556245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.556264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.556284] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.556299] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.556317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.556334] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  349.556350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.556365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.556380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.556394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.556398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.556412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.556415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.556430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.556444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.556459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.556472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.556496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.556509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.556522] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  349.556535] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  349.556548] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  349.556566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.556586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  349.556636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.556654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.556672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.556690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.556708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.556726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.556746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.556766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.556784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.556803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.556820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.556839] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  349.556856] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.558832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.558849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.558865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.558883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.560393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.560409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.560423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.561942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.561958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.563768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.566700] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.566724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.566740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  349.566762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.583518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.583544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.583579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.583675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.583715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.600199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  349.600222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.600257] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.619121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  349.619140] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.619160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.619176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.619193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.619208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.619222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.619238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.619255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.619271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.619287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.619303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.619317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.619331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.619362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  349.621688] [IGT] kms_flip: exiting, ret=0
>[  349.645423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.645442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.645462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.645483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.645499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.645517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.645535] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  349.645551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  349.645567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.645582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.645600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.645605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.645624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.645628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.645648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.645667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.645687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.645707] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  349.645727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.645746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.645766] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  349.645786] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  349.645805] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  349.645826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.645848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  349.645915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.645936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.645956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.645976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.645995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.646037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.646060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.646081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.646102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.646122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.646141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.646163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  349.646182] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.648177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.648193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.648207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.648221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.649731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.649745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.649758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.651256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.651270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.653081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.656109] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  349.656138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.656154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  349.656177] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.656231] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  349.656255] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  349.672896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.672920] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.672957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.673102] Console: switching to colour frame buffer device 240x75
>[  349.803797] Console: switching to colour dummy device 80x25
>[  349.803890] [IGT] kms_flip: executing
>[  349.815222] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  349.815252] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  349.817073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  349.817093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  349.819068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  349.819074] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  349.821066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  349.821087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  349.823066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  349.823072] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  349.823076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  349.823091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  349.823113] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  349.824150] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  349.825063] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  349.825086] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  349.825109] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  349.825129] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  349.826120] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  349.826136] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  349.827209] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  349.827212] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  349.827290] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  349.827292] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  349.827296] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  349.827298] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  349.827302] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  349.827304] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  349.827311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  349.827314] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.827317] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.827319] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.827322] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  349.827324] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  349.827327] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  349.827329] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  349.827332] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.827334] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  349.827337] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  349.827339] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  349.827341] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  349.827344] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  349.827346] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  349.827349] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  349.827351] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  349.827354] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  349.827356] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  349.827358] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  349.827361] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  349.827363] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  349.827366] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  349.827368] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  349.827371] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  349.827373] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  349.827375] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  349.827378] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  349.827380] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  349.827383] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  349.827385] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  349.827414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  349.827433] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  349.829057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  349.829077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  349.831066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  349.831071] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  349.833065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  349.833084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  349.835072] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  349.835077] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  349.835081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  349.835292] [IGT] kms_flip: starting subtest basic-flip-vs-wf_vblank
>[  349.835696] [drm:drm_mode_addfb2] [FB:76]
>[  349.835718] [drm:drm_mode_addfb2] [FB:79]
>[  349.877834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  349.877886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.889743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  349.889767] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  349.889806] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  349.908684] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  349.908707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  349.908727] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  349.908749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.908769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.908790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.908810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.908829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.908848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.908870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.908890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.908910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.908931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.908949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.908968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.909006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.909108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  349.909213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  349.909306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  349.909321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  349.909391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  349.909418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.909446] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  349.909476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.909500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.909527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.909553] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  349.909578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  349.909603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.909627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  349.909650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.909656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.909679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.909685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  349.909708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  349.909732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.909754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.909777] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  349.909801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  349.909824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.909847] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  349.909870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  349.909890] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  349.909915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.909943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  349.912497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  349.912513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  349.912528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  349.912542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  349.912555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  349.912569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  349.912585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  349.912600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  349.912615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  349.912628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  349.912640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  349.912657] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  349.912671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  349.914657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.914674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.914689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.914704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.916216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  349.916233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  349.916251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.917749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.917766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.919579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.922504] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  349.922530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  349.922547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  349.922568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  349.922607] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  349.922624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  349.939289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  349.939314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  349.939348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.576371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.592749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.592912] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  353.593767] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.610644] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.610697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  353.610721] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  353.610745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.610762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  353.610781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  353.610796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  353.610815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  353.610835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  353.610857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  353.610876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  353.610897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  353.610917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.610936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  353.610956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  353.611010] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.611215] [drm:drm_mode_addfb2] [FB:76]
>[  353.611292] [drm:drm_mode_addfb2] [FB:78]
>[  353.636962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  353.637046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  353.637102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  353.637156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  353.637165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  353.637214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  353.637234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.637290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  353.637322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  353.637344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  353.637368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.637392] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  353.637416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  353.637438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  353.637460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.637479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.637486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  353.637505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.637510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  353.637531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  353.637550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  353.637571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.637590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.637613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  353.637632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.637652] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  353.637672] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  353.637692] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  353.637713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.637738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  353.640292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.640311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  353.640327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  353.640346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  353.640365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  353.640384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  353.640404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  353.640424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  353.640444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.640462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  353.640480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  353.640501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  353.640519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  353.642508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.642525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.642539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.642554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.644062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  353.644077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.644091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.645591] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.645608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  353.647418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.650360] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  353.650389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  353.650406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  353.650428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.667177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  353.667202] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  353.667237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  357.304201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.304369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.304458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  357.304820] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.321750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  357.321771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  357.321794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.321812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  357.321831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  357.321847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  357.321863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  357.321879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  357.321899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  357.321917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  357.321938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  357.321960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  357.321981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  357.322001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  357.322042] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  357.322248] [drm:drm_mode_addfb2] [FB:76]
>[  357.322273] [drm:drm_mode_addfb2] [FB:78]
>[  357.345859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  357.345943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  357.345998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  357.346050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  357.346060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  357.346109] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  357.346126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.346143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  357.346162] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  357.346177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  357.346193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.346209] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  357.346223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.346238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  357.346255] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.346272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.346276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  357.346293] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.346297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  357.346315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  357.346333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  357.346350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.346367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.346385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  357.346402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.346420] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  357.346437] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  357.346455] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  357.346507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.346535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  357.349169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  357.349189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  357.349208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  357.349227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  357.349246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  357.349265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  357.349285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  357.349305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  357.349325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  357.349343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  357.349361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  357.349382] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  357.349400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  357.351412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.351429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.351444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.351459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.353000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  357.353016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.353030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.354533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.354549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  357.356352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.359289] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.359318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  357.359334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.359357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.376102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  357.376127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  357.376161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.012860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.012938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  361.012982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.013051] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  361.029910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  361.029930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  361.029950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.029967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  361.029985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  361.030000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  361.030015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  361.030031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  361.030052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  361.030072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  361.030090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  361.030111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.030130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  361.030148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  361.030188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  361.032539] [IGT] kms_flip: exiting, ret=0
>[  361.056154] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  361.056173] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.056193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  361.056214] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  361.056230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  361.056248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.056267] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.056287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.056307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  361.056327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.056346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.056351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  361.056370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.056373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  361.056393] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  361.056412] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  361.056432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.056452] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  361.056472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  361.056491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.056510] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  361.056530] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  361.056549] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  361.056570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.056592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  361.056658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.056678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  361.056711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  361.056731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  361.056751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  361.056771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  361.056793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  361.056815] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  361.056836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.056855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  361.056875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  361.056895] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  361.056915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  361.058927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.058943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.058957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.058972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.060486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  361.060499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  361.060512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.062015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.062029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  361.063843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.066873] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.066902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  361.066918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  361.066941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.066987] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.067003] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.083650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  361.083675] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.083731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.083855] Console: switching to colour frame buffer device 240x75
>[  361.392201] Console: switching to colour dummy device 80x25
>[  361.392294] [IGT] kms_flip: executing
>[  361.406996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  361.407026] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  361.408801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  361.408822] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  361.410762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  361.410770] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  361.412767] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  361.412787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  361.414763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  361.414769] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  361.414774] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  361.414790] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  361.414812] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  361.415843] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  361.416753] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  361.416778] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  361.416802] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  361.416819] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  361.417808] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  361.417831] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  361.418892] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  361.418895] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  361.418977] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  361.418979] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  361.418983] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  361.418985] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  361.418989] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  361.418991] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  361.418998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  361.419001] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  361.419003] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.419006] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.419008] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  361.419011] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  361.419013] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  361.419016] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  361.419018] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.419021] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.419023] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  361.419026] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  361.419028] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  361.419030] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  361.419033] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  361.419035] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  361.419038] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  361.419040] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  361.419043] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  361.419045] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  361.419047] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  361.419050] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  361.419052] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  361.419055] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  361.419057] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  361.419059] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  361.419062] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  361.419064] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  361.419067] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  361.419069] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  361.419071] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  361.419102] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  361.419120] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  361.420757] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  361.420776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  361.422755] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  361.422761] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  361.424762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  361.424784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  361.426767] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  361.426772] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  361.426776] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  361.426981] [IGT] kms_flip: starting subtest basic-plain-flip
>[  361.427385] [drm:drm_mode_addfb2] [FB:58]
>[  361.427408] [drm:drm_mode_addfb2] [FB:79]
>[  361.469682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  361.469776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.484008] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  361.484037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.484080] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.502951] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.502975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  361.502993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  361.503015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.503032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  361.503052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  361.503068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  361.503084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  361.503103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  361.503126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  361.503147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  361.503168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  361.503188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.503208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  361.503227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  361.503266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.503320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  361.503397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  361.503465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  361.503475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  361.503521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  361.503541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  361.503561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  361.503583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  361.503600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  361.503620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.503639] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  361.503658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.503677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  361.503696] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  361.503749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.503758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  361.503785] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.503793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  361.503819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  361.503844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  361.503870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.503894] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  361.503928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  361.503950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.503973] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  361.503995] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  361.504017] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  361.504043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.504069] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  361.506600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  361.506617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  361.506631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  361.506645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  361.506658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  361.506672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  361.506688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  361.506703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  361.506745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  361.506770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  361.506790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  361.506816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  361.506837] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  361.508834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.508850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.508865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.508879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.510383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  361.510401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  361.510418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.511917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.511934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  361.513743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.516680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.516707] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  361.516762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  361.516801] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.516959] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.516977] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.533498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  361.533523] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  361.533558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.886636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.903204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  364.903232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  364.903275] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.921894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.921918] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  364.921980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  364.922012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.922038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  364.922068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  364.922085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  364.922101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  364.922118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  364.922136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  364.922153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  364.922170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  364.922186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.922201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  364.922215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  364.922249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.922431] [drm:drm_mode_addfb2] [FB:58]
>[  364.922452] [drm:drm_mode_addfb2] [FB:78]
>[  364.945546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  364.945634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  364.945691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  364.945747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  364.945755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  364.945806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  364.945828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.945850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  364.945873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  364.945893] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  364.945915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.945969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  364.945995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.946018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  364.946042] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.946065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.946072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.946093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.946099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.946121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  364.946144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  364.946167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.946189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.946211] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  364.946232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.946256] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  364.946278] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  364.946300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  364.946324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.946351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  364.948878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.948894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  364.948909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  364.948949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  364.948972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  364.948997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  364.949023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  364.949046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  364.949070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.949091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  364.949112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  364.949138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  364.949160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  364.951157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.951173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.951187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.951201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.952708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  364.952726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  364.952743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.954241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.954258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  364.956064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.959006] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  364.959034] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  364.959058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  364.959078] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.975818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  364.975844] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  364.975879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  368.328961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.329042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  368.329088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  368.329236] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  368.346069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  368.346089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  368.346111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.346174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  368.346206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  368.346231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  368.346255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  368.346282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  368.346312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  368.346338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  368.346364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  368.346389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  368.346412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  368.346436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  368.346488] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  368.346723] [drm:drm_mode_addfb2] [FB:58]
>[  368.346747] [drm:drm_mode_addfb2] [FB:78]
>[  368.369846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  368.369930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  368.369987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  368.370040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  368.370050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  368.370101] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  368.370120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.370173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  368.370200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  368.370223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  368.370246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.370270] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  368.370293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  368.370315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  368.370333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.370350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.370355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  368.370372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.370376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  368.370394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  368.370412] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  368.370430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.370448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.370466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  368.370483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.370501] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  368.370518] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  368.370536] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  368.370555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.370576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  368.373184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  368.373201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  368.373216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  368.373230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  368.373244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  368.373259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  368.373278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  368.373297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  368.373315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  368.373333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  368.373350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  368.373369] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  368.373387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  368.375370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  368.375386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.375401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.375416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.376922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  368.376937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  368.376950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.378453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.378469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  368.380277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.383220] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  368.383249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  368.383266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  368.383289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  368.400037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  368.400063] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  368.400098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  371.753180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.753253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  371.753291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  371.753425] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  371.770254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  371.770273] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  371.770293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.770310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  371.770328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  371.770391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  371.770416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  371.770442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  371.770471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  371.770498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  371.770519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  371.770536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  371.770550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  371.770565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  371.770599] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  371.772961] [IGT] kms_flip: exiting, ret=0
>[  371.800774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  371.800793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.800815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  371.800838] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  371.800858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  371.800879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.800899] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  371.800918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  371.800935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  371.800954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  371.800973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.800978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  371.800997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.801000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  371.801020] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  371.801040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  371.801060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.801079] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  371.801099] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  371.801118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.801138] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  371.801158] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  371.801177] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  371.801198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  371.801220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  371.801286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  371.801306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  371.801326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  371.801358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  371.801378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  371.801398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  371.801421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  371.801442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  371.801463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  371.801483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  371.801502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  371.801524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  371.801543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  371.803540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  371.803556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  371.803571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.803589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  371.805104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  371.805118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  371.805131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.806633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  371.806647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  371.808460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  371.811494] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  371.811523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  371.811541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  371.811568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  371.811616] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  371.811635] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  371.828325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  371.828369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  371.828409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  371.828543] Console: switching to colour frame buffer device 240x75
>[  372.167181] Console: switching to colour dummy device 80x25
>[  372.167268] [IGT] kms_force_connector_basic: executing
>[  372.179669] [IGT] kms_force_connector_basic: exiting, ret=77
>[  372.212085] Console: switching to colour frame buffer device 240x75
>[  372.342427] Console: switching to colour dummy device 80x25
>[  372.342513] [IGT] kms_force_connector_basic: executing
>[  372.354608] [IGT] kms_force_connector_basic: exiting, ret=77
>[  372.378926] Console: switching to colour frame buffer device 240x75
>[  372.507186] Console: switching to colour dummy device 80x25
>[  372.507269] [IGT] kms_force_connector_basic: executing
>[  372.517675] [IGT] kms_force_connector_basic: exiting, ret=77
>[  372.545715] Console: switching to colour frame buffer device 240x75
>[  372.673360] Console: switching to colour dummy device 80x25
>[  372.673501] [IGT] kms_force_connector_basic: executing
>[  372.684627] [IGT] kms_force_connector_basic: exiting, ret=77
>[  372.712542] Console: switching to colour frame buffer device 240x75
>[  372.849796] Console: switching to colour dummy device 80x25
>[  372.849879] [IGT] kms_frontbuffer_tracking: executing
>[  372.864261] [drm:drm_mode_addfb2] [FB:58]
>[  372.864350] [drm:drm_mode_addfb2] [FB:79]
>[  372.864595] [drm:drm_mode_addfb2] [FB:80]
>[  372.866473] [drm:drm_mode_addfb2] [FB:81]
>[  372.877553] [drm:drm_mode_addfb2] [FB:82]
>[  372.877979] [IGT] kms_frontbuffer_tracking: starting subtest basic
>[  372.882019] [drm:drm_mode_addfb2] [FB:58]
>[  372.882114] [drm:drm_mode_addfb2] [FB:79]
>[  372.882208] [drm:drm_mode_addfb2] [FB:80]
>[  372.884335] [drm:drm_mode_addfb2] [FB:81]
>[  372.903924] [drm:drm_mode_addfb2] [FB:82]
>[  372.903960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  372.904032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.912618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  372.912648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  372.912698] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  372.931567] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  372.931591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  372.931609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  372.931631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.931649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  372.931668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  372.931686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  372.931706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  372.931727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  372.931749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  372.931771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  372.931792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  372.931813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  372.931833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  372.931852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  372.931892] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  372.931956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  372.932039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  372.936449] [drm:drm_mode_addfb2] [FB:78]
>[  372.938937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  372.938946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  372.938991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  372.939009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.939028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  372.939048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  372.939066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  372.939084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.939102] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  372.939119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  372.939137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  372.939154] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.939171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.939175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  372.939192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.939195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  372.939213] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  372.939230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  372.939248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.939265] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  372.939283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  372.939300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.939317] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  372.939335] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  372.939352] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  372.939371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.939390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  372.941929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  372.941948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  372.941966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  372.941984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  372.942001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  372.942018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  372.942037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  372.942056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  372.942075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  372.942092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  372.942109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  372.942128] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  372.942145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  372.944144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  372.944161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.944178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.944196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.945708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  372.945725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  372.945739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.947233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.947249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  372.949055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.951989] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  372.952017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  372.952034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  372.952056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  372.952108] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  372.952133] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  372.968834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  372.968860] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  372.968898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.019092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.019138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.035529] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  373.035556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.035604] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  373.054463] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  373.054486] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  373.054503] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  373.054522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.054538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  373.054556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  373.054572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  373.054587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  373.054603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  373.054621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  373.054638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  373.054654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  373.054670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.054684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  373.054702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  373.054740] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  373.054796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  373.054875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  373.059262] [drm:drm_mode_addfb2] [FB:78]
>[  373.063220] [drm:drm_mode_addfb2] [FB:83]
>[  373.068301] [drm:drm_mode_addfb2] [FB:96]
>[  373.072261] [drm:drm_mode_addfb2] [FB:97]
>[  373.201289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.201301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  373.201356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  373.201372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.201390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  373.201408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  373.201454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  373.201479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.201506] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  373.201531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  373.201555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  373.201578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.201600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.201606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  373.201627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.201633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  373.201655] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  373.201677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  373.201699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.201721] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  373.201743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  373.201764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.201783] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  373.201804] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  373.201825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  373.201850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.201876] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  373.204514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.204530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  373.204545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  373.204558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  373.204572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  373.204586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  373.204602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  373.204617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  373.204632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.204645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  373.204658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  373.204674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  373.204689] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  373.206684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.206701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.206715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.206733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.208239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  373.208255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  373.208269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.209765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.209780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  373.211587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.214537] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  373.214566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  373.214582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  373.214605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.214658] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  373.214683] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  373.231364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  373.231388] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  373.231463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.281485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.281501] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  373.348139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.348149] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  373.414897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.414906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  373.481654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.481723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.498275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  373.498313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  373.498379] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  373.517203] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  373.517226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  373.517242] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  373.517262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.517278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  373.517296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  373.517311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  373.517327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  373.517342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  373.517360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  373.517376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  373.517392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  373.517407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.517421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  373.517476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  373.517527] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  373.517611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  373.517726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  373.518310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  373.518318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  373.518361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  373.518377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.518395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  373.518413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  373.518429] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  373.518480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.518509] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  373.518531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  373.518554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  373.518575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  373.518596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.518602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  373.518623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.518629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  373.518651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  373.518670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  373.518691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.518711] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  373.518734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  373.518753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.518774] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  373.518793] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  373.518813] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  373.518835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  373.518860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  373.522415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  373.522433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  373.522496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  373.522520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  373.522542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  373.522565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  373.522586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  373.522602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  373.522616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.522630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  373.522643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  373.522661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  373.522676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  373.524653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  373.524669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  373.524683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.524697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  373.526205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  373.526220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  373.526233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  373.527731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  373.527749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  373.529557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  373.532461] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  373.532488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  373.532503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  373.532523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  373.532564] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  373.532580] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  373.549276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  373.549302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  373.549339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  373.653410] [drm:drm_mode_addfb2] [FB:78]
>[  374.383432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.400018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  374.400044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  374.400093] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  374.418966] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  374.418989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  374.419006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  374.419026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.419042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  374.419060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  374.419075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  374.419090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  374.419106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  374.419124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  374.419141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  374.419157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  374.419172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.419186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  374.419200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  374.419235] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  374.419520] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  374.440909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  374.440936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.440954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  374.440973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  374.440988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  374.441004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.441020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  374.441037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  374.441055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  374.441072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.441090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.441095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.441112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.441116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.441133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  374.441151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  374.441168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.441185] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  374.441203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  374.441220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.441238] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  374.441256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  374.441273] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  374.441292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.441312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  374.441381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.441399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  374.441417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  374.441435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  374.441453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  374.441470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  374.441488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  374.441542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  374.441567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.441588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  374.441608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  374.441642] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  374.441673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  374.443729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.443747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.443761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.443777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.445281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  374.445297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  374.445311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.446807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.446824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  374.448629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.451601] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  374.451632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  374.451651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  374.451692] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.451932] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  374.451983] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  374.468392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  374.468418] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  374.468453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.485156] Console: switching to colour frame buffer device 240x75
>[  374.649284] Console: switching to colour dummy device 80x25
>[  374.649379] [IGT] kms_pipe_crc_basic: executing
>[  374.658740] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  374.658766] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  374.660838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.660858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.662932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.662938] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  374.664996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.665019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.667093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.667099] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.667103] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  374.667119] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  374.667142] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  374.668169] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  374.669057] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  374.669074] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  374.669088] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  374.669103] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  374.670098] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  374.670115] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  374.671173] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  374.671176] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  374.671253] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.671255] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.671259] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  374.671261] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  374.671265] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.671267] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.671274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  374.671277] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.671279] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.671282] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.671284] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.671287] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.671289] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.671292] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  374.671294] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.671296] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.671299] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.671301] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.671304] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.671306] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  374.671309] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.671311] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.671313] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  374.671316] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.671318] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.671321] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  374.671323] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  374.671325] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  374.671328] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  374.671330] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  374.671333] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  374.671335] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.671337] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.671340] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  374.671342] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.671345] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.671347] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  374.671377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  374.671395] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  374.673464] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.673482] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.674558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.674564] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  374.676561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.676580] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.678561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.678567] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.678571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  374.688386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  374.688405] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  374.690481] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.690503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.692612] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.692618] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  374.694687] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.694707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.696784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.696789] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.696793] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  374.697056] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  374.697077] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  374.698129] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  374.699024] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  374.699040] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  374.699054] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  374.699068] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  374.700082] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  374.700098] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  374.701152] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  374.701155] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  374.701235] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.701237] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.701241] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  374.701243] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  374.701247] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.701249] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.701256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  374.701259] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.701261] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.701264] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.701266] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.701269] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.701271] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.701274] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  374.701276] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.701279] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.701281] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.701284] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.701286] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.701288] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  374.701291] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.701293] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.701296] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  374.701298] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.701300] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.701303] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  374.701305] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  374.701308] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  374.701310] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  374.701313] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  374.701315] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  374.701317] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.701320] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.701322] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  374.701324] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.701327] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.701329] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  374.701643] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  374.701669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  374.703568] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.703587] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.705563] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.705568] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  374.707646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.707667] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.709740] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.709746] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.709750] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  374.710035] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-1
>[  374.710101] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  374.710179] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  374.735411] Console: switching to colour frame buffer device 240x75
>[  374.893769] Console: switching to colour dummy device 80x25
>[  374.893864] [IGT] kms_pipe_crc_basic: executing
>[  374.903768] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  374.903794] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  374.905579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.905598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.907578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.907585] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  374.909575] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.909597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.911577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.911583] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.911587] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  374.911602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  374.911624] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  374.912667] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  374.913567] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  374.913585] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  374.913600] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  374.913613] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  374.914608] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  374.914624] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  374.915714] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  374.915717] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  374.915794] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.915796] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.915800] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  374.915802] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  374.915806] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.915808] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.915815] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  374.915818] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.915820] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.915823] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.915825] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.915828] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.915830] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.915833] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  374.915835] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.915838] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.915840] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.915842] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.915845] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.915847] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  374.915850] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.915852] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.915854] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  374.915857] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.915859] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.915862] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  374.915864] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  374.915867] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  374.915869] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  374.915871] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  374.915874] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  374.915876] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.915879] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.915881] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  374.915883] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.915886] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.915888] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  374.915917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  374.915935] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  374.917559] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.917577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.919583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.919589] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  374.921576] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.921595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.923582] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.923588] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.923592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  374.933612] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  374.933631] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  374.935707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.935727] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.937803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  374.937808] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  374.939885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.939905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  374.941980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  374.941986] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.941990] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  374.942257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  374.942278] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  374.943301] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  374.944190] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  374.944207] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  374.944221] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  374.944235] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  374.945222] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  374.945237] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  374.946284] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  374.946286] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  374.946365] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.946367] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.946371] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  374.946373] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  374.946377] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  374.946379] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  374.946386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  374.946389] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.946391] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.946394] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.946396] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.946399] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  374.946401] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.946404] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  374.946406] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.946408] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  374.946411] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  374.946413] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.946416] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  374.946418] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  374.946420] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.946423] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  374.946425] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  374.946428] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.946430] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  374.946433] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  374.946435] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  374.946437] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  374.946440] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  374.946442] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  374.946445] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  374.946447] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.946449] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  374.946452] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  374.946454] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.946457] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  374.946459] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  374.946895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  374.946920] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  374.948577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.948598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.950577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  374.950583] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  374.952661] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.952682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  374.954749] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  374.954754] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  374.954758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  374.955044] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-3
>[  374.955107] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3
>[  374.955121] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  374.955189] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  374.968951] Console: switching to colour frame buffer device 240x75
>[  375.129223] Console: switching to colour dummy device 80x25
>[  375.129314] [IGT] kms_pipe_crc_basic: executing
>[  375.138804] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.138833] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.140601] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.140621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.142594] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.142601] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.144589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.144609] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.146590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.146596] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.146600] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.146616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.146640] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.147669] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.148580] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.148605] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.148628] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.148650] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.149638] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.149661] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.150719] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.150722] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.150799] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.150801] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.150805] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.150807] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.150810] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.150812] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.150819] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.150822] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.150825] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.150827] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.150830] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.150832] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.150835] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.150837] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.150840] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.150842] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.150844] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.150847] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.150849] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.150852] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.150854] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.150857] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.150859] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.150862] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.150864] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.150866] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.150869] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.150871] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.150874] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.150876] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.150879] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.150881] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.150883] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.150886] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.150888] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.150891] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.150893] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.150923] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.150941] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.152562] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.152578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.154595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.154600] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.156589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.156610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.158589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.158595] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.158599] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.168378] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.168397] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.169590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.169610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.171685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.171691] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.173759] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.173777] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.175844] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.175849] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.175853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.176113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.176133] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.177154] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.178051] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.178068] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.178082] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.178096] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.179113] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.179130] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.180184] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.180187] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.180266] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.180268] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.180272] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.180274] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.180278] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.180280] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.180287] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.180290] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.180292] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.180295] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.180297] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.180300] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.180302] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.180305] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.180307] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.180310] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.180312] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.180314] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.180317] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.180319] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.180322] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.180324] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.180326] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.180329] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.180331] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.180334] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.180336] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.180338] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.180341] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.180343] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.180346] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.180348] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.180351] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.180353] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.180355] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.180358] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.180360] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.180659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.180683] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.182591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.182611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.184590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.184596] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.186673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.186693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.188769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.188774] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.188778] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.189061] [IGT] kms_pipe_crc_basic: starting subtest bad-pipe
>[  375.189125] [drm:display_crc_ctl_write [i915]] unknown pipe D
>[  375.189180] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  375.202496] Console: switching to colour frame buffer device 240x75
>[  375.355607] Console: switching to colour dummy device 80x25
>[  375.355701] [IGT] kms_pipe_crc_basic: executing
>[  375.364792] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.364819] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.366865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.366882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.368305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.368313] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.370391] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.370413] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.371605] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.371612] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.371616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.371632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.371656] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.372697] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.373597] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.373623] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.373646] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.373661] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.374653] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.374676] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.375756] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.375759] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.375837] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.375839] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.375843] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.375845] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.375849] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.375851] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.375858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.375861] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.375863] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.375866] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.375868] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.375871] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.375873] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.375876] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.375878] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.375880] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.375883] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.375885] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.375888] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.375890] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.375892] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.375895] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.375897] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.375900] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.375902] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.375905] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.375907] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.375909] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.375912] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.375914] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.375917] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.375919] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.375922] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.375924] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.375926] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.375929] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.375931] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.375961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.375980] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.378048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.378066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.380129] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.380133] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.382208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.382229] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.384303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.384309] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.384313] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.394038] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.394056] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.395610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.395630] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.397707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.397713] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.399788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.399807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.401882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.401888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.401892] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.402153] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.402174] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.403202] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.404103] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.404119] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.404134] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.404147] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.405137] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.405152] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.406197] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.406200] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.406279] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.406282] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.406286] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.406288] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.406291] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.406293] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.406300] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.406303] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.406306] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.406308] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.406311] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.406313] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.406316] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.406318] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.406320] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.406323] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.406325] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.406328] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.406330] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.406332] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.406335] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.406337] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.406340] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.406342] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.406345] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.406347] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.406349] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.406352] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.406354] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.406357] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.406359] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.406362] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.406364] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.406366] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.406369] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.406371] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.406374] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.406673] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.406699] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.408604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.408625] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.410606] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.410612] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.412689] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.412710] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.414785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.414791] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.414795] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.415078] [IGT] kms_pipe_crc_basic: starting subtest bad-source
>[  375.415244] [drm:intel_crtc_set_crc_source [i915]] unknown source foo
>[  375.415297] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  375.435990] Console: switching to colour frame buffer device 240x75
>[  375.595103] Console: switching to colour dummy device 80x25
>[  375.595196] [IGT] kms_pipe_crc_basic: executing
>[  375.604800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.604826] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.606624] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.606646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.608615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.608621] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.610617] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.610638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.612617] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.612623] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.612627] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.612642] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.612665] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.613693] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.614604] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.614621] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.614636] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.614650] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.615709] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.615727] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.616785] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.616788] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.616866] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.616868] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.616872] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.616874] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.616878] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.616880] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.616887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.616890] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.616892] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.616895] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.616897] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.616900] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.616902] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.616904] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.616907] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.616909] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.616912] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.616914] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.616917] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.616919] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.616921] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.616924] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.616926] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.616929] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.616931] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.616933] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.616936] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.616938] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.616941] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.616943] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.616946] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.616948] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.616950] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.616953] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.616955] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.616958] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.616960] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.616990] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.617008] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.618591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.618609] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.620623] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.620629] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.622616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.622635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.624616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.624622] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.624626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.634752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.634771] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.636618] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.636639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.638617] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.638623] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.640629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.640651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.642726] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.642732] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.642736] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.643004] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.643025] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.644048] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.644937] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.644954] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.644968] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.644982] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.645969] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.645984] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.647026] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.647029] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.647108] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.647110] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.647114] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.647116] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.647120] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.647122] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.647129] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.647132] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.647135] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.647137] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.647140] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.647142] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.647145] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.647147] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.647149] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.647152] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.647154] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.647157] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.647159] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.647162] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.647164] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.647166] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.647169] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.647171] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.647174] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.647176] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.647179] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.647181] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.647184] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.647186] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.647188] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.647191] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.647193] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.647196] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.647198] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.647201] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.647203] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.647426] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.647443] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.649512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.649532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.651616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.651622] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.653698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.653719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.655785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.655791] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.655794] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.656087] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A
>[  375.656537] [drm:drm_mode_addfb2] [FB:78]
>[  375.662566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  375.662577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.686161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  375.686257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  375.769666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.786249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  375.786275] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.786317] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  375.804113] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  375.804136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  375.804152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.804172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.804188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.804206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.804222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.804236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.804255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.804277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.804297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.804315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.804335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.804354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.804373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.804411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  375.805222] [drm:drm_mode_addfb2] [FB:58]
>[  375.811163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  375.811174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.811226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.811243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.811262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.811283] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.811301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.811320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.811338] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  375.811356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  375.811384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.811400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.811415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.811419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.811432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.811436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.811449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.811463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.811476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.811492] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  375.811510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.811527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.811545] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  375.811563] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  375.812650] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  375.812672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.812693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  375.815376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.815393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.815407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.815421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.815434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.815449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.815465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.815480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.815494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.815507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.815520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.815537] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  375.815552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.817626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.817643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.817661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.817679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.819218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.819235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.819250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.820754] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.820783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.822602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.825536] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  375.825566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.825626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  375.825651] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.825704] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  375.825729] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  375.842327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.842353] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  375.842390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.942491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.959090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  375.959115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.959163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  375.978117] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  375.978139] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  375.978155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.978175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.978192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.978210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.978225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.978240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.978256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.978274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.978291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.978307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.978322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.978336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.978355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.978393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  379.771931] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  383.744827] [drm] GPU HANG: ecode 8:0:0xe757fffe, in kms_pipe_crc_ba [8852], reason: Hang on render ring, action: reset
>[  383.744975] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  383.745188] drm/i915: Resetting chip after gpu hang
>[  383.746416] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8852]/0 marked guilty (score 10) banned? no
>[  383.746435] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x271d2c
>[  383.746815] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  383.750461] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  383.750481] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x271d2c, 0x0]
>[  383.750505] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  383.750527] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  383.750549] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  383.750570] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  383.750590] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  383.750607] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  383.751253] [drm:drm_mode_addfb2] [FB:58]
>[  383.759296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.759305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  383.759356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  383.759374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.759393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  383.759412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  383.759428] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  383.759444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.759461] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  383.759476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.759491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  383.759504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.759518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.759522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  383.759535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.759538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  383.759556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  383.759574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  383.759592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.759609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  383.759627] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  383.759644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.759661] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  383.759679] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  383.759696] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  383.759715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.759734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  383.762379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.762400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  383.762419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  383.762438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  383.762456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  383.762475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  383.762495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  383.762515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  383.762535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  383.762553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  383.762572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  383.762592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  383.762619] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  383.764617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.764634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.764651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.764670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.766187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  383.766203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  383.766218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.767713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.767730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  383.769556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.772515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.772544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  383.772560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  383.772583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.772636] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.772661] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.789310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  383.789336] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.789370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  383.889528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.906090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.906116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.906163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.925017] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.925039] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  383.925055] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  383.925119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.925146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  383.925175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  383.925200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  383.925220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  383.925236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  383.925255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  383.925272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  383.925293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  383.925314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  383.925333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  383.925353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  383.925392] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.925949] [drm:drm_mode_addfb2] [FB:58]
>[  383.931680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  383.931688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  383.931734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  383.931751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.931768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  383.931787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  383.931804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  383.931823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.931840] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  383.931858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.931876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  383.931893] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.931910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.931913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  383.931930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.931934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  383.931951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  383.931969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  383.931986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.932003] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  383.932021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  383.932038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.932055] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  383.932098] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  383.932125] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  383.932148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.932175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  383.934695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  383.934712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  383.934726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  383.934739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  383.934752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  383.934767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  383.934783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  383.934797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  383.934811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  383.934824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  383.934837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  383.934853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  383.934868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  383.936851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.936869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.936887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.936905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.938438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  383.938462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  383.938485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.940028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.940053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  383.941901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.944832] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.944860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  383.944877] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  383.944899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.944952] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.944977] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.961655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  383.961681] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  383.961718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.061889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.078473] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.078500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.078547] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  384.097403] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  384.097426] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  384.097442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  384.097462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.097478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.097496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.097512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.097531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.097550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.097572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.097591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.097608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.097629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.097648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.097667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.097705] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.098158] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  384.119486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  384.119508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.119530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  384.119552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  384.119569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  384.119587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.119606] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  384.119623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  384.119640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  384.119655] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.119670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.119675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.119689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.119692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.119707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  384.119721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  384.119735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.119748] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  384.119765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  384.119778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.119792] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  384.119805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  384.119818] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  384.119834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.119852] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  384.119909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.119924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.119939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.119953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.119966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.119980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.119997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.120012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.120027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.120041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.120054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.120071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  384.120107] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  384.122104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.122119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.122132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.122146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.123654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  384.123667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  384.123679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.125181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.125198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  384.127011] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.130030] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  384.130057] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  384.130073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  384.130107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.130161] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  384.130185] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  384.146819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.146843] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.146880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.147006] Console: switching to colour frame buffer device 240x75
>[  384.478193] Console: switching to colour dummy device 80x25
>[  384.478287] [IGT] kms_pipe_crc_basic: executing
>[  384.491300] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  384.491331] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  384.493402] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  384.493422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  384.495497] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  384.495503] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  384.497578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  384.497599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  384.499674] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  384.499680] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  384.499684] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  384.499699] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  384.499721] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  384.500756] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  384.501645] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  384.501662] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  384.501676] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  384.501690] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  384.502680] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  384.502696] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  384.503746] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  384.503748] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  384.503826] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  384.503828] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  384.503833] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  384.503835] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  384.503838] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  384.503840] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  384.503847] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  384.503850] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.503852] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.503855] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.503857] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  384.503860] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  384.503862] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  384.503865] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  384.503867] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.503870] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.503872] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  384.503874] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  384.503877] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  384.503879] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  384.503882] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  384.503884] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  384.503887] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  384.503889] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  384.503891] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  384.503894] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  384.503896] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  384.503899] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  384.503901] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  384.503903] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  384.503906] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  384.503908] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  384.503911] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  384.503913] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  384.503915] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  384.503918] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  384.503920] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  384.503950] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  384.503967] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  384.505132] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  384.505150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  384.507155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  384.507161] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  384.509152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  384.509171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  384.511154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  384.511160] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  384.511164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  384.521045] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  384.521064] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  384.522158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  384.522177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  384.524252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  384.524258] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  384.526327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  384.526345] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  384.528420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  384.528426] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  384.528430] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  384.528695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  384.528716] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  384.529858] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  384.530748] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  384.530765] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  384.530780] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  384.530793] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  384.531788] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  384.531807] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  384.532854] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  384.532857] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  384.532936] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  384.532938] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  384.532942] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  384.532944] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  384.532948] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  384.532950] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  384.532956] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  384.532959] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.532962] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.532964] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.532967] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  384.532969] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  384.532972] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  384.532974] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  384.532976] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.532979] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  384.532981] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  384.532984] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  384.532986] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  384.532989] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  384.532991] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  384.532993] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  384.532996] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  384.532998] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  384.533001] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  384.533003] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  384.533006] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  384.533008] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  384.533010] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  384.533013] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  384.533015] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  384.533018] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  384.533020] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  384.533022] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  384.533025] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  384.533027] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  384.533030] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  384.533358] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  384.533377] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  384.535454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  384.535474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  384.537159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  384.537165] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  384.539240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  384.539260] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  384.541334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  384.541340] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  384.541344] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  384.541635] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B
>[  384.542077] [drm:drm_mode_addfb2] [FB:58]
>[  384.548066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  384.548152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.563883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  384.563910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.563953] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  384.582818] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  384.582841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  384.582858] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  384.582878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.582895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.582912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.582927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.582942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.582958] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.582976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.582992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.583008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.583024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.583038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.583053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.583087] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  384.583239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  384.583254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  384.583324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  384.583349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.583377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  384.583406] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  384.583431] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  384.583457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.583483] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  384.583508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.583533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  384.583557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.583580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.583586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.583608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.583613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.583637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  384.583661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  384.583684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.583705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.583731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  384.583754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.583777] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  384.583800] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  384.583823] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  384.583849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.583877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  384.586544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.586564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.586584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.586602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.586621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.586640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.586660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.586680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.586699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.586718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.586736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.586756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  384.586774] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  384.588766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.588782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.588797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.588812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.590321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  384.590336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  384.590350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.591842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.591858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  384.593665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.596587] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.596613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  384.596629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  384.596651] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.613353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.613379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  384.613415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.630031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  384.696861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.696905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.696928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.696974] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.714951] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  384.714970] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  384.714991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.715008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.715026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.715041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.715056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.715072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.715090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.715107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.715163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.715188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.715212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.715234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.715287] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  384.715904] [drm:drm_mode_addfb2] [FB:58]
>[  384.721778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  384.721789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  384.721840] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  384.721856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.721873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  384.721892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  384.721906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  384.721922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.721937] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  384.721952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.721966] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  384.721980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  384.721992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.721996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.722012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.722016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  384.722034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  384.722052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  384.722069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.722086] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.722104] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  384.722169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.722195] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  384.722219] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  384.722242] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  384.722267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.722295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  384.724931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.724952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.724971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.724990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.725008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.725027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.725048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.725067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.725087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.725118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.725173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.725202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  384.725226] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  384.727242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  384.727261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  384.727277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.727293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  384.728809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  384.728827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  384.728842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  384.730349] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  384.730367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  384.732196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  384.735024] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.735052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  384.735069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  384.735091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  384.751808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.751834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  384.751869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.835376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  384.835460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.835503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.835574] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.853853] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  384.853872] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  384.853892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  384.853909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  384.853927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  384.853942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  384.853956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  384.853973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  384.853991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  384.854007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  384.854023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  384.854039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  384.854053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  384.854067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  384.854100] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.796533] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  395.777330] [drm] GPU HANG: ecode 8:0:0xe757fffe, in kms_pipe_crc_ba [8857], reason: Hang on render ring, action: reset
>[  395.777442] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  395.777501] drm/i915: Resetting chip after gpu hang
>[  395.778078] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8857]/0 marked guilty (score 10) banned? no
>[  395.778103] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x271d4d
>[  395.778434] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  395.780077] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  395.780096] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x271d4d, 0x0]
>[  395.780118] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  395.780141] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  395.780164] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  395.780187] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  395.780210] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  395.780229] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  395.780816] [drm:drm_mode_addfb2] [FB:58]
>[  395.788839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  395.788848] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  395.788898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.788915] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.788932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.788951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.788965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.788980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.788996] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  395.789011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  395.789025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.789038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.789051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.789054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.789067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.789070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.789083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.789096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.789109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.789121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.789136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.789148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.789165] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  395.789183] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  395.789201] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  395.789219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.789239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  395.791784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.791826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.791842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.791856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.791870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.791887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.791907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.791926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.791944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.791962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.791979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.791998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  395.792015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.794011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.794028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.794043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.794058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.795559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.795575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.795589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.797081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.797099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.798899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.801848] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  395.801877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.801893] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  395.801916] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.818651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.818678] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.818715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.902127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.902172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  395.902195] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.902233] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  395.920465] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  395.920484] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  395.920504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.920521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.920538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.920553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.920567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.920584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.920601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.920618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.920634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.920649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.920664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.920678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.920711] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.921481] [drm:drm_mode_addfb2] [FB:58]
>[  395.927382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  395.927393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  395.927445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.927462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.927479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.927499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.927517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.927535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.927552] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  395.927570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  395.927588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.927605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.927622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.927626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.927642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.927646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.927664] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.927681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.927698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.927715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.927733] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.927751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.927768] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  395.927817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  395.927841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  395.927866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.927891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  395.930527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.930552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.930575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.930596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.930617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.930639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.930664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.930687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.930710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.930730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.930750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.930775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  395.930823] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.932837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.932861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.932883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.932905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.934432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.934449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.934464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.935961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.935978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.937780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.940733] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  395.940761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.940778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  395.940848] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.957545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.957571] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.957606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.041021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.041067] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  396.041090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.041136] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  396.059420] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  396.059439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.059459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.059476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.059494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.059509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.059524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.059540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.059558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.059575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.059591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.059607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.059621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.059635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.059668] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  396.060308] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  396.081202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.081222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.081241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.081262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.081278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.081296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.081314] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  396.081330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.081346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.081361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.081376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.081380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.081395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.081397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.081412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.081431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.081451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.081471] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  396.081491] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.081511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.081531] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  396.081550] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  396.081570] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  396.081590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.081612] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  396.081677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.081697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.081717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.081737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.081757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.081777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.081813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.081835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.081856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.081876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.081895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.081916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  396.081936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.083945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.083963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.083979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.083998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.085513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.085528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.085542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.087046] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.087060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.088874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.091910] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.091936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.091950] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  396.091971] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.092020] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.092042] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.108729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.108755] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.108795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.108948] Console: switching to colour frame buffer device 240x75
>[  396.439594] Console: switching to colour dummy device 80x25
>[  396.439690] [IGT] kms_pipe_crc_basic: executing
>[  396.449099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  396.449130] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.450878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.450900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.452877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.452883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  396.454871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.454892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.456872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.456878] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.456882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  396.456897] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  396.456919] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  396.457953] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  396.458851] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  396.458868] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  396.458883] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  396.458897] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  396.459892] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  396.459917] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  396.460974] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  396.460977] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  396.461054] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.461056] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.461060] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  396.461062] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  396.461066] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.461068] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.461075] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  396.461078] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.461080] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.461083] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.461085] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.461088] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.461090] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.461093] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  396.461095] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.461098] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.461100] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.461102] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.461105] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.461107] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  396.461110] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.461112] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.461115] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  396.461117] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.461119] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.461122] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  396.461124] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  396.461127] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  396.461129] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  396.461132] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  396.461134] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  396.461136] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.461139] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.461141] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  396.461144] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.461146] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.461148] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  396.461178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  396.461196] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.462880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.462898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.464870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.464875] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  396.466862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.466880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.468870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.468875] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.468879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  396.478581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  396.478600] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.479879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.479899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.481975] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.481981] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  396.484056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.484077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.486153] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.486158] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.486162] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  396.486447] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  396.486469] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  396.487503] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  396.488392] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  396.488409] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  396.488427] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  396.488444] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  396.489432] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  396.489448] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  396.490495] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  396.490497] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  396.490577] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.490579] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.490583] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  396.490585] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  396.490589] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.490591] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.490598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  396.490600] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.490603] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.490605] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.490608] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.490611] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.490613] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.490615] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  396.490618] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.490620] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.490623] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.490625] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.490628] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.490630] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  396.490632] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.490635] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.490637] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  396.490640] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.490642] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.490645] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  396.490647] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  396.490649] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  396.490652] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  396.490654] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  396.490657] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  396.490659] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.490661] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.490664] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  396.490666] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.490669] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.490671] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  396.491017] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  396.491044] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.492878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.492899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.494873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.494879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  396.496956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.496976] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.499042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.499047] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.499051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  396.499340] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C
>[  396.499791] [drm:drm_mode_addfb2] [FB:58]
>[  396.505742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  396.505791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.509081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  396.509107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.509155] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.528025] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.528048] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  396.528065] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.528085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.528102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.528120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.528135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.528150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.528166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.528184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.528200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.528216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.528232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.528246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.528260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.528297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.528369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  396.528469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.528480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  396.528526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.528545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.528566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.528588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.528607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.528626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.528646] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.528675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.528693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.528708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.528722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.528726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.528739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.528742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.528755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.528768] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.528781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.528793] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.528808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.528863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.528887] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  396.528939] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  396.528961] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  396.528987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.529013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  396.531543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.531559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.531574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.531587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.531600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.531615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.531630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.531644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.531659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.531671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.531684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.531700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  396.531715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.533690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.533707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.533721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.533736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.535242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.535257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.535272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.536770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.536787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.538595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.541514] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.541541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.541557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.541579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.558305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.558330] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.558364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.641913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.641994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  396.642028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.642098] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  396.660499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  396.660520] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.660542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.660562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.660584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.660603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.660622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.660642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.660663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.660681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.660702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.660723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.660742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.660761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.660799] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.661428] [drm:drm_mode_addfb2] [FB:58]
>[  396.667325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.667336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  396.667386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.667403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.667421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.667439] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.667453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.667469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.667485] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.667500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.667514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.667528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.667541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.667544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.667557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.667560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.667573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.667586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.667598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.667611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.667626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.667643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.667660] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  396.667678] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  396.667696] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  396.667715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.667734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  396.670361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.670379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.670395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.670410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.670425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.670440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.670460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.670480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.670500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.670518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.670537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.670557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  396.670575] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.672585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.672602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.672616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.672632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.674165] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.674188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.674209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.675743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.675767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.677629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.680576] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.680604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.680621] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.680643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.697395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.697422] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.697460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.780993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.781075] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  396.781122] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.781192] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  396.799444] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  396.799463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.799484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.799501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.799519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.799535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.799554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.799573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.799595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.799614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.799635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.799656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.799675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.799694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.799732] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  400.765289] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  407.746099] [drm] GPU HANG: ecode 8:0:0xe757fffe, in kms_pipe_crc_ba [8861], reason: Hang on render ring, action: reset
>[  407.746208] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  407.746293] drm/i915: Resetting chip after gpu hang
>[  407.746777] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8861]/0 marked guilty (score 10) banned? no
>[  407.746802] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x271d6e
>[  407.747145] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  407.749320] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  407.749338] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x271d6e, 0x0]
>[  407.749358] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  407.749378] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  407.749397] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  407.749415] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  407.749433] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  407.749449] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  407.750057] [drm:drm_mode_addfb2] [FB:58]
>[  407.756651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  407.756661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  407.756713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  407.756730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.756748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  407.756766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  407.756781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  407.756797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.756813] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  407.756828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  407.756842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  407.756856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  407.756873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.756877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  407.756895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.756898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  407.756916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  407.756933] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  407.756951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.756968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.756986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  407.757003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.757020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  407.757038] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  407.757055] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  407.757074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.757093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  407.759730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  407.759750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  407.759770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  407.759789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  407.759807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  407.759826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  407.759846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  407.759866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  407.759886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  407.759905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  407.759923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  407.759943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  407.759962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  407.761951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  407.761968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  407.761982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.761997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  407.763500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  407.763608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  407.763628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.765121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  407.765137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  407.766936] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  407.769408] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  407.769436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  407.769453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  407.769475] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  407.786185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  407.786210] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  407.786245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  407.869768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.869849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  407.869896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.869967] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  407.888242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  407.888263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  407.888284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  407.888305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  407.888326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  407.888346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  407.888365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  407.888384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  407.888406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  407.888424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  407.888440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  407.888461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  407.888480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  407.888499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  407.888588] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  407.889350] [drm:drm_mode_addfb2] [FB:58]
>[  407.895272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  407.895284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  407.895334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  407.895350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.895368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  407.895389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  407.895406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  407.895424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.895442] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  407.895460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  407.895478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  407.895495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  407.895546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.895553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  407.895576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.895583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  407.895606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  407.895629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  407.895653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.895675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.895701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  407.895724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.895747] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  407.895769] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  407.895792] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  407.895816] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.895843] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  407.898481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  407.898506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  407.898555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  407.898577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  407.898600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  407.898622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  407.898647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  407.898670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  407.898693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  407.898713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  407.898733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  407.898758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  407.898781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  407.900791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  407.900808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  407.900823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.900838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  407.902344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  407.902360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  407.902374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.903869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  407.903885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  407.905683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  407.908627] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  407.908656] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  407.908672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  407.908694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  407.925436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  407.925463] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  407.925500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.008987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.009057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  408.009093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.009150] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  408.027320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  408.027339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  408.027359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.027376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.027394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.027409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.027424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.027440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.027457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.027474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.027489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.027505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.027562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.027585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.027638] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  408.028042] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  408.046003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  408.046026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.046049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  408.046074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  408.046096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  408.046117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.046139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  408.046160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.046180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  408.046200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.046221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.046225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.046245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.046248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.046269] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  408.046288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  408.046308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.046328] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  408.046348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  408.046368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.046388] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  408.046407] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  408.046427] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  408.046448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.046470] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  408.046558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.046579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.046599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.046619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.046638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.046658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.046681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.046709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.046727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.046742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.046756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.046773] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  408.046789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  408.048771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.048785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.048798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.048812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.050321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  408.050334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.050347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.051840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.051854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  408.053663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.056504] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.056552] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  408.056568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  408.056591] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.056637] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.056656] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.073319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.073344] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.073380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.073526] Console: switching to colour frame buffer device 240x75
>[  408.407259] Console: switching to colour dummy device 80x25
>[  408.407351] [IGT] kms_pipe_crc_basic: executing
>[  408.416771] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  408.416796] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  408.418843] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.418861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.420934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.420940] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  408.423015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.423037] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.425111] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.425117] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.425121] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  408.425136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  408.425158] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  408.426193] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  408.427082] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  408.427100] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  408.427118] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  408.427135] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  408.428232] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  408.428248] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  408.429298] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  408.429301] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  408.429379] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.429381] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.429385] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  408.429387] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  408.429390] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.429392] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.429399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  408.429402] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.429405] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.429407] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.429410] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.429412] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.429415] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.429417] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  408.429419] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.429422] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.429424] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.429427] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.429429] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.429432] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  408.429434] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.429436] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.429439] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  408.429441] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.429444] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.429446] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  408.429448] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  408.429451] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  408.429453] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  408.429456] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  408.429458] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  408.429461] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.429463] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.429465] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  408.429468] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.429470] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.429473] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  408.429502] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  408.429520] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  408.431562] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.431579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.433590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.433595] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  408.435590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.435611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.437591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.437596] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.437600] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  408.447582] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  408.447601] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  408.449679] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.449699] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.451775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.451781] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  408.453858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.453879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.455954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.455959] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.455963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  408.456227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  408.456249] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  408.457271] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  408.458159] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  408.458176] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  408.458190] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  408.458204] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  408.459192] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  408.459208] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  408.460257] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  408.460260] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  408.460338] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.460340] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.460344] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  408.460346] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  408.460350] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.460352] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.460359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  408.460361] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.460364] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.460366] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.460369] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.460372] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.460374] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.460377] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  408.460379] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.460381] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.460384] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.460386] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.460389] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.460391] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  408.460394] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.460396] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.460399] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  408.460401] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.460403] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.460406] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  408.460408] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  408.460411] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  408.460413] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  408.460415] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  408.460418] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  408.460420] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.460423] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.460425] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  408.460427] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.460430] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.460432] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  408.460798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  408.460824] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  408.462598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.462619] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.464603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.464609] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  408.466666] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.466686] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.468760] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.468766] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.468770] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  408.469081] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A
>[  408.469383] [drm:drm_mode_addfb2] [FB:58]
>[  408.475480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  408.475492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  408.507025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  408.507125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  408.607331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.623819] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.623846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.623888] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.642741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.642765] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  408.642785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  408.642807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.642827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.642848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.642868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.642887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.642906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.642928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.642946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.642963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.642983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.643002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.643021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.643059] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.643790] [drm:drm_mode_addfb2] [FB:58]
>[  408.649698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  408.649709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  408.649758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  408.649776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.649795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  408.649816] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  408.649833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  408.649851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.649869] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  408.649886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.649904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  408.649921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.649938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.649942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.649959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.649962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.649980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  408.649997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  408.650015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.650032] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  408.650050] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  408.650067] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.650084] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  408.650101] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  408.650119] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  408.650137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.650157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  408.652798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.652818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.652837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.652856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.652875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.652894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.652914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.652934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.652954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.652972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.652990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.653010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  408.653029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  408.655031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.655048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.655062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.655077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.656710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  408.656725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.656739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.658233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.658249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  408.660053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.663006] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.663034] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  408.663058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  408.663079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.663120] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.663136] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.679808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.679833] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.679868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.796685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.813251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.813277] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.813315] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.832167] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.832191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  408.832211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  408.832233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.832253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.832274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.832294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.832314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.832333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.832354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.832373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.832389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.832410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.832429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.832448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.832486] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.832981] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  408.851020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  408.851039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.851058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  408.851077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  408.851092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  408.851109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.851125] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  408.851140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.851155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  408.851169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.851187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.851192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.851210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.851213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.851232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  408.851251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  408.851269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.851287] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  408.851306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  408.851324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.851343] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  408.851361] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  408.851380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  408.851399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.851420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  408.851483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.851502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.851520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.851539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.851557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.851596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.851615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.851632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.851648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.851662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.851680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.851700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  408.851718] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  408.853712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.853728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.853741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.853756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.855266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  408.855279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.855292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.856790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.856807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  408.858621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.861651] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.861679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  408.861695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  408.861717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.861760] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.861776] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.878428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.878452] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.878489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.878633] Console: switching to colour frame buffer device 240x75
>[  409.031549] Console: switching to colour dummy device 80x25
>[  409.031725] [IGT] kms_pipe_crc_basic: executing
>[  409.040819] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  409.040843] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  409.042890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.042908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.044981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.044987] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  409.047063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.047084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.049158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.049164] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.049168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  409.049184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  409.049207] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  409.050248] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  409.051135] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  409.051152] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  409.051169] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  409.051186] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  409.052182] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  409.052198] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  409.053250] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  409.053252] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  409.053329] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.053331] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.053335] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  409.053337] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  409.053341] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.053343] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.053350] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  409.053353] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.053356] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.053358] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.053360] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.053363] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.053365] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.053368] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  409.053370] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.053373] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.053375] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.053378] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.053380] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.053382] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  409.053385] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.053387] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.053390] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  409.053392] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.053394] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.053397] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  409.053399] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  409.053402] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  409.053404] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  409.053407] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  409.053409] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  409.053411] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.053414] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.053416] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  409.053419] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.053421] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.053424] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  409.053453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  409.053470] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  409.054620] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.054636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.056634] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.056640] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  409.058630] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.058651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.060629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.060635] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.060638] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  409.070342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  409.070361] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  409.072439] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.072458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.074534] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.074539] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  409.076627] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.076646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.078720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.078726] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.078730] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  409.078992] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  409.079013] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  409.080034] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  409.080920] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  409.080936] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  409.080951] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  409.080965] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  409.081948] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  409.081965] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  409.083007] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  409.083010] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  409.083089] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.083091] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.083095] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  409.083097] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  409.083101] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.083103] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.083110] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  409.083113] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.083116] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.083118] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.083121] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.083123] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.083126] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.083128] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  409.083130] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.083133] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.083135] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.083138] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.083140] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.083143] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  409.083145] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.083147] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.083150] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  409.083152] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.083155] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.083157] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  409.083160] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  409.083162] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  409.083164] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  409.083167] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  409.083169] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  409.083172] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.083174] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.083176] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  409.083179] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.083181] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.083184] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  409.083400] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  409.083418] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  409.085494] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.085516] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.087612] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.087618] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  409.089694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.089716] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.091790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.091796] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.091800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  409.092088] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[  409.092381] [drm:drm_mode_addfb2] [FB:58]
>[  409.098438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  409.098449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  409.128639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  409.128727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  409.228844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.245410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  409.245438] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.245481] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  409.264359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  409.264381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  409.264398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  409.264418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.264434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.264452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.264468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.264483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.264499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.264518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.264534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.264554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.264575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.264634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.264657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.264710] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  409.265343] [drm:drm_mode_addfb2] [FB:58]
>[  409.271239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  409.271251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  409.271301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  409.271317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.271335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  409.271355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  409.271373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  409.271391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.271409] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  409.271426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  409.271444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  409.271461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  409.271478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.271481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.271498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.271502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.271519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  409.271537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  409.271554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.271571] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  409.271622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  409.271647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.271669] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  409.271689] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  409.271709] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  409.271732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.271757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  409.274287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.274311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.274333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.274353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.274374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.274397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.274421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.274444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.274466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.274487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.274507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.274531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  409.274554] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  409.276608] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  409.276632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  409.276654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.276677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  409.278198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  409.278222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  409.278243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.279740] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  409.279757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  409.281559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  409.284495] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  409.284523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  409.284540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  409.284562] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  409.284658] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  409.284685] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  409.301311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.301334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  409.301368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.418174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.434757] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  409.434781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.434817] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  409.453671] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  409.453694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  409.453710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  409.453730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.453747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.453764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.453780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.453795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.453811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.453828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.453845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.453861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.453876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.453890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.453904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.453937] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  409.454360] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  409.472061] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  409.472081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.472101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  409.472122] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  409.472138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  409.472156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.472173] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  409.472190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  409.472206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  409.472222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  409.472237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.472241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.472256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.472259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.472274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  409.472288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  409.472302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.472316] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  409.472333] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  409.472352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.472372] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  409.472392] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  409.472412] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  409.472432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.472455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  409.472518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.472538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.472558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.472578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.472598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.472635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.472658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.472679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.472700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.472727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.472744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.472764] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  409.472782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  409.474774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  409.474790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  409.474803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.474818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  409.476330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  409.476343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  409.476356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.477856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  409.477870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  409.479683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  409.482597] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  409.482642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  409.482658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  409.482681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  409.482725] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  409.482741] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  409.499397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.499422] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  409.499459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.499602] Console: switching to colour frame buffer device 240x75
>[  409.658369] Console: switching to colour dummy device 80x25
>[  409.658465] [IGT] kms_pipe_crc_basic: executing
>[  409.671820] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  409.671850] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  409.673676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.673697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.675667] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.675673] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  409.677672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.677693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.679669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.679675] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.679679] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  409.679695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  409.679717] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  409.680747] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  409.681655] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  409.681671] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  409.681686] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  409.681700] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  409.682692] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  409.682716] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  409.683774] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  409.683778] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  409.683855] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.683857] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.683861] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  409.683863] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  409.683867] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.683869] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.683876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  409.683879] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.683882] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.683884] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.683886] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.683889] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.683891] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.683894] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  409.683896] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.683899] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.683901] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.683903] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.683906] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.683908] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  409.683911] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.683913] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.683916] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  409.683918] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.683920] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.683923] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  409.683925] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  409.683928] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  409.683930] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  409.683933] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  409.683935] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  409.683937] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.683940] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.683942] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  409.683944] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.683947] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.683949] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  409.683979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  409.683997] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  409.685665] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.685683] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.687672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.687678] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  409.689669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.689687] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.691671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.691677] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.691681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  409.701694] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  409.701712] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  409.703781] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.703800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.705867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  409.705872] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  409.707950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.707971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  409.710047] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  409.710053] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.710057] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  409.710347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  409.710369] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  409.711396] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  409.712285] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  409.712302] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  409.712317] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  409.712331] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  409.713317] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  409.713333] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  409.714380] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  409.714383] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  409.714462] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.714464] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.714468] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  409.714470] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  409.714474] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  409.714476] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  409.714483] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  409.714486] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.714488] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.714491] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.714493] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.714496] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  409.714498] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.714500] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  409.714503] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.714505] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  409.714508] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  409.714510] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.714513] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  409.714515] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  409.714517] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.714520] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  409.714522] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  409.714525] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.714527] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  409.714529] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  409.714532] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  409.714534] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  409.714537] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  409.714539] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  409.714542] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  409.714544] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.714546] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  409.714549] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  409.714551] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.714554] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  409.714556] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  409.714963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  409.714981] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  409.716671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.716691] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.718669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  409.718674] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  409.720743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.720763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  409.722837] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  409.722843] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  409.722847] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  409.723140] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B
>[  409.723444] [drm:drm_mode_addfb2] [FB:58]
>[  409.729519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  409.729569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.732922] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  409.732948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.732988] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  409.751854] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  409.751877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  409.751893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  409.751913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.751931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.751949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.751964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.751979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.751995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.752013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.752029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.752045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.752061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.752075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.752089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.752122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  409.752199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  409.752208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  409.752251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  409.752267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.752286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  409.752309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  409.752327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  409.752347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.752366] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  409.752385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.752405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  409.752424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  409.752443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.752446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.752465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.752469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.752488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  409.752507] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  409.752526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.752545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.752572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  409.752589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.752604] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  409.752660] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  409.752686] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  409.752712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.752739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  409.755277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.755296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.755312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.755327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.755341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.755357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.755374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.755390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.755405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.755420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.755434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.755453] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  409.755472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  409.757459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  409.757476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  409.757493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.757512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  409.759025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  409.759040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  409.759055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.760562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  409.760578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  409.762388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  409.765313] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.765340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  409.765359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  409.765385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  409.782090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.782114] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  409.782148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.798765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  409.882312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.882368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.882396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.882440] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.900314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  409.900333] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  409.900355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.900374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.900396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.900416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.900436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.900455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.900477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.900496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.900512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.900533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.900552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.900571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.900612] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  409.901376] [drm:drm_mode_addfb2] [FB:58]
>[  409.907095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  409.907104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  409.907149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  409.907165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.907183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  409.907201] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  409.907216] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  409.907232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.907248] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  409.907262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.907277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  409.907290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  409.907303] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.907307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.907320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.907323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  409.907337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  409.907349] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  409.907362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.907374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.907389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  409.907402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.907415] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  409.907428] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  409.907440] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  409.907455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  409.907472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  409.910006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  409.910025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  409.910041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  409.910060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  409.910079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  409.910097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  409.910118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  409.910137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  409.910157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  409.910175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  409.910193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  409.910213] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  409.910232] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  409.912344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  409.912361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  409.912375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.912390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  409.913899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  409.913916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  409.913930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  409.915420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  409.915436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  409.917234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  409.919536] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.919564] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  409.919581] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  409.919603] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  409.936330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  409.936357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  409.936394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.036517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.036562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.036586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.036625] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.055433] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  410.055452] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  410.055474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.055494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.055516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.055536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.055555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.055575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.055596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.055614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.055631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.055697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.055727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.055753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.055808] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  410.056336] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  410.074110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  410.074129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.074149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  410.074170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  410.074186] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  410.074206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.074226] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  410.074246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  410.074266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  410.074285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  410.074304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.074309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.074328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.074331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.074351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  410.074371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  410.074391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.074410] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  410.074430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  410.074450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.074469] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  410.074489] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  410.074508] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  410.074529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.074551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  410.074616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.074636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.074674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.074694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.074714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.074733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.074763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.074783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.074802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.074819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.074837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.074856] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  410.074874] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  410.076870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  410.076886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  410.076900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.076914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  410.078422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  410.078437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  410.078454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.079950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  410.079965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  410.081771] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  410.084629] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  410.084666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  410.084683] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  410.084709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  410.084755] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  410.084774] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  410.101426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.101451] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  410.101488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.101614] Console: switching to colour frame buffer device 240x75
>[  410.256580] Console: switching to colour dummy device 80x25
>[  410.256725] [IGT] kms_pipe_crc_basic: executing
>[  410.265891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  410.265916] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  410.267707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.267725] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.269702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.269709] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  410.271700] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.271722] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.273702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.273708] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.273713] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  410.273729] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  410.273753] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  410.274784] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  410.275691] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  410.275717] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  410.275740] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  410.275757] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  410.276743] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  410.276767] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  410.277834] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  410.277837] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  410.277915] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.277917] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.277921] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  410.277923] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  410.277927] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.277929] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.277936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  410.277939] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.277941] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.277944] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.277946] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.277949] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.277951] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.277953] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  410.277956] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.277958] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.277961] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.277963] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.277966] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.277968] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  410.277970] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.277973] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.277975] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  410.277978] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.277980] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.277983] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  410.277985] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  410.277987] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  410.277990] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  410.277992] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  410.277995] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  410.277997] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.277999] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.278002] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  410.278004] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.278007] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.278009] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  410.278039] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  410.278057] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  410.279701] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.279721] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.281701] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.281707] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  410.283702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.283723] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.285708] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.285713] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.285717] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  410.295752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  410.295771] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  410.297840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.297861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.299927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.299932] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  410.302009] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.302028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.304104] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.304109] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.304113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  410.304382] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  410.304403] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  410.305429] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  410.306318] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  410.306335] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  410.306349] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  410.306363] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  410.307350] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  410.307368] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  410.308413] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  410.308416] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  410.308495] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.308497] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.308501] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  410.308503] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  410.308507] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.308509] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.308516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  410.308519] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.308521] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.308524] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.308526] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.308529] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.308531] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.308534] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  410.308536] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.308539] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.308541] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.308544] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.308546] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.308548] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  410.308551] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.308553] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.308556] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  410.308558] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.308561] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.308563] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  410.308565] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  410.308568] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  410.308570] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  410.308573] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  410.308575] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  410.308578] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.308580] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.308583] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  410.308585] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.308587] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.308590] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  410.308900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  410.308918] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  410.310702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.310720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.312706] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.312711] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  410.314703] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.314723] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.316703] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.316709] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.316713] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  410.317006] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence
>[  410.317306] [drm:drm_mode_addfb2] [FB:58]
>[  410.323296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  410.323345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.334961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  410.334988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.335030] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  410.353894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  410.353917] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  410.353934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  410.353955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.353975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.353996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.354016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.354035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.354054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.354076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.354097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.354117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.354137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.354156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.354175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.354213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  410.354295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  410.354305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  410.354351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  410.354371] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.354391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  410.354413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  410.354432] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  410.354451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.354471] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  410.354490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.354509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  410.354528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  410.354546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.354550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.354569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.354573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.354592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  410.354612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  410.354631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.354649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.354712] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  410.354738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.354769] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  410.354790] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  410.354810] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  410.354833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.354858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  410.357416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.357434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.357449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.357464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.357478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.357494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.357513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.357532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.357552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.357571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.357589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.357609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  410.357628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  410.359658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  410.359685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  410.359701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.359720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  410.361240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  410.361258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  410.361276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.362792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  410.362810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  410.364618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  410.367554] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.367582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  410.367598] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  410.367620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  410.384369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.384395] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  410.384429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.401038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  410.484556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.484601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.484627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.484706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.503458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  410.503478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  410.503498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.503515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.503533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.503548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.503563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.503579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.503597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.503614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.503630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.503645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.503702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.503725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.503780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  410.504483] [drm:drm_mode_addfb2] [FB:58]
>[  410.510334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  410.510345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  410.510396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  410.510413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.510430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  410.510449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  410.510463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  410.510479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.510494] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  410.510509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.510524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  410.510537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  410.510550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.510553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.510566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.510569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.510582] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  410.510595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  410.510608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.510621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.510636] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  410.510649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.510697] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  410.510719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  410.510743] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  410.510768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.510795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  410.513424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.513440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.513455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.513468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.513481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.513495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.513512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.513526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.513540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.513553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.513566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.513582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  410.513597] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  410.515582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  410.515600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  410.515614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.515629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  410.517131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  410.517146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  410.517160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.518689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  410.518705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  410.520504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  410.523424] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.523452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  410.523468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  410.523490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  410.540205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.540230] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  410.540265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.640383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.640429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.640453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.640491] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.658352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  410.658370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  410.658391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.658408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.658425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.658440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.658455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.658471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.658489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.658505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.658521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.658536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.658550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.658564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.658599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  410.659140] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  410.686082] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  410.686100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.686119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  410.686140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  410.686158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  410.686177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.686196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  410.686215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  410.686234] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  410.686252] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  410.686270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.686274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.686292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.686295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.686314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  410.686333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  410.686351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.686369] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  410.686388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  410.686406] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.686424] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  410.686443] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  410.686461] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  410.686480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.686501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  410.686563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.686582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.686601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.686620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.686639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.686657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.686700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.686719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.686735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.686749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.686762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.686780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  410.686795] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  410.688784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  410.688801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  410.688818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.688836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  410.690345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  410.690360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  410.690377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.691874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  410.691889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  410.693711] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  410.696649] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  410.696683] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  410.696699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  410.696721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  410.696765] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  410.696782] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  410.713464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.713487] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  410.713523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.713649] Console: switching to colour frame buffer device 240x75
>[  410.868468] Console: switching to colour dummy device 80x25
>[  410.868556] [IGT] kms_pipe_crc_basic: executing
>[  410.877924] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  410.877949] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  410.879749] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.879769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.881735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.881741] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  410.883736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.883756] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.885737] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.885743] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.885747] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  410.885762] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  410.885784] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  410.886827] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  410.887719] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  410.887736] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  410.887751] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  410.887767] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  410.888764] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  410.888791] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  410.889844] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  410.889847] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  410.889923] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.889925] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.889929] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  410.889931] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  410.889935] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.889937] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.889944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  410.889947] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.889950] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.889952] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.889955] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.889957] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.889960] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.889962] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  410.889964] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.889967] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.889969] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.889972] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.889974] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.889977] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  410.889979] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.889981] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.889984] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  410.889986] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.889989] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.889991] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  410.889994] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  410.889996] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  410.889998] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  410.890001] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  410.890003] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  410.890006] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.890008] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.890011] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  410.890013] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.890015] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.890018] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  410.890047] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  410.890065] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  410.891727] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.891744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.893735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.893741] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  410.895744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.895763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.897738] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.897744] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.897748] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  410.907487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  410.907506] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  410.909581] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.909601] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.911678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  410.911699] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  410.913776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.913796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  410.915873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  410.915878] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.915882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  410.916143] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  410.916165] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  410.917186] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  410.918073] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  410.918090] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  410.918104] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  410.918118] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  410.919103] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  410.919118] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  410.920163] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  410.920166] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  410.920245] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.920247] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.920251] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  410.920253] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  410.920257] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  410.920259] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  410.920266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  410.920269] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.920271] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.920274] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.920276] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.920278] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  410.920281] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.920284] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  410.920286] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.920288] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  410.920291] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  410.920293] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.920296] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  410.920298] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  410.920300] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.920303] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  410.920305] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  410.920308] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.920310] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  410.920313] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  410.920315] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  410.920317] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  410.920320] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  410.920322] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  410.920325] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  410.920327] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.920330] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  410.920332] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  410.920334] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.920337] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  410.920339] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  410.920565] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  410.920583] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  410.922661] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.922685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.924750] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  410.924756] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  410.926831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.926852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  410.928753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  410.928759] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  410.928763] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  410.929053] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[  410.929362] [drm:drm_mode_addfb2] [FB:58]
>[  410.935389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  410.935438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.947002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  410.947030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.947071] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  410.965922] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  410.965944] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  410.965961] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  410.965981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.965998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.966016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.966032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.966051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.966070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.966092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.966112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.966133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.966153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.966172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.966191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.966228] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  410.966300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  410.966397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  410.966407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  410.966453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  410.966472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.966492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  410.966515] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  410.966532] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  410.966551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.966570] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  410.966590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  410.966609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  410.966628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  410.966647] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.966651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.966669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.966673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  410.966737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  410.966767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  410.966794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.966826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.966851] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  410.966874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.966897] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  410.966919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  410.966942] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  410.966967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  410.966993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  410.969518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  410.969534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  410.969552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  410.969570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  410.969587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  410.969605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  410.969624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  410.969643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  410.969661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  410.969678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  410.969732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  410.969762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  410.969785] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  410.971777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  410.971793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  410.971807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.971821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  410.973325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  410.973341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  410.973354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  410.974862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  410.974880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  410.976685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  410.979632] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  410.979660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  410.979676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  410.979744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  410.996448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  410.996473] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  410.996508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.096797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.096886] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  411.096933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.097011] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  411.115383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  411.115402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  411.115422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.115439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.115460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.115480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.115499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.115519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.115540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.115561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.115579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.115600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.115619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.115638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.115676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.116345] [drm:drm_mode_addfb2] [FB:58]
>[  411.122200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  411.122211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  411.122261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  411.122278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.122296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  411.122317] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  411.122333] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  411.122351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.122369] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  411.122386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  411.122404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  411.122421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  411.122444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.122449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.122471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.122476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.122495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  411.122509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  411.122522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.122535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.122551] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  411.122565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.122578] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  411.122591] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  411.122604] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  411.122619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.122637] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  411.125179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.125199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.125218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.125237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.125255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.125274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.125295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.125315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.125335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.125353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.125371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.125391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  411.125410] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  411.127399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  411.127417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  411.127434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.127452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  411.128960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  411.128978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  411.128995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.130488] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  411.130505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  411.132303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  411.134610] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  411.134638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  411.134655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  411.134677] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  411.151399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.151426] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.151464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.251694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.251798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  411.251842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.251911] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  411.270536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  411.270555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  411.270575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.270592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.270610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.270625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.270640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.270657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.270675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.270695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.270757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.270785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.270808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.270831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.270884] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.271287] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  411.289197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  411.289220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.289241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  411.289264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  411.289282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  411.289302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.289323] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  411.289344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  411.289365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  411.289385] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  411.289405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.289409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.289430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.289433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.289453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  411.289473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  411.289493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.289513] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  411.289534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  411.289553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.289573] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  411.289593] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  411.289619] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  411.289638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.289658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  411.289739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.289758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.289777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.289796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.289815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.289833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.289854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.289874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.289894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.289912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.289930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.289950] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  411.289969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  411.291954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  411.291970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  411.291983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.291998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  411.293505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  411.293518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  411.293531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.295026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  411.295040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  411.296846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  411.299700] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  411.299746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  411.299762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  411.299785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  411.299829] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  411.299851] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  411.316504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.316529] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  411.316566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.316713] Console: switching to colour frame buffer device 240x75
>[  411.475232] Console: switching to colour dummy device 80x25
>[  411.475324] [IGT] kms_pipe_crc_basic: executing
>[  411.484957] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  411.484982] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  411.486784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  411.486803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  411.488772] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  411.488778] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  411.490773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  411.490793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  411.492776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  411.492782] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  411.492787] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  411.492801] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  411.492824] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  411.493866] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  411.494767] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  411.494785] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  411.494800] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  411.494814] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  411.495811] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  411.495833] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  411.496885] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  411.496888] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  411.496965] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  411.496967] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  411.496971] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  411.496973] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  411.496977] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  411.496979] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  411.496986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  411.496988] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.496991] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.496993] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.496996] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  411.496998] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  411.497001] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  411.497003] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  411.497006] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.497008] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.497011] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  411.497013] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  411.497015] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  411.497018] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  411.497020] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  411.497023] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  411.497025] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  411.497027] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  411.497030] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  411.497032] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  411.497035] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  411.497037] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  411.497040] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  411.497042] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  411.497044] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  411.497047] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  411.497049] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  411.497052] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  411.497054] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  411.497056] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  411.497059] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  411.497088] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  411.497106] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  411.498773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  411.498790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  411.500786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  411.500792] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  411.502775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  411.502795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  411.504775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  411.504781] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  411.504785] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  411.514702] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  411.514720] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  411.516825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  411.516846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  411.518921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  411.518926] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  411.521002] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  411.521022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  411.523096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  411.523102] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  411.523106] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  411.523395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  411.523417] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  411.524447] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  411.525337] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  411.525356] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  411.525374] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  411.525391] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  411.526384] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  411.526401] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  411.527444] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  411.527446] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  411.527525] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  411.527527] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  411.527532] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  411.527534] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  411.527538] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  411.527539] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  411.527546] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  411.527549] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.527552] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.527554] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.527557] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  411.527559] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  411.527562] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  411.527564] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  411.527567] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.527569] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  411.527572] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  411.527574] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  411.527577] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  411.527579] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  411.527581] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  411.527584] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  411.527586] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  411.527589] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  411.527591] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  411.527593] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  411.527596] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  411.527598] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  411.527601] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  411.527603] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  411.527606] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  411.527608] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  411.527610] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  411.527613] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  411.527615] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  411.527618] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  411.527620] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  411.528005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  411.528030] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  411.530101] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  411.530119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  411.532195] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  411.532201] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  411.534277] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  411.534296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  411.536371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  411.536377] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  411.536381] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  411.536698] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence
>[  411.537090] [drm:drm_mode_addfb2] [FB:58]
>[  411.543095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  411.543144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.550028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  411.550052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.550090] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  411.568949] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  411.568971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  411.568988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  411.569008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.569025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.569042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.569058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.569073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.569089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.569107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.569123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.569139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.569155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.569169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.569187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.569226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  411.569308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  411.569409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  411.569419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  411.569464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  411.569484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.569504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  411.569526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  411.569542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  411.569562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.569581] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  411.569600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  411.569620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  411.569645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  411.569661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.569665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.569679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.569682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.569697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  411.569711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  411.569766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.569790] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.569816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  411.569839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.569862] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  411.569884] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  411.569907] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  411.569932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.569958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  411.572483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.572499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.572514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.572527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.572541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.572555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.572571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.572586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.572600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.572613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.572626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.572642] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  411.572657] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  411.574631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  411.574647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  411.574661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.574675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  411.576182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  411.576199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  411.576216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.577713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  411.577741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  411.579545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  411.582470] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  411.582496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  411.582512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  411.582534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  411.599245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.599271] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.599306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.699509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.699577] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  411.699613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.699669] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  411.717508] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  411.717527] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  411.717547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.717565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.717582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.717597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.717612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.717628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.717649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.717669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.717687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.717708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.717727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.717789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.717847] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.718530] [drm:drm_mode_addfb2] [FB:58]
>[  411.724397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  411.724408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  411.724460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  411.724478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.724505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  411.724524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  411.724539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  411.724555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.724571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  411.724586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  411.724600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  411.724614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  411.724626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.724630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.724643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.724646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.724663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  411.724681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  411.724698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.724715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.724733] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  411.724782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.724806] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  411.724830] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  411.724853] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  411.724880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.724907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  411.727439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.727464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.727487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.727508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.727529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.727552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.727577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.727599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.727622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.727642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.727662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.727687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  411.727710] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  411.729761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  411.729784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  411.729806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.729829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  411.731368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  411.731392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  411.731414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.732908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  411.732924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  411.734767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  411.737649] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  411.737677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  411.737694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  411.737716] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  411.754469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.754495] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.754533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.854792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.854868] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  411.854907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.854971] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  411.873453] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  411.873472] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  411.873492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.873509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.873526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.873541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.873556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.873572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.873590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.873606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.873622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.873638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.873652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.873666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.873700] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  411.874266] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  411.892220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  411.892241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.892262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  411.892285] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  411.892305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  411.892325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.892345] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  411.892364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  411.892382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  411.892401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  411.892420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.892425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.892445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.892448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  411.892468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  411.892487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  411.892507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.892526] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  411.892546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  411.892565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.892585] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  411.892604] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  411.892624] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  411.892645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  411.892667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  411.892742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  411.892777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  411.892797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  411.892817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  411.892837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  411.892856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  411.892879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  411.892900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  411.892921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.892940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  411.892959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  411.892980] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  411.893000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  411.895001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  411.895017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  411.895031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.895046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  411.896553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  411.896567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  411.896580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  411.898074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  411.898088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  411.899893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  411.902743] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  411.902779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  411.902794] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  411.902815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  411.902858] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  411.902875] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  411.919548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  411.919572] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  411.919609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  411.919751] Console: switching to colour frame buffer device 240x75
>[  412.072892] Console: switching to colour dummy device 80x25
>[  412.072986] [IGT] kms_pipe_crc_basic: executing
>[  412.085957] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  412.085986] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  412.087830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.087850] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.089817] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.089823] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  412.091812] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.091834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.093834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.093840] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.093844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  412.093858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  412.093881] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  412.094909] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  412.095799] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  412.095817] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  412.095831] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  412.095845] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  412.096851] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  412.096875] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  412.097929] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  412.097932] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  412.098009] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.098011] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.098015] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  412.098017] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  412.098021] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.098023] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.098030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  412.098033] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.098035] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.098038] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.098040] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.098043] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.098045] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.098048] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  412.098050] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.098052] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.098055] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.098057] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.098060] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.098062] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  412.098065] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.098067] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.098069] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  412.098072] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.098074] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.098077] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  412.098079] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  412.098082] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  412.098084] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  412.098086] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  412.098089] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  412.098091] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.098094] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.098096] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  412.098098] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.098101] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.098103] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  412.098132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  412.098151] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  412.099802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.099820] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.101815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.101821] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  412.103811] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.103832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.105821] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.105827] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.105831] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  412.115762] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  412.115781] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  412.117827] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.117846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.119921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.119927] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  412.122003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.122023] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.124097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.124102] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.124106] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  412.124395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  412.124417] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  412.125442] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  412.126331] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  412.126347] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  412.126362] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  412.126376] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  412.127385] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  412.127401] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  412.128445] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  412.128448] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  412.128527] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.128529] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.128533] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  412.128535] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  412.128539] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.128541] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.128548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  412.128551] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.128553] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.128556] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.128558] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.128561] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.128563] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.128566] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  412.128568] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.128570] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.128573] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.128575] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.128578] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.128580] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  412.128583] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.128585] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.128587] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  412.128590] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.128592] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.128595] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  412.128597] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  412.128600] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  412.128602] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  412.128605] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  412.128607] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  412.128609] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.128612] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.128614] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  412.128617] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.128619] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.128621] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  412.128983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  412.129008] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  412.130819] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.130840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.132813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.132819] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  412.134896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.134916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.136984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.136989] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.136993] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  412.137284] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A
>[  412.137596] [drm:drm_mode_addfb2] [FB:58]
>[  412.143660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  412.143671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  412.169795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  412.169881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  412.253363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.269904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  412.269947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.270015] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  412.288880] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  412.288903] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  412.288920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  412.288940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.288957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.288974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.288990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.289005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.289021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.289039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.289056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.289072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.289088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.289102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.289116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.289149] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.290082] [drm:drm_mode_addfb2] [FB:58]
>[  412.296008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  412.296018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  412.296069] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  412.296086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.296103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  412.296122] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  412.296136] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  412.296152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.296168] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  412.296185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  412.296203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  412.296221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  412.296238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.296242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.296259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.296263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.296281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  412.296298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  412.296315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.296332] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  412.296350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  412.296367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.296384] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  412.296402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  412.296420] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  412.296438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.296458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  412.299007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.299026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.299042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.299057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.299076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.299094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.299115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.299135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.299155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.299173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.299191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.299211] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  412.299230] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  412.301241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  412.301266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  412.301288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.301312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  412.302958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  412.302981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  412.302996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.304487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  412.304503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  412.306300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  412.309221] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  412.309248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  412.309265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  412.309288] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  412.309341] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  412.309365] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  412.326004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.326029] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.326065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.426172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.442765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  412.442806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.442854] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  412.461708] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  412.461731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  412.461748] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  412.461768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.461826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.461855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.461879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.461904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.461928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.461956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.461983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.462008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.462033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.462054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.462076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.462128] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.462534] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  412.484278] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  412.484299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.484320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  412.484343] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  412.484363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  412.484383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.484403] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  412.484422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  412.484441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  412.484461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  412.484480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.484485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.484504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.484507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.484527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  412.484547] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  412.484566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.484586] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  412.484606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  412.484625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.484645] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  412.484664] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  412.484684] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  412.484704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.484726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  412.484805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.484822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.484837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.484852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.484866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.484881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.484898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.484915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.484935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.484953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.484970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.484990] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  412.485008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  412.486998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  412.487015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  412.487031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.487049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  412.488563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  412.488578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  412.488592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.490093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  412.490107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  412.491920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  412.494777] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  412.494823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  412.494838] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  412.494861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  412.494905] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  412.494927] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  412.511583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.511608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.511645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.511792] Console: switching to colour frame buffer device 240x75
>[  412.669457] Console: switching to colour dummy device 80x25
>[  412.669549] [IGT] kms_pipe_crc_basic: executing
>[  412.679005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  412.679030] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  412.680850] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.680871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.682854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.682860] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  412.684847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.684867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.686849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.686855] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.686859] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  412.686874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  412.686897] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  412.687936] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  412.688838] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  412.688864] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  412.688886] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  412.688901] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  412.689901] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  412.689924] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  412.690975] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  412.690978] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  412.691055] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.691057] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.691061] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  412.691063] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  412.691067] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.691069] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.691076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  412.691079] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.691081] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.691084] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.691086] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.691089] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.691091] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.691094] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  412.691096] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.691098] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.691101] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.691103] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.691106] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.691108] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  412.691111] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.691113] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.691115] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  412.691118] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.691120] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.691123] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  412.691125] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  412.691128] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  412.691130] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  412.691132] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  412.691135] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  412.691137] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.691140] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.691142] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  412.691144] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.691147] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.691149] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  412.691178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  412.691196] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  412.692825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.692841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.694855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.694860] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  412.696847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.696867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.698850] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.698856] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.698860] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  412.708917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  412.708936] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  412.710854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.710875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.712847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  412.712853] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  412.714860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.714880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  412.716956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  412.716961] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.716965] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  412.717234] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  412.717255] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  412.718277] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  412.719165] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  412.719182] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  412.719197] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  412.719210] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  412.720196] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  412.720212] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  412.721256] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  412.721259] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  412.721338] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.721340] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.721344] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  412.721346] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  412.721350] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  412.721352] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  412.721359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  412.721362] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.721364] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.721367] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.721369] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.721372] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  412.721374] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.721377] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  412.721379] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.721382] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  412.721384] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  412.721386] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.721389] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  412.721391] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  412.721394] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.721396] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  412.721399] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  412.721401] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.721403] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  412.721406] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  412.721408] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  412.721411] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  412.721413] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  412.721416] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  412.721418] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  412.721420] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.721423] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  412.721425] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  412.721428] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.721430] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  412.721432] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  412.721657] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  412.721675] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  412.723744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.723762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.725825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  412.725830] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  412.727890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.727908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  412.729976] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  412.729981] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  412.729985] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  412.730301] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  412.730604] [drm:drm_mode_addfb2] [FB:58]
>[  412.736578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  412.736590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  412.761828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  412.761932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  412.845319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.861909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  412.861937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.861979] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  412.880855] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  412.880877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  412.880894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  412.880914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.880930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.880948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.880963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.880978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.880994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.881015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.881035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.881053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.881074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.881093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.881112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.881149] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.881767] [drm:drm_mode_addfb2] [FB:58]
>[  412.887925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  412.887936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  412.887989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  412.888007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.888024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  412.888046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  412.888064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  412.888082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.888101] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  412.888119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  412.888137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  412.888155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  412.888173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.888176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.888194] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.888197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  412.888216] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  412.888240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  412.888256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.888270] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  412.888287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  412.888301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.888314] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  412.888327] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  412.888340] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  412.888356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  412.888373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  412.890918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  412.890937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  412.890953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  412.890969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  412.890983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  412.890999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  412.891017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  412.891033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  412.891048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  412.891062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  412.891076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  412.891094] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  412.891110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  412.893096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  412.893112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  412.893127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.893141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  412.894645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  412.894660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  412.894673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  412.896173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  412.896189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  412.898003] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  412.900715] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  412.900743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  412.900760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  412.900782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  412.900864] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  412.900889] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  412.917506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  412.917531] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  412.917567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.017676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.034268] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  413.034294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.034333] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.053184] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.053207] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  413.053223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.053243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.053260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.053277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.053292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.053308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.053323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.053341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.053362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.053382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.053403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.053422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.053441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.053480] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.053964] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  413.075263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.075285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.075307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.075330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.075349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.075369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.075389] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  413.075407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  413.075425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.075442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.075457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.075462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.075478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.075481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.075497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.075514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.075535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.075555] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  413.075576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.075596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.075615] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  413.075635] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  413.075655] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  413.075676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.075698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  413.075764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.075785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.075805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.075839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.075859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.075879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.075901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.075923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.075944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.075964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.075983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.076004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  413.076024] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.078016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.078033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.078050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.078067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.079581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.079596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.079613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.081115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.081131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.082948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.085993] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  413.086021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.086037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  413.086059] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.086104] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  413.086120] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  413.102814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.102858] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.102895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.103029] Console: switching to colour frame buffer device 240x75
>[  413.260419] Console: switching to colour dummy device 80x25
>[  413.260516] [IGT] kms_pipe_crc_basic: executing
>[  413.270044] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  413.270075] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  413.271891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.271913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.273884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.273890] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.275883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.275902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.277883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.277889] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.277893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  413.277909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  413.277933] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  413.278967] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  413.279885] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  413.279903] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  413.279921] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  413.279938] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  413.280926] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  413.280949] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.282019] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  413.282022] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.282101] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.282103] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.282107] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.282109] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.282113] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.282115] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.282122] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  413.282125] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.282127] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.282130] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.282132] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.282135] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.282137] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.282140] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.282142] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.282145] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.282147] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.282149] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.282152] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.282154] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  413.282157] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.282159] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.282162] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.282164] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.282166] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.282169] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.282171] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.282174] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.282176] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.282178] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.282181] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.282183] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.282186] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.282188] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.282190] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.282193] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.282195] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.282225] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  413.282243] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  413.283881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.283900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.285883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.285889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  413.287885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.287905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.289885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.289890] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.289894] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  413.299557] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  413.299576] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  413.301652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.301672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.303747] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.303753] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.305830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.305861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.307937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.307942] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.307946] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  413.308227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  413.308249] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  413.309275] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  413.310165] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  413.310183] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  413.310201] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  413.310218] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  413.311206] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  413.311223] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.312268] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  413.312271] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.312350] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.312353] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.312357] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.312359] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.312363] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.312365] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.312372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  413.312374] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.312377] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.312379] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.312382] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.312385] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.312387] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.312390] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.312392] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.312394] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.312397] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.312399] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.312402] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.312404] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  413.312406] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.312409] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.312411] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.312414] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.312416] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.312419] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.312421] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.312424] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.312426] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.312428] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.312431] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.312433] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.312436] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.312438] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.312440] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.312443] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.312445] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.312666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  413.312684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  413.313881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.313898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.315884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.315889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  413.317884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.317904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.319885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.319891] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.319895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  413.320181] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B
>[  413.320470] [drm:drm_mode_addfb2] [FB:58]
>[  413.326409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  413.326456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.336372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  413.336398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.336439] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.355308] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.355331] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  413.355347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.355368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.355384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.355402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.355418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.355433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.355449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.355467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.355483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.355500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.355516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.355530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.355543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.355577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.355650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  413.355660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  413.355702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.355718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.355736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.355755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.355770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.355786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.355802] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  413.355817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  413.355875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.355898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.355919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.355926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.355946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.355952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.355974] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.355996] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.356017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.356038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.356062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.356084] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.356106] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  413.356127] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  413.356148] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  413.356173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.356198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  413.359037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.359054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.359068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.359082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.359095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.359110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.359125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.359139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.359153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.359166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.359183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.359202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  413.359219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.361210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.361227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.361242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.361257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.362776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.362792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.362806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.364301] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.364317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.366119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.369062] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  413.369090] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.369106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  413.369129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.385871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.385897] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  413.385934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.402538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  413.469355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.469400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  413.469426] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.469473] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  413.487606] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  413.487625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.487645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.487662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.487680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.487695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.487709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.487725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.487742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.487759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.487774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.487790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.487804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.487818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.487901] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  413.488532] [drm:drm_mode_addfb2] [FB:58]
>[  413.494474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  413.494486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  413.494536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.494554] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.494571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.494590] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.494605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.494621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.494637] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  413.494652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  413.494667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.494687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.494700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.494704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.494716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.494720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.494733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.494745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.494758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.494770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.494785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.494799] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.494812] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  413.494824] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  413.494870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  413.494894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.494918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  413.497464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.497483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.497499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.497515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.497530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.497546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.497563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.497580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.497596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.497610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.497625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.497645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  413.497664] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.499665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.499689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.499712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.499735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.501254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.501278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.501299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.502799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.502816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.504641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.507558] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  413.507585] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.507602] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  413.507625] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.524340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.524364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  413.524398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.607975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.608061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  413.608110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.608183] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  413.626748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  413.626767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.626787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.626804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.626821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.626836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.626897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.626920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.626950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.626969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.626985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.627001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.627015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.627029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.627063] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  413.627429] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  413.645299] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.645319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.645339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.645360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.645377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.645397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.645418] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  413.645438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  413.645456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.645475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.645495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.645500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.645519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.645522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.645542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.645562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.645582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.645601] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  413.645622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.645641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.645660] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  413.645680] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  413.645700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  413.645720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.645742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  413.645820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.645840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.645879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.645899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.645919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.645938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.645960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.645982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.646003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.646022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.646042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.646063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  413.646083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.648084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.648100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.648114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.648128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.649640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.649653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.649666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.651165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.651179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.652990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.656023] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  413.656051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.656070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  413.656096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.656143] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  413.656162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  413.672848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.672892] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.672929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.673056] Console: switching to colour frame buffer device 240x75
>[  413.825501] Console: switching to colour dummy device 80x25
>[  413.825597] [IGT] kms_pipe_crc_basic: executing
>[  413.835076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  413.835105] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  413.836926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.836946] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.838917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.838923] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.840917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.840938] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.842917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.842923] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.842927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  413.842943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  413.842966] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  413.843997] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  413.844906] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  413.844930] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  413.844953] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  413.844972] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  413.845967] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  413.845991] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.847062] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  413.847065] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.847143] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.847145] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.847149] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.847151] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.847155] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.847157] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.847164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  413.847167] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.847169] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.847172] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.847174] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.847177] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.847179] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.847182] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.847184] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.847187] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.847189] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.847192] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.847194] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.847196] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  413.847199] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.847201] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.847204] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.847206] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.847208] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.847211] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.847213] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.847216] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.847218] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.847221] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.847223] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.847225] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.847228] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.847230] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.847233] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.847235] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.847237] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.847267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  413.847285] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  413.848914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.848931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.850918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.850923] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  413.852918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.852939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.854920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.854925] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.854930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  413.864766] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  413.864785] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  413.866384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.866405] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.868472] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.868476] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.870542] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.870561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.872636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.872642] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.872646] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  413.872979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  413.873000] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  413.874026] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  413.874932] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  413.874957] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  413.874980] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  413.875003] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  413.875989] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  413.876005] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.877054] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  413.877056] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.877135] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.877137] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.877141] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.877143] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.877147] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.877149] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.877156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  413.877158] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.877161] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.877163] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.877166] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.877168] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.877171] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.877173] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.877176] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.877178] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.877181] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.877183] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.877185] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.877188] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  413.877190] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.877193] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.877195] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.877198] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.877200] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.877202] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.877205] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.877207] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.877210] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.877212] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.877214] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.877217] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.877219] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.877222] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.877224] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.877226] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.877229] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.877450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  413.877468] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  413.878914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.878933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.880919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.880925] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  413.882917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.882939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.884918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.884923] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.884927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  413.885243] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence
>[  413.885543] [drm:drm_mode_addfb2] [FB:58]
>[  413.891614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  413.891670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.906384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  413.906410] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.906449] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.925303] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.925326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  413.925343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.925363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.925379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.925397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.925413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.925427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.925443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.925461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.925477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.925493] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.925508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.925522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.925536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.925569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.925644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  413.925654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  413.925696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.925712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.925729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.925749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.925764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.925780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.925796] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  413.925811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  413.925826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.925840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.925854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.925890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.925913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.925920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.925942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.925964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.925985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.926006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.926030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.926051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.926073] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  413.926094] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  413.926115] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  413.926140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.926166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  413.928734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.928753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.928768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.928783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.928797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.928815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.928836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.928856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.928915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.928937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.928958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.928983] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  413.929006] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.931003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.931019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.931033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.931047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.932554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.932569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.932582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.934080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.934096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.935906] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.938854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  413.938897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.938913] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  413.938936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.955676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.955702] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  413.955738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.972377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  414.039189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.039234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  414.039260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.039308] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  414.057643] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  414.057662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.057682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.057699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.057717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.057736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.057755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.057775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.057796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.057817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.057835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.057856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.057875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.057936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.057991] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  414.058595] [drm:drm_mode_addfb2] [FB:58]
>[  414.064463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  414.064474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  414.064524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.064542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.064561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.064581] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.064597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.064615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.064632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  414.064650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  414.064668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.064686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.064703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.064706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.064723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.064727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.064744] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.064762] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.064779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.064796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.064814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.064831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.064848] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  414.064866] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  414.064916] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  414.064942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.064967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  414.067616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.067637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.067656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.067675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.067694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.067712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.067733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.067753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.067773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.067791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.067809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.067829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  414.067848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.069873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.069901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.069916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.069931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.071443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.071459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.071473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.072970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.072986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.074822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.077763] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  414.077789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.077805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  414.077826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.094574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.094600] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  414.094635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.178064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.178109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  414.178133] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.178170] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  414.196648] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  414.196667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.196688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.196705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.196726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.196745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.196765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.196784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.196806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.196827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.196845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.196866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.196926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.196951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.197006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  414.197423] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  414.223321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.223340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.223360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.223380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.223396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.223417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.223437] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  414.223456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  414.223477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.223496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.223515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.223520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.223539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.223542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.223562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.223582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.223602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.223621] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  414.223641] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.223661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.223681] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  414.223700] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  414.223720] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  414.223741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.223763] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  414.223826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.223846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.223866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.223886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.223923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.223943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.223966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.223987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.224008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.224027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.224047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.224068] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  414.224087] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.226075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.226091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.226104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.226119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.227625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.227639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.227652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.229148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.229163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.230970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.234005] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  414.234033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.234050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  414.234072] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.234117] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  414.234135] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  414.250829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.250854] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.250910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.251033] Console: switching to colour frame buffer device 240x75
>[  414.410017] Console: switching to colour dummy device 80x25
>[  414.410112] [IGT] kms_pipe_crc_basic: executing
>[  414.419141] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  414.419168] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  414.420985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.421007] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.422950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.422956] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  414.424950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.424972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.426951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.426957] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.426961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  414.426976] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  414.426999] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  414.428035] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  414.428946] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  414.428962] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  414.428977] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  414.428991] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  414.429979] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  414.430000] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  414.431057] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  414.431060] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  414.431137] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.431139] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.431143] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  414.431145] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  414.431149] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.431151] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.431158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  414.431161] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.431164] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.431166] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.431169] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.431171] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.431174] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.431176] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  414.431178] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.431181] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.431183] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.431186] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.431188] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.431191] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  414.431193] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.431195] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.431198] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  414.431200] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.431203] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.431205] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  414.431207] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  414.431210] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  414.431212] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  414.431215] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  414.431217] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  414.431220] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.431222] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.431224] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  414.431227] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.431229] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.431231] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  414.431261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  414.431279] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  414.432950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.432971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.434961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.434967] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  414.436952] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.436972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.438954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.438959] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.438963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  414.448774] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  414.448793] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  414.450860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.450880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.452984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.452989] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  414.455057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.455077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.457152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.457157] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.457161] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  414.457450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  414.457471] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  414.458521] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  414.459416] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  414.459433] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  414.459448] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  414.459462] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  414.460479] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  414.460494] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  414.461548] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  414.461551] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  414.461631] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.461633] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.461637] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  414.461639] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  414.461642] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.461644] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.461651] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  414.461654] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.461657] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.461659] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.461662] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.461664] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.461667] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.461669] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  414.461672] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.461674] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.461676] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.461679] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.461681] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.461684] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  414.461686] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.461688] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.461691] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  414.461693] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.461696] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.461698] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  414.461701] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  414.461703] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  414.461705] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  414.461708] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  414.461710] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  414.461713] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.461715] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.461717] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  414.461720] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.461722] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.461725] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  414.462033] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  414.462058] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  414.463960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.463980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.465947] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.465952] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  414.468027] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.468045] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.470121] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.470126] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.470130] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  414.470424] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C
>[  414.470729] [drm:drm_mode_addfb2] [FB:58]
>[  414.476753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  414.476801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.484364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  414.484392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.484434] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  414.503282] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  414.503305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  414.503322] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.503341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.503358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.503376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.503391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.503406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.503422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.503439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.503456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.503472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.503487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.503501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.503515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.503549] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.503630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  414.503722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  414.503731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  414.503773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.503789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.503807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.503827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.503843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.503862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.503881] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  414.503901] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.503964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.503993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.504018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.504026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.504049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.504056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.504081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.504105] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.504130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.504154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.504187] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.504209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.504232] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  414.504254] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  414.504277] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  414.504302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.504328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  414.506859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.506875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.506889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.506937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.506959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.506983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.507008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.507030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.507053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.507072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.507092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.507115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  414.507137] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.509131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.509149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.509166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.509185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.510690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.510706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.510721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.512216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.512232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.514037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.516970] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.516996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.517012] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  414.517034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.533779] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.533804] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  414.533839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.617273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.617319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.617342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.617379] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.635666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  414.635685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.635705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.635722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.635740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.635759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.635778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.635797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.635819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.635839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.635856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.635877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.635896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.635957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.636012] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  414.636677] [drm:drm_mode_addfb2] [FB:58]
>[  414.642532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  414.642541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  414.642592] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.642609] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.642626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.642645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.642659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.642677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.642695] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  414.642713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.642731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.642748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.642766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.642769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.642786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.642790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.642808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.642825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.642843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.642860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.642878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.642895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.642943] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  414.642968] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  414.642990] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  414.643013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.643041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  414.645577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.645602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.645624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.645646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.645666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.645689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.645714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.645737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.645760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.645780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.645800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.645824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  414.645847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.647883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.647907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.647950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.647976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.649495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.649518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.649539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.651038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.651055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.652862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.654837] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.654865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.654882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  414.654905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.671656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.671683] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  414.671721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.755134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.755179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.755203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.755242] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.773600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  414.773619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.773640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.773656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.773673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.773688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.773703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.773719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.773736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.773753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.773768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.773784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.773798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.773812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.773846] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  414.774410] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  414.792377] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.792396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.792416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.792437] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.792456] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.792477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.792497] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  414.792516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  414.792536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.792555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.792575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.792579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.792599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.792602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.792622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.792641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.792661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.792680] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  414.792700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.792720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.792739] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  414.792759] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  414.792778] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  414.792800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.792822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  414.792888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.792908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.792954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.792971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.792986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.793002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.793020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.793036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.793051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.793069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.793088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.793107] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  414.793126] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.795124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.795139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.795152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.795167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.796675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.796692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.796709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.798209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.798225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.800038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.803071] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  414.803098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.803112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  414.803133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.803174] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  414.803189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  414.819896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.819921] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.819980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.820113] Console: switching to colour frame buffer device 240x75
>[  414.973885] Console: switching to colour dummy device 80x25
>[  414.974051] [IGT] kms_pipe_crc_basic: executing
>[  414.983177] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  414.983202] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  414.985249] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.985268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.987341] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.987347] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  414.989422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.989444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.991518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.991524] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.991528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  414.991543] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  414.991565] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  414.992598] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  414.993489] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  414.993507] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  414.993525] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  414.993542] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  414.994529] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  414.994546] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  414.995596] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  414.995599] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  414.995675] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.995678] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.995681] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  414.995683] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  414.995687] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.995689] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.995696] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  414.995699] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.995702] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.995704] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.995706] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.995709] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.995711] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.995714] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  414.995716] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.995719] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.995721] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.995724] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.995726] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.995728] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  414.995731] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.995733] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.995736] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  414.995738] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.995741] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.995743] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  414.995746] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  414.995748] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  414.995750] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  414.995753] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  414.995755] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  414.995758] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.995760] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.995762] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  414.995765] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.995767] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.995770] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  414.995798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  414.995816] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  414.997893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.997912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.999984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.999990] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  415.001999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.002018] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.003987] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.003992] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.003996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  415.014145] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  415.014164] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  415.016234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.016253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.018326] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.018331] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  415.020408] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.020428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.022504] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.022509] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.022513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  415.022803] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  415.022825] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  415.023856] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  415.024745] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  415.024762] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  415.024780] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  415.024797] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  415.025784] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  415.025802] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  415.026847] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  415.026850] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  415.026960] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.026964] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.026971] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  415.026974] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  415.026982] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.026986] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.026999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  415.027003] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.027009] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.027014] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.027019] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.027024] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.027029] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.027034] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  415.027038] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.027043] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.027048] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.027054] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.027059] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.027063] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  415.027067] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.027073] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.027078] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  415.027083] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.027087] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.027091] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  415.027097] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  415.027102] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  415.027106] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  415.027111] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  415.027115] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  415.027120] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.027125] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.027130] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  415.027134] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.027138] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.027144] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  415.027551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  415.027576] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  415.028988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.029007] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.030986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.030992] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  415.032987] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.033008] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.034988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.034993] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.034997] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  415.035292] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence
>[  415.035601] [drm:drm_mode_addfb2] [FB:58]
>[  415.041578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  415.041626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.053431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  415.053457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.053497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  415.071685] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  415.071708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  415.071724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  415.071744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.071761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.071779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.071795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.071809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.071825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.071843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.071860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.071876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.071892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.071906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.071919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.072003] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  415.072302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  415.072398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  415.072407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  415.072450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  415.072468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.072486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  415.072506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  415.072522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  415.072539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.072556] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  415.072575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.072595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  415.072614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  415.072632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.072636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.072655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.072659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.072678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  415.072698] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  415.072716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.072735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.072754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.072780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.072797] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  415.072812] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  415.072826] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  415.072842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.072859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  415.075382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.075400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.075417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.075432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.075449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.075467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.075487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.075507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.075527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.075545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.075563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.075583] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  415.075602] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  415.077588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  415.077605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  415.077620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.077635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  415.079145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  415.079161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  415.079175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.080670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  415.080686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  415.082494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  415.085418] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.085443] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  415.085460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  415.085482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  415.102222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.102248] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  415.102283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.185716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.185762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.185785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.185824] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.203636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  415.203656] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  415.203676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.203693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.203711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.203727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.203741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.203758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.203775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.203792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.203807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.203823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.203837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.203851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.203885] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  415.204681] [drm:drm_mode_addfb2] [FB:58]
>[  415.210616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  415.210627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  415.210678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  415.210695] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.210714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  415.210742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  415.210757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  415.210773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.210788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  415.210803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.210817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  415.210830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  415.210843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.210847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.210859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.210863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.210876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  415.210889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  415.210901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.210913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.210929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.210974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.210996] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  415.211017] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  415.211037] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  415.211059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.211086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  415.213623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.213647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.213670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.213691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.213711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.213733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.213758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.213781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.213804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.213824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.213844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.213869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  415.213892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  415.215937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  415.215975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  415.215997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.216020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  415.217547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  415.217564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  415.217579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.219078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  415.219094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  415.220903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  415.223840] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.223869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  415.223886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  415.223908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  415.240662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.240688] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  415.240723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.324176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.324222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.324245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.324284] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.342712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  415.342731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  415.342751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.342768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.342786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.342801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.342816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.342832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.342850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.342867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.342882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.342898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.342912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.342927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.343011] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  415.343494] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  415.361450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  415.361469] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.361489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  415.361510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  415.361529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  415.361549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.361570] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  415.361589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  415.361609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  415.361629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  415.361648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.361653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.361672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.361675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.361695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  415.361714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  415.361734] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.361753] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  415.361774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.361793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.361812] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  415.361832] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  415.361851] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  415.361872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.361894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  415.361956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.361994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.362014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.362034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.362054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.362074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.362096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.362118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.362139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.362158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.362177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.362198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  415.362218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  415.364211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  415.364226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  415.364240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.364254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  415.365765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  415.365779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  415.365791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.367291] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  415.367305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  415.369117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  415.371933] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  415.371975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  415.371990] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  415.372013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  415.372056] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  415.372072] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  415.388730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.388755] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  415.388791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.388920] Console: switching to colour frame buffer device 240x75
>[  415.543050] Console: switching to colour dummy device 80x25
>[  415.543145] [IGT] kms_pipe_crc_basic: executing
>[  415.552193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  415.552219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  415.554025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.554046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.556024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.556030] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  415.558020] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.558040] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.560021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.560027] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.560031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  415.560046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  415.560069] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  415.561110] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  415.562007] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  415.562024] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  415.562039] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  415.562053] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  415.563042] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  415.563064] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  415.564129] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  415.564132] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  415.564210] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.564212] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.564216] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  415.564218] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  415.564221] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.564223] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.564230] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  415.564233] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.564236] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.564238] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.564241] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.564243] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.564246] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.564248] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  415.564251] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.564253] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.564255] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.564258] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.564260] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.564263] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  415.564265] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.564268] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.564270] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  415.564273] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.564275] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.564277] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  415.564280] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  415.564282] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  415.564285] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  415.564287] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  415.564289] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  415.564292] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.564294] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.564297] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  415.564299] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.564301] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.564304] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  415.564334] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  415.564351] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  415.566011] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.566028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.568027] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.568033] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  415.570019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.570040] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.572025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.572031] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.572035] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  415.581818] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  415.581836] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  415.583033] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.583052] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.585127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.585133] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  415.587208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.587228] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.589303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.589309] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.589313] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  415.589598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  415.589620] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  415.590647] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  415.591539] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  415.591557] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  415.591571] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  415.591585] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  415.592645] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  415.592663] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  415.593709] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  415.593712] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  415.593792] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.593794] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.593798] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  415.593800] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  415.593804] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  415.593805] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  415.593812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  415.593815] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.593818] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.593820] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.593823] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.593825] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  415.593828] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.593830] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  415.593833] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.593835] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  415.593837] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  415.593840] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.593842] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  415.593845] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  415.593847] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.593850] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  415.593852] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  415.593855] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.593857] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  415.593859] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  415.593862] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  415.593864] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  415.593867] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  415.593869] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  415.593871] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  415.593874] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.593876] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  415.593879] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  415.593881] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.593883] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  415.593886] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  415.594189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  415.594207] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  415.596028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.596049] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.598022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.598028] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  415.600021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.600041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.602023] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  415.602028] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.602032] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  415.602320] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  415.683641] PM: Syncing filesystems ... done.
>[  415.707838] PM: Preparing system for sleep (mem)
>[  415.708225] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  415.709677] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  415.710942] PM: Suspending system (mem)
>[  415.711034] Suspending console(s) (use no_console_suspend to debug)
>[  415.712273] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  415.713273] e1000e: EEE TX LPI TIMER: 00000011
>[  415.720894] sd 3:0:0:0: [sda] Stopping disk
>[  415.731125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.739035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  415.739061] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  415.757835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  415.757858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  415.757878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  415.757900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.757919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.757941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.757960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.757979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.758024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.758046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.758066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.758086] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.758106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.758125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.758143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.758179] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  415.782088] PM: suspend of devices complete after 70.336 msecs
>[  415.783498] [drm:intel_power_well_disable [i915]] disabling display
>[  415.783520] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  415.783533] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.783553] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  415.795039] PM: late suspend of devices complete after 12.936 msecs
>[  415.796483] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  415.796643] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  415.796849] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  415.808060] PM: noirq suspend of devices complete after 13.016 msecs
>[  415.808319] ACPI: Preparing to enter system sleep state S3
>[  415.830659] PM: Saving platform NVS memory
>[  415.848643] Disabling non-boot CPUs ...
>[  415.859325] Broke affinity for irq 42
>[  415.860630] smpboot: CPU 1 is now offline
>[  415.876230] Broke affinity for irq 42
>[  415.876238] Broke affinity for irq 45
>[  415.877536] smpboot: CPU 2 is now offline
>[  415.886173] Broke affinity for irq 8
>[  415.886176] Broke affinity for irq 9
>[  415.886180] Broke affinity for irq 23
>[  415.886184] Broke affinity for irq 42
>[  415.886187] Broke affinity for irq 43
>[  415.886190] Broke affinity for irq 45
>[  415.887230] smpboot: CPU 3 is now offline
>[  415.889635] ACPI: Low-level resume complete
>[  415.889768] PM: Restoring platform NVS memory
>[  415.891689] Suspended for 15.912 seconds
>[  415.891769] Enabling non-boot CPUs ...
>[  415.891877] x86: Booting SMP configuration:
>[  415.891882] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  415.893607]  cache: parent cpu1 should not be sleeping
>[  415.894947] CPU1 is up
>[  415.895038] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  415.896188]  cache: parent cpu2 should not be sleeping
>[  415.896873] CPU2 is up
>[  415.896925] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  415.898002]  cache: parent cpu3 should not be sleeping
>[  415.899135] CPU3 is up
>[  415.918014] ACPI: Waking up from system sleep state S3
>[  415.928039] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  415.939621] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  415.939626] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  415.939719] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  415.940007] PM: noirq resume of devices complete after 12.283 msecs
>[  415.945127] hpet1: lost 7424 rtc interrupts
>[  415.945712] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  415.945772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.945800] [drm:intel_power_well_enable [i915]] enabling display
>[  415.947676] PM: early resume of devices complete after 2.432 msecs
>[  415.947903] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  415.947952] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  415.947975] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  415.949141] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  415.950971] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  415.953518] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  415.953538] [drm:intel_opregion_setup [i915]] ASLE supported
>[  415.953558] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  415.953577] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  415.953740] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  415.953759] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  415.953781] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  415.953801] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  415.953823] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  415.953842] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  415.953859] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  415.953896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  415.953958] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  415.953975] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  415.953994] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  415.954010] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  415.954028] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  415.954043] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  415.954063] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  415.954084] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  415.954104] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  415.954123] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  415.954141] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  415.954160] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  415.954181] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  415.954201] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  415.954217] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  415.954236] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  415.954255] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  415.954278] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  415.954300] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  415.954322] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  415.954347] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  415.954365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  415.954383] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  415.954401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.954406] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.954439] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954462] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  415.954478] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  415.954492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.954506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.954522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.954535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.954552] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  415.954570] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  415.954587] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  415.954606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  415.954623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  415.954640] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  415.954657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.954660] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.954680] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954697] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  415.954714] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  415.954732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.954749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.954766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.954783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.954800] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  415.954818] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  415.954836] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  415.954854] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  415.954872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  415.954887] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  415.954904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.954907] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.954927] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  415.954944] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  415.954961] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  415.954978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.954995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.955012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.955029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.955047] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  415.955064] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  415.955081] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  415.955101] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  415.955118] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  415.955135] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  415.955179] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  415.955197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.955215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  415.955235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  415.955252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  415.955270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.955287] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  415.955304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  415.955322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  415.955339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  415.955355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.955359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.955376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.955379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  415.955397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  415.955414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  415.955442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.955470] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  415.955487] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  415.955502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.955516] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  415.955529] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  415.955542] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  415.955558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.955575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  415.955632] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  415.957728] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  415.957749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.957767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.957787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.957807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.957827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.957848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  415.957871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  415.957894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.957916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.957938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.957959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.957979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.957999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.958021] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  415.958041] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  415.958285] sd 3:0:0:0: [sda] Starting disk
>[  415.960039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  415.960055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  415.960069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.960084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  415.962674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  415.962692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  415.962707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.964206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  415.964221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  415.966030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  415.969003] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  415.969038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  415.969054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  415.969076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  415.969109] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  415.969128] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  415.985777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.985799] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  415.985833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.985850] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  415.985869] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  415.985969] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  415.986003] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  415.988038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.988055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.990148] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  415.990154] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  415.992251] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.992270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  415.994364] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  415.994369] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  415.994373] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  415.994394] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  415.995420] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  415.996320] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  415.996336] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  415.996350] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  415.996367] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  415.997354] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  415.997369] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  415.998291] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  415.998308] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  416.000389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.000413] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.002503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.002508] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  416.004572] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.004588] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.006662] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.006668] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  416.006672] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  416.262880] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  416.303837] ata4.00: configured for UDMA/133
>[  416.476278] PM: resume of devices complete after 528.565 msecs
>[  416.477161] PM: Finishing wakeup.
>[  416.477163] Restarting tasks ... 
>[  416.477590] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  416.477593] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  416.487043] done.
>[  416.493991] [drm:drm_mode_addfb2] [FB:58]
>[  416.503835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  416.503851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  416.536269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  416.536350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  416.619783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.636361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  416.636387] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.636428] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  416.655300] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  416.655323] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  416.655340] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  416.655360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  416.655377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  416.655395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  416.655410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  416.655426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  416.655442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  416.655460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  416.655514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  416.655541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  416.655569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.655594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  416.655618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  416.655672] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  416.656333] [drm:drm_mode_addfb2] [FB:58]
>[  416.662224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  416.662235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  416.662287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  416.662303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  416.662320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  416.662339] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  416.662353] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  416.662369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  416.662384] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  416.662402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  416.662420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  416.662437] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  416.662454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.662486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.662509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.662515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.662539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  416.662564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  416.662587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.662610] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  416.662637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.662659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.662683] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  416.662705] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  416.662728] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  416.662753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.662781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  416.665315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  416.665340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  416.665361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  416.665382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  416.665403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  416.665425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  416.665450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  416.665509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  416.665532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.665553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  416.665573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  416.665599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  416.665621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  416.667630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  416.667654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  416.667675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.667698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  416.669219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  416.669241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  416.669262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.670760] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  416.670778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  416.672583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  416.675531] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  416.675560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  416.675577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  416.675600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  416.675644] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  416.675661] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  416.692334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  416.692358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  416.692391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.792530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.809143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  416.809184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.809248] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  416.828144] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  416.828168] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  416.828188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  416.828209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  416.828229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  416.828251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  416.828271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  416.828290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  416.828309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  416.828331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  416.828352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  416.828369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  416.828390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.828409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  416.828428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  416.828466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  416.828964] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  416.829682] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  416.846927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  416.846947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  416.846967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  416.846987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  416.847004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  416.847021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  416.847039] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  416.847055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  416.847075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  416.847095] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  416.847114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.847119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.847139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.847142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.847162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  416.847182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  416.847201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.847221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  416.847241] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.847260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.847280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  416.847300] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  416.847320] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  416.847341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.847363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  416.847429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  416.847449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  416.847469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  416.847513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  416.847532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  416.847552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  416.847574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  416.847596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  416.847617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.847636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  416.847655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  416.847677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  416.847696] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  416.849701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  416.849717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  416.849731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.849746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  416.851260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  416.851274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  416.851286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.852789] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  416.852803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  416.854616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  416.857653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  416.857679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  416.857694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  416.857715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  416.857757] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  416.857774] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  416.874474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  416.874517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  416.874554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.874681] Console: switching to colour frame buffer device 240x75
>[  417.034204] Console: switching to colour dummy device 80x25
>[  417.034297] [IGT] kms_pipe_crc_basic: executing
>[  417.043693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  417.043722] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.045562] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.045583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.047553] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.047559] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  417.049546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.049568] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.051545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.051551] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.051555] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  417.051571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  417.051593] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  417.052630] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  417.053532] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  417.053551] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  417.053566] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  417.053580] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  417.054573] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  417.054598] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  417.055677] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  417.055680] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  417.055758] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.055761] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.055765] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  417.055767] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  417.055771] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.055772] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.055780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  417.055783] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.055785] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.055788] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.055790] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.055793] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.055795] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.055798] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  417.055800] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.055802] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.055805] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.055807] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.055810] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.055812] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  417.055814] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.055817] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.055819] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  417.055822] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.055824] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.055827] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  417.055829] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  417.055832] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  417.055834] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  417.055836] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  417.055839] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  417.055841] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.055844] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.055846] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  417.055848] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.055851] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.055853] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  417.055882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  417.055900] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.057511] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.057529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.059546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.059551] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  417.061546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.061566] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.063554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.063560] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.063564] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  417.073596] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  417.073614] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.075559] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.075579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.077655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.077660] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  417.079736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.079756] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.081830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.081836] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.081840] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  417.082108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  417.082130] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  417.083164] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  417.084057] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  417.084075] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  417.084092] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  417.084110] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  417.085174] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  417.085190] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  417.086237] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  417.086240] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  417.086319] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.086322] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.086325] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  417.086327] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  417.086332] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.086333] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.086341] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  417.086344] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.086346] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.086349] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.086351] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.086354] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.086356] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.086359] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  417.086361] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.086364] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.086366] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.086368] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.086371] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.086373] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  417.086376] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.086378] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.086380] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  417.086383] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.086385] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.086388] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  417.086390] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  417.086393] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  417.086395] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  417.086397] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  417.086400] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  417.086402] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.086405] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.086407] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  417.086409] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.086412] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.086414] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  417.086807] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  417.086834] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.088553] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.088573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.090558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.090564] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  417.092641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.092662] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.094731] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.094737] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.094740] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  417.095036] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
>[  417.173309] PM: Syncing filesystems ... done.
>[  417.182769] PM: Preparing system for sleep (mem)
>[  417.183092] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  417.184553] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  417.185607] PM: Suspending system (mem)
>[  417.185691] Suspending console(s) (use no_console_suspend to debug)
>[  417.187008] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  417.187969] e1000e: EEE TX LPI TIMER: 00000011
>[  417.196198] sd 3:0:0:0: [sda] Stopping disk
>[  417.199995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.208082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  417.208121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  417.226084] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  417.226112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  417.226133] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  417.226158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.226179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.226202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.226222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.226241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.226262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  417.226286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.226308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.226329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.226351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.226370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.226388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.226431] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.256621] PM: suspend of devices complete after 70.187 msecs
>[  417.258044] [drm:intel_power_well_disable [i915]] disabling display
>[  417.258072] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  417.258084] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.258104] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  417.269563] PM: late suspend of devices complete after 12.929 msecs
>[  417.270947] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  417.271158] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  417.271252] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  417.282598] PM: noirq suspend of devices complete after 13.031 msecs
>[  417.282857] ACPI: Preparing to enter system sleep state S3
>[  417.305196] PM: Saving platform NVS memory
>[  417.305331] Disabling non-boot CPUs ...
>[  417.315785] Broke affinity for irq 42
>[  417.317280] smpboot: CPU 1 is now offline
>[  417.330883] Broke affinity for irq 42
>[  417.330891] Broke affinity for irq 45
>[  417.332250] smpboot: CPU 2 is now offline
>[  417.344829] Broke affinity for irq 8
>[  417.344833] Broke affinity for irq 9
>[  417.344838] Broke affinity for irq 23
>[  417.344842] Broke affinity for irq 42
>[  417.344845] Broke affinity for irq 43
>[  417.344848] Broke affinity for irq 45
>[  417.345885] smpboot: CPU 3 is now offline
>[  417.348000] ACPI: Low-level resume complete
>[  417.348134] PM: Restoring platform NVS memory
>[  417.348615] Suspended for 15.545 seconds
>[  417.348696] Enabling non-boot CPUs ...
>[  417.348803] x86: Booting SMP configuration:
>[  417.348808] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  417.350519]  cache: parent cpu1 should not be sleeping
>[  417.351908] CPU1 is up
>[  417.351999] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  417.353186]  cache: parent cpu2 should not be sleeping
>[  417.353874] CPU2 is up
>[  417.353929] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  417.355036]  cache: parent cpu3 should not be sleeping
>[  417.356870] CPU3 is up
>[  417.367752] ACPI: Waking up from system sleep state S3
>[  417.384326] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  417.395827] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  417.395834] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  417.395955] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  417.396335] PM: noirq resume of devices complete after 12.461 msecs
>[  417.396833] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  417.396927] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.396955] [drm:intel_power_well_enable [i915]] enabling display
>[  417.399268] PM: early resume of devices complete after 2.806 msecs
>[  417.399821] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  417.399964] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  417.400031] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  417.400063] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  417.403729] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  417.406174] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  417.406202] [drm:intel_opregion_setup [i915]] ASLE supported
>[  417.406228] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  417.406248] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  417.406447] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  417.406475] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  417.406506] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  417.406538] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  417.406594] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  417.406620] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  417.406646] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  417.406900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  417.406991] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  417.407019] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  417.407049] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  417.407073] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  417.407100] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  417.407126] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  417.407151] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  417.407177] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  417.407198] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  417.407221] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  417.407244] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  417.407267] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  417.407293] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  417.407317] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  417.407335] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  417.407357] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  417.407378] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  417.407401] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  417.407429] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  417.407458] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  417.407491] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  417.407515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  417.407539] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.407575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.407581] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.407605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.407610] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.407635] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.407659] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.407683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.407707] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.407731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.407755] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.407780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  417.407804] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  417.407829] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  417.407855] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  417.407879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  417.407903] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.407927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.407931] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.407955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.407959] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.407983] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.408008] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.408032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.408056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.408080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.408104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.408128] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  417.408153] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  417.408177] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  417.408203] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  417.408227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  417.408251] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.408275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.408279] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.408303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.408307] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.408331] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.408356] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.408380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.408404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.408428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.408452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.408477] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  417.408501] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  417.408525] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  417.408553] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  417.408591] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  417.408615] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  417.408672] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  417.408697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.408723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  417.408751] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  417.408775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  417.408801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.408825] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  417.408849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  417.408874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  417.408898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.408921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.408926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.408950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.408954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.408979] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  417.409003] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  417.409027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.409051] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  417.409076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.409099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.409124] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  417.409148] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  417.409172] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  417.409198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.409226] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  417.409317] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  417.410247] sd 3:0:0:0: [sda] Starting disk
>[  417.411370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  417.411395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.411419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.411444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.411469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.411494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.411518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.411546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.411595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.411622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.411648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.411674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.411698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.411722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.411749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  417.411773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  417.413816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.413839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.413859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.413880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.415432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  417.415456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  417.415480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.417025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.417047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  417.418901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.422000] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  417.422068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  417.422088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  417.422116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  417.422157] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  417.422177] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  417.438811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  417.438842] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.438893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.438921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  417.438948] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  417.439083] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.439280] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  417.441153] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.441183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.443246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.443252] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  417.445313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.445331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.447394] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.447399] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.447403] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  417.447422] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  417.448448] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  417.449338] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  417.449353] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  417.449367] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  417.449380] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  417.450366] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  417.450381] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  417.451303] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  417.451322] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.453378] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.453396] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.455454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.455458] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  417.457513] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.457529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.459589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.459593] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.459597] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  417.720977] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  417.761931] ata4.00: configured for UDMA/133
>[  417.920638] PM: resume of devices complete after 521.334 msecs
>[  417.921387] PM: Finishing wakeup.
>[  417.921389] Restarting tasks ... 
>[  417.924522] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  417.924527] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  417.924979] done.
>[  417.929631] [drm:drm_mode_addfb2] [FB:58]
>[  417.939194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  417.939264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.955992] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  417.956025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  417.956078] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  417.974374] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  417.974400] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  417.974419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  417.974443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.974462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.974482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.974500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.974517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.974535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  417.974553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.974574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.974636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.974663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.974686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.974710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.974765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.974910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  417.974925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  417.974993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  417.975014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.975039] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  417.975066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  417.975087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  417.975110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.975131] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  417.975153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.975173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  417.975194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.975213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.975219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.975239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.975244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.975265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  417.975284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  417.975304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.975322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.975345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.975364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.975384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  417.975403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  417.975423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  417.975446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.975471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  417.978138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.978157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.978173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.978188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.978203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.978218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.978238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.978258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.978278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.978296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.978314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.978334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  417.978353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  417.980337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.980356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.980373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.980391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.981900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  417.981917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  417.981931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.983424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.983440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  417.985248] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.988183] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.988258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  417.988275] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  417.988297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  418.004997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.005032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  418.005082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.021719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  418.088497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.088545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  418.088569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  418.088662] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  418.107312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  418.107331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  418.107352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.107369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.107386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.107402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.107416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.107433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.107450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.107467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.107483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.107499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.107513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.107527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.107560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  418.108189] [drm:drm_mode_addfb2] [FB:58]
>[  418.114024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  418.114036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  418.114085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  418.114102] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  418.114120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  418.114138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  418.114152] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  418.114167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  418.114183] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  418.114198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  418.114212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  418.114225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  418.114238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.114242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.114254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.114257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.114274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  418.114292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  418.114309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.114326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  418.114344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.114361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.114379] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  418.114396] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  418.114413] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  418.114432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.114452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  418.116989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.117008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.117026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.117045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.117064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.117083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.117104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.117124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.117143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.117162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.117180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.117200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  418.117219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  418.119220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.119245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.119267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.119291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.120811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  418.120833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  418.120855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.122350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.122366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  418.124169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.126256] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  418.126285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  418.126304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  418.126331] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  418.143070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.143096] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  418.143131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.226587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.226665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  418.226688] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  418.226725] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  418.245285] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  418.245304] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  418.245324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.245341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.245358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.245374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.245389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.245405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.245422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.245439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.245455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.245471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.245485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.245499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.245533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  418.245982] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  418.246730] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  418.268004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  418.268023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  418.268043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  418.268063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  418.268079] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  418.268097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  418.268114] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  418.268131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  418.268151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  418.268170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  418.268190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.268194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.268214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.268217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.268237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  418.268256] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  418.268276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.268295] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  418.268315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.268335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.268354] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  418.268374] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  418.268394] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  418.268415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.268437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  418.268502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.268523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.268543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.268563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.268583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.268602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.268639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.268660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.268681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.268701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.268728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.268747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  418.268763] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  418.270748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.270763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.270776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.270791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.272298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  418.272312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  418.272324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.273818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.273835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  418.275667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.278696] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  418.278725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  418.278741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  418.278764] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  418.278818] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  418.278841] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  418.295475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.295500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  418.295536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.295683] Console: switching to colour frame buffer device 240x75
>[  418.451900] Console: switching to colour dummy device 80x25
>[  418.451993] [IGT] kms_pipe_crc_basic: executing
>[  418.461848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  418.461877] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  418.463676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.463696] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.465672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.465679] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  418.467673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.467693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.469679] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.469685] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.469689] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  418.469705] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  418.469728] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  418.470759] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  418.471658] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  418.471684] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  418.471707] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  418.471725] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  418.472712] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  418.472735] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  418.473810] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  418.473813] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  418.473892] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.473894] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.473898] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  418.473900] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  418.473904] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.473906] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.473913] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  418.473916] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.473918] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.473921] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.473923] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.473926] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.473928] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  418.473931] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  418.473933] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.473936] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.473938] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  418.473940] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.473943] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.473945] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  418.473948] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.473950] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.473953] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  418.473955] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.473957] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.473960] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  418.473962] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  418.473965] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  418.473967] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  418.473970] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  418.473972] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  418.473974] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.473977] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.473979] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  418.473982] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.473984] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.473986] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  418.474016] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  418.474034] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  418.475663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.475683] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.477688] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.477694] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  418.479675] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.479696] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.481682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.481687] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.481691] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  418.491542] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  418.491560] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  418.493652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.493669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.495744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.495749] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  418.497817] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.497836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.499904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.499909] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.499913] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  418.500174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  418.500194] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  418.501234] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  418.502128] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  418.502145] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  418.502160] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  418.502174] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  418.503189] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  418.503204] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  418.504256] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  418.504259] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  418.504336] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.504338] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.504343] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  418.504345] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  418.504349] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.504350] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.504357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  418.504360] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.504363] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.504366] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.504368] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.504370] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.504373] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  418.504375] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  418.504378] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.504380] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.504383] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  418.504385] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.504387] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.504390] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  418.504392] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.504395] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.504397] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  418.504399] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.504402] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.504404] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  418.504407] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  418.504409] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  418.504412] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  418.504414] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  418.504416] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  418.504419] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.504421] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.504424] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  418.504426] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.504428] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.504431] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  418.504739] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  418.504765] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  418.506682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.506703] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.508678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.508683] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  418.510673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.510694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.512677] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.512683] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.512687] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  418.512977] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  418.578038] PM: Syncing filesystems ... done.
>[  418.603838] PM: Preparing system for sleep (mem)
>[  418.604161] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  418.605608] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  418.606886] PM: Suspending system (mem)
>[  418.606969] Suspending console(s) (use no_console_suspend to debug)
>[  418.608205] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  418.609531] e1000e: EEE TX LPI TIMER: 00000011
>[  418.616670] sd 3:0:0:0: [sda] Stopping disk
>[  418.622046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.629085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  418.629118] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  418.647880] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  418.647906] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  418.647927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  418.647952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.647973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.647997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.648018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.648039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.648060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.648084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.648106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.648129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.648151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.648171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.648192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.648231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  418.677730] PM: suspend of devices complete after 70.030 msecs
>[  418.679165] [drm:intel_power_well_disable [i915]] disabling display
>[  418.679188] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  418.679202] [drm:intel_power_well_disable [i915]] disabling always-on
>[  418.679223] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  418.690691] PM: late suspend of devices complete after 12.955 msecs
>[  418.692138] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  418.692418] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  418.692526] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  418.703721] PM: noirq suspend of devices complete after 13.025 msecs
>[  418.703981] ACPI: Preparing to enter system sleep state S3
>[  418.726252] PM: Saving platform NVS memory
>[  418.726395] Disabling non-boot CPUs ...
>[  418.736926] Broke affinity for irq 42
>[  418.738220] smpboot: CPU 1 is now offline
>[  418.745902] Broke affinity for irq 42
>[  418.745909] Broke affinity for irq 45
>[  418.746962] smpboot: CPU 2 is now offline
>[  418.751847] Broke affinity for irq 8
>[  418.751850] Broke affinity for irq 9
>[  418.751854] Broke affinity for irq 23
>[  418.751857] Broke affinity for irq 42
>[  418.751860] Broke affinity for irq 43
>[  418.751864] Broke affinity for irq 45
>[  418.752897] smpboot: CPU 3 is now offline
>[  418.754998] ACPI: Low-level resume complete
>[  418.755123] PM: Restoring platform NVS memory
>[  418.755606] Suspended for 15.595 seconds
>[  418.755720] Enabling non-boot CPUs ...
>[  418.755829] x86: Booting SMP configuration:
>[  418.755833] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  418.757593]  cache: parent cpu1 should not be sleeping
>[  418.759215] CPU1 is up
>[  418.759306] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  418.760505]  cache: parent cpu2 should not be sleeping
>[  418.761203] CPU2 is up
>[  418.761258] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  418.762342]  cache: parent cpu3 should not be sleeping
>[  418.763417] CPU3 is up
>[  418.769475] ACPI: Waking up from system sleep state S3
>[  418.782552] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  418.793836] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  418.793840] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  418.793923] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  418.794164] PM: noirq resume of devices complete after 11.903 msecs
>[  418.794410] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  418.794474] [drm:intel_power_well_enable [i915]] enabling always-on
>[  418.794495] [drm:intel_power_well_enable [i915]] enabling display
>[  418.796219] PM: early resume of devices complete after 1.940 msecs
>[  418.796431] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  418.796475] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  418.796496] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  418.797422] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  418.799272] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  418.801719] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  418.801739] [drm:intel_opregion_setup [i915]] ASLE supported
>[  418.801759] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  418.801779] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  418.801932] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  418.801952] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  418.801976] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  418.802001] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  418.802025] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  418.802049] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  418.802069] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  418.802099] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  418.802158] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  418.802179] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  418.802203] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  418.802223] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  418.802247] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  418.802267] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  418.802289] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  418.802311] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  418.802333] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  418.802353] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  418.802374] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  418.802394] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  418.802416] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  418.802438] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  418.802456] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  418.802476] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  418.802497] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  418.802521] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  418.802545] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  418.802568] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  418.802595] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  418.802625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  418.802655] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  418.802672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.802676] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.802690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.802693] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.802706] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  418.802719] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  418.802732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.802744] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  418.802760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.802773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.802786] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  418.802798] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  418.802811] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  418.802825] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  418.802837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  418.802849] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  418.802861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.802864] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.802875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.802878] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.802890] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  418.802902] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  418.802914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.802926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  418.802940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.802953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.802965] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  418.802977] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  418.802989] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  418.803002] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  418.803014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  418.803026] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  418.803037] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.803040] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.803052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.803055] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  418.803067] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  418.803078] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  418.803090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.803102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  418.803118] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.803135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.803153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  418.803171] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  418.803188] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  418.803208] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  418.803225] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  418.803242] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  418.803285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  418.803303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  418.803321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  418.803341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  418.803358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  418.803376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  418.803393] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  418.803411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  418.803428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  418.803445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  418.803462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  418.803465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.803482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  418.803485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  418.803502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  418.803520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  418.803537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  418.803554] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  418.803571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  418.803587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  418.803605] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  418.803622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  418.803648] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  418.803667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  418.803687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  418.803746] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  418.805844] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  418.805865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  418.805883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  418.805899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  418.805919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  418.805940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  418.805960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  418.805984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  418.806007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  418.806028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  418.806050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  418.806071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.806091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  418.806111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  418.806133] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  418.806153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  418.806815] sd 3:0:0:0: [sda] Starting disk
>[  418.809279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.809297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.809312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.809328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.813033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  418.813052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  418.813071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.815623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.815656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  418.818531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.821506] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  418.821539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  418.821555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  418.821577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  418.821611] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  418.821643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  418.838285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  418.838311] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  418.838350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  418.838372] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  418.838397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  418.838504] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  418.838543] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  418.840583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.840600] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.842686] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  418.842692] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  418.844769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.844788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  418.846862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  418.846868] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.846872] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  418.846892] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  418.847924] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  418.848818] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  418.848834] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  418.848848] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  418.848861] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  418.849871] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  418.849887] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  418.850811] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  418.850830] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  418.852896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.852915] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.854983] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.854987] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  418.857051] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.857066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.859140] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.859146] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.859149] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  419.115182] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  419.156136] ata4.00: configured for UDMA/133
>[  419.330154] PM: resume of devices complete after 533.888 msecs
>[  419.331068] PM: Finishing wakeup.
>[  419.331071] Restarting tasks ... 
>[  419.331499] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  419.331502] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  419.335856] done.
>[  419.342029] [drm:drm_mode_addfb2] [FB:58]
>[  419.352353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  419.352400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.356572] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  419.356597] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  419.356642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  419.373283] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  419.373308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  419.373325] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  419.373345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.373362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.373379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.373394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.373409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.373425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.373442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.373459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.373474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.373490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.373504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.373518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.373554] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  419.373635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  419.373793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  419.373803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  419.373848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  419.373866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  419.373884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  419.373907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  419.373926] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  419.373947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.373967] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  419.373987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  419.374006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  419.374026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  419.374046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.374051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.374069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.374073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.374093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  419.374112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  419.374132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.374151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  419.374171] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  419.374190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.374209] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  419.374228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  419.374247] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  419.374268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.374290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  419.376837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.376856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.376872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.376891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.376909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.376928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.376948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.376968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.376988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.377006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.377024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.377044] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  419.377063] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  419.380137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  419.380155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  419.380171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.380187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  419.383915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  419.383933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  419.383949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.386516] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  419.386534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  419.389410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  419.392348] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  419.392421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  419.392437] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  419.392462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  419.409171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.409197] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  419.409232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.492728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.492781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  419.492807] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  419.492850] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  419.511434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  419.511453] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  419.511474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.511492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.511510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.511525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.511540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.511559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.511581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.511601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.511619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.511640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.511659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.511721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.511779] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  419.512419] [drm:drm_mode_addfb2] [FB:58]
>[  419.518378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  419.518389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  419.518441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  419.518458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  419.518476] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  419.518494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  419.518508] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  419.518524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.518539] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  419.518554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  419.518568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  419.518581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  419.518594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.518598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.518610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.518613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.518626] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  419.518639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  419.518651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.518696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  419.518721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  419.518741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.518760] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  419.518779] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  419.518799] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  419.518822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.518846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  419.521474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.521497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.521520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.521540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.521561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.521583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.521607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.521630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.521652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.521706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.521728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.521754] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  419.521777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  419.524871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  419.524890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  419.524907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.524926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  419.528614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  419.528635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  419.528654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.531287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  419.531307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  419.534192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  419.537130] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  419.537159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  419.537175] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  419.537198] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  419.553931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.553955] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  419.553989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.637433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.637478] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  419.637500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  419.637536] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  419.655504] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  419.655523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  419.655543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.655560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.655578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.655593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.655608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.655624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.655642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.655662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.655726] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.655754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.655777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.655799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.655852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  419.656243] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  419.656959] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  419.674165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  419.674184] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  419.674203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  419.674224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  419.674240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  419.674258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.674276] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  419.674292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  419.674311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  419.674331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  419.674350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.674355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.674374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.674377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  419.674398] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  419.674417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  419.674437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.674457] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  419.674477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  419.674496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.674516] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  419.674536] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  419.674555] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  419.674576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.674598] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  419.674663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  419.674701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  419.674721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  419.674741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  419.674760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  419.674780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  419.674803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  419.674824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  419.674845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.674865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  419.674884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  419.674905] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  419.674925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  419.676924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  419.676940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  419.676953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.676967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  419.680654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  419.680676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  419.680703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.683273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  419.683289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  419.686180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  419.688676] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  419.688713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  419.688730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  419.688754] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  419.688798] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  419.688815] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  419.705482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  419.705508] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  419.705548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  419.705702] Console: switching to colour frame buffer device 240x75
>[  419.835808] Console: switching to colour dummy device 80x25
>[  419.835896] [IGT] kms_setmode: executing
>[  419.847942] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
>[  419.848071] [IGT] kms_setmode: exiting, ret=0
>[  419.889076] Console: switching to colour frame buffer device 240x75
>[  420.053575] Console: switching to colour dummy device 80x25
>[  420.053668] [IGT] kms_sink_crc_basic: executing
>[  420.076481] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  420.076508] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  420.077763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  420.077785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  420.079860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  420.079866] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  420.081943] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  420.081963] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  420.084038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  420.084044] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  420.084048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  420.084311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  420.084334] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  420.085371] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  420.086274] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  420.086293] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  420.086307] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  420.086321] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  420.087311] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  420.087326] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  420.088385] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  420.088389] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  420.088467] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  420.088469] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  420.088473] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  420.088475] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  420.088479] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  420.088481] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  420.088489] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  420.088491] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  420.088494] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  420.088496] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  420.088499] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  420.088501] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  420.088504] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  420.088506] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  420.088509] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  420.088511] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  420.088514] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  420.088516] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  420.088518] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  420.088521] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  420.088523] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  420.088526] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  420.088528] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  420.088531] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  420.088533] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  420.088536] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  420.088538] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  420.088540] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  420.088543] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  420.088545] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  420.088548] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  420.088550] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  420.088553] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  420.088555] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  420.088557] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  420.088560] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  420.088562] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  420.088890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  420.088916] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  420.090767] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  420.090787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  420.092757] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  420.092763] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  420.094759] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  420.094779] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  420.096855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  420.096861] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  420.096865] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  420.097147] [IGT] kms_sink_crc_basic: exiting, ret=77
>[  420.122612] Console: switching to colour frame buffer device 240x75
>[  420.274542] Console: switching to colour dummy device 80x25
>[  420.274635] [IGT] pm_backlight: executing
>[  420.274876] [IGT] pm_backlight: exiting, ret=77
>[  420.289460] Console: switching to colour frame buffer device 240x75
>[  420.424745] Console: switching to colour dummy device 80x25
>[  420.424834] [IGT] pm_rpm: executing
>[  420.436211] [drm:drm_mode_addfb2] [FB:76]
>[  420.468282] ahci 0000:00:1f.2: port does not support device sleep
>[  421.477978] [IGT] pm_rpm: starting subtest basic-pci-d3-state
>[  421.478042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  421.478139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.490404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  421.490430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  421.490469] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  421.508532] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  421.508555] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  421.508572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  421.508592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.508609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  421.508629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  421.508648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  421.508668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  421.508687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  421.508707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  421.508725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  421.508745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  421.508765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.508784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  421.508845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  421.508906] [drm:intel_power_well_disable [i915]] disabling display
>[  421.509012] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  421.509049] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  421.509076] [drm:intel_power_well_disable [i915]] disabling always-on
>[  421.509350] [drm:intel_runtime_suspend [i915]] Suspending device
>[  421.509404] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  421.509922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  421.510021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  421.511503] [drm:intel_runtime_suspend [i915]] Device suspended
>[  421.612269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  421.612288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  421.612384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  421.612423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  421.612462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  421.612504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  421.612537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  421.612577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  421.612618] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  421.612658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  421.612699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  421.612738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  421.612777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  421.612844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  421.612897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  421.612910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  421.612959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  421.613004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  421.613049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  421.613092] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  421.613140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  421.613186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  421.613232] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  421.613277] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  421.613320] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  421.613378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.613426] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  421.624911] [drm:intel_runtime_resume [i915]] Resuming device
>[  421.626998] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  421.629366] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  421.629587] [drm:intel_runtime_resume [i915]] Device resumed
>[  421.632339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  421.632353] [drm:intel_power_well_enable [i915]] enabling display
>[  421.632366] [drm:hsw_set_power_well [i915]] Enabling power well
>[  421.632411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.632429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  421.632447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  421.632465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  421.632482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  421.632500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  421.632519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  421.632538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  421.632556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.632573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  421.632591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  421.632609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  421.632627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  421.634613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  421.634630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  421.634645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  421.634660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  421.638396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  421.638414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  421.638430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  421.641029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  421.641049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  421.643948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  421.646900] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  421.646959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  421.646975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  421.646998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  421.647042] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  421.647059] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  421.663704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  421.663729] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  421.663764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.663880] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  421.665788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.665953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  421.665985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  421.668061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  421.668068] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  421.670144] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  421.670164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  421.672239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  421.672246] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  421.672251] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  421.672272] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  421.673301] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  421.674192] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  421.674210] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  421.674228] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  421.674246] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  421.675233] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  421.675250] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  421.677708] ahci 0000:00:1f.2: port does not support device sleep
>[  421.680389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  421.680432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  421.680638] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  421.697506] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  421.697560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  421.697584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  421.697607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.697625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  421.697642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  421.697658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  421.697673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  421.697690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  421.697708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  421.697725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  421.697741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  421.697756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.697771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  421.697785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  421.697896] [drm:intel_power_well_disable [i915]] disabling display
>[  421.697997] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  421.698039] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  421.698317] [IGT] pm_rpm: exiting, ret=0
>[  421.699170] [drm:intel_power_well_disable [i915]] disabling always-on
>[  421.699190] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  421.699209] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  421.699228] [drm:intel_power_well_enable [i915]] enabling always-on
>[  421.701293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  421.701313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  421.702846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  421.702852] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  421.704927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  421.704947] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  421.707021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  421.707028] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  421.707045] [drm:intel_power_well_disable [i915]] disabling always-on
>[  421.707050] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  421.729024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  421.729045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  421.729066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  421.729088] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  421.729105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  421.729124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  421.729142] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  421.729159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  421.729176] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  421.729196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  421.729216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  421.729221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  421.729241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  421.729245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  421.729265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  421.729286] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  421.729306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  421.729327] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  421.729347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  421.729367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  421.729388] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  421.729409] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  421.729429] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  421.729451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  421.729474] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  421.729553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  421.729598] [drm:intel_power_well_enable [i915]] enabling display
>[  421.729627] [drm:hsw_set_power_well [i915]] Enabling power well
>[  421.729708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  421.729730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  421.729750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  421.729771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  421.729792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  421.729842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  421.729872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  421.729898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  421.729924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.729946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  421.729967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  421.729994] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  421.730017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  421.732295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  421.732312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  421.732326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  421.732343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  421.736039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  421.736059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  421.736079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  421.738650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  421.738670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  421.741555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  421.744497] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  421.744563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  421.744578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  421.744599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  421.744640] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  421.744655] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  421.761312] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  421.761338] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  421.761373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  421.778083] Console: switching to colour frame buffer device 240x75
>[  421.914695] Console: switching to colour dummy device 80x25
>[  421.914779] [IGT] pm_rpm: executing
>[  421.926251] [drm:drm_mode_addfb2] [FB:76]
>[  421.958038] ahci 0000:00:1f.2: port does not support device sleep
>[  422.209488] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  422.972702] [IGT] pm_rpm: starting subtest basic-rte
>[  422.972757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  422.972834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  422.979089] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  422.979116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  422.979163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  422.998030] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  422.998053] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  422.998070] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  422.998090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  422.998107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  422.998125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  422.998141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  422.998156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  422.998172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  422.998190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  422.998207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  422.998226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  422.998247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  422.998266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  422.998285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  422.998314] [drm:intel_power_well_disable [i915]] disabling display
>[  422.998336] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  422.998362] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  422.998379] [drm:intel_power_well_disable [i915]] disabling always-on
>[  422.998404] [drm:intel_runtime_suspend [i915]] Suspending device
>[  422.998456] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  422.998562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  422.998640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  423.000565] [drm:intel_runtime_suspend [i915]] Device suspended
>[  423.098825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  423.098835] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  423.098885] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  423.098946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  423.098975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  423.099005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  423.099029] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  423.099057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  423.099075] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  423.099095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  423.099114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  423.099133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  423.099153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  423.099157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  423.099177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  423.099181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  423.099201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  423.099220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  423.099240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  423.099259] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  423.099279] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  423.099298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  423.099318] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  423.099338] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  423.099358] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  423.099378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  423.099400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  423.110975] [drm:intel_runtime_resume [i915]] Resuming device
>[  423.113044] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  423.115295] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  423.115467] [drm:intel_runtime_resume [i915]] Device resumed
>[  423.118172] [drm:intel_runtime_suspend [i915]] Suspending device
>[  423.118218] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  423.120315] [drm:intel_runtime_suspend [i915]] Device suspended
>[  423.143976] [drm:intel_runtime_resume [i915]] Resuming device
>[  423.146042] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  423.148431] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  423.148596] [drm:intel_runtime_resume [i915]] Device resumed
>[  423.148614] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.148631] [drm:intel_power_well_enable [i915]] enabling display
>[  423.148646] [drm:hsw_set_power_well [i915]] Enabling power well
>[  423.148677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  423.148696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  423.148713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  423.148730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  423.148746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  423.148763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  423.148781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  423.148798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  423.148817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  423.148838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  423.148858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  423.148880] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  423.148943] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  423.152049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  423.152067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  423.152082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  423.152098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  423.155801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  423.155820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  423.155836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  423.158431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  423.158450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  423.161405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  423.164329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  423.164363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  423.164380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  423.164402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  423.164446] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  423.164462] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  423.181109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  423.181134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  423.181168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  423.181253] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  423.181656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  423.183335] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  423.183355] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  423.185429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  423.185436] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  423.187512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  423.187534] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  423.189608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  423.189615] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  423.189619] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  423.189640] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  423.190673] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  423.191568] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  423.191585] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  423.191600] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  423.191614] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  423.192605] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  423.192621] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  423.194000] ahci 0000:00:1f.2: port does not support device sleep
>[  423.197780] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  423.197806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  423.197845] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  423.216704] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  423.216727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  423.216743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  423.216763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  423.216780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  423.216798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  423.216814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  423.216833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  423.216853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  423.216875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  423.216939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  423.216968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  423.216994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  423.217017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  423.217041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  423.217086] [drm:intel_power_well_disable [i915]] disabling display
>[  423.217123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  423.217152] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  423.217266] [IGT] pm_rpm: exiting, ret=0
>[  423.218361] [drm:intel_power_well_disable [i915]] disabling always-on
>[  423.218367] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  423.218386] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  423.218400] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.220500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  423.220520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  423.221948] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  423.221954] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  423.224030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  423.224050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  423.226109] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  423.226115] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  423.226131] [drm:intel_power_well_disable [i915]] disabling always-on
>[  423.226135] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  423.226162] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  423.226177] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.228251] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  423.228270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  423.230344] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  423.230350] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  423.232425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  423.232447] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  423.234521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  423.234527] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  423.234544] [drm:intel_power_well_disable [i915]] disabling always-on
>[  423.234548] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  423.234568] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  423.234584] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.235666] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  423.236560] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  423.236577] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  423.236591] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  423.236605] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  423.237594] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  423.237609] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  423.238547] [drm:intel_power_well_disable [i915]] disabling always-on
>[  423.238552] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  423.238569] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  423.238582] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.240658] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  423.240678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  423.242753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  423.242759] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  423.244835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  423.244856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  423.246942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  423.246948] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  423.246965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  423.246969] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  423.247115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  423.247134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  423.247154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  423.247175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  423.247191] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  423.247209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  423.247228] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  423.247248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  423.247269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  423.247289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  423.247309] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  423.247313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  423.247334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  423.247337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  423.247358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  423.247379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  423.247399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  423.247419] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  423.247440] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  423.247460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  423.247480] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  423.247501] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  423.247521] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  423.247543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  423.247565] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  423.247625] [drm:intel_power_well_enable [i915]] enabling always-on
>[  423.247643] [drm:intel_power_well_enable [i915]] enabling display
>[  423.247660] [drm:hsw_set_power_well [i915]] Enabling power well
>[  423.247692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  423.247714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  423.247734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  423.247755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  423.247776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  423.247796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  423.247816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  423.247838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  423.247860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  423.247880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  423.247942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  423.247969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  423.247994] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  423.250007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  423.250025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  423.250039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  423.250055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  423.253708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  423.253726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  423.253741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  423.256307] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  423.256325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  423.259197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  423.262163] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  423.262207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  423.262223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  423.262246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  423.262289] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  423.262305] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  423.278954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  423.278980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  423.279017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  423.295724] Console: switching to colour frame buffer device 240x75
>[  423.461584] Console: switching to colour dummy device 80x25
>[  423.461674] [IGT] pm_rps: executing
>[  423.475815] [IGT] pm_rps: starting subtest basic-api
>[  423.477407] [IGT] pm_rps: exiting, ret=0
>[  423.529269] Console: switching to colour frame buffer device 240x75
>[  423.686409] Console: switching to colour dummy device 80x25
>[  423.686501] [IGT] prime_busy: executing
>[  423.777593] [IGT] prime_busy: starting subtest basic-after-default
>[  424.933120] [IGT] prime_busy: exiting, ret=0
>[  424.980569] Console: switching to colour frame buffer device 240x75
>[  425.146965] Console: switching to colour dummy device 80x25
>[  425.147130] [IGT] prime_busy: executing
>[  425.178858] [IGT] prime_busy: starting subtest basic-before-default
>[  426.370173] [IGT] prime_busy: exiting, ret=0
>[  426.415207] Console: switching to colour frame buffer device 240x75
>[  426.582561] Console: switching to colour dummy device 80x25
>[  426.582655] [IGT] prime_busy: executing
>[  426.696734] [IGT] prime_busy: starting subtest basic-wait-after-default
>[  427.813258] [IGT] prime_busy: exiting, ret=0
>[  427.866468] Console: switching to colour frame buffer device 240x75
>[  428.031301] Console: switching to colour dummy device 80x25
>[  428.031395] [IGT] prime_busy: executing
>[  428.089856] [IGT] prime_busy: starting subtest basic-wait-before-default
>[  429.270393] [IGT] prime_busy: exiting, ret=0
>[  429.317774] Console: switching to colour frame buffer device 240x75
>[  429.473467] Console: switching to colour dummy device 80x25
>[  429.473560] [IGT] prime_self_import: executing
>[  429.473660] [IGT] prime_self_import: starting subtest basic-llseek-bad
>[  429.486526] [IGT] prime_self_import: exiting, ret=0
>[  429.534640] Console: switching to colour frame buffer device 240x75
>[  429.696061] Console: switching to colour dummy device 80x25
>[  429.696154] [IGT] prime_self_import: executing
>[  429.696254] [IGT] prime_self_import: starting subtest basic-llseek-size
>[  429.705851] [IGT] prime_self_import: exiting, ret=0
>[  429.751495] Console: switching to colour frame buffer device 240x75
>[  429.910176] Console: switching to colour dummy device 80x25
>[  429.910268] [IGT] prime_self_import: executing
>[  429.910468] [IGT] prime_self_import: starting subtest basic-with_fd_dup
>[  429.928601] [IGT] prime_self_import: exiting, ret=0
>[  429.968369] Console: switching to colour frame buffer device 240x75
>[  430.124362] Console: switching to colour dummy device 80x25
>[  430.124457] [IGT] prime_self_import: executing
>[  430.124557] [IGT] prime_self_import: starting subtest basic-with_one_bo
>[  430.159871] [IGT] prime_self_import: exiting, ret=0
>[  430.185199] Console: switching to colour frame buffer device 240x75
>[  430.354182] Console: switching to colour dummy device 80x25
>[  430.354274] [IGT] prime_self_import: executing
>[  430.354454] [IGT] prime_self_import: starting subtest basic-with_one_bo_two_files
>[  430.363673] [IGT] prime_self_import: exiting, ret=0
>[  430.418753] Console: switching to colour frame buffer device 240x75
>[  430.575609] Console: switching to colour dummy device 80x25
>[  430.575703] [IGT] prime_self_import: executing
>[  430.575804] [IGT] prime_self_import: starting subtest basic-with_two_bos
>[  430.594651] [IGT] prime_self_import: exiting, ret=0
>[  430.635616] Console: switching to colour frame buffer device 240x75
>[  430.787007] Console: switching to colour dummy device 80x25
>[  430.787099] [IGT] prime_vgem: executing
>[  430.816570] [IGT] prime_vgem: starting subtest basic-busy-default
>[  430.834422] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  430.835020] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  430.835086] [IGT] prime_vgem: exiting, ret=0
>[  430.885836] Console: switching to colour frame buffer device 240x75
>[  431.046670] Console: switching to colour dummy device 80x25
>[  431.046762] [IGT] prime_vgem: executing
>[  431.074590] [IGT] prime_vgem: starting subtest basic-fence-flip
>[  431.074625] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  431.078096] [drm:drm_mode_addfb2] [FB:58]
>[  431.078116] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  431.081475] [drm:drm_mode_addfb2] [FB:79]
>[  431.081512] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  431.081535] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  431.083617] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  431.083638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  431.085719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  431.085725] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  431.087802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  431.087823] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  431.089899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  431.089905] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  431.089909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  431.089917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  431.089938] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  431.090974] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  431.091904] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  431.091920] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  431.091935] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  431.091951] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  431.092943] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  431.092959] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  431.094016] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  431.094019] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  431.094099] [drm:drm_mode_debug_printmodeline] Modeline 115:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  431.094101] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  431.094105] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  431.094107] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  431.094111] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  431.094113] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  431.094120] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  431.094123] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  431.094126] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.094128] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.094131] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  431.094133] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  431.094135] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  431.094138] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  431.094140] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.094143] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.094145] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  431.094148] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  431.094150] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  431.094152] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  431.094155] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  431.094157] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  431.094160] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  431.094162] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  431.094165] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  431.094167] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  431.094170] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  431.094172] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  431.094174] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  431.094177] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  431.094179] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  431.094182] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  431.094184] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  431.094187] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  431.094189] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  431.094191] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  431.094194] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  431.094225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  431.094233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  431.094279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  431.094295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  431.094311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 78750KHz
>[  431.094329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  431.094343] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  431.094358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  431.094417] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  431.094444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  431.094468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  431.094491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  431.094514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  431.094520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  431.094542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  431.094549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  431.094572] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  431.094594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  431.094616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  431.094638] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  431.094664] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  431.094686] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  431.094709] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  431.094732] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  431.094752] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  431.094777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.094804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  431.102601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  431.102626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  431.102665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  431.120054] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  431.120077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  431.120094] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  431.120114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  431.120134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  431.120153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  431.120173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  431.120192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  431.120211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  431.120233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  431.120253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  431.120273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  431.120292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  431.120311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  431.120331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  431.120350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  431.122394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  431.122412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  431.122429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.122447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  431.123950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  431.123968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  431.123982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.125476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  431.125494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  431.127308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  431.130249] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  431.130277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  431.130301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  431.130322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  431.130358] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  431.130404] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  431.143711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  431.143741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  431.143776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  431.463738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.476924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  431.476947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  431.476985] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  431.490973] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  431.490997] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  431.491017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  431.491039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  431.491059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  431.491081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  431.491100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  431.491120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  431.491139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  431.491161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  431.491180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  431.491201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  431.491221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  431.491240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  431.491259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  431.491309] [drm:intel_power_well_disable [i915]] disabling display
>[  431.491443] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  431.491479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  431.491509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.491627] [drm:intel_runtime_suspend [i915]] Suspending device
>[  431.491706] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  431.491812] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  431.491930] [IGT] prime_vgem: exiting, ret=0
>[  431.493816] [drm:intel_runtime_suspend [i915]] Device suspended
>[  431.517502] [drm:intel_runtime_resume [i915]] Resuming device
>[  431.519591] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  431.521958] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  431.522154] [drm:intel_runtime_resume [i915]] Device resumed
>[  431.522314] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  431.522331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.523438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  431.523461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  431.525452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  431.525459] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  431.527444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  431.527462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  431.529445] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  431.529452] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  431.529468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.529473] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  431.529492] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  431.529506] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.530591] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  431.531482] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  431.531499] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  431.531513] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  431.531527] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  431.532535] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  431.532553] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  431.533489] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.533493] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  431.533511] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  431.533524] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.535451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  431.535469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  431.537446] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  431.537452] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  431.539458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  431.539477] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  431.541446] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  431.541452] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  431.541469] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.541473] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  431.548593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  431.548614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  431.548634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  431.548658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  431.548679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  431.548700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  431.548721] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  431.548741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  431.548762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  431.548782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  431.548802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  431.548807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  431.548827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  431.548831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  431.548852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  431.548872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  431.548892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  431.548912] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  431.548933] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  431.548953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  431.548974] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  431.548994] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  431.549015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  431.549037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.549060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  431.549120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.549138] [drm:intel_power_well_enable [i915]] enabling display
>[  431.549155] [drm:hsw_set_power_well [i915]] Enabling power well
>[  431.549188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  431.549209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  431.549230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  431.549251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  431.549271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  431.549292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  431.549314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  431.549333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  431.549355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  431.549375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  431.549424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  431.549458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  431.549482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  431.551539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  431.551556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  431.551571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.551586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  431.553096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  431.553112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  431.553126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.554625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  431.554641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  431.556448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  431.559336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  431.559485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  431.559512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  431.559543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  431.559587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  431.559605] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  431.576153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  431.576178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  431.576213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  431.592919] Console: switching to colour frame buffer device 240x75
>[  431.750661] Console: switching to colour dummy device 80x25
>[  431.750757] [IGT] prime_vgem: executing
>[  431.780588] [IGT] prime_vgem: starting subtest basic-fence-mmap
>[  431.780647] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  431.789549] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  431.789624] [IGT] prime_vgem: exiting, ret=0
>[  431.843149] Console: switching to colour frame buffer device 240x75
>[  432.002500] Console: switching to colour dummy device 80x25
>[  432.002593] [IGT] prime_vgem: executing
>[  432.029642] [IGT] prime_vgem: starting subtest basic-fence-read
>[  432.029701] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  432.043105] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  432.043189] [IGT] prime_vgem: exiting, ret=0
>[  432.093401] Console: switching to colour frame buffer device 240x75
>[  432.252232] Console: switching to colour dummy device 80x25
>[  432.252323] [IGT] prime_vgem: executing
>[  432.278619] [IGT] prime_vgem: starting subtest basic-fence-wait-default
>[  432.290532] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  433.292622] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  433.292919] [IGT] prime_vgem: exiting, ret=0
>[  433.344586] Console: switching to colour frame buffer device 240x75
>[  433.501905] Console: switching to colour dummy device 80x25
>[  433.501998] [IGT] prime_vgem: executing
>[  433.528695] [IGT] prime_vgem: starting subtest basic-gtt
>[  433.528728] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  433.538517] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  433.538603] [IGT] prime_vgem: exiting, ret=0
>[  433.578031] Console: switching to colour frame buffer device 240x75
>[  433.735738] Console: switching to colour dummy device 80x25
>[  433.735829] [IGT] prime_vgem: executing
>[  433.762704] [IGT] prime_vgem: starting subtest basic-read
>[  433.762736] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  433.771719] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  433.771809] [IGT] prime_vgem: exiting, ret=0
>[  433.811591] Console: switching to colour frame buffer device 240x75
>[  433.968265] Console: switching to colour dummy device 80x25
>[  433.968358] [IGT] prime_vgem: executing
>[  433.995716] [IGT] prime_vgem: starting subtest basic-sync-default
>[  434.007634] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  434.008401] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  434.008468] [IGT] prime_vgem: exiting, ret=0
>[  434.061798] Console: switching to colour frame buffer device 240x75
>[  434.221971] Console: switching to colour dummy device 80x25
>[  434.222062] [IGT] prime_vgem: executing
>[  434.249751] [IGT] prime_vgem: starting subtest basic-wait-default
>[  434.261647] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  434.262303] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  434.262373] [IGT] prime_vgem: exiting, ret=0
>[  434.295370] Console: switching to colour frame buffer device 240x75
>[  434.455939] Console: switching to colour dummy device 80x25
>[  434.456031] [IGT] prime_vgem: executing
>[  434.482746] [IGT] prime_vgem: starting subtest basic-write
>[  434.482779] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  434.492193] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  434.492263] [IGT] prime_vgem: exiting, ret=0
>[  434.545592] Console: switching to colour frame buffer device 240x75
>[  434.701166] Console: switching to colour dummy device 80x25
>[  434.701257] [IGT] vgem_basic: executing
>[  434.712420] [IGT] vgem_basic: starting subtest create
>[  434.712461] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  434.712495] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576
>[  434.712523] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648
>[  434.712759] [IGT] vgem_basic: exiting, ret=0
>[  434.729072] Console: switching to colour frame buffer device 240x75
>[  434.887277] Console: switching to colour dummy device 80x25
>[  434.887370] [IGT] vgem_basic: executing
>[  434.895897] [IGT] vgem_basic: starting subtest debugfs
>[  434.896145] [IGT] vgem_basic: exiting, ret=0
>[  434.912556] Console: switching to colour frame buffer device 240x75
>[  435.070545] Console: switching to colour dummy device 80x25
>[  435.070707] [IGT] vgem_basic: executing
>[  435.079388] [IGT] vgem_basic: starting subtest dmabuf-export
>[  435.091775] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  435.091899] [IGT] vgem_basic: exiting, ret=0
>[  435.146097] Console: switching to colour frame buffer device 240x75
>[  435.299039] Console: switching to colour dummy device 80x25
>[  435.299132] [IGT] vgem_basic: executing
>[  435.312937] [IGT] vgem_basic: starting subtest dmabuf-fence
>[  435.312973] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  435.313105] [IGT] vgem_basic: exiting, ret=0
>[  435.329597] Console: switching to colour frame buffer device 240x75
>[  435.486204] Console: switching to colour dummy device 80x25
>[  435.486296] [IGT] vgem_basic: executing
>[  435.496435] [IGT] vgem_basic: starting subtest dmabuf-fence-before
>[  435.496472] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  435.496555] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  435.496703] [IGT] vgem_basic: exiting, ret=0
>[  435.513093] Console: switching to colour frame buffer device 240x75
>[  435.670321] Console: switching to colour dummy device 80x25
>[  435.670415] [IGT] vgem_basic: executing
>[  435.679927] [IGT] vgem_basic: starting subtest dmabuf-mmap
>[  435.679965] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  435.680197] [IGT] vgem_basic: exiting, ret=0
>[  435.696591] Console: switching to colour frame buffer device 240x75
>[  435.848756] Console: switching to colour dummy device 80x25
>[  435.848851] [IGT] vgem_basic: executing
>[  435.863418] [IGT] vgem_basic: starting subtest mmap
>[  435.863456] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  435.863575] [IGT] vgem_basic: exiting, ret=0
>[  435.880089] Console: switching to colour frame buffer device 240x75
>[  436.040389] Console: switching to colour dummy device 80x25
>[  436.040482] [IGT] vgem_basic: executing
>[  436.046922] [IGT] vgem_basic: starting subtest second-client
>[  436.080316] [IGT] vgem_basic: exiting, ret=0
>[  436.096949] Console: switching to colour frame buffer device 240x75
>[  436.250783] Console: switching to colour dummy device 80x25
>[  436.250876] [IGT] vgem_basic: executing
>[  436.263800] [IGT] vgem_basic: starting subtest sysfs
>[  436.264172] [IGT] vgem_basic: exiting, ret=0
>[  436.280446] Console: switching to colour frame buffer device 240x75
>[  436.435152] Console: switching to colour dummy device 80x25
>[  436.435242] [IGT] vgem_basic: executing
>[  436.435339] [IGT] vgem_basic: starting subtest unload
>[  436.453300] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  436.468209] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  436.484986] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  436.497323] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  436.521780] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  436.530701] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  436.548106] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  436.564152] [IGT] vgem_basic: exiting, ret=0
>[  436.580741] Console: switching to colour frame buffer device 240x75
>[  436.745542] Console: switching to colour dummy device 80x25
>[  436.745635] [IGT] drv_module_reload: executing
>[  436.746135] [IGT] drv_module_reload: starting subtest basic-reload
>[  436.768816] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  436.768827] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  436.794782] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  436.794787] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  436.831786] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  436.831827] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  436.831853] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  436.831883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  436.831906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  436.831930] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  436.831954] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  436.831977] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  436.911899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.914269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  436.914350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  436.932584] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  436.932641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  436.932665] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  436.932691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  436.932709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  436.932778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  436.932801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  436.932818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  436.932835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  436.932855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  436.932877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  436.932899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  436.932921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  436.932941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  436.932962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  436.933019] [drm:intel_power_well_disable [i915]] disabling display
>[  436.933121] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  436.933154] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  436.933179] [drm:intel_power_well_disable [i915]] disabling always-on
>[  436.945202] [drm:intel_power_well_enable [i915]] enabling always-on
>[  436.945220] [drm:intel_power_well_enable [i915]] enabling display
>[  436.945238] [drm:hsw_set_power_well [i915]] Enabling power well
>[  437.168993] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  437.169020] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  437.170011] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  437.170033] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  437.170054] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  437.170075] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  437.170095] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  437.170116] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  437.170137] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  437.170158] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  437.170178] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  437.170199] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  437.170220] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  437.170241] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  437.170264] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  437.170293] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  437.170320] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  437.170347] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  437.170373] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  437.170398] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  437.170423] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  437.170449] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  437.170475] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  437.170500] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  437.170525] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  437.170550] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  437.170575] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  437.170600] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  437.170625] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  437.170650] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  437.170675] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  437.170700] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  437.170725] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  437.171433] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  437.171462] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  437.171490] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  437.171517] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  437.173980] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  437.174012] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  437.174041] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  437.174068] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  437.174095] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  437.174122] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  437.174148] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  437.174174] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  437.174200] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  437.174226] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  437.174255] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  437.174282] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  437.174326] [drm] Memory usable by graphics device = 4096M
>[  437.174357] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  437.174388] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  437.174398] [drm] Replacing VGA console driver
>[  437.174481] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  437.174613] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  437.174672] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  437.174703] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  437.179838] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  437.179868] [drm:intel_opregion_setup [i915]] ASLE supported
>[  437.179895] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  437.179923] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  437.180096] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  437.180104] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  437.180106] [drm] Driver supports precise vblank timestamp query.
>[  437.180134] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  437.180162] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  437.180190] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  437.180217] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  437.182291] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  437.182319] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  437.182342] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  437.182369] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  437.182375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  437.182396] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  437.182421] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  437.182451] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  437.182454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  437.182481] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  437.182510] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  437.182537] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  437.182564] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  437.182590] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  437.182617] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  437.182643] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  437.182669] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  437.183107] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  437.183153] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  437.183258] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.183301] [drm:intel_power_well_enable [i915]] enabling display
>[  437.185083] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  437.185119] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  437.185148] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  437.185176] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  437.185203] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  437.185229] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  437.185255] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  437.185281] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  437.185308] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  437.185333] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  437.185359] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  437.185384] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  437.185409] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  437.185434] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  437.185459] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  437.185484] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  437.185519] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  437.186314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  437.186642] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  437.186675] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  437.187037] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  437.187079] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  437.187185] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  437.187221] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  437.187296] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  437.187333] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  437.187503] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  437.187538] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  437.187575] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  437.187606] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  437.187642] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  437.187672] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  437.187704] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  437.187734] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  437.187801] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  437.187828] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  437.187855] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  437.187879] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  437.187908] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  437.187936] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  437.187961] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  437.187986] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  437.188009] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  437.188051] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  437.188081] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  437.188110] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  437.188148] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  437.188175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  437.188202] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  437.188227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.188235] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.188260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.188265] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.188291] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  437.188315] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  437.188340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.188363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.188394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  437.188418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.188444] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  437.188468] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  437.188493] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  437.188521] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  437.188544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  437.188568] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  437.188591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.188597] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.188620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.188625] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.188649] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  437.188672] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  437.188697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.188719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.188763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  437.188787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.188812] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  437.188836] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  437.188860] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  437.188887] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  437.188911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  437.188935] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  437.188957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.188963] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.188986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.188991] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  437.189016] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  437.189039] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  437.189063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.189086] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.189115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  437.189138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.189163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  437.189187] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  437.189211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  437.189241] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  437.189268] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  437.189294] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  437.189340] [drm:intel_power_well_disable [i915]] disabling display
>[  437.189411] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  437.189438] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.189773] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  437.189845] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  437.190064] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  437.191406] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  437.191432] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  437.191459] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  437.191483] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  437.191508] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  437.191530] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  437.191552] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  437.192059] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  437.192093] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  437.192123] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  437.192153] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  437.194876] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  437.195324] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  437.196135] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  437.205526] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  437.206160] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input11
>[  437.206880] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  437.206883] [drm] DRM_I915_DEBUG enabled
>[  437.206890] [drm:drm_setup_crtcs] 
>[  437.206895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  437.206896] [drm] DRM_I915_DEBUG_GEM enabled
>[  437.206941] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  437.206989] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.208801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  437.208849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  437.210785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  437.210795] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  437.212789] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  437.212815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  437.214841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  437.214852] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  437.214884] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.214891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  437.214907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  437.214912] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  437.214947] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  437.214980] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.216159] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  437.217077] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  437.217113] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  437.217145] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  437.217175] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  437.218193] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  437.218227] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  437.231789] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  437.232686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.232693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  437.232948] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  437.232953] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  437.233011] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  437.233013] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  437.233018] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  437.233020] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  437.233024] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  437.233026] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  437.233034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  437.233037] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  437.233039] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  437.233042] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  437.233045] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  437.233047] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  437.233050] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  437.233053] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  437.233055] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  437.233058] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  437.233060] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  437.233063] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  437.233066] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  437.233068] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  437.233071] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  437.233073] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  437.233076] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  437.233079] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  437.233081] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  437.233084] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  437.233086] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  437.233089] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  437.233092] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  437.233094] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  437.233097] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  437.233099] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  437.233102] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  437.233104] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  437.233107] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  437.233110] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  437.233112] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  437.233116] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  437.233147] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  437.233173] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.235266] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  437.235297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  437.237383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  437.237390] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  437.239478] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  437.239507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  437.241591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  437.241598] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  437.241626] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.241631] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  437.241634] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  437.241649] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  437.241652] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  437.241654] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  437.241687] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  437.241694] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  437.241696] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  437.241699] [drm:drm_setup_crtcs] found mode 1920x1200
>[  437.241701] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  437.241710] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  437.241794] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  437.242500] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  437.243054] fbcon: inteldrmfb (fb0) is primary device
>[  437.243699] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  437.243733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  437.243785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  437.243820] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  437.243849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  437.243882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  437.243915] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  437.243945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  437.243974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  437.244001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  437.244028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.244033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  437.244059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.244064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  437.244090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  437.244117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  437.244142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.244168] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  437.244199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  437.244225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.244250] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  437.244275] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  437.244299] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  437.244329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  437.244362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  437.244593] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.244630] [drm:intel_power_well_enable [i915]] enabling display
>[  437.244664] [drm:hsw_set_power_well [i915]] Enabling power well
>[  437.244744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  437.244789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  437.244820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  437.244849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  437.244877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  437.244906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  437.244944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  437.244973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  437.245002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  437.245027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  437.245052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  437.245147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  437.245182] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  437.247339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  437.247371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  437.247402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.247427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  437.248978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  437.249001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  437.249025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.250544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  437.250568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  437.252395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  437.255452] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  437.255513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  437.255537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  437.255624] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  437.255683] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  437.255716] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  437.272389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  437.272425] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  437.272477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  437.272638] Console: switching to colour frame buffer device 240x75
>[  437.292686] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  437.304660] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  437.314229] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.314268] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.314293] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.314333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  437.314356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  437.314379] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.314402] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.314424] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.315351] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  437.315364] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  437.315368] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  437.315371] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  437.315374] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  437.315378] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  437.318433] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input12
>[  437.319941] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input13
>[  437.320562] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input14
>[  437.321405] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input15
>[  437.322066] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input16
>[  437.324423] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  437.362976] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input17
>[  437.363483] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input18
>[  437.539286] [IGT] drv_module_reload: exiting, ret=0
>[  437.675698] Console: switching to colour dummy device 80x25
>[  437.675860] [IGT] drv_module_reload: executing
>[  437.676201] [IGT] drv_module_reload: starting subtest basic-no-display
>[  437.697839] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  437.697845] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  437.723832] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  437.723838] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  437.755160] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.755198] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.755217] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  437.755238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  437.755254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  437.755270] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.755285] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.755301] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.794936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  437.806073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  437.806131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  437.825056] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  437.825151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  437.825175] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  437.825200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  437.825217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  437.825236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  437.825251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  437.825266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  437.825283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  437.825300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  437.825317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  437.825333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  437.825349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  437.825363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  437.825377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  437.825409] [drm:intel_power_well_disable [i915]] disabling display
>[  437.825456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  437.825480] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  437.825497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.837217] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.837233] [drm:intel_power_well_enable [i915]] enabling display
>[  437.837249] [drm:hsw_set_power_well [i915]] Enabling power well
>[  437.937244] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  437.937271] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  437.937923] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  437.937953] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  437.937982] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  437.938009] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  437.938035] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  437.938062] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  437.938088] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  437.938115] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  437.938137] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  437.938158] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  437.938179] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  437.938200] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  437.938221] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  437.938242] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  437.938263] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  437.938287] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  437.938315] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  437.938343] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  437.938369] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  437.938395] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  437.938421] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  437.938446] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  437.938473] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  437.938498] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  437.938523] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  437.938548] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  437.938573] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  437.938598] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  437.938623] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  437.938649] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  437.938674] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  437.938699] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  437.938723] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  437.938749] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  437.938773] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  437.941990] [drm] Display disabled (module parameter)
>[  437.942025] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  437.942046] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  437.942067] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  437.942087] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  437.942108] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  437.942129] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  437.942150] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  437.942170] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  437.942191] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  437.942212] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  437.942232] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  437.942252] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  437.942292] [drm] Memory usable by graphics device = 4096M
>[  437.942316] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  437.942347] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  437.942354] [drm] Replacing VGA console driver
>[  437.942411] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  437.942552] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  437.942611] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  437.942641] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  437.947928] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  437.947960] [drm:intel_opregion_setup [i915]] ASLE supported
>[  437.947987] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  437.948012] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  437.948183] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  437.948213] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  437.948238] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  437.948263] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  437.948285] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  437.949837] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  437.949873] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  437.949898] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  437.949925] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  437.949930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  437.949949] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  437.949968] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  437.949988] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  437.949991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  437.950009] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  437.950029] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  437.950047] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  437.950064] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  437.950080] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  437.950103] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  437.950127] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  437.950152] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  437.950409] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  437.950441] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  437.950520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.950552] [drm:intel_power_well_enable [i915]] enabling display
>[  437.952049] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  437.952074] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  437.952096] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  437.952117] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  437.952138] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  437.952159] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  437.952180] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  437.952201] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  437.952222] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  437.952243] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  437.952263] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  437.952284] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  437.952305] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  437.952326] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  437.952347] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  437.952368] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  437.952425] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  437.952477] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  437.952685] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  437.955904] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  437.955932] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  437.955958] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  437.955988] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  437.956018] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  437.956047] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  437.956072] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  437.957199] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  437.958264] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  437.958268] [drm] DRM_I915_DEBUG enabled
>[  437.958270] [drm] DRM_I915_DEBUG_GEM enabled
>[  437.964283] [IGT] drv_module_reload: exiting, ret=0
>[  437.970656] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  437.970666] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  437.974441] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  437.974450] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  437.974453] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  437.974457] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  437.974459] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  437.974463] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  438.024281] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input19
>[  438.025447] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input20
>[  438.110051] [IGT] drv_module_reload: executing
>[  438.110389] [IGT] drv_module_reload: starting subtest basic-reload-inject
>[  438.241025] Setting dangerous option inject_load_failure - tainting kernel
>[  438.250860] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  438.250887] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  438.251692] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  438.251722] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  438.251750] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  438.251777] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  438.251890] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  438.251917] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  438.251944] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  438.251970] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  438.251996] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  438.252022] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  438.252049] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  438.252075] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  438.252101] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  438.252127] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  438.252154] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  438.252180] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  438.252206] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  438.252232] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  438.252257] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  438.252282] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  438.252307] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  438.252332] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  438.252357] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  438.252382] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  438.252407] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  438.252432] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  438.252457] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  438.252482] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  438.252506] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  438.252531] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  438.252555] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  438.252580] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  438.252604] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  438.252628] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  438.252653] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  438.255465] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  438.255491] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  438.255513] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  438.255534] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  438.255554] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  438.255574] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  438.255594] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  438.255620] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  438.255642] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  438.255668] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  438.255689] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  438.255708] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  438.255743] [drm] Memory usable by graphics device = 4096M
>[  438.255766] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  438.255791] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  438.255835] [drm] Replacing VGA console driver
>[  438.255922] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  438.256084] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  438.256146] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  438.256176] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  438.261867] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  438.261903] [drm:intel_opregion_setup [i915]] ASLE supported
>[  438.261933] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  438.261963] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  438.262138] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  438.262146] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  438.262148] [drm] Driver supports precise vblank timestamp query.
>[  438.262177] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  438.262205] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  438.262234] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  438.262262] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  438.263852] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  438.263878] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  438.263901] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  438.263927] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  438.263932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  438.263951] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  438.263970] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  438.263991] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  438.263995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  438.264012] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  438.264033] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  438.264050] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  438.264068] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  438.264084] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  438.264101] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  438.264125] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  438.264150] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  438.264417] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  438.264450] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  438.264528] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.264557] [drm:intel_power_well_enable [i915]] enabling display
>[  438.266057] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  438.266084] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  438.266106] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  438.266128] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  438.266150] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  438.266171] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  438.266192] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  438.266214] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  438.266235] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  438.266256] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  438.266277] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  438.266298] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  438.266319] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  438.266340] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  438.266361] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  438.266382] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  438.266409] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  438.266646] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  438.267649] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  438.267683] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  438.268050] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  438.268092] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  438.268199] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  438.268237] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  438.268317] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  438.268352] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  438.268532] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  438.268568] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  438.268606] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  438.268639] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  438.268676] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  438.268707] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  438.268739] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  438.268770] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  438.268800] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  438.269244] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  438.269275] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  438.269301] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  438.269330] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  438.269357] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  438.269383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  438.269408] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  438.269434] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  438.269476] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  438.269505] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  438.269533] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  438.269565] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  438.269591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  438.269616] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  438.269641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.269647] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.269671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.269675] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.269701] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  438.269726] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  438.269751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.269776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.269808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  438.269870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.269902] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  438.269933] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  438.269962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  438.269993] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  438.270021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  438.270048] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  438.270075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.270081] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.270107] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.270112] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.270139] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  438.270165] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  438.270191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.270216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.270248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  438.270274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.270301] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  438.270326] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  438.270353] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  438.270380] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  438.270406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  438.270431] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  438.270456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.270462] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.270487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.270492] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  438.270517] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  438.270542] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  438.270567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.270592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.270623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  438.270649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.270675] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  438.270700] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  438.270726] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  438.270758] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  438.270786] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  438.270828] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  438.270877] [drm:intel_power_well_disable [i915]] disabling display
>[  438.270954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  438.270983] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.271370] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  438.271444] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  438.271673] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  438.274250] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  438.274279] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  438.274309] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  438.274339] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  438.274370] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  438.274399] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  438.274424] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  438.274892] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  438.274917] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  438.274943] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  438.274968] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  438.275243] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  438.275300] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.276163] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  438.276603] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  438.277069] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  438.277116] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  438.277595] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  438.278843] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  438.278853] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  438.280851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  438.280886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  438.282862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  438.282872] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.282905] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.282912] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  438.282949] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  438.282981] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.284195] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  438.285111] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  438.285148] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  438.285180] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  438.285208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  438.286222] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  438.286255] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.289935] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  438.290934] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input21
>[  438.291623] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  438.291626] [drm] DRM_I915_DEBUG enabled
>[  438.291629] [drm] DRM_I915_DEBUG_GEM enabled
>[  438.299981] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  438.300924] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.300932] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  438.300970] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  438.301001] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.302851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.302886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.304848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.304858] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  438.306832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.306857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.308848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.308859] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.308893] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.308900] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  438.309162] [drm:drm_setup_crtcs] 
>[  438.309167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  438.309201] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  438.309259] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.310857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  438.310906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  438.312899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  438.312910] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  438.314873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  438.314902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  438.316857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  438.316864] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.316890] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.316898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  438.316902] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  438.316929] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  438.316954] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.318204] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  438.319101] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  438.319126] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  438.319147] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  438.319167] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  438.320158] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  438.320181] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.321205] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.321353] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  438.321356] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  438.321396] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.321399] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.321403] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  438.321406] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  438.321410] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.321412] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.321419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  438.321422] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  438.321425] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.321427] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.321430] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.321433] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.321435] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  438.321438] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  438.321440] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.321443] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.321446] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  438.321448] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.321451] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.321453] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  438.321456] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.321458] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.321461] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  438.321464] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.321466] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.321469] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  438.321471] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  438.321474] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  438.321477] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  438.321479] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  438.321482] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  438.321484] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.321487] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.321490] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  438.321492] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.321495] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.321497] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  438.321500] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  438.321526] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  438.321549] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.322862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.322890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.324852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.324858] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  438.326875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.326902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.328863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.328869] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.328895] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.328899] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  438.328912] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  438.328914] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  438.328916] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  438.328946] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  438.328952] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  438.328955] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  438.328957] [drm:drm_setup_crtcs] found mode 1920x1200
>[  438.328960] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  438.328967] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  438.329002] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  438.329636] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  438.330040] fbcon: inteldrmfb (fb0) is primary device
>[  438.330524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  438.330559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  438.330596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  438.330632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  438.330662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  438.330706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  438.330738] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  438.330767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  438.330795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  438.330839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  438.330865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.330870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  438.330895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.330899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  438.330925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  438.330951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  438.330975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.331000] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  438.331031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  438.331057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.331083] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  438.331108] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  438.331133] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  438.331163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  438.331196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  438.331405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.331442] [drm:intel_power_well_enable [i915]] enabling display
>[  438.331477] [drm:hsw_set_power_well [i915]] Enabling power well
>[  438.331558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  438.331589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  438.331618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  438.331645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  438.331671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  438.331700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  438.331736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  438.331765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  438.331794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  438.331833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  438.331858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  438.331929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  438.331965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  438.334077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  438.334109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  438.334137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  438.334166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  438.335711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  438.335733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  438.335753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  438.337268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  438.337289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  438.339114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  438.342209] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  438.342286] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  438.342313] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  438.342410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  438.342467] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  438.342501] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  438.359106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  438.359139] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  438.359185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  438.359334] Console: switching to colour frame buffer device 240x75
>[  438.379438] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  438.388184] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  438.391291] Console: switching to colour dummy device 80x25
>[  438.398338] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.398379] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.398405] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.398446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  438.398470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  438.398494] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.398518] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.398541] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.402744] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  438.402760] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.402763] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.402766] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  438.402769] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  438.402773] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  438.414743] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input22
>[  438.415973] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input23
>[  438.418657] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input24
>[  438.418988] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input25
>[  438.419741] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input26
>[  438.456667] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input27
>[  438.457497] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input28
>[  438.460869] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.460911] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.460936] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  438.460966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  438.460991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  438.461015] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.461039] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.461063] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.532955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  438.542522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  438.542571] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  438.561486] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  438.561580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  438.561605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  438.561632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  438.561653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  438.561677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  438.561699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  438.561720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  438.561741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  438.561764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  438.561786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  438.561807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  438.561878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  438.561903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  438.561928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  438.561978] [drm:intel_power_well_disable [i915]] disabling display
>[  438.562051] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  438.562088] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  438.562110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.570180] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.570196] [drm:intel_power_well_enable [i915]] enabling display
>[  438.570213] [drm:hsw_set_power_well [i915]] Enabling power well
>[  438.664859] Setting dangerous option inject_load_failure - tainting kernel
>[  438.674902] [drm] Injecting failure at checkpoint 1 [i915_driver_init_early:810]
>[  438.674936] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  438.681013] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  438.681023] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  438.688771] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  438.688777] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.688779] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.688781] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  438.688782] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  438.688784] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  438.738680] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input29
>[  438.741359] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input30
>[  438.846926] Setting dangerous option inject_load_failure - tainting kernel
>[  438.857820] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  438.857856] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  438.858393] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  438.858413] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  438.858432] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  438.858450] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  438.858468] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  438.858486] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  438.858503] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  438.858520] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  438.858540] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  438.858561] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  438.858582] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  438.858603] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  438.858624] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  438.858644] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  438.858665] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  438.858686] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  438.858707] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  438.858736] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  438.858764] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  438.858791] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  438.858817] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  438.859336] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  438.859365] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  438.859393] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  438.859420] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  438.859447] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  438.859473] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  438.859499] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  438.859525] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  438.859551] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  438.859577] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  438.859602] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  438.859628] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  438.859654] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  438.859679] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  438.859684] [drm] Injecting failure at checkpoint 2 [i915_driver_init_mmio:943]
>[  438.871162] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  438.883436] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  438.883443] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  438.889240] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  438.889246] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.889248] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  438.889250] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  438.889251] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  438.889253] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  438.936871] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input31
>[  438.938118] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input32
>[  439.045150] Setting dangerous option inject_load_failure - tainting kernel
>[  439.055068] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  439.055095] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  439.055689] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  439.055710] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  439.055728] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  439.055747] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  439.055764] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  439.055781] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  439.055798] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  439.055815] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  439.055832] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  439.055887] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  439.055915] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  439.055941] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  439.055965] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  439.055991] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  439.056015] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  439.056040] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  439.056064] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  439.056087] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  439.056112] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  439.056135] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  439.056160] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  439.056183] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  439.056207] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  439.056230] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  439.056255] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  439.056278] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  439.056302] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  439.056324] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  439.056348] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  439.056370] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  439.056394] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  439.056416] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  439.056440] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  439.056463] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  439.056488] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  439.058891] [drm] Injecting failure at checkpoint 3 [i915_driver_init_hw:1007]
>[  439.080061] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  439.084556] [IGT] drv_module_reload: exiting, ret=0
>[  439.088061] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  439.088072] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  439.100994] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  439.101003] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  439.101007] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  439.101011] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  439.101014] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  439.101019] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  439.146614] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input33
>[  439.147711] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input34
>[  439.248983] [IGT] drv_module_reload: executing
>[  439.249307] [IGT] drv_module_reload: starting subtest basic-reload-final
>[  439.341444] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  439.341471] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  439.342121] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  439.342143] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  439.342165] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  439.342186] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  439.342207] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  439.342227] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  439.342248] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  439.342269] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  439.342290] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  439.342310] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  439.342331] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  439.342352] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  439.342372] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  439.342393] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  439.342413] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  439.342434] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  439.342455] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  439.342475] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  439.342496] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  439.342517] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  439.342538] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  439.342557] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  439.342575] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  439.342593] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  439.342610] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  439.342627] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  439.342644] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  439.342661] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  439.342677] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  439.342694] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  439.342710] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  439.342726] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  439.342742] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  439.342758] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  439.342774] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  439.345235] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  439.345266] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  439.345294] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  439.345322] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  439.345349] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  439.345376] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  439.345402] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  439.345428] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  439.345455] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  439.345480] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  439.345509] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  439.345533] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  439.345568] [drm] Memory usable by graphics device = 4096M
>[  439.345590] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  439.345612] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  439.345619] [drm] Replacing VGA console driver
>[  439.345678] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  439.345784] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  439.345831] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  439.345858] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  439.351935] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  439.351964] [drm:intel_opregion_setup [i915]] ASLE supported
>[  439.351992] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  439.352019] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  439.352193] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  439.352200] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  439.352202] [drm] Driver supports precise vblank timestamp query.
>[  439.352230] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  439.352257] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  439.352285] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  439.352313] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  439.354388] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  439.354419] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  439.354444] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  439.354474] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  439.354480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  439.354503] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  439.354525] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  439.354549] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  439.354553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  439.354573] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  439.354596] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  439.354624] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  439.354652] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  439.354681] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  439.354710] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  439.354739] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  439.354767] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  439.355189] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  439.355235] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  439.355339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.355380] [drm:intel_power_well_enable [i915]] enabling display
>[  439.357107] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  439.357142] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  439.357171] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  439.357199] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  439.357226] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  439.357252] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  439.357278] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  439.357304] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  439.357330] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  439.357356] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  439.357381] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  439.357407] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  439.357432] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  439.357457] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  439.357482] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  439.357507] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  439.357542] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  439.357864] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  439.358052] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  439.358083] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  439.358444] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  439.358484] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  439.358586] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  439.358622] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  439.358700] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  439.358734] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  439.358990] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  439.359027] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  439.359064] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  439.359096] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  439.359131] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  439.359163] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  439.359195] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  439.359226] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  439.359256] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  439.359283] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  439.359310] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  439.359337] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  439.359366] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  439.359395] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  439.359421] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  439.359447] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  439.359473] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  439.359516] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  439.359547] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  439.359578] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  439.359618] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  439.359646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  439.359674] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  439.359700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.359707] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.359733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.359739] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.359765] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  439.359792] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  439.359818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.359844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.360013] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  439.360045] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.360074] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  439.360103] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  439.360131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  439.360160] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  439.360187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  439.360214] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  439.360241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.360246] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.360271] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.360277] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.360303] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  439.360329] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  439.360355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.360380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.360411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  439.360437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.360462] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  439.360488] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  439.360513] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  439.360541] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  439.360567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  439.360592] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  439.360617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.360622] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.360647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.360653] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  439.360678] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  439.360703] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  439.360729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.360754] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.360786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  439.360811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.360837] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  439.360863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  439.361035] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  439.361070] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  439.361101] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  439.361129] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  439.361177] [drm:intel_power_well_disable [i915]] disabling display
>[  439.361251] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  439.361277] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.361492] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  439.361545] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  439.361696] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  439.364373] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  439.364414] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  439.364456] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  439.364486] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  439.364512] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  439.364537] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  439.364559] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  439.365150] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  439.365177] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  439.365203] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  439.365227] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  439.365498] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  439.365546] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.366862] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  439.367637] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  439.368462] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  439.369046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  439.369096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  439.370907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  439.370915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  439.372970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  439.372994] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  439.375063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  439.375074] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  439.375106] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.375113] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  439.375150] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  439.375182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.376360] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  439.377259] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  439.377284] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  439.377305] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  439.377325] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  439.378323] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  439.378350] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  439.379328] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  439.380212] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input35
>[  439.380802] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  439.380805] [drm] DRM_I915_DEBUG enabled
>[  439.380807] [drm] DRM_I915_DEBUG_GEM enabled
>[  439.392012] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  439.393088] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.393096] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  439.393134] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  439.393167] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.394921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  439.394946] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  439.396899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  439.396906] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  439.398913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  439.398950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  439.400931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  439.400939] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  439.400967] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.400972] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  439.401331] [drm:drm_setup_crtcs] 
>[  439.401337] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  439.401373] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  439.401442] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.401744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  439.401957] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  439.403962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  439.403970] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  439.405944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  439.405971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  439.408022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  439.408029] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  439.408055] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.408063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  439.408066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  439.408094] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  439.408119] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.409203] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  439.410103] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  439.410127] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  439.410151] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  439.410176] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  439.411172] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  439.411196] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  439.412169] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.412315] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  439.412318] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  439.412357] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  439.412360] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  439.412364] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  439.412366] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  439.412371] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  439.412373] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  439.412379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  439.412382] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  439.412385] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  439.412388] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  439.412390] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  439.412393] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  439.412396] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  439.412398] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  439.412401] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  439.412404] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  439.412406] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  439.412409] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  439.412411] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  439.412414] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  439.412416] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  439.412419] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  439.412422] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  439.412424] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  439.412427] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  439.412430] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  439.412432] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  439.412435] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  439.412437] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  439.412440] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  439.412443] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  439.412445] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  439.412448] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  439.412450] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  439.412453] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  439.412455] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  439.412458] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  439.412461] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  439.412487] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  439.412510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.413912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  439.413941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  439.415933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  439.415939] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  439.417928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  439.417956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  439.419940] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  439.419946] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  439.419971] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.419975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  439.419988] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  439.419991] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  439.419993] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  439.420022] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  439.420029] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  439.420032] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  439.420034] [drm:drm_setup_crtcs] found mode 1920x1200
>[  439.420036] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  439.420044] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  439.420078] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  439.420705] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  439.421060] fbcon: inteldrmfb (fb0) is primary device
>[  439.421537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  439.421570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  439.421604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  439.421638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  439.421666] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  439.421698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.421729] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  439.421759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  439.421786] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  439.421813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  439.421838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.421843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  439.421868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.421892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  439.421918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  439.421944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  439.421969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.421993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  439.422024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  439.422050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.422075] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  439.422101] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  439.422127] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  439.422156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.422189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  439.422397] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.422435] [drm:intel_power_well_enable [i915]] enabling display
>[  439.422469] [drm:hsw_set_power_well [i915]] Enabling power well
>[  439.422552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  439.422583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  439.422613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  439.422641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  439.422668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  439.422697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  439.422734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  439.422763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  439.422793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  439.422819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  439.422844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  439.422932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  439.422969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  439.426145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.426169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.426189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.426211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.429943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  439.429971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  439.429998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.432615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.432642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  439.435550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.438625] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  439.438679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  439.438703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  439.438785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.438833] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  439.438871] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  439.455507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  439.455541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  439.455591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  439.455749] Console: switching to colour frame buffer device 240x75
>[  439.475882] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  439.485451] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  439.490529] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  439.496787] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.496819] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.496839] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.496868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.497086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.497115] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.497140] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.497166] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.499303] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  439.499319] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  439.499323] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  439.499326] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  439.499329] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  439.499332] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  439.501703] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input36
>[  439.503140] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input37
>[  439.503781] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input38
>[  439.508294] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input39
>[  439.509180] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input40
>[  439.548007] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input41
>[  439.548731] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input42
>[  439.739119] [IGT] drv_module_reload: exiting, ret=0
>[  439.884959] Console: switching to colour dummy device 80x25
>[  439.885056] [IGT] gvt_basic: executing
>[  439.981994] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.982035] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.982061] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  439.982091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.982115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  439.982140] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.982164] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.982188] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  440.022052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.022619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  440.022674] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  440.040882] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  440.041000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  440.041031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  440.041061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.041082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  440.041106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  440.041127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  440.041148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  440.041169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  440.041192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  440.041213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  440.041235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  440.041256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  440.041276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  440.041295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  440.041329] [drm:intel_power_well_disable [i915]] disabling display
>[  440.041387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  440.041415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  440.041433] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.053342] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.053359] [drm:intel_power_well_enable [i915]] enabling display
>[  440.053375] [drm:hsw_set_power_well [i915]] Enabling power well
>[  440.147146] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  440.147173] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  440.148017] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x162b rev=0x09
>[  440.148047] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  440.148075] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  440.148101] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  440.148127] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  440.148153] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  440.148179] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  440.148205] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  440.148230] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  440.148256] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  440.148281] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  440.148306] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  440.148331] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  440.148358] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  440.148384] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  440.148410] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  440.148435] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  440.148461] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  440.148486] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  440.148512] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  440.148537] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  440.148562] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  440.148586] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  440.148612] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  440.148636] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  440.148661] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  440.148687] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  440.148712] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  440.148736] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  440.148761] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  440.148786] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  440.148810] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  440.148834] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  440.148859] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  440.148884] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  440.151125] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  440.151158] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  440.151186] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  440.151213] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  440.151240] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  440.151267] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  440.151293] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  440.151320] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  440.151345] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  440.151371] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  440.151399] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  440.151426] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  440.151467] [drm] Memory usable by graphics device = 4096M
>[  440.151498] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  440.151528] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  440.151538] [drm] Replacing VGA console driver
>[  440.151623] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  440.151774] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  440.151835] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  440.151865] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  440.158979] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  440.159009] [drm:intel_opregion_setup [i915]] ASLE supported
>[  440.159034] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  440.159056] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  440.159228] [drm:intel_gvt_init [i915]] Not in host or MPT modules not found
>[  440.159235] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  440.159237] [drm] Driver supports precise vblank timestamp query.
>[  440.159264] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  440.159288] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  440.159310] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  440.159331] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  440.161022] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  440.161060] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  440.161093] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  440.161127] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  440.161132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  440.161152] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  440.161172] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  440.161199] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  440.161203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  440.161229] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  440.161258] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  440.161284] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  440.161309] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  440.161335] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  440.161360] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  440.161386] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  440.161411] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  440.161673] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  440.161706] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  440.161785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.161817] [drm:intel_power_well_enable [i915]] enabling display
>[  440.163585] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  440.163620] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  440.163650] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  440.163678] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  440.163705] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  440.163732] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  440.163758] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  440.163784] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  440.163810] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  440.163836] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  440.163861] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  440.163886] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  440.163912] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  440.163976] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  440.164000] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  440.164023] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  440.164057] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  440.164386] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  440.164920] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  440.165083] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  440.165448] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  440.165490] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  440.165596] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  440.165633] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  440.165710] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  440.165745] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  440.166175] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  440.166211] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  440.166250] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  440.166282] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  440.166319] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  440.166350] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  440.166382] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  440.166413] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  440.166444] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  440.166472] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  440.166499] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  440.166525] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  440.166554] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  440.166583] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  440.166609] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  440.166636] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  440.166662] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  440.166707] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  440.166739] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  440.166770] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  440.166809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  440.166838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  440.166867] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  440.166894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.167515] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.167551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.167557] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.167590] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  440.167620] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  440.167650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.167679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.167713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  440.167742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.167769] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  440.167793] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  440.167819] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  440.167849] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  440.167876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  440.167902] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  440.167960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.167966] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.167993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.168000] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.168028] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  440.168054] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  440.168082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.168108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.168139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  440.168165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.168191] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  440.168217] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  440.168242] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  440.168270] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  440.168295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  440.168320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  440.168345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.168351] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.168375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.168381] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  440.168405] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  440.168431] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  440.168455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.168480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.168510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  440.168536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.168561] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  440.168587] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  440.168613] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  440.168646] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  440.168675] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  440.168702] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  440.168752] [drm:intel_power_well_disable [i915]] disabling display
>[  440.168829] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  440.168858] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.169275] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  440.169355] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  440.169576] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  440.170876] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  440.170912] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  440.171057] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  440.171095] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  440.171134] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  440.171168] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  440.171191] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  440.171739] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  440.171765] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  440.171790] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  440.171815] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  440.173281] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  440.174129] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  440.175152] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  440.184737] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  440.185377] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input43
>[  440.185788] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  440.185791] [drm] DRM_I915_DEBUG enabled
>[  440.185795] [drm:drm_setup_crtcs] 
>[  440.185796] [drm] DRM_I915_DEBUG_GEM enabled
>[  440.185802] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  440.185846] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  440.185905] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.187986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.188034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.189958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  440.189967] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  440.192103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.192140] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  440.194207] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  440.194217] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.194242] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.194249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  440.194262] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  440.194266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  440.194295] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  440.194320] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.196131] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  440.197114] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  440.197150] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  440.197181] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  440.197211] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  440.198216] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  440.198240] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  440.211934] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  440.212829] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.212837] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  440.213050] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  440.213053] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  440.213094] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.213097] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.213101] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  440.213104] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  440.213108] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.213110] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.213117] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  440.213120] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  440.213122] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.213125] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.213128] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.213130] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.213133] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  440.213136] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  440.213138] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.213141] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.213144] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  440.213146] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  440.213149] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  440.213152] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  440.213155] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.213157] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.213160] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  440.213162] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.213165] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.213168] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  440.213170] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  440.213173] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  440.213176] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  440.213178] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  440.213181] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  440.213184] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.213186] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.213189] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  440.213191] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.213194] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.213197] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  440.213200] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  440.213231] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  440.213254] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.215346] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  440.215375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  440.217453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  440.217460] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  440.219537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  440.219563] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  440.221647] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  440.221654] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.221681] [drm:intel_power_well_disable [i915]] disabling always-on
>[  440.221686] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  440.221689] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  440.221702] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  440.221705] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  440.221707] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  440.221740] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  440.221746] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  440.221749] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  440.221752] [drm:drm_setup_crtcs] found mode 1920x1200
>[  440.221754] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  440.221762] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  440.221801] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  440.222554] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  440.222842] fbcon: inteldrmfb (fb0) is primary device
>[  440.223258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  440.223283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  440.223310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  440.223338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  440.223362] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  440.223388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  440.223413] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  440.223438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  440.223462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  440.223487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  440.223511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.223514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  440.223538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.223541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  440.223566] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  440.223590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  440.223614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.223639] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  440.223665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  440.223689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.223714] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  440.223738] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  440.223762] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  440.223788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  440.223816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  440.224026] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.224052] [drm:intel_power_well_enable [i915]] enabling display
>[  440.224075] [drm:hsw_set_power_well [i915]] Enabling power well
>[  440.224133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  440.224158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  440.224183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  440.224209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  440.224233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  440.224258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  440.224291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  440.224318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  440.224344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  440.224369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  440.224393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  440.224474] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  440.224511] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  440.227930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  440.227976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  440.228000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.228026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  440.230644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  440.230669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  440.230691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.233322] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  440.233348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  440.236278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  440.239371] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  440.239446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  440.239467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  440.239551] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  440.239604] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  440.239630] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  440.256322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  440.256356] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  440.256403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  440.256555] Console: switching to colour frame buffer device 240x75
>[  440.276642] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  440.285191] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  440.289674] [IGT] gvt_basic: exiting, ret=77
>[  440.297059] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  440.297102] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  440.297129] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  440.297174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  440.297197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  440.297219] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  440.297241] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  440.297263] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  440.299494] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  440.299507] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  440.299510] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  440.299513] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  440.299515] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  440.299519] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  440.304830] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input44
>[  440.309815] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input45
>[  440.310487] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input46
>[  440.311116] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input47
>[  440.311636] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input48
>[  440.347922] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input49
>[  440.348386] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input50
>[  440.451026] Console: switching to colour dummy device 80x25
>[  440.451125] [IGT] core_auth: executing
>[  440.452293] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  440.464242] [IGT] core_auth: starting subtest many-magics
>[  446.284245] [IGT] core_auth: exiting, ret=0
>[  446.311701] Console: switching to colour frame buffer device 240x75
>[  446.466380] Console: switching to colour dummy device 80x25
>[  446.466475] [IGT] core_getclient: executing
>[  446.491452] [IGT] core_getclient: exiting, ret=0
>[  446.528574] Console: switching to colour frame buffer device 240x75
>[  446.685787] Console: switching to colour dummy device 80x25
>[  446.685881] [IGT] core_get_client_auth: executing
>[  446.685980] [IGT] core_get_client_auth: starting subtest master-drop
>[  446.695864] [IGT] core_get_client_auth: exiting, ret=0
>[  446.745422] Console: switching to colour frame buffer device 240x75
>[  446.902036] Console: switching to colour dummy device 80x25
>[  446.902128] [IGT] core_get_client_auth: executing
>[  446.902229] [IGT] core_get_client_auth: starting subtest simple
>[  446.927515] [IGT] core_get_client_auth: exiting, ret=0
>[  446.962268] Console: switching to colour frame buffer device 240x75
>[  447.122304] Console: switching to colour dummy device 80x25
>[  447.122480] [IGT] core_getstats: executing
>[  447.147486] [IGT] core_getstats: exiting, ret=0
>[  447.179134] Console: switching to colour frame buffer device 240x75
>[  447.337737] Console: switching to colour dummy device 80x25
>[  447.337833] [IGT] core_getversion: executing
>[  447.347774] [IGT] core_getversion: exiting, ret=0
>[  447.395993] Console: switching to colour frame buffer device 240x75
>[  447.553272] Console: switching to colour dummy device 80x25
>[  447.553421] [IGT] core_prop_blob: executing
>[  447.578526] [IGT] core_prop_blob: starting subtest invalid-get-prop
>[  447.578604] [IGT] core_prop_blob: exiting, ret=0
>[  447.612848] Console: switching to colour frame buffer device 240x75
>[  447.771452] Console: switching to colour dummy device 80x25
>[  447.771550] [IGT] core_prop_blob: executing
>[  447.796527] [IGT] core_prop_blob: starting subtest blob-prop-lifetime
>[  447.796736] [IGT] core_prop_blob: exiting, ret=0
>[  447.829719] Console: switching to colour frame buffer device 240x75
>[  447.982213] Console: switching to colour dummy device 80x25
>[  447.982308] [IGT] core_prop_blob: executing
>[  447.991836] [IGT] core_prop_blob: starting subtest invalid-set-prop-any
>[  447.991940] [IGT] core_prop_blob: exiting, ret=0
>[  448.029884] Console: switching to colour frame buffer device 240x75
>[  448.187481] Console: switching to colour dummy device 80x25
>[  448.187579] [IGT] core_prop_blob: executing
>[  448.212555] [IGT] core_prop_blob: starting subtest invalid-set-prop
>[  448.212632] [IGT] core_prop_blob: exiting, ret=0
>[  448.246745] Console: switching to colour frame buffer device 240x75
>[  448.405764] Console: switching to colour dummy device 80x25
>[  448.405856] [IGT] core_prop_blob: executing
>[  448.415841] [IGT] core_prop_blob: starting subtest blob-prop-validate
>[  448.415966] [IGT] core_prop_blob: exiting, ret=0
>[  448.463606] Console: switching to colour frame buffer device 240x75
>[  448.619851] Console: switching to colour dummy device 80x25
>[  448.619943] [IGT] core_prop_blob: executing
>[  448.629842] [IGT] core_prop_blob: starting subtest blob-multiple
>[  448.630193] [IGT] core_prop_blob: exiting, ret=0
>[  448.680482] Console: switching to colour frame buffer device 240x75
>[  448.842022] Console: switching to colour dummy device 80x25
>[  448.842117] [IGT] core_prop_blob: executing
>[  448.851894] [IGT] core_prop_blob: starting subtest blob-prop-core
>[  448.851984] [IGT] core_prop_blob: exiting, ret=0
>[  448.897329] Console: switching to colour frame buffer device 240x75
>[  449.053724] Console: switching to colour dummy device 80x25
>[  449.053818] [IGT] core_prop_blob: executing
>[  449.063914] [IGT] core_prop_blob: starting subtest invalid-get-prop-any
>[  449.064004] [IGT] core_prop_blob: exiting, ret=0
>[  449.114184] Console: switching to colour frame buffer device 240x75
>[  449.269545] Console: switching to colour dummy device 80x25
>[  449.269639] [IGT] core_setmaster_vs_auth: executing
>[  449.294791] [IGT] core_setmaster_vs_auth: exiting, ret=0
>[  449.331062] Console: switching to colour frame buffer device 240x75
>[  449.490841] Console: switching to colour dummy device 80x25
>[  449.490934] [IGT] drm_read: executing
>[  449.500950] [IGT] drm_read: starting subtest empty-nonblock
>[  449.501016] [IGT] drm_read: exiting, ret=0
>[  449.531231] Console: switching to colour frame buffer device 240x75
>[  449.679155] Console: switching to colour dummy device 80x25
>[  449.679248] [IGT] drm_read: executing
>[  449.688914] [IGT] drm_read: starting subtest short-buffer-block
>[  449.689018] [IGT] drm_read: exiting, ret=0
>[  449.714697] Console: switching to colour frame buffer device 240x75
>[  449.866471] Console: switching to colour dummy device 80x25
>[  449.866644] [IGT] drm_read: executing
>[  449.875946] [IGT] drm_read: starting subtest empty-block
>[  450.876152] [IGT] drm_read: exiting, ret=0
>[  450.899119] Console: switching to colour frame buffer device 240x75
>[  450.915742] [drm:drm_fb_helper_hotplug_event] 
>[  450.915754] [drm:drm_setup_crtcs] 
>[  450.915758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  450.915785] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  450.917881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  450.917910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  450.919978] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  450.919985] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  450.922062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  450.922082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  450.924157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  450.924163] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  450.924168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  450.924171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  450.924193] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  450.925274] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  450.926167] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  450.926184] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  450.926200] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  450.926217] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  450.927217] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  450.927235] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  450.928377] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  450.928380] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  450.928475] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  450.928477] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  450.928482] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  450.928484] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  450.928488] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  450.928490] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  450.928645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  450.928651] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  450.928656] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.928660] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.928665] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  450.928669] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  450.928675] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  450.928680] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  450.928686] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.928690] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.928695] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  450.928701] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  450.928706] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  450.928710] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  450.928715] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  450.928720] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  450.928725] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  450.928730] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  450.928734] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  450.928739] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  450.928744] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  450.928748] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  450.928753] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  450.928758] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  450.928763] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  450.928768] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  450.928772] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  450.928777] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  450.928783] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  450.928788] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  450.928792] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  450.928796] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  450.928821] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  450.930618] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  450.930638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  450.932612] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  450.932617] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  450.934611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  450.934632] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  450.936597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  450.936603] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  450.936607] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  450.936620] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  450.936622] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  450.936624] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  450.936645] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  450.936651] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  450.936653] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  450.936655] [drm:drm_setup_crtcs] found mode 1920x1200
>[  450.936657] [drm:drm_setup_crtcs] picking CRTCs for 1920x1200 config
>[  450.936667] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  451.087526] Console: switching to colour dummy device 80x25
>[  451.087685] [IGT] drm_read: executing
>[  451.112751] [IGT] drm_read: starting subtest invalid-buffer
>[  451.112815] [IGT] drm_read: exiting, ret=0
>[  451.132671] Console: switching to colour frame buffer device 240x75
>[  451.282010] Console: switching to colour dummy device 80x25
>[  451.282101] [IGT] drm_read: executing
>[  451.292043] [IGT] drm_read: starting subtest short-buffer-nonblock
>[  451.292135] [IGT] drm_read: exiting, ret=0
>[  451.316151] Console: switching to colour frame buffer device 240x75
>[  451.468663] Console: switching to colour dummy device 80x25
>[  451.468759] [IGT] drm_read: executing
>[  451.478049] [IGT] drm_read: starting subtest fault-buffer
>[  451.478315] [IGT] drm_read: exiting, ret=0
>[  451.516337] Console: switching to colour frame buffer device 240x75
>[  451.670537] Console: switching to colour dummy device 80x25
>[  451.670690] [IGT] kms_render: executing
>[  451.680085] [IGT] kms_render: starting subtest direct-render
>[  451.680356] [drm:drm_mode_addfb2] [FB:77]
>[  451.680380] [drm:drm_mode_addfb2] [FB:79]
>[  451.680398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  451.680408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  458.927563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.939575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  458.939637] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  458.939733] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  458.957837] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  458.957928] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  458.957952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  458.957977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  458.957994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  458.958012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  458.958028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  458.958088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  458.958114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  458.958144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  458.958164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  458.958180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  458.958197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  458.958211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  458.958226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  458.958264] [drm:intel_power_well_disable [i915]] disabling display
>[  458.958312] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  458.958335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  458.958353] [drm:intel_power_well_disable [i915]] disabling always-on
>[  458.958534] [drm:drm_mode_addfb2] [FB:75]
>[  458.958556] [drm:drm_mode_addfb2] [FB:77]
>[  458.958574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  458.958583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  458.958628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  458.958644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  458.958661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  458.958679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  458.958693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  458.958708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  458.958724] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  458.958739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  458.958753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  458.958766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  458.958779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  458.958783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  458.958795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  458.958799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  458.958812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  458.958825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  458.958837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.958850] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  458.958865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  458.958878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  458.958890] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  458.958908] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  458.958925] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  458.958944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.958963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  458.967737] [drm:intel_power_well_enable [i915]] enabling always-on
>[  458.967761] [drm:intel_power_well_enable [i915]] enabling display
>[  458.967779] [drm:hsw_set_power_well [i915]] Enabling power well
>[  458.967827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  458.967845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  458.967861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  458.967877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  458.967892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  458.967908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  458.967928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  458.967948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  458.967968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  458.967986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  458.968004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  458.968033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  458.968103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  458.971219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  458.971237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  458.971251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.971266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  458.974963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  458.974982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  458.974997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.977568] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  458.977586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  458.980476] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  458.982955] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  458.983032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  458.983088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  458.983137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  458.983241] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  458.983287] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  458.999784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  458.999810] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  458.999848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  466.065799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.072919] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  466.073013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  466.073191] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  466.091139] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  466.091162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  466.091182] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  466.091204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.091224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  466.091246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  466.091266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  466.091285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  466.091305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  466.091327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  466.091347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  466.091368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  466.091389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  466.091408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  466.091427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  466.091456] [drm:intel_power_well_disable [i915]] disabling display
>[  466.091529] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  466.091569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  466.091598] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.091747] [drm:drm_mode_addfb2] [FB:75]
>[  466.091795] [drm:drm_mode_addfb2] [FB:77]
>[  466.091825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  466.091840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  466.091907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  466.091931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.091957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  466.091984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  466.092008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  466.092032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.092056] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  466.092079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  466.092102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  466.092124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.092145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.092151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  466.092172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.092177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  466.092199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  466.092221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  466.092242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.092263] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  466.092287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  466.092310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.092331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  466.092352] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  466.092371] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  466.092395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.092420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  466.100713] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.100732] [drm:intel_power_well_enable [i915]] enabling display
>[  466.100748] [drm:hsw_set_power_well [i915]] Enabling power well
>[  466.100780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  466.100800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  466.100819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  466.100838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  466.100856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  466.100875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  466.100896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  466.100915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  466.100935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  466.100962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  466.100980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  466.101001] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  466.101018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  466.103092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.103109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.103124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.103142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.104650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  466.104666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  466.104681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.106174] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.106190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  466.108005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.110383] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  466.110460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  466.110577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  466.110601] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.110654] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  466.110680] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  466.127205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  466.127231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  466.127266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.547136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.550496] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  473.550524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  473.550573] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  473.568431] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  473.568454] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  473.568474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  473.568496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.568516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  473.568538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  473.568558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  473.568577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  473.568597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  473.568619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  473.568639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  473.568660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  473.568680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.568699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  473.568718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  473.568747] [drm:intel_power_well_disable [i915]] disabling display
>[  473.568771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  473.568797] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  473.568815] [drm:intel_power_well_disable [i915]] disabling always-on
>[  473.568985] [drm:drm_mode_addfb2] [FB:75]
>[  473.569027] [drm:drm_mode_addfb2] [FB:77]
>[  473.569061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  473.569072] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  473.569232] [drm:drm_mode_addfb2] [FB:75]
>[  473.569267] [drm:drm_mode_addfb2] [FB:79]
>[  473.569281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  473.569294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  473.569361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  473.569384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  473.569409] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  473.569436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  473.569457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  473.569480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  473.569502] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  473.569524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  473.569545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  473.569566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  473.569585] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  473.569591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  473.569610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  473.569615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  473.569636] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  473.569656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  473.569676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  473.569695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  473.569718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  473.569737] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  473.569757] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  473.569776] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  473.569796] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  473.569819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.569844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  473.574615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  473.574629] [drm:intel_power_well_enable [i915]] enabling display
>[  473.574642] [drm:hsw_set_power_well [i915]] Enabling power well
>[  473.574672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.574688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  473.574705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  473.574723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  473.574741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  473.574759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  473.574778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  473.574797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  473.574815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.574833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  473.574848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  473.574867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  473.574884] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  473.576915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.576943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.576960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.576978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.578492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  473.578509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  473.578524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.580022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.580040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  473.581871] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.584774] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  473.584830] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  473.584848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  473.584872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  473.601574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  473.601599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.601636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.824358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  480.824471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  480.824508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  480.824583] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  480.826866] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  480.826886] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  480.826907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  480.826924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  480.826942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  480.826958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  480.826973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  480.826989] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  480.827007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  480.827024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  480.827039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  480.827055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.827069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  480.827083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  480.827112] [drm:intel_power_well_disable [i915]] disabling display
>[  480.827134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  480.827158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  480.827174] [drm:intel_power_well_disable [i915]] disabling always-on
>[  480.827296] [drm:drm_mode_addfb2] [FB:75]
>[  480.827319] [drm:drm_mode_addfb2] [FB:79]
>[  480.827338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  480.827376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  480.827451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  480.827471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  480.827491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  480.827511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  480.827527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  480.827544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  480.827562] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  480.827577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  480.827593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  480.827607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  480.827622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  480.827626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  480.827640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  480.827644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  480.827658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  480.827671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  480.827685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  480.827698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  480.827714] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  480.827728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  480.827742] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  480.827756] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  480.827769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  480.827785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  480.827803] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  480.835937] [drm:intel_power_well_enable [i915]] enabling always-on
>[  480.835954] [drm:intel_power_well_enable [i915]] enabling display
>[  480.835968] [drm:hsw_set_power_well [i915]] Enabling power well
>[  480.835999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  480.836017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  480.836033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  480.836050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  480.836069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  480.836088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  480.836109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  480.836129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  480.836148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.836167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  480.836185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  480.836206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  480.836224] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  480.838210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  480.838227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  480.838244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  480.838263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  480.839773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  480.839790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  480.839804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  480.841299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  480.841315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  480.843123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  480.846054] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  480.846133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  480.846150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  480.846173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  480.862879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  480.862906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  480.862941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.899467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  487.899643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  487.899742] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  487.900117] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  487.904347] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  487.904380] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  487.904415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  487.904444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  487.904475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  487.904501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  487.904526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  487.904554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  487.904584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  487.904612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  487.904639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  487.904666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.904690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  487.904714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  487.904761] [drm:intel_power_well_disable [i915]] disabling display
>[  487.904856] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  487.904912] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  487.904954] [drm:intel_power_well_disable [i915]] disabling always-on
>[  487.905121] [drm:drm_mode_addfb2] [FB:75]
>[  487.905146] [drm:drm_mode_addfb2] [FB:79]
>[  487.905164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  487.905174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  487.905218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  487.905236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  487.905254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  487.905274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  487.905291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  487.905309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  487.905326] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  487.905343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  487.905358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  487.905374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  487.905388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  487.905392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  487.905406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  487.905409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  487.905424] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  487.905438] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  487.905451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  487.905466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  487.905482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  487.905496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  487.905510] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  487.905525] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  487.905538] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  487.905555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  487.905573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  487.913972] [drm:intel_power_well_enable [i915]] enabling always-on
>[  487.913990] [drm:intel_power_well_enable [i915]] enabling display
>[  487.914004] [drm:hsw_set_power_well [i915]] Enabling power well
>[  487.914035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  487.914054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  487.914073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  487.914093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  487.914111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  487.914130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  487.914151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  487.914171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  487.914191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.914217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  487.914236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  487.914256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  487.914274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  487.916265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  487.916281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  487.916295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  487.916309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  487.917857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  487.917874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  487.917889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  487.919379] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  487.919396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  487.921197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  487.923679] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  487.923752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  487.923769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  487.924850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  487.940506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  487.940532] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  487.940566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.354669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  495.354846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  495.354934] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  495.355116] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  495.364809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  495.364841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  495.364877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  495.364911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  495.364949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  495.364983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  495.365016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  495.365050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  495.365087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  495.365123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  495.365158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  495.365194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.365226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  495.365314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  495.365393] [drm:intel_power_well_disable [i915]] disabling display
>[  495.365453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  495.365514] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  495.365558] [drm:intel_power_well_disable [i915]] disabling always-on
>[  495.365751] [drm:drm_mode_addfb2] [FB:75]
>[  495.365792] [drm:drm_mode_addfb2] [FB:79]
>[  495.365822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  495.365833] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  495.365989] [drm:drm_mode_addfb2] [FB:75]
>[  495.366012] [drm:drm_mode_addfb2] [FB:80]
>[  495.366029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  495.366038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  495.366083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  495.366101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.366120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  495.366140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  495.366156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  495.366173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.366189] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  495.366206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  495.366221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  495.366266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  495.366292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.366299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  495.366322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.366329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  495.366353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  495.366376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  495.366399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.366421] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  495.366447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  495.366469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.366492] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  495.366514] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  495.366537] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  495.366565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  495.366594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  495.371429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  495.371445] [drm:intel_power_well_enable [i915]] enabling display
>[  495.371458] [drm:hsw_set_power_well [i915]] Enabling power well
>[  495.371488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  495.371504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  495.371518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  495.371532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  495.371545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  495.371562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  495.371582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  495.371601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  495.371619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.371637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  495.371654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  495.371673] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  495.371691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  495.373698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  495.373716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  495.373730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  495.373746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  495.375253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  495.375269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  495.375282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  495.376797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  495.376815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  495.378629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  495.381576] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  495.381640] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  495.381659] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  495.381686] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  495.398383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  495.398409] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  495.398443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  502.606403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  502.606578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  502.606669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.607057] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  502.623169] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  502.623188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  502.623209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  502.623226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  502.623244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  502.623259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  502.623274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  502.623290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  502.623308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  502.623324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  502.623340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  502.623355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  502.623369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  502.623383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  502.623412] [drm:intel_power_well_disable [i915]] disabling display
>[  502.623434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  502.623456] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  502.623471] [drm:intel_power_well_disable [i915]] disabling always-on
>[  502.623623] [drm:drm_mode_addfb2] [FB:75]
>[  502.623648] [drm:drm_mode_addfb2] [FB:80]
>[  502.623704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  502.623721] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  502.623795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  502.623819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  502.623846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  502.623875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  502.623897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  502.623922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  502.623946] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  502.623969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  502.623991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  502.624015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  502.624036] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  502.624041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  502.624063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  502.624069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  502.624091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  502.624111] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  502.624133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  502.624153] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  502.624177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  502.624197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  502.624219] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  502.624239] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  502.624260] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  502.624283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  502.624309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  502.631789] [drm:intel_power_well_enable [i915]] enabling always-on
>[  502.631812] [drm:intel_power_well_enable [i915]] enabling display
>[  502.631834] [drm:hsw_set_power_well [i915]] Enabling power well
>[  502.631865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  502.631881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  502.631897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  502.631915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  502.631933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  502.631951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  502.631970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  502.631988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  502.632007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  502.632024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  502.632041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  502.632060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  502.632078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  502.634073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  502.634091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  502.634106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  502.634121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  502.635630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  502.635646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  502.635660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  502.637199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  502.637216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  502.639026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  502.641570] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  502.641630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  502.641647] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  502.641709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  502.658383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  502.658409] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  502.658445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  509.696338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  509.696514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  509.696603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  509.696750] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  509.698799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  509.698869] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  509.698946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  509.699011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  509.699078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  509.699266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  509.699357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  509.699447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  509.699560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  509.699657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  509.699761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  509.699862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  509.699956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  509.700046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  509.700276] [drm:intel_power_well_disable [i915]] disabling display
>[  509.700414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  509.700547] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  509.700651] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.701014] [drm:drm_mode_addfb2] [FB:75]
>[  509.701217] [drm:drm_mode_addfb2] [FB:80]
>[  509.701282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  509.701339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  509.701614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  509.701718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  509.701825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  509.701905] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  509.701965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  509.702035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.702110] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  509.702276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  509.702367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  509.702455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  509.702538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.702566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  509.702647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.702671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  509.702762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  509.702847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  509.702932] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.703022] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.703123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  509.703279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.703369] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  509.703459] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  509.703548] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  509.703644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  509.703743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  509.719012] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.719031] [drm:intel_power_well_enable [i915]] enabling display
>[  509.719047] [drm:hsw_set_power_well [i915]] Enabling power well
>[  509.719082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  509.719151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  509.719181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  509.719208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  509.719236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  509.719264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  509.719294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  509.719323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  509.719350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  509.719375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  509.719400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  509.719430] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  509.719459] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  509.721484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  509.721503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  509.721519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  509.721536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  509.723058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  509.723076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  509.723093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  509.724626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  509.724645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  509.726469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  509.729012] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  509.729075] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  509.729092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  509.729154] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  509.745824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  509.745850] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  509.745885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  517.156985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  517.157068] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  517.157108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  517.157178] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  517.171056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  517.171077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  517.171100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  517.171120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  517.171142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  517.171162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  517.171181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  517.171201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  517.171223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  517.171243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  517.171264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  517.171285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  517.171304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  517.171323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  517.171352] [drm:intel_power_well_disable [i915]] disabling display
>[  517.171375] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  517.171401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  517.171418] [drm:intel_power_well_disable [i915]] disabling always-on
>[  517.171573] [drm:drm_mode_addfb2] [FB:75]
>[  517.171615] [drm:drm_mode_addfb2] [FB:80]
>[  517.171645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  517.171656] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  517.171969] [IGT] kms_render: exiting, ret=0
>[  517.191798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  517.191817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  517.191837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  517.191860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  517.191879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  517.191899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  517.191919] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  517.191938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  517.191958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  517.191976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  517.191995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  517.192000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  517.192019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  517.192023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  517.192043] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  517.192062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  517.192081] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  517.192100] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  517.192119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  517.192137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  517.192157] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  517.192176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  517.192195] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  517.192215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  517.192237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  517.192312] [drm:intel_power_well_enable [i915]] enabling always-on
>[  517.192339] [drm:intel_power_well_enable [i915]] enabling display
>[  517.192358] [drm:hsw_set_power_well [i915]] Enabling power well
>[  517.192420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  517.192440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  517.192460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  517.192479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  517.192499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  517.192518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  517.192540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  517.192600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  517.192628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  517.192654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  517.192677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  517.192717] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  517.192753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  517.194819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  517.194837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  517.194853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  517.194871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  517.196379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  517.196395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  517.196410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  517.197906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  517.197922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  517.199730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  517.202706] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  517.202739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  517.202756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  517.202790] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  517.202899] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  517.202950] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  517.219493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  517.219519] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  517.219600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  517.236261] Console: switching to colour frame buffer device 240x75
>[  517.377943] Console: switching to colour dummy device 80x25
>[  517.378028] [IGT] kms_setmode: executing
>[  517.389070] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
>[  517.389194] [IGT] kms_setmode: exiting, ret=0
>[  517.436440] Console: switching to colour frame buffer device 240x75
>[  517.586812] [drm:drm_mode_addfb2] [FB:75]
>[  517.650222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  517.650235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  522.653822] [drm:drm_mode_addfb2] [FB:77]
>[  522.725340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  522.725357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  522.725433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  522.725458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  522.725483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  522.725511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  522.725537] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  522.725563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  522.725589] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  522.725615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  522.725641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  522.725667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  522.725692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  522.725697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  522.725723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  522.725728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  522.725754] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  522.725780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  522.725805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  522.725831] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  522.725857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  522.725882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  522.725949] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  522.725982] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  522.726015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  522.726050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  522.726089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  522.741089] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  522.741130] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  522.741215] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  522.759993] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  522.760021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  522.760037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  522.760057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  522.760074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  522.760090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  522.760109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  522.760129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  522.760148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  522.760169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  522.760189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  522.760210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  522.760229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  522.760247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  522.760267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  522.760287] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  522.762257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  522.762273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  522.762288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  522.762304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  522.763817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  522.763832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  522.763846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  522.765340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  522.765355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  522.767159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  522.770084] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  522.770110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  522.770126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  522.770148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  522.770187] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  522.770204] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  522.786850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  522.786880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  522.786941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  527.787621] [drm:drm_mode_addfb2] [FB:75]
>[  527.859164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  527.859208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  527.859286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  527.859311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  527.859337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148352KHz
>[  527.859364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  527.859390] [drm:intel_dp_compute_config [i915]] DP link bw required 445056 available 648000
>[  527.859417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  527.859444] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  527.859470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  527.859496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64
>[  527.859521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  527.859546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  527.859552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  527.859577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  527.859582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  527.859609] [drm:intel_dump_pipe_config [i915]] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  527.859634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148352
>[  527.859660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  527.859685] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  527.859712] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  527.859737] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  527.859764] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  527.859790] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  527.859816] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  527.859844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  527.859873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  527.870519] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  527.870552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  527.870601] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  527.888300] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  527.888323] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  527.888339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  527.888361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  527.888377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  527.888393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  527.888408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  527.888423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  527.888439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  527.888456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  527.888472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  527.888487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  527.888501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  527.888515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  527.888532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  527.888551] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  527.890530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  527.890546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  527.890560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  527.890575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  527.892081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  527.892096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  527.892109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  527.893606] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  527.893622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  527.895429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  527.898361] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  527.898388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  527.898407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  527.898434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  527.898474] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  527.898494] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  527.915178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  527.915222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  527.915256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  532.915913] [drm:drm_mode_addfb2] [FB:77]
>[  532.987821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  532.987837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  532.987913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  532.987940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  532.987967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  532.987994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  532.988019] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  532.988046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  532.988072] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  532.988098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  532.988124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  532.988150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  532.988175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  532.988180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  532.988205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  532.988210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  532.988236] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  532.988262] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  532.988288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  532.988313] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  532.988339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  532.988365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  532.988392] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  532.988418] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  532.988443] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  532.988471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  532.988499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  533.003902] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  533.003928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  533.003967] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  533.022838] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  533.022862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  533.022882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  533.022905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  533.022925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  533.022944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  533.022964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  533.022983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  533.023003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  533.023024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  533.023044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  533.023064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  533.023083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  533.023100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  533.023120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  533.023139] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  533.025120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  533.025137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  533.025151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  533.025166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  533.026654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  533.026669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  533.026686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  533.028162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  533.028177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  533.029966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  533.032902] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  533.032930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  533.032946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  533.032978] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  533.033016] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  533.033034] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  533.049713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  533.049741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  533.049774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  538.050429] [drm:drm_mode_addfb2] [FB:75]
>[  538.121718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  538.121734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  538.121811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  538.121879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  538.121916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  538.121953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  538.121981] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  538.122005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  538.122029] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  538.122055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  538.122082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  538.122108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  538.122133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  538.122139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  538.122164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  538.122170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  538.122196] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  538.122222] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  538.122247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  538.122273] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  538.122299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  538.122325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  538.122351] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  538.122377] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  538.122403] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  538.122431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  538.122460] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  538.133362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  538.133388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  538.133428] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  538.152286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  538.152309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  538.152326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  538.152346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  538.152363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  538.152379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  538.152395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  538.152410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  538.152426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  538.152443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  538.152459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  538.152475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  538.152490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  538.152504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  538.152521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  538.152537] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  538.154513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  538.154528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  538.154542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  538.154557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  538.156045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  538.156060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  538.156076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  538.157553] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  538.157569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  538.159359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  538.162275] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  538.162301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  538.162317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  538.162339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  538.162377] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  538.162393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  538.179080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  538.179109] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  538.179143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  543.179640] [drm:drm_mode_addfb2] [FB:77]
>[  543.224976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  543.224989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  543.225046] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  543.225063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  543.225080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  543.225098] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  543.225147] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  543.225172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  543.225196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  543.225217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  543.225239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  543.225261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  543.225284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  543.225289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  543.225310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  543.225316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  543.225338] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  543.225358] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  543.225379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  543.225398] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  543.225414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  543.225428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  543.225441] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  543.225454] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  543.225467] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  543.225483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  543.225501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  543.234434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  543.234462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  543.234503] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  543.253360] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  543.253383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  543.253400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  543.253421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  543.253438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  543.253454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  543.253469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  543.253484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  543.253501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  543.253518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  543.253535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  543.253551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  543.253566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  543.253580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  543.253597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  543.253616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  543.255595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  543.255611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  543.255625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  543.255640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  543.257177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  543.257192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  543.257206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  543.258702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  543.258719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  543.260540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  543.263496] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  543.263523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  543.263540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  543.263563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  543.263602] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  543.263618] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  543.283622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  543.283653] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  543.283689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  548.284351] [drm:drm_mode_addfb2] [FB:75]
>[  548.353389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  548.353441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  548.353551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  548.353587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.353624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  548.353650] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  548.353670] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  548.353694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.353716] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  548.353738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  548.353759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  548.353779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  548.353798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.353804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  548.353822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.353827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  548.353853] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  548.353878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  548.353904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.353929] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  548.353955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  548.353980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.354007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  548.354032] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  548.354058] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  548.354085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  548.354114] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  548.363932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  548.363958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  548.363999] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.384911] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.384934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  548.384951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  548.384971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  548.384988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  548.385004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  548.385020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  548.385035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  548.385051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  548.385068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  548.385085] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  548.385101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  548.385115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  548.385129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  548.385147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  548.385163] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  548.387149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  548.387166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  548.387181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  548.387196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  548.388697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  548.388714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  548.388729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  548.390208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  548.390224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  548.392016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  548.394952] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  548.394980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  548.394999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  548.395026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  548.395067] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  548.395086] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  548.415112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  548.415142] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  548.415177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  553.415918] [drm:drm_mode_addfb2] [FB:77]
>[  553.461023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  553.461035] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  553.461091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  553.461107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  553.461125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  553.461143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  553.461157] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  553.461173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  553.461189] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  553.461204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  553.461218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  553.461232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  553.461245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  553.461248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  553.461261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  553.461264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  553.461278] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  553.461291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  553.461303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  553.461316] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  553.461331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  553.461344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  553.461358] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  553.461370] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  553.461383] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  553.461398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  553.461416] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  553.475407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  553.475432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  553.475472] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  553.496384] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  553.496407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  553.496423] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  553.496443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  553.496460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  553.496476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  553.496491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  553.496505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  553.496521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  553.496538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  553.496554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  553.496570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  553.496584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  553.496602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  553.496623] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  553.496642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  553.498645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  553.498663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  553.498680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  553.498698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  553.500191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  553.500207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  553.500221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  553.501702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  553.501719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  553.503536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  553.506460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  553.506486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  553.506503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  553.506525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  553.506563] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  553.506579] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  553.539895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  553.539926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  553.539961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  558.540619] [drm:drm_mode_addfb2] [FB:75]
>[  558.587075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  558.587087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  558.587145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  558.587164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  558.587184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  558.587204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  558.587222] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  558.587240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  558.587259] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  558.587277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  558.587295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  558.587313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  558.587331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  558.587334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  558.587352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  558.587355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  558.587373] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  558.587391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  558.587409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  558.587427] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  558.587445] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  558.587463] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  558.587482] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  558.587500] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  558.587518] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  558.587537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  558.587557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  558.606882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  558.606910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  558.606951] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  558.642154] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  558.642178] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  558.642198] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  558.642221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  558.642241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  558.642260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  558.642280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  558.642299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  558.642319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  558.642340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  558.642360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  558.642380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  558.642399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  558.642416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  558.642436] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  558.642455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  558.644434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  558.644451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  558.644465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  558.644480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  558.645972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  558.645987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  558.646001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  558.647482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  558.647498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  558.649287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  558.652233] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  558.652261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  558.652278] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  558.652301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  558.652340] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  558.652356] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  558.685734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  558.685764] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  558.685799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  563.686362] [drm:drm_mode_addfb2] [FB:77]
>[  563.748417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  563.748430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  563.748498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  563.748519] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  563.748541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  563.748563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  563.748580] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  563.748600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  563.748620] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  563.748641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  563.748664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  563.748686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  563.748708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  563.748713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  563.748734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  563.748738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  563.748761] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  563.748783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  563.748804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  563.748826] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  563.748849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  563.748870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  563.748893] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  563.748915] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  563.748937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  563.748960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  563.748985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  563.757781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  563.757807] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.757847] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  563.793059] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  563.793081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  563.793098] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  563.793119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  563.793135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  563.793151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  563.793167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  563.793181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  563.793197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  563.793215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  563.793231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  563.793246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  563.793265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  563.793284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  563.793304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  563.793324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  563.795341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  563.795369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  563.795384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  563.795399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  563.796898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  563.796915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  563.796929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  563.798420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  563.798438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  563.800229] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  563.803157] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  563.803182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  563.803199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  563.803221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  563.803270] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  563.803296] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  563.843263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  563.843294] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  563.843329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  568.844019] [drm:drm_mode_addfb2] [FB:75]
>[  568.915509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  568.915525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  568.915601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  568.915626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  568.915652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  568.915709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  568.915737] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  568.915768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  568.915795] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  568.915823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  568.915852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  568.915878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  568.915904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  568.915911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  568.915938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  568.915943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  568.915969] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  568.915995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  568.916021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  568.916047] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  568.916073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  568.916098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  568.916125] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  568.916151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  568.916177] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  568.916204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  568.916233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  568.923576] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  568.923603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  568.923642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  568.964957] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  568.964980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  568.964997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  568.965018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  568.965035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  568.965051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  568.965070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  568.965090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  568.965109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  568.965130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  568.965151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  568.965171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  568.965190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  568.965207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  568.965227] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  568.965246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  568.967246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  568.967263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  568.967278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  568.967293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  568.968783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  568.968798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  568.968811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  568.970287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  568.970303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  568.972093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  568.975044] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  568.975070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  568.975086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  568.975108] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  568.975147] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  568.975163] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  569.016866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  569.016911] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  569.016966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  574.017650] [drm:drm_mode_addfb2] [FB:77]
>[  574.083885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  574.083897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  574.083954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  574.084003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  574.084028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  574.084055] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  574.084076] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  574.084100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  574.084118] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  574.084133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  574.084147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  574.084161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  574.084174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  574.084177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  574.084194] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  574.084198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  574.084216] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  574.084233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  574.084251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  574.084268] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  574.084286] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  574.084303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  574.084322] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  574.084340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  574.084357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  574.084377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  574.084397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  574.100490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  574.100517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  574.100556] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  574.143931] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  574.143963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  574.144019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  574.144050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  574.144075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  574.144100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  574.144123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  574.144146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  574.144169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  574.144196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  574.144221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  574.144245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  574.144268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  574.144287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  574.144305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  574.144321] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  574.146296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  574.146311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  574.146325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  574.146339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  574.147825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  574.147840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  574.147854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  574.149333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  574.149348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  574.151136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  574.154074] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  574.154102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  574.154119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  574.154141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  574.154180] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  574.154197] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  574.195926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  574.195957] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  574.196060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  579.196733] [drm:drm_mode_addfb2] [FB:75]
>[  579.242614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  579.242626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  579.242680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  579.242698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  579.242717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 162000KHz
>[  579.242738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  579.242755] [drm:intel_dp_compute_config [i915]] DP link bw required 486000 available 648000
>[  579.242773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.242791] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  579.242809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  579.242826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6291456, gmch_n: 8388608, link_m: 262144, link_n: 262144, tu: 64
>[  579.242844] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  579.242861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  579.242864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  579.242881] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  579.242885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  579.242903] [drm:intel_dump_pipe_config [i915]] crtc timings: 162000 1600 1664 1856 2160 1200 1201 1204 1250, type: 0x40 flags: 0x5
>[  579.242920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x1200, pixel rate 162000
>[  579.242937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.242955] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  579.242973] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  579.242990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  579.243008] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  579.243025] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  579.243043] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  579.243061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  579.243081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  579.284687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  579.284728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  579.284790] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  579.328451] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  579.328482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  579.328504] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  579.328531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  579.328553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  579.328574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  579.328594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  579.328614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  579.328636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  579.328659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  579.328680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  579.328702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  579.328721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  579.328740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  579.328763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  579.328784] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  579.330820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  579.330844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  579.330865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  579.330887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  579.332456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  579.332479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  579.332500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  579.334042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  579.334065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  579.335926] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  579.338980] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  579.339016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  579.339037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  579.339066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  579.339115] [drm:intel_fbc_enable [i915]] reserved 15360000 bytes of contiguous stolen space for FBC, threshold: 1
>[  579.339136] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  579.355770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  579.355800] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  579.355835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  584.356495] [drm:drm_mode_addfb2] [FB:77]
>[  584.423016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  584.423033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  584.423110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  584.423134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  584.423160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 135000KHz
>[  584.423187] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  584.423210] [drm:intel_dp_compute_config [i915]] DP link bw required 405000 available 648000
>[  584.423237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  584.423263] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  584.423289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  584.423316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5242880, gmch_n: 8388608, link_m: 218453, link_n: 262144, tu: 64
>[  584.423341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  584.423366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  584.423372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  584.423397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  584.423402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  584.423428] [drm:intel_dump_pipe_config [i915]] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  584.423454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 135000
>[  584.423480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  584.423505] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  584.423532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  584.423557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  584.423584] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1600x1200 format = XR24 little-endian (0x34325258)
>[  584.423654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  584.423687] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  584.423722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  584.423759] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  584.439434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  584.439467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  584.439517] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  584.458387] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  584.458410] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  584.458427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  584.458448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  584.458465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  584.458480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  584.458496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  584.458515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  584.458535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  584.458556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  584.458576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  584.458622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  584.458643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  584.458664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  584.458685] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  584.458704] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  584.460685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  584.460701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  584.460715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  584.460733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  584.462237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  584.462252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  584.462267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  584.463763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  584.463778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  584.465581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  584.468511] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  584.468536] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  584.468553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  584.468581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  584.468639] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  584.468662] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  584.481943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  584.481972] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  584.482005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  589.482539] [drm:drm_mode_addfb2] [FB:75]
>[  589.525495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  589.525508] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  589.525563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  589.525580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  589.525598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  589.525616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  589.525630] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  589.525646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  589.525661] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  589.525676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  589.525690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  589.525703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  589.525716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  589.525720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  589.525733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  589.525736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  589.525749] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  589.525762] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 108000
>[  589.525774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  589.525787] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  589.525802] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  589.525819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  589.525837] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  589.525855] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  589.525873] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  589.525892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  589.525944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  589.533957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  589.533983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  589.534024] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  589.548819] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  589.548843] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  589.548859] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  589.548879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  589.548934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  589.548960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  589.548983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  589.548998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  589.549015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  589.549033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  589.549050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  589.549066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  589.549081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  589.549095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  589.549112] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  589.549128] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  589.551111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  589.551127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  589.551141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  589.551159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  589.552649] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  589.552664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  589.552678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  589.554160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  589.554176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  589.555969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  589.558912] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  589.558939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  589.558955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  589.558978] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  589.559026] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  589.559052] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  589.575707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  589.575737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  589.575772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  594.576303] [drm:drm_mode_addfb2] [FB:77]
>[  594.617472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  594.617484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  594.617541] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  594.617558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  594.617576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  594.617594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  594.617608] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  594.617624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  594.617640] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  594.617655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  594.617669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  594.617682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  594.617695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  594.617699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  594.617711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  594.617715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  594.617728] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5
>[  594.617741] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1152x864, pixel rate 108000
>[  594.617753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  594.617770] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  594.617788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  594.617806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  594.617824] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  594.617842] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  594.617860] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  594.617879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  594.617899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  594.624367] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  594.624393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  594.624440] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  594.643230] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  594.643252] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  594.643271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  594.643294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  594.643314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  594.643334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  594.643353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  594.643373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  594.643392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  594.643413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  594.643433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  594.643454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  594.643473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  594.643491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  594.643512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  594.643531] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  594.645510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  594.645529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  594.645546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  594.645564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  594.647054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  594.647071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  594.647085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  594.648566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  594.648582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  594.650373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  594.653300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  594.653327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  594.653347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  594.653373] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  594.653422] [drm:intel_fbc_enable [i915]] reserved 7962624 bytes of contiguous stolen space for FBC, threshold: 1
>[  594.653448] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  594.666716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  594.666745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  594.666781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  599.667435] [drm:drm_mode_addfb2] [FB:75]
>[  599.732460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  599.732476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  599.732608] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  599.732643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  599.732680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  599.732717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  599.732748] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  599.732784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  599.732816] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  599.732849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  599.732880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  599.732910] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  599.732938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  599.732946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  599.732974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  599.732982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  599.733013] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  599.733041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  599.733070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  599.733098] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  599.733132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  599.733160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  599.733192] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1152x864 format = XR24 little-endian (0x34325258)
>[  599.733219] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  599.733249] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  599.733284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  599.733322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  599.747070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  599.747103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  599.747163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  599.761945] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  599.761969] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  599.761989] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  599.762012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  599.762032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  599.762051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  599.762071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  599.762090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  599.762110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  599.762131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  599.762151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  599.762172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  599.762190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  599.762206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  599.762227] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  599.762246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  599.764229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  599.764245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  599.764260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  599.764275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  599.765765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  599.765780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  599.765793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  599.767273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  599.767289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  599.769080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  599.771999] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  599.772025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  599.772041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  599.772064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  599.772112] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  599.772137] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  599.788775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  599.788805] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  599.788840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  604.789373] [drm:drm_mode_addfb2] [FB:77]
>[  604.849121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  604.849137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  604.849211] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  604.849235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  604.849259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  604.849282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  604.849305] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  604.849330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  604.849355] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  604.849381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  604.849406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  604.849430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  604.849454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  604.849459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  604.849483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  604.849488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  604.849513] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  604.849538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74176
>[  604.849561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  604.849586] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  604.849611] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  604.849635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  604.849661] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  604.849686] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  604.849711] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  604.849737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  604.849765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  604.855768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  604.855798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  604.855893] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  604.874775] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  604.874798] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  604.874814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  604.874875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  604.874900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  604.874924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  604.874946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  604.874969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  604.874991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  604.875018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  604.875044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  604.875069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  604.875090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  604.875112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  604.875138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  604.875161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  604.877151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  604.877167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  604.877181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  604.877195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  604.878680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  604.878695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  604.878708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  604.880185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  604.880201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  604.881985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  604.884925] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  604.884953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  604.884970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  604.884992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  604.885041] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  604.885073] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  604.901745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  604.901774] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  604.901808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  609.902396] [drm:drm_mode_addfb2] [FB:75]
>[  609.955927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  609.955941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  609.956005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  609.956026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  609.956047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  609.956070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  609.956091] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  609.956113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  609.956171] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  609.956199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  609.956226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  609.956250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  609.956274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  609.956282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  609.956305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  609.956312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  609.956339] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5
>[  609.956370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  609.956390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  609.956409] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  609.956434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  609.956455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  609.956478] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  609.956500] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  609.956521] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  609.956545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  609.956571] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  609.973825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  609.973852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  609.973893] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  609.992778] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  609.992801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  609.992817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  609.992838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  609.992854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  609.992870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  609.992885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  609.992900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  609.992916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  609.992934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  609.992950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  609.992966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  609.992980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  609.992995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  609.993015] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  609.993034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  609.995053] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  609.995070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  609.995084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  609.995099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  609.996635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  609.996650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  609.996664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  609.998159] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  609.998174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  609.999965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  610.002901] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  610.002929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  610.002948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  610.002975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  610.003017] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  610.003037] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  610.023043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  610.023074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  610.023109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  615.023833] [drm:drm_mode_addfb2] [FB:77]
>[  615.087134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  615.087151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  615.087226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  615.087251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  615.087276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 78750KHz
>[  615.087303] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  615.087324] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  615.087347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  615.087370] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  615.087393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  615.087414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  615.087434] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  615.087493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  615.087502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  615.087535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  615.087543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  615.087574] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  615.087604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  615.087636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  615.087664] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  615.087699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  615.087727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  615.087759] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  615.087787] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  615.087817] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  615.087851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  615.087888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  615.103378] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  615.103411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  615.103521] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  615.124433] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  615.124473] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  615.124489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  615.124510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  615.124527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  615.124542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  615.124558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  615.124573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  615.124588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  615.124606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  615.124622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  615.124638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  615.124652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  615.124666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  615.124683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  615.124699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  615.126672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  615.126688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  615.126704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  615.126723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  615.128211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  615.128227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  615.128241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  615.129720] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  615.129736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  615.131522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  615.134462] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  615.134496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  615.134512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  615.134536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  615.134573] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  615.134591] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  615.147921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  615.147950] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  615.147984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  620.148635] [drm:drm_mode_addfb2] [FB:75]
>[  620.189174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  620.189187] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  620.189243] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  620.189259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  620.189277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 65000KHz
>[  620.189295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  620.189309] [drm:intel_dp_compute_config [i915]] DP link bw required 195000 available 324000
>[  620.189325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  620.189343] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  620.189361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  620.189379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2524349, gmch_n: 4194304, link_m: 105181, link_n: 262144, tu: 64
>[  620.189396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  620.189413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  620.189417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  620.189434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  620.189438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  620.189456] [drm:intel_dump_pipe_config [i915]] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  620.189473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 65000
>[  620.189491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  620.189508] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  620.189527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  620.189544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  620.189562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  620.189580] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  620.189597] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  620.189616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  620.189635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  620.199641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  620.199669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  620.199709] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  620.214500] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  620.214523] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  620.214540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  620.214560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  620.214580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  620.214600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  620.214619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  620.214639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  620.214658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  620.214679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  620.214700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  620.214720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  620.214739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  620.214797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  620.214825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  620.214852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  620.216850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  620.216865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  620.216879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  620.216894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  620.218382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  620.218400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  620.218417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  620.219900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  620.219917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  620.221708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  620.224662] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  620.224690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  620.224707] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  620.224729] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  620.224815] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  620.224839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  620.241475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  620.241504] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  620.241539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  625.242246] [drm:drm_mode_addfb2] [FB:77]
>[  625.302769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  625.302785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  625.302862] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  625.302888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  625.302915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 49500KHz
>[  625.302946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  625.302973] [drm:intel_dp_compute_config [i915]] DP link bw required 148500 available 162000
>[  625.303001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  625.303028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  625.303055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  625.303130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1922389, gmch_n: 2097152, link_m: 80099, link_n: 262144, tu: 64
>[  625.303166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  625.303198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  625.303207] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  625.303238] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  625.303247] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  625.303278] [drm:intel_dump_pipe_config [i915]] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5
>[  625.303309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 49500
>[  625.303340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  625.303370] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  625.303407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  625.303439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  625.303472] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  625.303505] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  625.303538] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  625.303575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  625.303615] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  625.308104] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  625.308132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  625.308173] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  625.327041] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  625.327081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  625.327098] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  625.327118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  625.327134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  625.327150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  625.327166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  625.327181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  625.327197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  625.327214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  625.327230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  625.327246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  625.327260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  625.327274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  625.327291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  625.327307] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  625.329286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  625.329302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  625.329316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  625.329330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  625.330809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  625.330827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  625.330844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  625.332319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  625.332336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  625.334118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  625.337051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  625.337094] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  625.337111] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  625.337134] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  625.337172] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  625.337189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  625.350535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  625.350567] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  625.350605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  630.351258] [drm:drm_mode_addfb2] [FB:75]
>[  630.405692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  630.405707] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  630.405780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  630.405806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  630.405832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 40000KHz
>[  630.405861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  630.405886] [drm:intel_dp_compute_config [i915]] DP link bw required 120000 available 162000
>[  630.405911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  630.405936] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  630.405961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  630.405986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1553445, gmch_n: 2097152, link_m: 64726, link_n: 262144, tu: 64
>[  630.406010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  630.406034] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  630.406039] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  630.406064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  630.406068] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  630.406093] [drm:intel_dump_pipe_config [i915]] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5
>[  630.406117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 40000
>[  630.406142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  630.406166] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  630.406192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  630.406216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  630.406242] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  630.406266] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  630.406291] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  630.406318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  630.406345] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  630.417534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  630.417562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  630.417604] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  630.432387] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  630.432410] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  630.432426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  630.432446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  630.432463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  630.432479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  630.432494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  630.432509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  630.432525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  630.432542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  630.432558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  630.432574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  630.432589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  630.432603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  630.432620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  630.432636] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  630.434611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  630.434626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  630.434640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  630.434654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  630.437212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  630.437231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  630.437247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  630.439815] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  630.439833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  630.441615] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  630.444583] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  630.444611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  630.444627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  630.444650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  630.444688] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  630.444705] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  630.461296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  630.461326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  630.461387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  635.462047] [drm:drm_mode_addfb2] [FB:77]
>[  635.521407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  635.521424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  635.521501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  635.521527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  635.521554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  635.521579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  635.521601] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  635.521626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  635.521650] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  635.521720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  635.521754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  635.521786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  635.521816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  635.521825] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  635.521855] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  635.521864] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  635.521895] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa
>[  635.521925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x576, pixel rate 27000
>[  635.521957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  635.521989] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  635.522024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  635.522057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  635.522092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  635.522125] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  635.522157] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  635.522195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  635.522235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  635.534879] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  635.534905] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  635.534944] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  635.553763] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  635.553786] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  635.553802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  635.553823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  635.553840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  635.553856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  635.553871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  635.553886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  635.553902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  635.553920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  635.553936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  635.553952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  635.553966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  635.553980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  635.553998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  635.554013] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  635.555993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  635.556009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  635.556023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  635.556037] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  635.557519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  635.557534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  635.557549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  635.559024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  635.559040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  635.560822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  635.563770] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  635.563797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  635.563814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  635.563837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  635.563875] [drm:intel_fbc_enable [i915]] reserved 3317760 bytes of contiguous stolen space for FBC, threshold: 1
>[  635.563894] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  635.583903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  635.583934] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  635.583971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  640.584609] [drm:drm_mode_addfb2] [FB:75]
>[  640.633677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  640.633694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  640.633773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  640.633801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  640.633829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27027KHz
>[  640.633855] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  640.633879] [drm:intel_dp_compute_config [i915]] DP link bw required 81081 available 162000
>[  640.633904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  640.633930] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  640.633954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  640.634027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1049624, gmch_n: 2097152, link_m: 43734, link_n: 262144, tu: 64
>[  640.634061] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  640.634094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  640.634105] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  640.634136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  640.634145] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  640.634178] [drm:intel_dump_pipe_config [i915]] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  640.634209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27027
>[  640.634241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  640.634272] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  640.634310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  640.634343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  640.634376] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 720x576 format = XR24 little-endian (0x34325258)
>[  640.634409] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  640.634443] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  640.634481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  640.634522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  640.644277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  640.644303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  640.644343] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  640.665254] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  640.665277] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  640.665293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  640.665314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  640.665330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  640.665346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  640.665361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  640.665376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  640.665392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  640.665409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  640.665425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  640.665441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  640.665455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  640.665469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  640.665486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  640.665505] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  640.667521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  640.667537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  640.667553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  640.667571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  640.669060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  640.669076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  640.669090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  640.670569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  640.670585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  640.672387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  640.675335] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  640.675363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  640.675382] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  640.675409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  640.675449] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  640.675469] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  640.692129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  640.692160] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  640.692198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  645.692853] [drm:drm_mode_addfb2] [FB:77]
>[  645.741640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  645.741656] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  645.741736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  645.741764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  645.741793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  645.741819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  645.741846] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  645.741876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  645.741905] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  645.741933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  645.741962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  645.741990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  645.742018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  645.742024] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  645.742051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  645.742057] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  645.742086] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  645.742114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27000
>[  645.742142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  645.742170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  645.742198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  645.742226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  645.742255] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  645.742283] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  645.742359] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  645.742401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  645.742443] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  645.759141] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  645.759167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  645.759207] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  645.778083] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  645.778107] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  645.778127] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  645.778150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  645.778169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  645.778189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  645.778208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  645.778228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  645.778247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  645.778268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  645.778334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  645.778367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  645.778393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  645.778419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  645.778448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  645.778474] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  645.780474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  645.780490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  645.780504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  645.780519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  645.781997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  645.782012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  645.782026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  645.783500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  645.783516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  645.785314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  645.788246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  645.788273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  645.788332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  645.788370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  645.788519] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  645.788537] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  645.805073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  645.805103] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  645.805139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  650.805672] [drm:drm_mode_addfb2] [FB:75]
>[  650.844457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  650.844471] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  650.844537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  650.844559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  650.844581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 31500KHz
>[  650.844629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  650.844654] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000
>[  650.844681] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  650.844706] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  650.844729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  650.844755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  650.844779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  650.844803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  650.844809] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  650.844833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  650.844838] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  650.844861] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa
>[  650.844884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500
>[  650.844909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  650.844933] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  650.844957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  650.844979] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  650.845003] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  650.845026] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  650.845049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  650.845073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  650.845098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  650.860538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  650.860568] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  650.860668] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  650.879572] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  650.879614] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  650.879632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  650.879654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  650.879672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  650.879689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  650.879705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  650.879722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  650.879739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  650.879758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  650.879779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  650.879801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  650.879821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  650.879841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  650.879863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  650.879884] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  650.881882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  650.881902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  650.881918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  650.881936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  650.883435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  650.883453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  650.883468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  650.884957] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  650.884975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  650.886773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  650.889726] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  650.889754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  650.889772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  650.889799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  650.889843] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  650.889863] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  650.903209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  650.903241] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  650.903277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  655.903854] [drm:drm_mode_addfb2] [FB:77]
>[  655.934789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  655.934800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  655.934854] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  655.934872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  655.934921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 25200KHz
>[  655.934947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  655.934968] [drm:intel_dp_compute_config [i915]] DP link bw required 75600 available 162000
>[  655.934993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  655.935017] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  655.935039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  655.935063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 978670, gmch_n: 2097152, link_m: 40777, link_n: 262144, tu: 64
>[  655.935086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  655.935107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  655.935113] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  655.935134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  655.935140] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  655.935161] [drm:intel_dump_pipe_config [i915]] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  655.935182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25200
>[  655.935201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  655.935213] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  655.935230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  655.935243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  655.935257] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  655.935270] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  655.935282] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  655.935298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  655.935316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  655.943527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  655.943553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  655.943594] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  655.957564] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  655.957587] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  655.957604] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  655.957625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  655.957642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  655.957658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  655.957673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  655.957688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  655.957704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  655.957721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  655.957737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  655.957754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  655.957768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  655.957782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  655.957800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  655.957815] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  655.959802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  655.959820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  655.959837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  655.959856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  655.961342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  655.961358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  655.961372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  655.962844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  655.962860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  655.964646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  655.967589] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  655.967617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  655.967635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  655.967661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  655.967701] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  655.967720] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  655.984391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  655.984421] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  655.984456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  660.985110] [drm:drm_mode_addfb2] [FB:75]
>[  661.021450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  661.021462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  661.021523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  661.021543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  661.021563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 25175KHz
>[  661.021582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  661.021599] [drm:intel_dp_compute_config [i915]] DP link bw required 75525 available 162000
>[  661.021618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  661.021636] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  661.021653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  661.021670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 977700, gmch_n: 2097152, link_m: 40737, link_n: 262144, tu: 64
>[  661.021686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  661.021701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  661.021706] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  661.021720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  661.021724] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  661.021739] [drm:intel_dump_pipe_config [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  661.021754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25175
>[  661.021769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  661.021784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  661.021801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  661.021816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  661.021832] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  661.021847] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  661.021862] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  661.021880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  661.021899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  661.034822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  661.034849] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  661.034889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  661.053768] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  661.053791] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  661.053807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  661.053827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  661.053844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  661.053860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  661.053875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  661.053889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  661.053905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  661.053922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  661.053938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  661.053954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  661.053968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  661.053982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  661.054000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  661.054016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  661.055995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  661.056011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  661.056025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  661.056040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  661.057521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  661.057535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  661.057548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  661.059015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  661.059030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  661.060812] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  661.063727] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  661.063753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  661.063771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  661.063798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  661.063839] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  661.063858] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  661.080521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  661.080551] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  661.080585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  666.081241] [drm:drm_mode_addfb2] [FB:77]
>[  666.108233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  666.108244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  666.108300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  666.108318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  666.108337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 28320KHz
>[  666.108358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  666.108375] [drm:intel_dp_compute_config [i915]] DP link bw required 84960 available 162000
>[  666.108393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  666.108411] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  666.108428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  666.108446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1099839, gmch_n: 2097152, link_m: 45826, link_n: 262144, tu: 64
>[  666.108463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  666.108480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  666.108484] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  666.108530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  666.108537] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  666.108561] [drm:intel_dump_pipe_config [i915]] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6
>[  666.108582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x400, pixel rate 28320
>[  666.108602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  666.108622] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  666.108645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  666.108665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  666.108686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:75, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  666.108706] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  666.108725] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  666.108748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  666.108773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  666.119216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  666.119242] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  666.119280] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  666.138150] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  666.138173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  666.138189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  666.138211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  666.138231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  666.138250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  666.138270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  666.138290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  666.138309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  666.138330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  666.138350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  666.138371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  666.138389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  666.138405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  666.138426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  666.138445] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  666.140421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  666.140439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  666.140456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  666.140474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  666.141958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  666.141975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  666.141989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  666.143457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  666.143475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  666.145259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  666.148195] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  666.148223] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  666.148243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  666.148269] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  666.148310] [drm:intel_fbc_enable [i915]] reserved 2304000 bytes of contiguous stolen space for FBC, threshold: 1
>[  666.148330] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  666.162604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  666.162633] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  666.162668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.163289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  671.171457] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  671.171503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  671.171571] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  671.186354] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  671.186390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  671.186417] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  671.186449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  671.186477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  671.186505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  671.186530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  671.186555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  671.186581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  671.186610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  671.186637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  671.186663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  671.186689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.186712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  671.186735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  671.186779] [drm:intel_power_well_disable [i915]] disabling display
>[  671.186852] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  671.186891] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  671.186920] [drm:intel_power_well_disable [i915]] disabling always-on
>[  671.187420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  671.187454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  671.187483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  671.187514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  671.187537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  671.187563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  671.187589] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  671.187613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  671.187637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  671.187660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  671.187681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  671.187687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  671.187708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  671.187712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  671.187734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  671.187756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  671.187777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  671.187801] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  671.187871] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  671.187891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  671.187910] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  671.187930] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  671.187948] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  671.187971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  671.187994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  671.188090] [drm:intel_power_well_enable [i915]] enabling always-on
>[  671.188107] [drm:intel_power_well_enable [i915]] enabling display
>[  671.188124] [drm:hsw_set_power_well [i915]] Enabling power well
>[  671.188178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  671.188193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  671.188208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  671.188222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  671.188236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  671.188252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  671.188272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  671.188287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  671.188302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.188320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  671.188338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  671.188367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  671.188390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  671.190416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  671.190431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  671.190445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  671.190459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  671.191961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  671.191974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  671.191987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  671.193481] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  671.193495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  671.195325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  671.198284] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  671.198334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  671.198350] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  671.198382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  671.198577] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  671.198601] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  671.215092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  671.215116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  671.215152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.444708] Console: switching to colour dummy device 80x25
>[  671.444803] [IGT] kms_flip: executing
>[  671.454386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  671.454415] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  671.455886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  671.455913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  671.457884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  671.457891] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  671.459880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  671.459901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  671.461880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  671.461886] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  671.461891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  671.461907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  671.461930] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  671.462999] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  671.463892] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  671.463909] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  671.463924] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  671.463937] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  671.464924] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  671.464946] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  671.466033] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  671.466036] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  671.466116] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  671.466118] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  671.466122] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  671.466124] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  671.466128] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  671.466130] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  671.466138] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  671.466141] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  671.466143] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  671.466146] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  671.466148] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  671.466151] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  671.466153] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  671.466156] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  671.466158] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  671.466161] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  671.466163] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  671.466165] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  671.466168] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  671.466170] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  671.466173] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  671.466175] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  671.466177] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  671.466180] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  671.466182] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  671.466185] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  671.466187] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  671.466189] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  671.466192] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  671.466194] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  671.466197] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  671.466199] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  671.466201] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  671.466204] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  671.466206] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  671.466209] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  671.466211] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  671.466240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  671.466258] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  671.467875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  671.467892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  671.469880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  671.469885] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  671.471879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  671.471901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  671.473880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  671.473886] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  671.473890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  671.475168] [IGT] kms_flip: starting subtest wf_vblank-interruptible
>[  671.475649] [drm:drm_mode_addfb2] [FB:78]
>[  671.475671] [drm:drm_mode_addfb2] [FB:79]
>[  671.518342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  671.518394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  671.532029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  671.532057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  671.532098] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  671.550327] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  671.550350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  671.550367] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  671.550387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  671.550407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  671.550429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  671.550449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  671.550468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  671.550488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  671.550510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  671.550530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  671.550551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  671.550571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.550590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  671.550606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  671.550635] [drm:intel_power_well_disable [i915]] disabling display
>[  671.550673] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  671.550699] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  671.550717] [drm:intel_power_well_disable [i915]] disabling always-on
>[  671.550810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  671.550957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  671.551052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  671.551068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  671.551137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  671.551162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  671.551189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  671.551218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  671.551241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  671.551266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  671.551290] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  671.551314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  671.551337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  671.551359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  671.551380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  671.551386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  671.551408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  671.551413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  671.551436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  671.551457] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  671.551480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  671.551501] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  671.551526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  671.551547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  671.551569] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  671.551590] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  671.551612] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  671.551635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  671.551662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  671.554322] [drm:intel_power_well_enable [i915]] enabling always-on
>[  671.554338] [drm:intel_power_well_enable [i915]] enabling display
>[  671.554353] [drm:hsw_set_power_well [i915]] Enabling power well
>[  671.554381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  671.554398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  671.554414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  671.554429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  671.554444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  671.554459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  671.554479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  671.554499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  671.554519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  671.554538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  671.554554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  671.554582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  671.554601] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  671.556584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  671.556601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  671.556615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  671.556630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  671.558137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  671.558155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  671.558172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  671.559666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  671.559683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  671.561489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  671.564412] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  671.564446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  671.564462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  671.564485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  671.564524] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  671.564540] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  671.581190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  671.581214] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  671.581247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.606871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.623486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  681.623511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.623549] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  681.642408] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  681.642431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  681.642494] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.642525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.642552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.642581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.642606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.642624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.642641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.642660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.642677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.642693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.642710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.642724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.642739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.642767] [drm:intel_power_well_disable [i915]] disabling display
>[  681.642789] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.642811] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  681.642829] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.643014] [drm:drm_mode_addfb2] [FB:77]
>[  681.643044] [drm:drm_mode_addfb2] [FB:78]
>[  681.668709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  681.668789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.668846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.668899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.668909] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.668957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.668974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.668991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.669010] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.669024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.669040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.669055] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  681.669070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  681.669084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.669098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.669111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.669115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.669127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.669130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.669143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.669156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.669169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.669181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.669196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.669209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.669222] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  681.669235] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  681.669247] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  681.669262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.669279] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  681.671791] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.671806] [drm:intel_power_well_enable [i915]] enabling display
>[  681.671819] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.671848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.671863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.671878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.671892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.671905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.671920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.671936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.671951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.671965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.671978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.671991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.672007] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  681.672021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.674021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.674040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.674057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.674076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.675600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.675618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.675632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.677129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.677146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.678958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.681893] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  681.681968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.681984] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  681.682008] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.698712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.698737] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.698773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  691.724397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  691.724449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  691.724476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  691.724519] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  691.743382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  691.743402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  691.743423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  691.743440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  691.743459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  691.743475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  691.743491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  691.743507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  691.743525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  691.743542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  691.743558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  691.743573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  691.743588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  691.743602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  691.743630] [drm:intel_power_well_disable [i915]] disabling display
>[  691.743652] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  691.743674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  691.743690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  691.743915] [drm:drm_mode_addfb2] [FB:77]
>[  691.743938] [drm:drm_mode_addfb2] [FB:78]
>[  691.767030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  691.767129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  691.767191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  691.767248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  691.767258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  691.767309] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  691.767328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  691.767347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  691.767369] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  691.767388] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  691.767408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  691.767427] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  691.767446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  691.767465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  691.767484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  691.767502] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  691.767506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  691.767524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  691.767528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  691.767547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  691.767565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  691.767584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  691.767602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  691.767621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  691.767640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  691.767658] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  691.767677] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  691.767695] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  691.767715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  691.767736] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  691.770258] [drm:intel_power_well_enable [i915]] enabling always-on
>[  691.770275] [drm:intel_power_well_enable [i915]] enabling display
>[  691.770290] [drm:hsw_set_power_well [i915]] Enabling power well
>[  691.770320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  691.770340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  691.770359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  691.770378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  691.770396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  691.770415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  691.770436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  691.770455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  691.770475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  691.770493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  691.770509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  691.770529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  691.770548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  691.772543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  691.772561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  691.772575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  691.772591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  691.774123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  691.774140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  691.774154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  691.775657] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  691.775673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  691.777482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  691.780447] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  691.780489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  691.780505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  691.780527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  691.797220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  691.797244] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  691.797278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  701.822913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  701.822965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  701.822989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  701.823030] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  701.841332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  701.841351] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  701.841374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  701.841393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  701.841415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  701.841435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  701.841455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  701.841474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  701.841496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  701.841517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  701.841537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  701.841558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  701.841577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  701.841596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  701.841625] [drm:intel_power_well_disable [i915]] disabling display
>[  701.841689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  701.841726] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  701.841750] [drm:intel_power_well_disable [i915]] disabling always-on
>[  701.843100] [IGT] kms_flip: exiting, ret=0
>[  701.864167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  701.864186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  701.864206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  701.864227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  701.864243] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  701.864261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  701.864278] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  701.864298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  701.864318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  701.864338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  701.864357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  701.864362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  701.864381] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  701.864385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  701.864404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  701.864424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  701.864444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  701.864463] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  701.864483] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  701.864503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  701.864522] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  701.864542] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  701.864561] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  701.864582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  701.864604] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  701.864706] [drm:intel_power_well_enable [i915]] enabling always-on
>[  701.864728] [drm:intel_power_well_enable [i915]] enabling display
>[  701.864749] [drm:hsw_set_power_well [i915]] Enabling power well
>[  701.864813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  701.864833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  701.864853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  701.864873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  701.864893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  701.864913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  701.864935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  701.864956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  701.864977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  701.864997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  701.865016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  701.865047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  701.865071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  701.867131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  701.867147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  701.867161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  701.867175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  701.868701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  701.868717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  701.868734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  701.870240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  701.870255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  701.872072] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  701.875107] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  701.875182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  701.875200] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  701.875242] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  701.875346] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  701.875376] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  701.891937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  701.891962] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  701.891998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  701.892123] Console: switching to colour frame buffer device 240x75
>[  702.199951] Console: switching to colour dummy device 80x25
>[  702.200047] [IGT] kms_flip: executing
>[  702.214200] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  702.214229] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  702.215732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  702.215753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  702.217728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  702.217734] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  702.219728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  702.219748] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  702.221735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  702.221741] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  702.221745] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  702.221760] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  702.221782] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  702.222818] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  702.223723] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  702.223741] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  702.223756] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  702.223770] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  702.224759] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  702.224783] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  702.225838] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  702.225841] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  702.225919] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  702.225922] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  702.225926] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  702.225928] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  702.225932] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  702.225934] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  702.225941] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  702.225944] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.225946] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  702.225949] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  702.225951] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  702.225953] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  702.225956] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  702.225958] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  702.225961] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  702.225963] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  702.225966] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  702.225968] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  702.225970] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  702.225973] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  702.225975] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  702.225978] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  702.225980] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  702.225983] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  702.225985] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  702.225987] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  702.225990] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  702.225992] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  702.225995] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  702.225997] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  702.225999] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  702.226002] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  702.226004] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  702.226007] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  702.226009] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  702.226012] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  702.226014] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  702.226047] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  702.226065] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  702.227735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  702.227753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  702.229736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  702.229742] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  702.231735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  702.231756] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  702.233831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  702.233837] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  702.233841] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  702.234068] [IGT] kms_flip: starting subtest flip-vs-dpms-off-vs-modeset
>[  702.234473] [drm:drm_mode_addfb2] [FB:75]
>[  702.234494] [drm:drm_mode_addfb2] [FB:79]
>[  702.276757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.276810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.292283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.292309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.292350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.311219] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.311242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.311259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.311280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.311300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.311322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.311341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.311360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.311380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.311401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.311422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.311442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.311463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.311482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.311498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.311526] [drm:intel_power_well_disable [i915]] disabling display
>[  702.311549] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.311575] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.311593] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.311796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  702.311894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  702.311957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.311967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.312011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.312030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.312049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.312070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.312085] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.312103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.312120] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.312137] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.312153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.312169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.312183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.312188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.312202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.312205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.312220] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.312235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.312249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.312262] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.312280] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.312294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.312320] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.312334] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.312347] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.312363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.312381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.314891] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.314907] [drm:intel_power_well_enable [i915]] enabling display
>[  702.314922] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.314950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.314967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.314983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.315001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.315020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.315038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.315058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.315078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.315098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.315116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.315132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.315152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.315171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.317154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.317171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.317185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.317200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.318739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.318754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.318768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.320277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.320295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.322115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.325066] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.325125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.325142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.325164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.325205] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.325222] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.341875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.341900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.341934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.358669] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.358707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.358727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.358749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.358768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.358788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.358807] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.358826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.358846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.358865] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.358884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.358888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.358906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.358910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.358929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.358948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.358967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.358986] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.359005] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.359024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.359044] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  702.359063] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.359082] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.359102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.359122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.375258] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.375282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.375319] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.394213] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.394234] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.394250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.394271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.394291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.394311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.394330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.394350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.394369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.394389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.394410] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.394430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.394449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.394465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.394493] [drm:intel_power_well_disable [i915]] disabling display
>[  702.394515] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.394534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.394555] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.394577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.394592] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.394639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.394648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.394741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.394768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.394797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.394828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.394851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.394879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.394904] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.394930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.394953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.394977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.394999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.395006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.395029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.395035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.395059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.395080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.395108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.395128] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.395152] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.395171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.395194] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  702.395213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.395233] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.395254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.395278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.395344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.395367] [drm:intel_power_well_enable [i915]] enabling display
>[  702.395389] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.395424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.395445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.395466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.395486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.395506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.395527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.395550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.395574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.395598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.395617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.395637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.395660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.395683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.397712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.397730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.397747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.397766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.399283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.399299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.399314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.400814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.400831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.402641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.405577] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.405652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.405669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.405727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.405787] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.405811] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.422394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.422424] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.422461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.422556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.422598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.455796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.455842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.455911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.472936] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.472974] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.473003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.473036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.473065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.473095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.473122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.473147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.473174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.473204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.473232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.473260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.473287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.473311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.473334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.473379] [drm:intel_power_well_disable [i915]] disabling display
>[  702.473414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.473450] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.473478] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.473630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.473646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.473793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.473834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.473885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.473937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.473978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.474023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.474064] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.474108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.474147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.474188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.474225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.474238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.474276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.474287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.474327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.474784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.474807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.474831] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.474855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.474878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.474900] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.474923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.474944] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.474969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.474996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.475064] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.475089] [drm:intel_power_well_enable [i915]] enabling display
>[  702.475113] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.475152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.475174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.475198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.475219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.475242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.475264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.475289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.475315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.475340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.475360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.475382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.475407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.475431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.477438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.477455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.477470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.477485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.478997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.479012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.479025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.480522] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.480538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.482350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.485287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.485359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.485376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.485398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.485437] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.485454] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.502111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.502137] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.502171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.502275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.502328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.535492] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.535516] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.535552] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.554415] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.554437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.554456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.554478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.554498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.554519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.554538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.554557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.554576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.554598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.554619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.554639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.554659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.554678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.554727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.554771] [drm:intel_power_well_disable [i915]] disabling display
>[  702.554806] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.555042] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.555070] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.555214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.555223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.555267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.555285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.555303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.555323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.555342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.555362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.555382] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.555401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.555420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.555439] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.555458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.555462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.555480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.555484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.555503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.555523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.555542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.555560] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.555580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.555598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.555617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.555636] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.555655] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.555675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.555695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.555792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.555818] [drm:intel_power_well_enable [i915]] enabling display
>[  702.555849] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.556082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.556105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.556128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.556149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.556170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.556192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.556216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.556239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.556263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.556282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.556303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.556326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.556348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.558349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.558366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.558381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.558397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.559914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.559932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.559947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.561442] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.561460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.563271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.566209] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.566281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.566297] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.566320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.566368] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.566393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.583025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.583050] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.583085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.583184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.583223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.616381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.616405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.616449] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.635363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.635385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.635401] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.635422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.635442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.635463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.635483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.635502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.635521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.635543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.635564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.635584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.635605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.635624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.635640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.635667] [drm:intel_power_well_disable [i915]] disabling display
>[  702.635689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.635759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.635789] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.635944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.635958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.636020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.636045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.636069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.636095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.636116] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.636139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.636161] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.636183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.636204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.636225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.636244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.636250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.636270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.636275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.636296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.636315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.636336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.636355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.636378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.636397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.636417] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.636436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.636457] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.636478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.636502] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.636563] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.636585] [drm:intel_power_well_enable [i915]] enabling display
>[  702.636607] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.636642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.636663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.636684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.636721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.636744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.636765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.636790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.636814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.636839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.636859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.636880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.636906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.636927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.638921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.638938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.638952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.638966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.640473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.640488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.640502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.641999] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.642015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.643822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.646761] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.646831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.646850] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.646876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.646925] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.646952] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.663576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.663601] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.663636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.663773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.663812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.696964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.696988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.697025] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.715477] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.715499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.715516] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.715535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.715552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.715569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.715584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.715599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.715615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.715633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.715649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.715665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.715680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.715699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.715758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.715802] [drm:intel_power_well_disable [i915]] disabling display
>[  702.715837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.715860] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.715877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.715979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.715988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.716031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.716048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.716068] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.716091] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.716110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.716130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.716151] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.716171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.716191] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.716210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.716230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.716234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.716253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.716257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.716277] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.716296] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.716316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.716335] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.716355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.716374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.716394] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.716413] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.716433] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.716453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.716474] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.716521] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.716537] [drm:intel_power_well_enable [i915]] enabling display
>[  702.716553] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.716582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.716602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.716622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.716642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.716659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.716677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.716698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.716750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.716778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.716801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.716824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.716851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.716875] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.718877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.718893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.718907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.718922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.720426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.720440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.720455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.721953] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.721968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.723774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.726696] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.726783] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.726799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.726821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.726869] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.726895] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.743528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.743553] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.743588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.743688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.743783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.776884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.776908] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.776952] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.795810] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.795833] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.795853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.795874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.795894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.795915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.795935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.795954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.795973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.795995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.796015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.796035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.796056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.796075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.796091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.796118] [drm:intel_power_well_disable [i915]] disabling display
>[  702.796141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.796166] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.796183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.796294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.796303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.796349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.796369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.796389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.796411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.796430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.796449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.796469] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  702.796488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  702.796507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.796526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.796545] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.796549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.796567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.796571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.796591] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.796610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.796629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.796648] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  702.796667] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.796685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.796704] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  702.796775] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  702.796803] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  702.796830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.796857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  702.796923] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.796947] [drm:intel_power_well_enable [i915]] enabling display
>[  702.796969] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.797007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.797030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.797054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.797077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.797099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.797122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.797147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.797171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.797194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.797216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.797237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.797262] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  702.797285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.799288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.799305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.799321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.799340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.800864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.800881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.800896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.802392] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.802408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.804218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.807228] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  702.807277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.807293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  702.807316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.807363] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  702.807389] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  702.824020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.824044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.824077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.824176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.824214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.857409] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  702.857446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.857513] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  702.876460] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  702.876488] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  702.876509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.876534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.876555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.876577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.876596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.876615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.876635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.876658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.876679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.876701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.876782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.876811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.876839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.876892] [drm:intel_power_well_disable [i915]] disabling display
>[  702.876925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.876952] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  702.876976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.877171] [drm:drm_mode_addfb2] [FB:75]
>[  702.877200] [drm:drm_mode_addfb2] [FB:78]
>[  702.905039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  702.905117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  702.905170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  702.905224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  702.905234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.905282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.905299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.905317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.905336] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.905351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.905367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.905382] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  702.905397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  702.905411] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.905424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.905437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.905441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.905453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.905457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.905470] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.905483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.905500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.905517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  702.905536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.905553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.905571] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  702.905588] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  702.905606] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  702.905624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.905644] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  702.908193] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.908210] [drm:intel_power_well_enable [i915]] enabling display
>[  702.908225] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.908255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.908272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.908289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.908304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.908319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.908335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.908352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.908368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.908384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.908398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.908412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.908429] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  702.908446] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.910447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.910464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.910479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.910494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.912007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.912022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.912036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.913533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.913549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.915361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.918297] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  702.918371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.918388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  702.918410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.935115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.935141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  702.935175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.951873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.951891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.951910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.951932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.951951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.951971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.951991] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  702.952010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  702.952029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.952048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.952066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.952071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.952089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.952093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.952112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.952131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.952150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.952178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  702.952207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.952224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.952240] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  702.952255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  702.952268] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  702.952284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.952301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  702.952351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  702.952370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  702.952400] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  702.969201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  702.969220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  702.969241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.969258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.969274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.969289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.969304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.969320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.969337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.969353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.969368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.969382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.969401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.969429] [drm:intel_power_well_disable [i915]] disabling display
>[  702.969451] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  702.969471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.969492] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  702.969512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.969528] [drm:intel_power_well_disable [i915]] disabling always-on
>[  702.969572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  702.969582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  702.969629] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  702.969648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  702.969668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  702.969690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  702.969709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  702.969772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  702.969798] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  702.969825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  702.969849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  702.969873] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  702.969895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  702.969902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.969926] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  702.969932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  702.969956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  702.969978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  702.970002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  702.970023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  702.970050] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  702.970071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  702.970096] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  702.970118] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  702.970141] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  702.970168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  702.970194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  702.970265] [drm:intel_power_well_enable [i915]] enabling always-on
>[  702.970288] [drm:intel_power_well_enable [i915]] enabling display
>[  702.970312] [drm:hsw_set_power_well [i915]] Enabling power well
>[  702.970352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  702.970374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  702.970398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  702.970419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  702.970442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  702.970464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  702.970490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  702.970514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  702.970539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.970566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  702.970586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  702.970608] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  702.970630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  702.972627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  702.972643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  702.972657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.972672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  702.974183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  702.974197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  702.974211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  702.975709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  702.975738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  702.977545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  702.980483] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  702.980554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  702.980571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  702.980593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  702.997323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  702.997355] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  702.997390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  702.997507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  702.997555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.013996] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.014020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.014057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.032936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.032955] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.032975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.032992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.033009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.033024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.033039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.033057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.033079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.033100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.033121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.033141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.033160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.033177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.033204] [drm:intel_power_well_disable [i915]] disabling display
>[  703.033227] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.033251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.033267] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.033375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.033385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.033430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.033450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.033470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.033492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.033511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.033530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.033549] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.033569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.033588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.033607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.033625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.033629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.033648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.033652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.033671] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.033690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.033709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.033771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.033798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.033825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.033849] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.033874] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.033896] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.033923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.033956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.034023] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.034046] [drm:intel_power_well_enable [i915]] enabling display
>[  703.034067] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.034104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.034125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.034147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.034167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.034188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.034208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.034232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.034255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.034278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.034297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.034318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.034340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.034362] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.036360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.036377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.036392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.036407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.037916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.037932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.037946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.039440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.039455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.041268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.044203] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.044277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.044295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.044316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.061020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.061047] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.061085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.061180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.061221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.077720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.077764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.077800] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.096675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.096696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.096718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.096779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.096815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.096841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.096866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.096887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.096907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.096924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.096944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.096965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.096985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.097005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.097032] [drm:intel_power_well_disable [i915]] disabling display
>[  703.097054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.097079] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.097096] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.097194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.097204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.097250] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.097278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.097297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.097316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.097330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.097347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.097363] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.097379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.097393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.097407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.097420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.097425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.097438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.097441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.097455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.097468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.097482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.097494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.097510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.097523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.097536] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.097548] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.097562] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.097577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.097594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.097636] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.097649] [drm:intel_power_well_enable [i915]] enabling display
>[  703.097662] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.097687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.097702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.097715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.097752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.097772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.097793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.097816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.097839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.097861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.097880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.097900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.097924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.097945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.099940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.099956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.099971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.099986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.101489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.101504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.101519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.103018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.103035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.104843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.107778] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.107851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.107868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.107889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.124590] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.124615] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.124648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.124798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.124858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.141295] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.141318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.141355] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.159320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.159339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.159359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.159376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.159393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.159408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.159423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.159439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.159457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.159473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.159489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.159505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.159519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.159532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.159559] [drm:intel_power_well_disable [i915]] disabling display
>[  703.159580] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.159601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.159616] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.159766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.159780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.159847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.159871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.159897] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.159925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.159948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.159973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.159998] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.160021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.160045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.160067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.160089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.160095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.160116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.160122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.160144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.160166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.160188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.160209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.160233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.160255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.160277] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.160299] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.160319] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.160343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.160368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.160435] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.160457] [drm:intel_power_well_enable [i915]] enabling display
>[  703.160480] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.160518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.160541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.160564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.160584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.160607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.160630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.160656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.160680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.160705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.160733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.160772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.160798] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.160822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.162819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.162835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.162850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.162864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.164369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.164384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.164398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.165896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.165912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.167721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.170666] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.170780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.170801] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.170825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.187485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.187510] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.187545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.187643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.187683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.204184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.204208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.204244] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.223121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.223139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.223160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.223176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.223194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.223209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.223223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.223239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.223256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.223272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.223288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.223304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.223318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.223332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.223358] [drm:intel_power_well_disable [i915]] disabling display
>[  703.223379] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.223400] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.223415] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.223497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.223506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.223548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.223564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.223582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.223602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.223621] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.223641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.223661] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.223680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.223699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.223718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.223776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.223783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.223807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.223813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.223837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.223860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.223883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.223904] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.223929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.223950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.223972] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.223993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.224015] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.224040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.224066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.224296] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.224309] [drm:intel_power_well_enable [i915]] enabling display
>[  703.224323] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.224348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.224364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.224379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.224393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.224411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.224429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.224449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.224468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.224487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.224505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.224521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.224540] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.224558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.226536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.226552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.226566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.226581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.228088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.228103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.228117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.229609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.229625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.231433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.234377] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.234442] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.234458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.234479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.251174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.251198] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.251231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.251325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.251363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.267866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.267890] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.267934] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.286805] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.286824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.286844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.286861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.286878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.286894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.286908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.286924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.286942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.286958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.286978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.286998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.287017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.287034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.287062] [drm:intel_power_well_disable [i915]] disabling display
>[  703.287084] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.287108] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.287125] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.287231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.287240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.287286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.287306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.287326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.287348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.287367] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.287386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.287406] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.287425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.287444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.287463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.287481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.287485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.287504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.287508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.287527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.287546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.287565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.287584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.287609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.287626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.287641] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.287655] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.287669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.287684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.287701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.287780] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.287800] [drm:intel_power_well_enable [i915]] enabling display
>[  703.287820] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.287859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.287880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.287901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.287921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.287941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.287962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.287985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.288007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.288030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.288049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.288069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.288092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.288113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.290107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.290123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.290137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.290152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.291682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.291697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.291711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.293206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.293221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.295029] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.297958] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.297986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.298002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.298024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.314726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.314768] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.314802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.314899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.314937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.331411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.331434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.331478] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.350347] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.350366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.350386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.350403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.350420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.350435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.350450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.350469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.350491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.350512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.350532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.350552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.350571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.350588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.350616] [drm:intel_power_well_disable [i915]] disabling display
>[  703.350638] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.350663] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.350679] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.350866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.350880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.350949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.350968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.350988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.351008] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.351030] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.351047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.351062] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.351077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.351092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.351106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.351119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.351123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.351136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.351139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.351152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.351166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.351179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.351191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.351207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.351219] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.351233] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.351245] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.351262] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.351285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.351309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.351372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.351393] [drm:intel_power_well_enable [i915]] enabling display
>[  703.351414] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.351452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.351474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.351495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.351516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.351535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.351557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.351580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.351602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.351624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.351645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.351665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.351688] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.351710] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.353856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.353873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.353887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.353902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.355406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.355421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.355435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.356932] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.356948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.358777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.361711] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.361825] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.361852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.361889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.378529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.378555] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.378590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.378680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.378719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.395209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.395233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.395277] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.414142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.414161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.414181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.414198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.414215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.414231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.414246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.414262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.414279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.414295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.414311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.414326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.414340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.414354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.414381] [drm:intel_power_well_disable [i915]] disabling display
>[  703.414401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.414422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.414437] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.414519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.414528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.414570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.414586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.414604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.414623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.414639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.414655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.414672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  703.414687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  703.414702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.414716] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.414730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.414771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.414794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.414800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.414823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.414845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.414867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.414888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.414912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.414934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.414956] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  703.414977] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  703.414999] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  703.415024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.415049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  703.415118] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.415140] [drm:intel_power_well_enable [i915]] enabling display
>[  703.415165] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.415208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.415234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.415258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.415282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.415306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.415330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.415358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.415385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.415411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.415434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.415459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.415476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  703.415493] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.417471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.417489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.417506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.417524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.419039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.419055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.419069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.420563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.420579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.422388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.425311] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  703.425345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.425361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  703.425383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.442090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.442116] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.442150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.442247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.442286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.458812] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  703.458836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.458879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  703.477742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  703.477778] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.477798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.477815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.477833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.477852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.477871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.477890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.477912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.477933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.477953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.477973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.477992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.478011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.478038] [drm:intel_power_well_disable [i915]] disabling display
>[  703.478061] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.478085] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  703.478101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.478261] [drm:drm_mode_addfb2] [FB:75]
>[  703.478285] [drm:drm_mode_addfb2] [FB:78]
>[  703.503892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  703.503976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  703.504034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.504088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.504098] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.504145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.504162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.504179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.504198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.504212] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.504228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.504244] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.504258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.504273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.504287] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.504300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.504303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.504316] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.504319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.504333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.504350] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.504368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.504385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.504403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.504420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.504438] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.504455] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.504473] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.504492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.504511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.507037] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.507055] [drm:intel_power_well_enable [i915]] enabling display
>[  703.507070] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.507102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.507121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.507140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.507159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.507178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.507196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.507217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.507237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.507256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.507275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.507291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.507311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.507330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.509330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.509348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.509364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.509383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.510904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.510921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.510936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.512434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.512451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.514261] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.517218] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.517271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.517288] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.517311] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.534040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.534067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.534105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.550793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.550814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.550836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.550859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.550879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.550900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.550921] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.550941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.550962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.550982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.551002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.551006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.551026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.551030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.551050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.551071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.551091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.551111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.551131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.551151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.551172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  703.551193] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.551213] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.551234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.551256] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.551306] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.551331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.551370] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.568177] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.568196] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.568217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.568234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.568249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.568264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.568279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.568295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.568312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.568328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.568344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.568358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.568372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.568399] [drm:intel_power_well_disable [i915]] disabling display
>[  703.568420] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.568439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.568460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.568481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.568496] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.568534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.568543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.568590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.568609] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.568629] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.568651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.568670] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.568689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.568709] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.568728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.568747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.568810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.568835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.568849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.568870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.568875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.568897] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.568917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.568938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.568957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.568980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.569000] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.569022] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  703.569041] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.569061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.569084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.569108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.569162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.569183] [drm:intel_power_well_enable [i915]] enabling display
>[  703.569206] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.569246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.569269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.569291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.569313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.569335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.569358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.569383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.569407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.569428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.569442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.569454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.569471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.569485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.571465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.571481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.571497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.571515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.573029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.573044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.573058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.574554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.574569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.576379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.579304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.579336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.579352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.579374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.596083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.596113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.596147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.596239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.596277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.612785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.612809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.612845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.631718] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.631736] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.631756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.631816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.631846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.631869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.631895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.631918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.631947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.631972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.631998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.632023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.632043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.632066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.632106] [drm:intel_power_well_disable [i915]] disabling display
>[  703.632139] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.632170] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.632195] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.632349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.632357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.632397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.632412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.632428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.632446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.632461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.632476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.632492] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.632506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.632520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.632533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.632546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.632550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.632562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.632565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.632578] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.632591] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.632604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.632617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.632631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.632644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.632657] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.632670] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.632682] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.632697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.632713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.632748] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.632789] [drm:intel_power_well_enable [i915]] enabling display
>[  703.632814] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.632851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.632872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.632895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.632915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.632937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.632959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.632984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.633008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.633032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.633052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.633073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.633097] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.633120] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.635117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.635133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.635147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.635161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.636669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.636684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.636698] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.638196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.638211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.640018] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.642967] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.643028] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.643048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.643073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.659787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.659815] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.659853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.659969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.660018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.676464] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.676487] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.676520] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.695385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.695404] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.695425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.695442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.695460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.695475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.695489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.695505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.695523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.695540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.695556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.695571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.695585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.695599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.695625] [drm:intel_power_well_disable [i915]] disabling display
>[  703.695646] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.695667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.695682] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.695848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.695863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.695931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.695954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.695981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.696010] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.696032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.696057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.696081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.696106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.696128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.696152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.696173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.696179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.696200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.696206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.696229] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.696250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.696272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.696293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.696318] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.696338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.696361] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.696381] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.696403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.696426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.696453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.696521] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.696545] [drm:intel_power_well_enable [i915]] enabling display
>[  703.696568] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.696613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.696634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.696655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.696675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.696695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.696716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.696739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.696762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.696803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.696825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.696845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.696870] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.696892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.698890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.698906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.698920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.698935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.700440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.700456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.700469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.701967] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.701983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.703791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.706728] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.706838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.706860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.706889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.723537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.723564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.723600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.723717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.723764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.740235] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.740259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.740303] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.759166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.759185] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.759206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.759226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.759247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.759267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.759286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.759305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.759327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.759348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.759368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.759388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.759407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.759426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.759453] [drm:intel_power_well_disable [i915]] disabling display
>[  703.759475] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.759500] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.759516] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.759595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.759604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.759650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.759669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.759689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.759712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.759731] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.759750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.759813] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.759838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.759862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.759885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.759907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.759914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.759935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.759942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.759964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.759985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.760007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.760028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.760052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.760074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.760096] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.760117] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.760138] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.760169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.760195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.760259] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.760281] [drm:intel_power_well_enable [i915]] enabling display
>[  703.760303] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.760343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.760366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.760388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.760410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.760432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.760454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.760470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.760485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.760500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.760513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.760526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.760542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.760557] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.762534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.762551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.762564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.762579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.764089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.764105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.764122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.765618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.765635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.767446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.770378] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.770453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.770469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.770489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.787198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.787224] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.787259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.787356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.787395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.803866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.803892] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.803937] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.822804] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.822823] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.822843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.822861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.822878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.822893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.822908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.822924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.822942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.822958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.822974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.822990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.823004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.823018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.823044] [drm:intel_power_well_disable [i915]] disabling display
>[  703.823067] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.823091] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.823108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.823214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.823223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.823268] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.823288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.823308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.823330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.823349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.823369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.823388] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.823407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.823427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.823445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.823464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.823468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.823487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.823491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.823510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.823529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.823548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.823567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.823586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.823612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.823629] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.823645] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.823658] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.823675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.823692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.823733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.823746] [drm:intel_power_well_enable [i915]] enabling display
>[  703.823758] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.823830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.823851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.823873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.823893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.823913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.823934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.823958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.823981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.824003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.824023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.824043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.824066] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.824087] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.826080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.826096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.826113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.826132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.827638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.827656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.827673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.829172] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.829190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.831004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.833940] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.834013] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.834032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.834058] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.850756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.850800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.850835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.850933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.850973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.867436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.867460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.867504] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.886374] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.886393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.886414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.886430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.886448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.886463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.886477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.886493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.886514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.886535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.886555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.886576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.886594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.886611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.886639] [drm:intel_power_well_disable [i915]] disabling display
>[  703.886661] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.886686] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.886702] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.886885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.886896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.886942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.886960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.886978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.887005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.887019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.887036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.887051] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.887069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.887087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.887105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.887123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.887127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.887144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.887148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.887166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.887183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.887201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.887219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.887237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.887255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.887273] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.887291] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.887309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.887328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.887347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.887389] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.887403] [drm:intel_power_well_enable [i915]] enabling display
>[  703.887417] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.887445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.887463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.887481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.887499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.887517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.887534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.887554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.887572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.887592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.887609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.887627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.887645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.887663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.889643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.889660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.889674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.889689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.891197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.891212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.891226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.892722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.892737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.894547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.897473] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.897506] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.897525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.897551] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.914248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.914275] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.914310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.914400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.914441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.930930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.930955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.931001] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  703.949867] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  703.949886] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  703.949906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.949923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.949941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.949956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.949971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.949987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.950005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.950021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.950037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.950052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.950067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.950080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.950107] [drm:intel_power_well_disable [i915]] disabling display
>[  703.950128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  703.950149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.950164] [drm:intel_power_well_disable [i915]] disabling always-on
>[  703.950250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.950259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  703.950301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  703.950317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  703.950335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  703.950357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  703.950376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  703.950396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  703.950415] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  703.950435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  703.950454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  703.950473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  703.950492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  703.950496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.950514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  703.950518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  703.950537] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  703.950557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  703.950576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  703.950595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  703.950614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  703.950640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  703.950657] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  703.950672] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  703.950686] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  703.950702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.950719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  703.950760] [drm:intel_power_well_enable [i915]] enabling always-on
>[  703.950813] [drm:intel_power_well_enable [i915]] enabling display
>[  703.950834] [drm:hsw_set_power_well [i915]] Enabling power well
>[  703.950871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  703.950893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  703.950914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  703.950934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  703.950955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  703.950976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  703.950999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  703.951022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  703.951045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.951065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  703.951084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  703.951108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  703.951130] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  703.953126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  703.953142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  703.953157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.953171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  703.954676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  703.954691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  703.954705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  703.956202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  703.956218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  703.958025] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  703.960968] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  703.961035] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  703.961052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  703.961074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  703.977778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  703.977821] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  703.977858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  703.977959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  703.978001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  703.994458] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  703.994482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  703.994526] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  704.013396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  704.013415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.013435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.013452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.013469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.013485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.013499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.013515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.013533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.013550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.013566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.013581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.013595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.013609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.013636] [drm:intel_power_well_disable [i915]] disabling display
>[  704.013657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.013681] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  704.013698] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.013868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.013883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.013954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.013981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.014009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.014040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.014055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.014071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.014087] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  704.014104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  704.014122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.014140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.014158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.014162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.014179] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.014183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.014201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.014219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.014237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.014254] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  704.014272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.014290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.014308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  704.014326] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  704.014344] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  704.014362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.014382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  704.014424] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.014438] [drm:intel_power_well_enable [i915]] enabling display
>[  704.014452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.014480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.014498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.014516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.014534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.014553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.014570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.014590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.014610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.014629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.014646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.014664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.014683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  704.014698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.016689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.016707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.016724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.016742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.018252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.018268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.018282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.019783] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.019810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.021617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.023700] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  704.023765] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.023812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  704.023849] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.040505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.040530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  704.040567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.040668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.040708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.057191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  704.057216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.057262] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  704.076127] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  704.076146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.076166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.076183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.076201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.076216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.076230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.076249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.076270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.076291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.076311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.076332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.076350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.076366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.076394] [drm:intel_power_well_disable [i915]] disabling display
>[  704.076416] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.076441] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  704.076457] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.078714] [IGT] kms_flip: exiting, ret=0
>[  704.098295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.098314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.098334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.098355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.098372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.098389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.098407] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.098426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.098447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.098466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.098486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.098490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.098509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.098512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.098532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.098552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.098572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.098591] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.098612] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.098631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.098651] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.098670] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.098690] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.098711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.098733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.098804] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.098828] [drm:intel_power_well_enable [i915]] enabling display
>[  704.098843] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.098872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.098891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.098909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.098927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.098945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.098963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.098984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.099003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.099023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.099041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.099058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.099078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.099096] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.101098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.101114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.101128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.101145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.102660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.102674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.102688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.104193] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.104207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.106024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.109054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.109081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.109096] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.109117] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.109168] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.109189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.125829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.125853] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.125889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.126012] Console: switching to colour frame buffer device 240x75
>[  704.261752] Console: switching to colour dummy device 80x25
>[  704.261905] [IGT] kms_flip: executing
>[  704.273276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  704.273304] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  704.274860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  704.274881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  704.276852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  704.276859] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  704.278853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  704.278873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  704.280854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  704.280860] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  704.280864] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  704.280880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  704.280903] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  704.281955] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  704.282845] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  704.282862] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  704.282877] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  704.282891] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  704.283889] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  704.283913] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  704.284968] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  704.284971] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  704.285051] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  704.285053] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  704.285057] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  704.285059] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  704.285063] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  704.285065] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  704.285072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  704.285074] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.285077] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  704.285079] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  704.285082] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  704.285085] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  704.285087] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  704.285089] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  704.285092] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  704.285094] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  704.285097] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  704.285099] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  704.285101] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  704.285104] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  704.285106] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  704.285109] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  704.285111] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  704.285114] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  704.285116] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  704.285119] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  704.285121] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  704.285123] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  704.285126] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  704.285128] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  704.285131] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  704.285133] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  704.285135] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  704.285138] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  704.285140] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  704.285143] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  704.285145] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  704.285174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  704.285192] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  704.286843] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  704.286861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  704.288858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  704.288864] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  704.290859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  704.290880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  704.292855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  704.292861] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  704.292864] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  704.294168] [IGT] kms_flip: starting subtest single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
>[  704.294580] [drm:drm_mode_addfb2] [FB:77]
>[  704.294602] [drm:drm_mode_addfb2] [FB:79]
>[  704.337101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.337155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.342718] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.342746] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.342789] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.361280] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.361302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.361319] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.361339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.361355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.361374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.361389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.361404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.361420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.361438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.361458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.361479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.361499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.361518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.361537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.361565] [drm:intel_power_well_disable [i915]] disabling display
>[  704.361588] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.361614] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.361632] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.361685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  704.361752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.361836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.361852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.361916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.361939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.361964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.361992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.362013] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.362037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.362059] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.362081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.362102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.362124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.362143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.362149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.362169] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.362174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.362196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.362215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.362235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.362254] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.362277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.362296] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.362316] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.362335] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.362356] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.362377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.362402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.364954] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.364970] [drm:intel_power_well_enable [i915]] enabling display
>[  704.364984] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.365013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.365030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.365046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.365062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.365076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.365095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.365115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.365135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.365155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.365173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.365189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.365209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.365228] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.367208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.367226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.367240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.367256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.368768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.368783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.368797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.370336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.370354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.372171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.375120] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.375180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.375197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.375219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.375259] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.375276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.391932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.391958] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.391992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.408692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.408715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.408736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.408760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.408780] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.408800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.408864] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.408894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.408922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.408947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.408972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.408980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.409004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.409010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.409034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.409057] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.409083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.409106] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.409131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.409154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.409179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  704.409202] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.409223] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.409248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.409277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.425313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.425338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.425377] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.443580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.443602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.443619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.443638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.443655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.443670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.443685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.443700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.443716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.443733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.443750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.443766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.443780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.443794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.443871] [drm:intel_power_well_disable [i915]] disabling display
>[  704.443907] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.443933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.443960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.443989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.444013] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.444100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.444114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.444183] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.444215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.444241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.444267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.444290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.444314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.444338] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.444361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.444383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.444405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.444426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.444432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.444453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.444458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.444480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.444502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.444523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.444545] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.444569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.444591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.444613] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  704.444634] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.444653] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.444677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.444702] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.444770] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.444793] [drm:intel_power_well_enable [i915]] enabling display
>[  704.444835] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.444876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.444901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.444924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.444947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.444969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.444993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.445019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.445043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.445067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.445089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.445112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.445137] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.445161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.447166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.447184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.447200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.447218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.448748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.448764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.448778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.450276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.450292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.452101] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.455048] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.455111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.455128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.455153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.455202] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.455228] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.455295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.455326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.455359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.471928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.471971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.505210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.505234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.505277] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.524147] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.524171] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.524191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.524212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.524232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.524253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.524272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.524291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.524310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.524332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.524353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.524373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.524393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.524412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.524428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.524455] [drm:intel_power_well_disable [i915]] disabling display
>[  704.524478] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.524503] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.524521] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.524619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.524628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.524675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.524695] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.524714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.524736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.524755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.524774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.524794] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.524813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.524875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.524900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.524923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.524930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.524952] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.524958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.524981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.525002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.525024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.525053] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.525076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.525095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.525115] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.525135] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.525154] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.525178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.525201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.525254] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.525275] [drm:intel_power_well_enable [i915]] enabling display
>[  704.525298] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.525326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.525343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.525362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.525380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.525397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.525415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.525434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.525453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.525472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.525489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.525506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.525525] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.525541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.527519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.527535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.527550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.527565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.529074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.529089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.529102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.530596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.530611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.532421] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.535342] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.535377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.535394] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.535415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.535462] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.535488] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.552112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.552137] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.552172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.552280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.552320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.585476] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.585500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.585545] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.603949] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.603971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.603987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.604007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.604024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.604041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.604056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.604071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.604087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.604105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.604121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.604137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.604152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.604166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.604185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.604213] [drm:intel_power_well_disable [i915]] disabling display
>[  704.604235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.604259] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.604277] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.604391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.604400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.604446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.604466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.604486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.604508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.604526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.604546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.604565] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.604584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.604603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.604622] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.604641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.604645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.604663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.604667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.604687] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.604706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.604725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.604743] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.604763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.604781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.604800] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.604863] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.604891] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.604914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.604942] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.605008] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.605032] [drm:intel_power_well_enable [i915]] enabling display
>[  704.605055] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.605092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.605371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.605393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.605415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.605435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.605458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.605482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.605506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.605529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.605549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.605570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.605592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.605615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.607624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.607643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.607660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.607678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.609190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.609206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.609221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.610715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.610732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.612543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.615465] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.615500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.615516] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.615538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.615586] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.615611] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.632242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.632267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.632303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.632413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.632453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.665603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.665626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.665670] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.684524] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.684546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.684562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.684582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.684599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.684616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.684631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.684646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.684662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.684679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.684695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.684711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.684726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.684740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.684754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.684780] [drm:intel_power_well_disable [i915]] disabling display
>[  704.684801] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.684863] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.684890] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.685078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.685092] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.685143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.685160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.685179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.685198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.685214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.685232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.685249] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.685266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.685281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.685297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.685311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.685316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.685329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.685333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.685348] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.685362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.685377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.685390] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.685407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.685421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.685435] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.685449] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.685463] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.685480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.685507] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.685556] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.685573] [drm:intel_power_well_enable [i915]] enabling display
>[  704.685596] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.685621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.685636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.685653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.685669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.685687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.685705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.685724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.685743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.685763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.685780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.685797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.685816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.685862] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.687858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.687875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.687889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.687904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.689414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.689429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.689443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.690946] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.690962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.692772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.695706] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.695781] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.695805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.695862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.696019] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.696035] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.712526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.712552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.712586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.712686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.712742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.745883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.745907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.745942] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.764793] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.764816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.764879] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.764910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.764937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.764963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.764979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.764994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.765011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.765030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.765047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.765064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.765079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.765096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.765120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.765149] [drm:intel_power_well_disable [i915]] disabling display
>[  704.765172] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.765196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.765214] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.765311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.765320] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.765366] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.765386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.765414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.765435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.765453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.765471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.765489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.765506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.765524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.765543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.765560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.765564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.765582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.765585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.765604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.765621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.765640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.765657] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.765675] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.765692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.765710] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.765728] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.765746] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.765765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.765784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.765848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.765869] [drm:intel_power_well_enable [i915]] enabling display
>[  704.765889] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.765927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.765950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.765971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.765992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.766012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.766033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.766057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.766080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.766103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.766123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.766142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.766165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.766187] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.768182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.768199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.768213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.768228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.769733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.769748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.769761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.771258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.771274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.773083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.776023] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.776092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.776109] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.776131] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.776170] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.776187] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.792846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.792871] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.792905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.793012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.793052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.826191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.826215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.826250] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.845092] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.845113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.845130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.845149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.845166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.845184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.845199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.845215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.845231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.845249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.845265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.845281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.845297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.845315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.845333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.845361] [drm:intel_power_well_disable [i915]] disabling display
>[  704.845384] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.845408] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.845426] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.845542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.845551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.845599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.845618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.845638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.845660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.845679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.845699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.845718] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  704.845737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  704.845756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.845775] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.845794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.845798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.845817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.845859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.845887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.845911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.845936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.845958] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  704.845983] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.846005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.846028] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  704.846049] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  704.846071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  704.846097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.846123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  704.846193] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.846223] [drm:intel_power_well_enable [i915]] enabling display
>[  704.846246] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.846285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.846309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.846331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.846353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.846374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.846397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.846422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.846446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.846470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.846491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.846509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.846526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  704.846541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.848519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.848535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.848549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.848564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.850072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.850088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.850102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.851596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.851612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.853423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.856345] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  704.856381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.856404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  704.856424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.856459] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  704.856474] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  704.873127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.873152] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.873186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.873295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.873335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.906485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  704.906511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.906548] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  704.925413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  704.925434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  704.925451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.925470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.925486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.925504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.925519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.925534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.925550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.925567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.925584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.925600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.925615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.925629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.925643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.925670] [drm:intel_power_well_disable [i915]] disabling display
>[  704.925691] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.925711] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  704.925728] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.925973] [drm:drm_mode_addfb2] [FB:77]
>[  704.926019] [drm:drm_mode_addfb2] [FB:78]
>[  704.951560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.951648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  704.951699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.951749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  704.951759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.951808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.951824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.951885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.951911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.951933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.951956] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.951980] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  704.952003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  704.952024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.952044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.952065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.952071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.952090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.952096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.952116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.952138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.952153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.952166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  704.952182] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.952195] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.952208] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  704.952220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  704.952233] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  704.952248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.952265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  704.954773] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.954789] [drm:intel_power_well_enable [i915]] enabling display
>[  704.954803] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.954834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.954881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.954908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.954929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.954952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.954974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.955000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.955024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.955049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.955070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.955092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.955117] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  704.955140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.957143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.957159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.957173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.957188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.958694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.958709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.958722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.960230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.960248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.962057] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.964580] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  704.964619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.964635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  704.964655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.981346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.981371] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  704.981404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.998121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.998141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.998159] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.998179] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.998195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.998212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.998229] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  704.998245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  704.998260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.998275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.998289] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.998293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.998307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.998310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.998325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.998339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.998353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.998366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  704.998383] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.998397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.998412] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  704.998426] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  704.998439] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  704.998456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.998473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  704.998528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  704.998547] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.998581] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.016615] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.016634] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.016654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.016671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.016687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.016702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.016716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.016732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.016749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.016765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.016781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.016795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.016809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.016836] [drm:intel_power_well_disable [i915]] disabling display
>[  705.016904] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.016932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.016959] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.016987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.017012] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.017255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.017270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.017341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.017367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.017394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.017424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.017448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.017475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.017501] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.017526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.017551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.017575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.017598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.017604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.017627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.017633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.017656] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.017680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.017702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.017723] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.017748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.017771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.017796] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  705.017817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.017839] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.017890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.017919] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.017980] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.018165] [drm:intel_power_well_enable [i915]] enabling display
>[  705.018178] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.018205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.018220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.018235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.018248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.018261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.018278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.018297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.018316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.018335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.018352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.018368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.018387] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.018404] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.020405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.020423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.020439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.020457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.021971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.021988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.022002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.023497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.023513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.025339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.028274] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.028347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.028364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.028386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.028443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.028471] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.028507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.045169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.045212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.061791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.061817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.061893] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.080754] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.080772] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.080792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.080809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.080826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.080849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.080910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.080935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.080965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.080992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.081019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.081045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.081066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.081089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.081129] [drm:intel_power_well_disable [i915]] disabling display
>[  705.081163] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.081196] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.081221] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.081401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.081409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.081449] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.081464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.081481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.081498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.081512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.081527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.081543] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.081557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.081571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.081584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.081597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.081600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.081613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.081616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.081629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.081642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.081655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.081671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.081689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.081707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.081724] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.081741] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.081759] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.081777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.081796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.081839] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.081880] [drm:intel_power_well_enable [i915]] enabling display
>[  705.081905] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.081944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.081967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.081991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.082012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.082035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.082057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.082082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.082108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.082132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.082152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.082173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.082197] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.082221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.084217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.084233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.084247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.084264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.085789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.085805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.085819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.087316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.087332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.089145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.092085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.092153] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.092170] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.092195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.108897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.108923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.108957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.109067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.109107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.125597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.125621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.125667] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.144543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.144564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.144586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.144605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.144627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.144646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.144666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.144685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.144707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.144727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.144748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.144768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.144787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.144803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.144831] [drm:intel_power_well_disable [i915]] disabling display
>[  705.144895] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.144932] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.144958] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.145253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.145268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.145334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.145352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.145370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.145390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.145406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.145422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.145441] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.145461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.145481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.145500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.145519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.145523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.145541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.145545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.145565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.145584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.145603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.145622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.145655] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.145678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.145694] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.145708] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.145721] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.145737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.145756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.145799] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.145813] [drm:intel_power_well_enable [i915]] enabling display
>[  705.145826] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.145882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.145908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.145931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.145953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.145976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.145997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.146023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.146048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.146073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.146092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.146114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.146140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.146161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.148457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.148474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.148488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.148503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.150013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.150029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.150042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.151538] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.151554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.153365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.156324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.156374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.156391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.156413] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.173118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.173143] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.173178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.173285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.173326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.189796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.189820] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.189894] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.208742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.208761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.208782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.208799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.208816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.208832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.208847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.208910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.208936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.208953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.208970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.208985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.208999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.209013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.209041] [drm:intel_power_well_disable [i915]] disabling display
>[  705.209062] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.209084] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.209100] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.209208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.209217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.209260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.209277] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.209295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.209315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.209331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.209348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.209364] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.209384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.209403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.209423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.209443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.209448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.209466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.209470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.209490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.209510] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.209529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.209548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.209568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.209587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.209606] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.209626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.209645] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.209665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.209685] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.209731] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.209746] [drm:intel_power_well_enable [i915]] enabling display
>[  705.209762] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.209792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.209812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.209832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.209853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.209898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.209924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.209951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.209976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.210000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.210022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.210044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.210076] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.210098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.212093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.212110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.212127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.212146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.213652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.213669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.213683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.215181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.215197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.217006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.219940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.220015] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.220031] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.220053] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.236758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.236784] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.236819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.236999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.237040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.253441] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.253465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.253501] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.272376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.272395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.272415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.272432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.272449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.272464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.272483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.272502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.272524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.272545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.272565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.272586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.272605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.272623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.272652] [drm:intel_power_well_disable [i915]] disabling display
>[  705.272674] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.272698] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.272714] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.272835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.272877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.272952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.272980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.273009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.273039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.273062] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.273080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.273098] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.273114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.273130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.273146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.273160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.273164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.273182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.273188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.273212] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.273227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.273241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.273255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.273271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.273293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.273306] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.273319] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.273331] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.273346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.273362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.273405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.273418] [drm:intel_power_well_enable [i915]] enabling display
>[  705.273431] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.273456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.273470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.273484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.273497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.273510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.273523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.273539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.273553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.273567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.273580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.273592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.273608] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.273623] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.275605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.275622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.275636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.275650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.277158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.277173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.277187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.278681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.278697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.280509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.283432] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.283464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.283480] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.283500] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.300210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.300236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.300272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.300385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.300425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.316891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.316917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.316954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.335812] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.335830] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.335851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.335911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.335941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.335965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.335989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.336014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.336037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.336054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.336070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.336087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.336101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.336116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.336142] [drm:intel_power_well_disable [i915]] disabling display
>[  705.336164] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.336190] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.336206] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.336307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.336316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.336363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.336383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.336403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.336426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.336445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.336465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.336485] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.336504] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.336523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.336543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.336561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.336565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.336584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.336588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.336609] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.336628] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.336648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.336667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.336686] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.336705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.336725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.336752] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.336769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.336788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.336808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.336850] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.336889] [drm:intel_power_well_enable [i915]] enabling display
>[  705.336911] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.336950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.336972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.336994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.337014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.337035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.337056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.337080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.337102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.337125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.337144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.337164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.337188] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.337209] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.339205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.339222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.339236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.339251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.340756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.340771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.340785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.342282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.342300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.344108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.347048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.347118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.347135] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.347157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.363859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.363903] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.363939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.364046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.364087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.380539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.380564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.380598] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.399474] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.399493] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.399514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.399533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.399555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.399574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.399593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.399612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.399634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.399654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.399674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.399695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.399714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.399730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.399758] [drm:intel_power_well_disable [i915]] disabling display
>[  705.399780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.399805] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.399821] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.400009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.400023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.400102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.400124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.400142] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.400161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.400176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.400192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.400208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.400222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.400237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.400250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.400264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.400268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.400281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.400284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.400298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.400311] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.400324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.400340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.400358] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.400376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.400394] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.400412] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.400430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.400449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.400468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.400511] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.400525] [drm:intel_power_well_enable [i915]] enabling display
>[  705.400539] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.400567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.400586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.400604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.400622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.400640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.400658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.400678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.400697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.400717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.400734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.400752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.400772] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.400798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.402783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.402799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.402813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.402828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.404335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.404351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.404365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.405861] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.405889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.407696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.410632] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.410706] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.410723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.410745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.427448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.427474] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.427508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.427616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.427656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.444147] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.444175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.444227] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.463098] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.463119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.463141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.463161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.463182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.463202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.463221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.463240] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.463261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.463282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.463302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.463323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.463342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.463358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.463386] [drm:intel_power_well_disable [i915]] disabling display
>[  705.463408] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.463433] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.463449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.463565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.463574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.463617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.463635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.463654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.463675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.463693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.463711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.463729] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  705.463747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  705.463765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.463783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.463801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.463804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.463822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.463825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.463843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.463861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.463920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.463943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.463967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.463990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.464011] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  705.464032] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  705.464052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  705.464076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.464100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  705.464168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.464191] [drm:intel_power_well_enable [i915]] enabling display
>[  705.464213] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.464250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.464266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.464281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.464295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.464308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.464323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.464339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.464354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.464369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.464383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.464396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.464413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  705.464428] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.466412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.466428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.466442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.466456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.467970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.467988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.468006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.469503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.469520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.471330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.474276] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  705.474339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.474358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  705.474384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.491081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.491107] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.491142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.491242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.491283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.507761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  705.507785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.507829] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  705.526647] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  705.526667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.526689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.526709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.526730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.526750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.526769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.526788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.526810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.526830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.526850] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.526871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.526932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.526958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.527002] [drm:intel_power_well_disable [i915]] disabling display
>[  705.527035] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.527069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  705.527094] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.527345] [drm:drm_mode_addfb2] [FB:77]
>[  705.527370] [drm:drm_mode_addfb2] [FB:78]
>[  705.552975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  705.553083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  705.553140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.553193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.553203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.553252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.553269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.553286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.553305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.553319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.553335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.553351] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.553368] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.553386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.553404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.553421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.553424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.553441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.553445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.553463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.553480] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.553498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.553515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.553533] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.553551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.553568] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.553586] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.553603] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.553622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.553641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.556168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.556184] [drm:intel_power_well_enable [i915]] enabling display
>[  705.556199] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.556229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.556247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.556263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.556278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.556293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.556308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.556326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.556342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.556358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.556372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.556386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.556403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.556420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.558427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.558444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.558458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.558473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.559988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.560005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.560023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.561520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.561537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.563347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.566297] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.566356] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.566372] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.566394] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.583125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.583152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.583187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.599864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.599902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.599922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.599944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.599962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.599983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.600003] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.600024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.600044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.600065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.600085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.600089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.600109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.600112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.600133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.600154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.600174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.600194] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.600214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.600234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.600255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  705.600276] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.600296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.600317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.600339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.600389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.600414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.600452] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.617622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.617641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.617661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.617679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.617694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.617709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.617724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.617740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.617757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.617773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.617789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.617803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.617817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.617844] [drm:intel_power_well_disable [i915]] disabling display
>[  705.617865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.617924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.617950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.617980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.618005] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.618092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.618107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.618176] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.618201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.618229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.618258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.618283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.618309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.618335] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.618360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.618384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.618408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.618431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.618437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.618459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.618465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.618489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.618512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.618535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.618556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.618581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.618604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.618629] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  705.618652] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.618681] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.618705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.618730] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.618785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.618807] [drm:intel_power_well_enable [i915]] enabling display
>[  705.618829] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.618867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.618908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.618931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.618954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.618976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.619000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.619025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.619050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.619075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.619097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.619119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.619145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.619168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.621161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.621176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.621190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.621205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.622710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.622725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.622739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.624234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.624249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.626060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.628998] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.629068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.629085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.629106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.629188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.629229] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.629278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.645909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.645950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.662491] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.662515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.662560] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.681417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.681436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.681456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.681473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.681490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.681505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.681519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.681535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.681553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.681569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.681585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.681601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.681615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.681628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.681655] [drm:intel_power_well_disable [i915]] disabling display
>[  705.681676] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.681697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.681713] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.681805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.681814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.681857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.681873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.681935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.681967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.681992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.682020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.682054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.682078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.682101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.682124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.682146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.682153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.682174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.682180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.682203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.682225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.682247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.682268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.682293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.682315] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.682337] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.682359] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.682381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.682406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.682431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.682495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.682518] [drm:intel_power_well_enable [i915]] enabling display
>[  705.682537] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.682575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.682598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.682619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.682639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.682660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.682682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.682707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.682730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.682754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.682776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.682796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.682822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.682845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.684861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.684878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.684925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.684952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.686464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.686479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.686496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.688005] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.688023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.689836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.692475] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.692543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.692563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.692589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.709281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.709306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.709341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.709447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.709485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.725964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.725986] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.726021] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.744878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.744915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.744935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.744952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.744969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.744984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.744999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.745015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.745032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.745048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.745064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.745080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.745094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.745108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.745135] [drm:intel_power_well_disable [i915]] disabling display
>[  705.745156] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.745177] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.745192] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.745300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.745309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.745351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.745367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.745385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.745404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.745420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.745436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.745453] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.745471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.745491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.745510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.745529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.745533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.745551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.745555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.745574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.745593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.745613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.745631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.745651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.745669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.745689] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.745708] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.745727] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.745747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.745767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.745813] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.745828] [drm:intel_power_well_enable [i915]] enabling display
>[  705.745843] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.745872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.745921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.745948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.745974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.745998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.746023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.746051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.746076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.746103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.746125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.746148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.746177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.746208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.748198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.748215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.748233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.748251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.749756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.749773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.749787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.751282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.751298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.753104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.756043] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.756114] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.756131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.756153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.772853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.772878] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.772969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.773095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.773134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.789535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.789558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.789592] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.807656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.807675] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.807695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.807712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.807733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.807752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.807772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.807791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.807812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.807833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.807853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.807874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.807936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.807966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.808010] [drm:intel_power_well_disable [i915]] disabling display
>[  705.808229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.808263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.808289] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.808419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.808427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.808472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.808489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.808507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.808533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.808548] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.808563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.808578] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.808593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.808606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.808619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.808632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.808636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.808648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.808651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.808664] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.808677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.808690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.808702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.808717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.808730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.808743] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.808755] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.808767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.808782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.808799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.808841] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.808854] [drm:intel_power_well_enable [i915]] enabling display
>[  705.808866] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.808922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.808947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.808970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.808993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.809016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.809039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.809065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.809089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.809113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.809135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.809157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.809184] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.809208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.811434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.811451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.811465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.811480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.813010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.813027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.813042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.814534] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.814550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.816378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.819317] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.819387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.819404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.819429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.836128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.836154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.836189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.836299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.836351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.852817] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.852840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.852873] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.871793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.871812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.871832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.871849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.871867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.871882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.871942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.871966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.871996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.872022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.872049] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.872075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.872092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.872107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.872134] [drm:intel_power_well_disable [i915]] disabling display
>[  705.872155] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.872176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.872192] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.872293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.872302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.872346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.872363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.872381] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.872400] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.872416] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.872434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.872450] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.872466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.872482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.872496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.872511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.872515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.872529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.872533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.872552] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.872571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.872592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.872611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.872631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.872650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.872670] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.872689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.872709] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.872730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.872751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.872798] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.872814] [drm:intel_power_well_enable [i915]] enabling display
>[  705.872836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.872864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.872880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.872917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.872939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.872960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.872981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.873005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.873028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.873050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.873070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.873090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.873115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.873136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.875134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.875151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.875165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.875182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.876687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.876703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.876717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.878216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.878232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.880040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.882982] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.883049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.883066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.883096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.899793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.899819] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.899854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.900037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.900090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.916485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.916508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.916542] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.934623] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.934642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.934661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.934678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.934696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.934712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.934726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.934743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.934760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.934777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.934792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.934808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.934823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.934836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.934863] [drm:intel_power_well_disable [i915]] disabling display
>[  705.934884] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.934950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.934974] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.935238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.935247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.935300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.935316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.935333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.935351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.935365] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.935381] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.935397] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.935412] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.935426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.935440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.935453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.935457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.935469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.935473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.935486] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.935499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.935512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.935525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.935540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.935553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.935570] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.935588] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.935606] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.935624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.935643] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.935686] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.935700] [drm:intel_power_well_enable [i915]] enabling display
>[  705.935714] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.935742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.935760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.935778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.935796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.935814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.935832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.935852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.935870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.935890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.935934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.935957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.935982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.936003] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  705.937997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  705.938014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  705.938028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.938043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  705.939548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  705.939563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  705.939577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  705.941077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  705.941093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  705.942902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  705.945846] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  705.945949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  705.945976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  705.946006] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  705.962661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.962687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.962722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.962848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.962896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.979354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  705.979377] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  705.979422] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  705.998290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  705.998309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  705.998329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.998346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.998364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.998379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.998394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.998410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  705.998428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.998445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.998461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.998477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.998491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.998505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.998532] [drm:intel_power_well_disable [i915]] disabling display
>[  705.998553] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  705.998574] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  705.998590] [drm:intel_power_well_disable [i915]] disabling always-on
>[  705.998686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  705.998694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  705.998741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  705.998761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  705.998781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  705.998803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  705.998822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  705.998841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  705.998861] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  705.998880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  705.998899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  705.998959] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  705.998984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  705.998991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.999013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  705.999020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  705.999043] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  705.999064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  705.999086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  705.999107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  705.999133] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  705.999155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  705.999177] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  705.999198] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  705.999219] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  705.999245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  705.999271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  705.999520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  705.999534] [drm:intel_power_well_enable [i915]] enabling display
>[  705.999547] [drm:hsw_set_power_well [i915]] Enabling power well
>[  705.999574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  705.999590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  705.999605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  705.999619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  705.999633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  705.999648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  705.999664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  705.999678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  705.999693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  705.999707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  705.999720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  705.999736] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  705.999750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  706.001729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  706.001746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  706.001760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.001774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  706.003282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  706.003297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  706.003311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.004805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  706.004821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  706.006631] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  706.009557] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  706.009596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  706.009612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  706.009632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  706.026334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.026360] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  706.026395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.026524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  706.026574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.043030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  706.043053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  706.043097] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  706.061964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  706.061983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  706.062003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.062020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.062038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.062053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.062068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.062084] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.062102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.062118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.062134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.062149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.062163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.062177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.062204] [drm:intel_power_well_disable [i915]] disabling display
>[  706.062225] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  706.062246] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  706.062261] [drm:intel_power_well_disable [i915]] disabling always-on
>[  706.062368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  706.062377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  706.062420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  706.062436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  706.062456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  706.062478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  706.062496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  706.062516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  706.062536] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  706.062555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  706.062574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  706.062593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  706.062612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  706.062616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.062634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  706.062638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.062657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  706.062677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  706.062696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  706.062714] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  706.062740] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  706.062757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  706.062773] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  706.062787] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  706.062800] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  706.062816] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.062832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  706.062874] [drm:intel_power_well_enable [i915]] enabling always-on
>[  706.062887] [drm:intel_power_well_enable [i915]] enabling display
>[  706.062934] [drm:hsw_set_power_well [i915]] Enabling power well
>[  706.062973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.062994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.063015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.063035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.063055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.063075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.063099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.063121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.063144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.063163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.063183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.063206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  706.063227] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  706.065443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  706.065459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  706.065473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.065487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  706.067000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  706.067015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  706.067029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.068525] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  706.068542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  706.070354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  706.073311] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  706.073363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  706.073380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  706.073402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  706.090107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.090132] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  706.090167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.090290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  706.090339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.106800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  706.106823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  706.106867] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  706.125681] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  706.125700] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  706.125720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.125736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.125754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.125769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.125784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.125800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.125817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.125834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.125849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.125865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.125884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.125901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.125975] [drm:intel_power_well_disable [i915]] disabling display
>[  706.126009] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  706.126042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  706.126068] [drm:intel_power_well_disable [i915]] disabling always-on
>[  706.127455] [IGT] kms_flip: exiting, ret=0
>[  706.148385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  706.148404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  706.148424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  706.148445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  706.148461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  706.148478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  706.148496] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  706.148512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  706.148530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  706.148549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  706.148569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  706.148574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.148593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  706.148596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.148616] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  706.148636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  706.148655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  706.148675] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  706.148695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  706.148715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  706.148734] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  706.148754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  706.148774] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  706.148795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.148817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  706.148882] [drm:intel_power_well_enable [i915]] enabling always-on
>[  706.148899] [drm:intel_power_well_enable [i915]] enabling display
>[  706.148930] [drm:hsw_set_power_well [i915]] Enabling power well
>[  706.148963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.148983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.149003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.149023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.149043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.149063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.149085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.149106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.149127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.149147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.149167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.149187] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  706.149207] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  706.151201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  706.151217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  706.151234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.151252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  706.152762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  706.152777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  706.152791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.154287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  706.154302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  706.156115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  706.159154] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  706.159226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  706.159241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  706.159264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  706.159319] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  706.159343] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  706.175974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.175999] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  706.176035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.176160] Console: switching to colour frame buffer device 240x75
>[  706.309629] Console: switching to colour dummy device 80x25
>[  706.309722] [IGT] kms_flip: executing
>[  706.321389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  706.321418] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  706.322984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  706.323004] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  706.324976] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  706.324982] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  706.326977] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  706.326998] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  706.328977] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  706.328983] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  706.328987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  706.329003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  706.329026] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  706.330062] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  706.330960] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  706.330978] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  706.330993] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  706.331007] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  706.331999] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  706.332023] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  706.333080] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  706.333083] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  706.333162] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  706.333164] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  706.333168] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  706.333170] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  706.333174] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  706.333176] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  706.333183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  706.333186] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.333189] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.333191] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.333193] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  706.333196] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  706.333198] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  706.333201] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  706.333203] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.333206] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.333208] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  706.333211] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  706.333213] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  706.333215] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  706.333218] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  706.333220] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  706.333223] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  706.333225] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  706.333228] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  706.333230] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  706.333232] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  706.333235] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  706.333237] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  706.333240] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  706.333242] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  706.333245] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  706.333247] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  706.333249] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  706.333252] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  706.333254] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  706.333257] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  706.333286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  706.333304] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  706.334966] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  706.334982] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  706.336977] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  706.336982] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  706.338989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  706.339010] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  706.340978] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  706.340983] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  706.340987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  706.341187] [IGT] kms_flip: starting subtest 2x-wf_vblank-ts-check
>[  706.343597] [IGT] kms_flip: exiting, ret=77
>[  706.376240] Console: switching to colour frame buffer device 240x75
>[  706.506111] Console: switching to colour dummy device 80x25
>[  706.506206] [IGT] kms_flip: executing
>[  706.516429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  706.516458] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  706.517989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  706.518010] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  706.519993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  706.519999] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  706.521989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  706.522010] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  706.523989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  706.523995] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  706.523999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  706.524016] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  706.524040] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  706.525077] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  706.525982] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  706.526001] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  706.526016] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  706.526030] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  706.527026] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  706.527051] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  706.528107] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  706.528110] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  706.528190] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  706.528192] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  706.528196] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  706.528198] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  706.528202] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  706.528204] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  706.528211] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  706.528214] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.528216] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.528219] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.528221] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  706.528224] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  706.528226] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  706.528229] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  706.528231] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.528234] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  706.528236] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  706.528238] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  706.528241] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  706.528243] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  706.528246] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  706.528248] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  706.528251] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  706.528253] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  706.528256] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  706.528258] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  706.528261] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  706.528263] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  706.528265] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  706.528268] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  706.528270] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  706.528273] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  706.528275] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  706.528277] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  706.528280] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  706.528282] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  706.528285] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  706.528315] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  706.528332] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  706.529962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  706.529981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  706.532000] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  706.532007] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  706.533989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  706.534008] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  706.535990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  706.535995] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  706.535999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  706.536206] [IGT] kms_flip: starting subtest absolute-wf_vblank
>[  706.536607] [drm:drm_mode_addfb2] [FB:77]
>[  706.536630] [drm:drm_mode_addfb2] [FB:79]
>[  706.579030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  706.579083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.592999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  706.593023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  706.593070] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  706.611940] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  706.611979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  706.611996] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  706.612016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.612033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.612051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.612067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.612082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.612098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.612116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.612132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.612148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.612163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.612177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.612191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.612218] [drm:intel_power_well_disable [i915]] disabling display
>[  706.612241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  706.612266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  706.612285] [drm:intel_power_well_disable [i915]] disabling always-on
>[  706.612326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  706.612393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  706.612457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  706.612468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  706.612519] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  706.612535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  706.612551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  706.612572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  706.612589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  706.612607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  706.612625] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  706.612642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  706.612660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  706.612677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  706.612695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  706.612698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.612715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  706.612719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  706.612737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  706.612754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  706.612771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  706.612788] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  706.612806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  706.612823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  706.612840] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  706.612858] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  706.612875] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  706.612894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  706.612913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  706.615486] [drm:intel_power_well_enable [i915]] enabling always-on
>[  706.615502] [drm:intel_power_well_enable [i915]] enabling display
>[  706.615517] [drm:hsw_set_power_well [i915]] Enabling power well
>[  706.615545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  706.615563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  706.615579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  706.615594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  706.615608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  706.615624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  706.615644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  706.615664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  706.615684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  706.615702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  706.615719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  706.615739] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  706.615758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  706.617742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  706.617759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  706.617773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.617789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  706.619301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  706.619316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  706.619330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  706.620826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  706.620842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  706.622652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  706.625579] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  706.625611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  706.625630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  706.625657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  706.625711] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  706.625727] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  706.642359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  706.642383] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  706.642416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.668363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.684741] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  716.684784] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  716.684864] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  716.703749] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  716.703772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  716.703789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  716.703810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.703827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.703845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.703860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.703875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.703892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.703910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.703926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.703942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.703958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.703973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.703986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.704014] [drm:intel_power_well_disable [i915]] disabling display
>[  716.704036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  716.704058] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  716.704075] [drm:intel_power_well_disable [i915]] disabling always-on
>[  716.704279] [drm:drm_mode_addfb2] [FB:77]
>[  716.704302] [drm:drm_mode_addfb2] [FB:78]
>[  716.727320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  716.727407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.727465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.727519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.727530] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  716.727635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  716.727660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  716.727687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  716.727714] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  716.727737] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  716.727762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  716.727786] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  716.727809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  716.727833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  716.727855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  716.727876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  716.727882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.727903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  716.727908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.727930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  716.727951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  716.727971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  716.727992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  716.728016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  716.728036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  716.728056] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  716.728078] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  716.728099] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  716.728123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.728149] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  716.730670] [drm:intel_power_well_enable [i915]] enabling always-on
>[  716.730685] [drm:intel_power_well_enable [i915]] enabling display
>[  716.730698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  716.730726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.730742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.730756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.730770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.730783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.730798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.730814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.730828] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.730843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.730856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.730869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.730886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  716.730900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  716.732884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  716.732901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  716.732915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.732930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  716.734436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  716.734451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  716.734465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.735963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  716.735979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  716.737786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  716.740733] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  716.740796] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  716.740816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  716.740842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  716.757539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.757582] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  716.757617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.783556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.783737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  726.783825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.784002] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  726.800892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  726.800911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.800932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.800949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.800967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.800982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.800997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.801012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.801030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.801047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.801062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.801078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.801096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.801115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.801145] [drm:intel_power_well_disable [i915]] disabling display
>[  726.801214] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.801251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  726.801278] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.801533] [drm:drm_mode_addfb2] [FB:77]
>[  726.801573] [drm:drm_mode_addfb2] [FB:78]
>[  726.827055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  726.827135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  726.827244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.827303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.827313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.827360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.827377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.827395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.827413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.827427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.827443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.827459] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.827474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.827488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.827501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.827515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.827518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.827531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.827534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.827547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.827560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.827572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.827584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.827602] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.827619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.827637] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.827655] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.827672] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.827691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.827710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.830230] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.830247] [drm:intel_power_well_enable [i915]] enabling display
>[  726.830263] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.830294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.830313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.830332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.830351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.830370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.830388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.830409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.830429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.830449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.830467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.830485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.830505] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.830524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.832516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.832534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.832548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.832564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.834097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.834113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.834127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.835624] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.835640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.837448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.840400] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.840459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.840479] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.840512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.857203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.857230] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.857268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.883204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.883381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  736.883470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.883645] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  736.900835] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  736.900867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.900901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.900929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.900958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.900984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.901008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.901034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.901069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.901103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.901137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.901171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.901202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.901233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.901280] [drm:intel_power_well_disable [i915]] disabling display
>[  736.901316] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.901358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  736.901385] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.903918] [IGT] kms_flip: exiting, ret=0
>[  736.923265] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.923285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.923305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.923325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.923342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.923359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.923377] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  736.923393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  736.923409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.923424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.923438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.923443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.923457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.923460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.923475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.923489] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.923503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.923518] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  736.923535] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.923549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.923564] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  736.923578] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  736.923592] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  736.923609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.923628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  736.923682] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.923699] [drm:intel_power_well_enable [i915]] enabling display
>[  736.923716] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.923749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.923784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.923804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.923824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.923844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.923864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.923886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.923907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.923929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.923948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.923967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.923989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  736.924008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.926000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.926015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.926029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.926043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.927555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.927568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.927581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.929083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.929097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.930914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.933939] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  736.933973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.933992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  736.934019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.934067] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  736.934085] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  736.950729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.950754] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  736.950811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.950936] Console: switching to colour frame buffer device 240x75
>[  737.255487] Console: switching to colour dummy device 80x25
>[  737.255580] [IGT] kms_flip: executing
>[  737.269316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  737.269345] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  737.271425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  737.271445] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  737.273518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  737.273525] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  737.275600] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  737.275620] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  737.277694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  737.277700] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  737.277704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  737.277720] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  737.277743] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  737.278770] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  737.279668] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  737.279684] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  737.279699] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  737.279712] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  737.280696] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  737.280711] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  737.281758] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  737.281761] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  737.281878] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  737.281881] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  737.281885] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  737.281887] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  737.281891] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  737.281893] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  737.281900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  737.281903] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.281906] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  737.281908] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  737.281911] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  737.281913] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  737.281916] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  737.281918] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  737.281921] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  737.281923] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  737.281926] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  737.281928] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  737.281931] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  737.281933] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  737.281936] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  737.281938] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  737.281941] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  737.281943] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  737.281945] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  737.281948] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  737.281951] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  737.281953] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  737.281955] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  737.281958] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  737.281960] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  737.281963] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  737.281965] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  737.281968] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  737.281970] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  737.281972] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  737.281975] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  737.282004] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  737.282022] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  737.283836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  737.283856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  737.285839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  737.285844] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  737.287839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  737.287858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  737.289839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  737.289844] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  737.289848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  737.291080] [IGT] kms_flip: starting subtest nonexisting-fb-interruptible
>[  737.291483] [drm:drm_mode_addfb2] [FB:75]
>[  737.291506] [drm:drm_mode_addfb2] [FB:79]
>[  737.333785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.333839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.334383] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  737.334407] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.334452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  737.353325] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  737.353348] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  737.353365] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.353385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.353402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.353423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.353443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.353463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.353482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.353504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.353525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.353545] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.353566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.353585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.353601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.353630] [drm:intel_power_well_disable [i915]] disabling display
>[  737.353653] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.353678] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  737.353697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.353753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.353905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  737.353995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.354006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  737.354049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.354067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.354086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.354107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.354125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.354144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.354162] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  737.354180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  737.354198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.354217] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.354234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.354239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.354256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.354259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.354277] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.354295] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.354313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.354330] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  737.354348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.354366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.354383] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  737.354401] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  737.354419] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  737.354437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.354457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  737.356958] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.356973] [drm:intel_power_well_enable [i915]] enabling display
>[  737.356986] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.357013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.357031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.357049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.357066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.357084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.357101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.357120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.357138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.357157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.357174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.357189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.357208] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  737.357225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.359206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.359224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.359241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.359260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.360766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.360788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.360834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.362332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.362348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.364163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.367109] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  737.367178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.367194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  737.367214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.367260] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  737.367284] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  737.383918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.383944] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  737.383981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.400615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.400973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.400978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.401981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.401985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.402963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.402996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.403993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.403997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.404964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.404968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.405983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.405988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.406976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.406982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.407974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.407979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.408992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.408996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.409984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.409988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.410970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.410974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.411988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.411993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.412994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.412998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.413993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.413998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.414972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.414976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.415962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.415995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.416994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.416999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.417965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.417969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.418990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.418995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.419976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.419980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.420990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.420994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.421988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.421992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.422964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.422999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.423971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.423975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.424968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.424972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.425981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.425985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.426971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.426975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.427988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.427992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.428964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.428998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.429962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.429966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.430986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.430990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.431959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.431963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.432964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.432968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.433964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.433968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.434986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.434990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.435980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.435985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.436962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.436966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.437990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.437996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.438963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.438967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.439971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.439975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.440968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.440972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.441981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.441985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.442965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.442969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.443995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.443999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.444989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.444993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.445987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.445992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.446967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.446971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.447984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.447989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.448975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.448979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.449959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.449963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.450974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.450978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.451985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.451989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.452966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.452970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.453964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.453968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.454976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.454999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.455990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.455994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.456960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.456996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.457980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.457984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.458983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.458988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.459960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.459964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.460965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.460969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.461961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.461966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.462963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.462967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.463978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.463982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.464963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.464967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.465961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.465997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.466966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.466970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.467963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.467967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.468988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.468992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.469987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.469991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.470982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.470986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.471986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.471990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.472994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.472998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.473991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.473995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.474962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.474999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.475964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.475999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.476993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.476998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.477984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.477988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.478983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.478986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.479954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.479958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.480966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.480970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.481968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.481972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.482984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.482989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.483981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.483985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.484960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.484964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.485984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.485988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.486984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.486989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.487966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.487999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.488994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.488999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.489972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.489976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.490980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.490984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.491969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.491973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.492971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.492975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.493992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.493996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.494980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.494984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.495995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.495999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.496977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.496981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.497970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.497974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.498988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.498992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.499961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.499997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.500986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.500991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.501989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.501994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.502978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.502982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.503979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.503983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.504977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.504981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.505988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.505992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.506976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.506980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.507973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.507978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.508992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.508996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.509966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.509970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.510983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.510987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.511993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.511996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.512989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.512994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.513982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.513986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.514965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.514969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.515963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.515999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.516979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.516983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.517964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.517998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.518980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.518984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.519969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.519973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.520979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.520983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.521992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.521996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.522964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.522996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.523974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.523979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.524972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.524976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.525986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.525990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.526964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.526968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.527983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.527987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.528994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.528999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.529986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.529991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.530994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.530997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.531969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.531973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.532981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.532986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.533985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.533989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.534983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.534987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.535963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.535967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.536962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.536967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.537973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.537977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.538988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.538991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.539973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.539977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.540984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.540988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.541993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.541997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.542993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.542997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.543991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.543995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.544971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.544975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.545980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.545984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.546963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.546997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.547988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.547992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.548980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.548985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.549988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.549992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.550978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.550982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.551981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.551985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.552995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.552999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.553961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.553996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.554994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.554999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.555991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.555996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.556991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.556995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.557995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.557999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.558974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.558998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.559961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.559998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.560993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.560998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.561969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.561973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.562984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.562988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.563979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.563983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.564985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.564989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.565966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.565970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.566969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.566973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.567985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.567990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.568973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.568977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.569961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.569965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.570963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.570999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.571990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.571994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.572970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.572974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.573962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.573999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.574971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.574975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.575964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.575998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.576963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.576997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.577979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.577983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.578972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.578977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.579977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.579981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.580993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.580997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.581983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.581987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.582986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.582991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.583981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.583985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.584961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.584997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.585994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.585999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.586973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.586977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.587987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.587991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.588977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.589985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.589989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.590978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.590982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.591979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.591983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.592987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.592991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.593982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.593986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.594963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.594967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.595974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.595978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.596993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.596997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.597976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.597980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.598992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.598997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.599991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.599995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.600966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.600970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.601971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.601975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.602973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.602997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.603977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.603981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.604961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.604998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.605986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.605990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.606992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.606996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.607972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.607976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.608982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.608987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.609980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.609985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.610961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.610964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.611964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.611967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.612966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.612970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.613974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.613978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.614995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.614999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.615960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.615965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.616971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.616975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.617968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.617972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.618980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.618984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.619979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.619983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.620965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.620969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.621975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.621980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.622978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.622982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.623989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.623993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.624965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.624969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.625963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.625968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.626995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.626999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.627992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.627996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.628975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.628999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.629993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.629997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.630970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.630974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.631988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.631992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.632974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.632978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.633994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.633998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.634968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.634972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.635981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.635985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.636965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.636998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.637978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.637982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.638966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.638971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.639975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.639979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.640990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.640994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.641977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.641981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.642983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.642988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.643994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.643998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.644965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.644999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.645989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.645993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.646988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.646993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.647985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.647989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.648970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.648975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.649963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.649999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.650995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.650999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.651976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.651980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.652972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.652977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.653980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.653984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.654985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.654989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.655970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.655974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.656967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.656971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.657988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.657994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.658988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.658992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.659963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.659967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.660978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.660982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.661980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.661984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.662981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.662985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.663986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.663990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.664992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.664996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.665990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.665994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.666970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.666974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.667977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.667982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.668966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.668998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.669970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.669974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.670992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.670996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.671964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.671998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.672975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.672979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.673991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.673995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.674966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.674970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.675977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.675981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.676987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.676991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.677969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.677974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.678979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.678983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.679967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.679971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.680966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.680970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.681994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.681998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.682966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.682999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.683972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.683996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.684981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.684985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.685988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.685993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.686990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.686994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.687984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.687988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.688959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.688963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.689962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.689997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.690978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.690981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.691986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.691990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.692984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.692988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.693994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.693998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.694979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.694983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.695990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.695994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.696970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.696974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.697965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.697969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.698992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.698997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.699969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.699974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.700977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.700981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.701981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.701985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.702973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.702997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.703961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.703965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.704967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.704971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.705988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.705992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.706994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.706998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.707983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.707986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.708969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.708973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.709962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.709998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.710962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.710966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.711985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.711989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.712982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.712986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.713989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.713993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.714970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.714974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.715991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.715995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.716974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.716998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.717989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.717993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.718959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.718994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.719966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.719971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.720980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.720984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.721995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.721999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.722991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.722995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.723969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.723973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.724969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.724973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.725967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.725971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.726980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.726984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.727961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.727965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.728971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.728975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.729965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.729999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.730971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.730975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.731985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.731989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.732964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.732968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.733967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.733971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.734985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.734989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.735969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.735974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.736983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.736987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.737967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.737971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.738993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.738998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.739965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.739969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.740979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.740984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.741985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.741989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.742962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.742998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.743977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.743981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.744989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.744993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.745989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.745994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.746961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.746998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.747983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.747987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.748962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.748966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.749982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.749986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.750978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.750982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.751971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.751975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.752972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.752976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.753991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.753995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.754975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.754979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.755968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.755972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.756991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.756995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.757959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.757964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.758990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.758994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.759987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.759991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.760981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.760985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.761976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.761980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.762970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.762974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.763994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.763998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.764985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.764989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.765985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.765989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.766962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.766966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.767962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.767966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.768967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.768971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.769984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.769988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.770962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.770967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.771961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.771965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.772979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.772983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.773966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.773970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.774985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.774989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.775959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.775963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.776962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.776998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.777991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.777996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.778979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.778983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.779988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.779993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.780977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.780981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.781989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.781993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.782969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.782974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.783974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.783978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.784979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.784983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.785959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.785963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.786979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.786983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.787991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.787995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.788971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.788975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.789994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.789999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.790987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.790991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.791990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.791994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.792964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.792968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.793963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.793995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.794978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.794983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.795971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.795975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.796973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.796977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.797964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.797998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.798976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.798980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.799989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.799994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.800973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.800977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.801982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.801986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.802984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.802988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.803975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.803999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.804973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.804997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.805965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.805969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.806960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.806995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.807973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.807977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.808980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.808984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.809986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.809990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.810983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.810987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.811985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.811989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.812969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.812973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.813974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.813978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.814974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.814978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.815989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.815993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.816988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.816993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.817976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.817980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.818987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.818992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.819990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.819994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.820975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.820979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.821963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.821998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.822986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.822990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.823989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.823993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.824970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.824974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.825962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.825966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.826983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.826987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.827990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.827994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.828985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.828989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.829992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.829996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.830969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.830973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.831990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.831994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.832983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.832987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.833990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.833994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.834964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.834998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.835989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.835993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.836975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.836978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.837964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.837968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.838957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.838962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.839993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.839997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.840991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.840995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.841977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.841982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.842990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.842994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.843966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.843970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.844990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.844994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.845966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.845999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.846995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.846999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.847971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.847975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.848976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.848980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.849965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.849969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.850976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.850980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.851959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.851964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.852985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.852989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.853992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.853996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.854965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.854969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.855994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.855999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.856972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.856976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.857961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.857997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.858980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.858985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.859993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.859997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.860985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.860989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.861972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.861997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.862989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.862993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.863961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.863995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.864989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.864993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.865967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.865971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.866991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.866996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.867978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.867981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.868992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.868996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.869971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.869975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.870991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.870995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.871989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.871993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.872995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.872999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.873968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.873972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.874983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.874987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.875964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.875968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.876965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.876969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.877979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.877984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.878964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.878998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.879985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.879989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.880983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.880987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.881961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.881965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.882976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.882981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.883986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.883990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.884973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.884977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.885980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.885984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.886992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.886996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.887962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.887966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.888991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.888995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.889973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.889978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.890962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.890999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.891990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.891994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.892971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.892976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.893975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.893980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.894978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.894982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.895983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.895987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.896994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.896998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.897971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.897975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.898968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.898972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.899994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.899998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.900635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.900722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.901023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  737.901056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.901105] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  737.919463] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  737.919485] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  737.919501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.919520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.919535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.919552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.919567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.919581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.919595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.919612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.919628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.919643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.919658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.919675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.919693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.919722] [drm:intel_power_well_disable [i915]] disabling display
>[  737.919744] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.919768] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  737.919785] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.920036] [drm:drm_mode_addfb2] [FB:75]
>[  737.920075] [drm:drm_mode_addfb2] [FB:78]
>[  737.947579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.947672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.947730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  737.947784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.947794] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  737.947873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.947899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.947926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.947953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.947976] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.947993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.948009] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.948025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.948039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.948053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.948067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.948070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.948084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.948087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.948101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.948114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.948128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.948140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.948156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.948170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.948183] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  737.948197] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.948209] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.948226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.948243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.950852] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.950867] [drm:intel_power_well_enable [i915]] enabling display
>[  737.950880] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.950908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.950924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.950939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.950953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.950967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.950982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.950998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.951018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.951042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.951056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.951069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.951086] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.951101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.953080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.953104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.953120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.953135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.954642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.954665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.954685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.956186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.956203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.958007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.960893] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.960963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.960979] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.961000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.977690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.977713] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.977746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.994391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.994960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.994965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.995995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.995999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.996975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.996979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.997991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.997996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.998976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.998980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  737.999993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.999997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.000979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.000983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.001992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.001997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.002987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.002991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.003995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.003999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.004987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.004991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.005966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.005971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.006980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.006985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.007977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.007982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.008993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.008997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.009985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.009989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.010961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.010996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.011969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.011973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.012982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.012986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.013982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.013986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.014990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.014994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.015986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.015990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.016987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.016991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.017992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.017996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.018969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.018973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.019987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.019991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.020994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.020998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.021980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.021984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.022989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.022993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.023993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.023997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.024976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.024980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.025991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.025995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.026979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.026983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.027972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.027976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.028976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.028980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.029962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.029996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.030970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.030974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.031994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.031999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.032977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.032981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.033995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.033999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.034963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.034967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.035980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.035984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.036972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.036977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.037979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.037983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.038959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.038964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.039970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.039974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.040977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.040981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.041974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.041998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.042960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.042964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.043967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.043971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.044987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.044992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.045982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.045987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.046963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.046999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.047970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.047974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.048984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.048988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.049983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.049987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.050987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.050991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.051970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.051974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.052977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.052982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.053963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.053967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.054975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.054979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.055962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.055966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.056975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.056980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.057990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.057994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.058993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.058997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.059965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.059969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.060990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.060994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.061962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.061966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.062971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.062976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.063983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.063987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.064968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.064973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.065989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.065993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.066985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.066990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.067979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.067983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.068966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.068970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.069982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.069986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.070976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.070981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.071988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.071992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.072995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.072999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.073970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.073974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.074984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.074988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.075959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.075963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.076961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.076997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.077979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.077983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.078963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.078997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.079979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.079983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.080993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.080997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.081986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.081990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.082982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.082986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.083993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.083997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.084993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.084997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.085984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.085988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.086992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.086996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.087962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.087997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.088982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.088986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.089969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.089973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.090993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.090997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.091962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.091966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.092964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.092968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.093978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.093982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.094989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.094994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.095975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.095999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.096964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.096968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.097963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.097967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.098977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.098981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.099963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.099996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.100991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.100996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.101969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.101974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.102982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.102986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.103966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.103970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.104978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.104982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.105964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.105968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.106964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.106999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.107969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.107973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.108989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.108993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.109993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.109997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.110983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.110987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.111963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.111967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.112992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.112996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.113980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.113985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.114992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.114996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.115962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.115966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.116967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.116971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.117981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.117985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.118963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.118997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.119982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.119986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.120995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.120999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.121980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.121984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.122963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.122968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.123978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.123982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.124974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.124998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.125976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.125980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.126991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.126995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.127965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.127969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.128979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.128984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.129982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.129987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.130985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.130990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.131975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.131979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.132983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.132987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.133994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.133998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.134973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.134998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.135965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.135969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.136963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.136967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.137980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.137984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.138993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.138997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.139990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.139994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.140966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.140970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.141995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.141999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.142985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.142989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.143992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.143996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.144964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.144968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.145960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.145965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.146962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.146966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.147981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.147985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.148976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.148980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.149983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.149988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.150967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.150972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.151969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.151973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.152963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.152997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.153989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.153992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.154961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.154965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.155979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.155983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.156960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.156996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.157965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.157999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.158987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.158991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.159972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.159997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.160963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.160967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.161962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.161998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.162989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.162993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.163989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.163993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.164976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.164980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.165972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.165977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.166966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.166970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.167976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.167981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.168975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.168979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.169986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.169990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.170961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.170965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.171962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.171998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.172983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.172987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.173967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.173971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.174977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.174981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.175991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.175995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.176992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.176996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.177970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.177974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.178961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.178995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.179965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.179998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.180974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.180998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.181959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.181996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.182961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.182997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.183993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.183997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.184965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.184969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.185974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.185978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.186959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.186996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.187974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.187979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.188976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.188980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.189989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.189993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.190975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.190979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.191973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.191997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.192974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.192978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.193981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.193985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.194965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.194969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.195967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.195971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.196995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.196998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.197980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.197984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.198962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.198996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.199966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.199971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.200973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.200997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.201971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.201976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.202994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.202998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.203961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.203996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.204979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.204983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.205965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.205970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.206978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.206982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.207980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.207984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.208968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.208973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.209968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.209972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.210983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.210988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.211976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.211980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.212970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.212974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.213981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.213985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.214987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.214992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.215983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.215987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.216971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.216996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.217974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.217978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.218974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.218979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.219983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.219987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.220964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.220998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.221990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.221995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.222968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.222972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.223975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.223979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.224963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.224967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.225982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.225986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.226994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.226998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.227974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.227978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.228987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.228991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.229969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.229973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.230978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.230982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.231972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.231976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.232981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.232986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.233968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.233972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.234978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.234982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.235990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.235994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.236990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.236994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.237962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.237967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.238964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.238967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.239971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.239976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.240994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.240998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.241992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.241997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.242990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.242994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.243968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.243972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.244963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.244967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.245982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.245986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.246991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.246996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.247971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.247975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.248979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.248983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.249963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.249995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.250983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.250987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.251961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.251965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.252977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.252981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.253992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.253996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.254973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.254977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.255983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.255988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.256983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.256987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.257960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.257996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.258977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.258982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.259986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.259990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.260959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.260996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.261964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.261968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.262975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.262979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.263986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.263990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.264985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.264990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.265960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.265963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.266963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.266967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.267963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.267967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.268967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.268972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.269972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.269997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.270984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.270988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.271987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.271991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.272964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.272999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.273964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.273997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.274976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.274980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.275978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.275982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.276995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.276999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.277991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.277995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.278977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.278981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.279980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.279984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.280989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.280994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.281986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.281990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.282967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.282971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.283971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.283975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.284985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.284989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.285979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.285983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.286984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.286988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.287971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.287975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.288963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.288968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.289977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.289981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.290973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.290977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.291965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.291969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.292963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.292967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.293961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.293966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.294991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.294995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.295976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.295999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.296959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.296964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.297973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.297977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.298994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.298998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.299994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.299999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.300994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.300998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.301995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.301999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.302981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.302986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.303962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.303996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.304978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.304982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.305988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.305993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.306975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.306979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.307990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.307994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.308963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.308997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.309976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.309980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.310984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.310988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.311971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.311975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.312962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.312997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.313983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.313987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.314982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.314986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.315972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.315996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.316978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.316982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.317980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.317984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.318995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.318999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.319968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.319972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.320984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.320988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.321985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.321989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.322959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.322995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.323970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.323974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.324969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.324974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.325962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.325998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.326973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.326977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.327982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.327986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.328987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.328992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.329994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.329998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.330960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.330997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.331992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.331997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.332987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.332991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.333965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.333998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.334974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.334998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.335973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.335978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.336969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.336973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.337964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.337998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.338963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.338968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.339994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.339998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.340976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.340980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.341968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.341971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.342978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.342982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.343978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.343983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.344969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.344974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.345971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.345975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.346990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.346994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.347962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.347998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.348964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.348969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.349995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.349999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.350993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.350997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.351966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.351971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.352992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.352996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.353990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.353994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.354982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.354986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.355963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.355999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.356963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.356968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.357965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.357970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.358962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.358967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.359984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.359988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.360972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.360977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.361969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.361974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.362972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.362975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.363974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.363999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.364961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.364965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.365993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.365997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.366983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.366987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.367970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.367975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.368984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.368988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.369963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.369998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.370992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.370997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.371986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.371990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.372981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.372986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.373959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.373964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.374962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.374996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.375989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.375994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.376991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.376995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.377971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.377975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.378962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.378997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.379969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.379974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.380987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.380991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.381958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.381963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.382966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.382971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.383962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.383966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.384975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.384979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.385981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.385985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.386967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.386971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.387981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.387985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.388973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.388978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.389992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.389996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.390983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.390988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.391978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.391982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.392968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.392973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.393977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.393981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.394964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.394969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.395982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.395986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.396984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.396987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.397991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.397995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.398995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.398999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.399986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.399990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.400991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.400995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.401985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.401989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.402975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.402979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.403969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.403973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.404971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.404976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.405995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.405999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.406976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.406980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.407970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.407975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.408971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.408975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.409964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.409968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.410989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.410993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.411985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.411989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.412976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.412980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.413983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.413988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.414973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.414977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.415986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.415990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.416983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.416987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.417959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.417964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.418982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.418986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.419966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.419999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.420974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.420978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.421990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.421995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.422976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.422980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.423965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.423998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.424966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.424971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.425985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.425989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.426968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.426973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.427967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.427973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.428932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.428977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.429990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.429994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.430984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.430988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.431987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.431991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.432982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.432986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.433964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.433999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.434990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.434996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.435989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.435993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.436990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.436995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.437988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.437992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.438984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.438988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.439980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.439984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.440993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.440998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.441960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.441965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.442938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.442982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.443994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.443999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.444978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.444981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.445971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.445976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.446922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.446967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.447992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.447996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.448978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.448982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.449975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.449980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.450993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.450997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.451970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.451974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.452965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.452999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.453973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.453997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.454980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.454984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.455962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.455998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.456973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.456977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.457975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.457998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.458989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.458993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.459963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.459997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.460984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.460988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.461974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.461978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.462970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.462975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.463984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.463990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.464976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.464980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.465956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.465960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.466929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.466965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.467984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.467989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.468970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.468974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.469978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.469983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.470985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.470989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.471995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.471999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.472966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.472971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.473995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.473999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.474984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.474988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.475974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.475979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.476931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.476972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.477945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.477980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.478981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.478985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.479975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.479979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.480962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.480967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.481976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.481982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.482974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.482978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.483979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.483983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.484995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.484999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.485930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.485975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.486990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.486994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.487976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.487981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.488992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.488997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.489961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.489997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.490968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.490973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.491969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.491974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.492981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.492985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.493958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.493964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.494319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  738.494473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.494520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  738.494542] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.497103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  738.497121] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.497141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.497173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.497203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.497235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.497251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.497266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.497294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.497307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.497355] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.497375] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  738.497546] [drm:drm_mode_addfb2] [FB:75]
>[  738.497569] [drm:drm_mode_addfb2] [FB:78]
>[  738.524196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.524263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  738.524329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.524347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.524366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.524380] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.524397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.524412] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.524428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.524442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.524456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.524473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.524478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.524495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.524498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.524516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.524534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.524552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.524570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.524589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.524606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.524624] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  738.524642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.524660] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.524679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.524699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.527312] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.527328] [drm:intel_power_well_enable [i915]] enabling display
>[  738.527341] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.527370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.527386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.527402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.527420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.527438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.527456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.527476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.527496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.527515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.527533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.527550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.527570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.527588] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.529567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.529584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.529598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.529615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.531122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.531138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.531153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.533700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.535526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.538407] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.538483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.538503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.538531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.555199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.555222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.555254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.571903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.571909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.571942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.571945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.571964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.571967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.571985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.571988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.572977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.572982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.573976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.573980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.574968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.574973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.575962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.575991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.576994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.576998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.577943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.577983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.578955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.578982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.579975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.579980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.580971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.580976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.581947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.581987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.582972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.582996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.583972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.583977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.584982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.584986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.585993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.585997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.586967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.586972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.587981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.587985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.588973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.588978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.589988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.589992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.590959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.590996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.591975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.591999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.592963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.592991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.593990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.593994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.594964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.594999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.595992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.595996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.596986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.596989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.597986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.597990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.598922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.598961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.599991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.599995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.600955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.600985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.601983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.601986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.602966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.602970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.603984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.603988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.604941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.604970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.605958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.605963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.606985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.606989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.607924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.607964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.608973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.608997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.609959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.609996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.610975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.610980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.611983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.611988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.612972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.612977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.613994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.613999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.614960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.614995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.615988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.615992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.616989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.616993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.617945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.617974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.618975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.618980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.619995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.619999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.620973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.620979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.621977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.621982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.622976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.622981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.623961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.623966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.624982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.624987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.625977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.625982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.626990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.626995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.627962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.627968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.628994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.628998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.629966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.629970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.630974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.630998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.631959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.631995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.632973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.632978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.633963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.633997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.634991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.634995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.635985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.635989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.636954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.636998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.637988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.637992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.638986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.638991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.639973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.639997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.640978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.640983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.641994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.641998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.642970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.642975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.643991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.643995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.644971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.644976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.645964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.645969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.646991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.646994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.647988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.647992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.648975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.648980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.649960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.649995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.650990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.650994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.651945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.651998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.652964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.652970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.653962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.653967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.654964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.654999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.655987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.655991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.656934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.656977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.657981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.657985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.658975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.658980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.659966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.659971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.660988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.660991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.661966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.661971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.662978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.662983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.663973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.663978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.664976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.664981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.665981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.665985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.666967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.666972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.667987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.667991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.668968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.668973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.669990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.669994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.670982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.670988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.671974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.671979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.672604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.672808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.673974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.673979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.674988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.674992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.675961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.675967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.676964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.676969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.677963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.677968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.678995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.678999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.679972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.679977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.680964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.680999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.681981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.681986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.682986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.682990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.683973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.683997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.684960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.684966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.685983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.685988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.686963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.686968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.687994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.687998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.688989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.688993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.689967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.689972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.690983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.690988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.691971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.691996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.692977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.692982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.693965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.693971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.694994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.694997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.695981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.695987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.696991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.696995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.697961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.697996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.698979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.698984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.699966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.699970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.700977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.700982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.701988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.701992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.702977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.702982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.703977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.703982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.704981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.704986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.705993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.705997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.706964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.706999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.707981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.707986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.708979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.708984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.709964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.709969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.710911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.710990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.711729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.711974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.712926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.712994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.713786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.713969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.714831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.714982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.715873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.715981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.716816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.716979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.717782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.717969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.718815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.718994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.719950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.719990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.720724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.720991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.721782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.721962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.722813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.722988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.723894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.723971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.724757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.724986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.725956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.725985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.726879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.726960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.727963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.727968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.728959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.728998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.729765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.729961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.730838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.730959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.731825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.731968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.732743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.732996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.733879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.733987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.734760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.734991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.735799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.735962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.736687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.736970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.737946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.737985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.738970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.738999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.739807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.739980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.740940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.740979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.741693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.741979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.742773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.742978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.743938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.743979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.744879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.744998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.745894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.745972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.746726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.746991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.747821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.747995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.748814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.748992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.749897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.749974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.750855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.750962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.751730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.751975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.752790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.752971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.753702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.753965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.754000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.754994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.755891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.755968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.756846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.756969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.757945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.757980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.758743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.758992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.759793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.759973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.760757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.760952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.761800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.761993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.762677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.762982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.763916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.763985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.764958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.764992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.765801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.765993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.766704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.766969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.767854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.767966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.768912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.768972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.769700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.769957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.770724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.770963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.771904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.771981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.772941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.772978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.773857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.773906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.774926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.774962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.775838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.775967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.776856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.776987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.777928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.777977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.778944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.778979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.779694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.779970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.780953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.780984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.781871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.781990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.782939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.782974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.783734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.783978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.784930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.784969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.785928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.785986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.786716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.786989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.787711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.787979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.788710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.788964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.789818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.789976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.790898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.790945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.791958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.791999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.792910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.792987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.793767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.793999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.794772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.794979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.795788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.795966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.796734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.796979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.797785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.797991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.798805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.798973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.799715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.799981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.800838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.800982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.801763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.801998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.802969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.802998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.803898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.803981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.804716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.804961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.805959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.805999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.806945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.806971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.807800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.807960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.808805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.808996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.809795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.809970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.810760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.810984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.811915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.811982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.812844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.812965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.813766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.813998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.814935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.814969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.815809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.815995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.816956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.816986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.817936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.817971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.818798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.818972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.819787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.819958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.820943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.820967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.821921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.821998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.822844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.822977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.823803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.823987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.824923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.824982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.825813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.825982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.826961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.826998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.827987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.827992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.828984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.828989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.829958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.829963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.830972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.830978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.831961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.831996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.832966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.832999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.833973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.833978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.834975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.834980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.835981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.835985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.836976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.836981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.837992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.837997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.838962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.838967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.839964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.839969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.840993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.840997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.841976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.841980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.842978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.842984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.843964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.843970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.844974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.844979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.845989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.845994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.846975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.846999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.847984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.847989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.848961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.848966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.849978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.849983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.850973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.850998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.851983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.851988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.852979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.852984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.853961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.853966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.854981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.854986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.855978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.855983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.856960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.856965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.857963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.857968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.858981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.858986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.859974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.859979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.860993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.860997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.861978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.861983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.862971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.862976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.863987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.863992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.864988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.864992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.865959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.865964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.866987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.866992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.867995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.867999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.868965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.868998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.869976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.869999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.870986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.870991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.871961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.871996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.872973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.872979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.873973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.873978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.874991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.874996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.875967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.875972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.876980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.876985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.877970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.877976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.878993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.878998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.879960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.879965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.880967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.880972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.881991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.881996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.882983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.882988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.883979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.883984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.884961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.884967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.885989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.885994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.886979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.886984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.887973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.887977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.888994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.888999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.889990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.889993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.890989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.890994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.891989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.891994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.892972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.892978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.893959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.893964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.894966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.894970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.895961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.895966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.896977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.896982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.897964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.897969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.898976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.898981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.899993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.899998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.900983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.900988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.901973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.901997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.902967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.902972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.903973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.903978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.904974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.904979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.905969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.905974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.906964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.906968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.907972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.907977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.908980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.908985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.909971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.909976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.910960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.910998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.911987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.911991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.912964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.912970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.913977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.913982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.914979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.914984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.915960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.915965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.916962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.916968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.917994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.917999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.918962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.918967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.919984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.919989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.920982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.920986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.921982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.921986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.922963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.922968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.923972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.923996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.924976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.924981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.925972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.925977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.926993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.926997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.927984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.927989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.928959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.928964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.929971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.929976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.930978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.930983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.931961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.931966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.932979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.932983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.933990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.933995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.934963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.934999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.935964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.935998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.936982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.936988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.937978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.937983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.938962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.938967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.939966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.939971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.940988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.940993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.941959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.941996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.942969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.942974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.943976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.943982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.944982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.944987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.945989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.945994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.946989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.946994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.947979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.947984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.948961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.948995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.949963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.949968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.950968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.950973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.951963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.951968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.952960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.952965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.953971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.953976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.954010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.954015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.954999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.955963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.955996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.956990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.956995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.957967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.957972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.958991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.958996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.959971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.959996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.960975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.960980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.961992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.961997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.962992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.962997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.963986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.963991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.964963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.964968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.965989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.965994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.966975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.966980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.967982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.967987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.968987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.968992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.969959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.969964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.970985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.970989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.971966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.971970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.972985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.972990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.973981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.973986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.974963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.974969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.975965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.975970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.976981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.976986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.977980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.977985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.978959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.978995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.979970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.979976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.980984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.980988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.981987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.981993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.982970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.982976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.983990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.983995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.984973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.984978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.985987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.985992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.986979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.986983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.987972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.987977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.988973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.988978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.989991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.989996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.990982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.990987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.991976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.991982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.992962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.992998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.993978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.993983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.994990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.994995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.995986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.995990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996528] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.996529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.996963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.996992] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.997000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997009] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.997029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997343] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.997347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997360] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.997385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997678] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.997682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.997992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.997997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998008] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.998032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998322] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.998324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998648] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.998662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.998971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.998978] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  738.999006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  738.999974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  738.999979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.000992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.000997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.001961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.001996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.002983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.002988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.003980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.003984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.004989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.004994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.005988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.005993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.006988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.006993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.007964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.007999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.008988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.008993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.009972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.009977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.010959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.010964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.011973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.011978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.012964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.012998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.013974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.013979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.014957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.014995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.015984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.015988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.016983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.016988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.017971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.017976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.018974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.018980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.019983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.019987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.020992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.020997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.021963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.021999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.022965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.022970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.023977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.023982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.024988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.024993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.025992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.025997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.026985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.026989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.027971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.027995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.028987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.028992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.029975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.029980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.030978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.030983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.031963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.031997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.032991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.032996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.033963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.033999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.034987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.034992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.035963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.035997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.036962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.036997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.037988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.037993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.038980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.038984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.039971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.039976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.040966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.040971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.041975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.041980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.042974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.042978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.043960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.043965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.044992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.044997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.045963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.045968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.046973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.046997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.047969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.047973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.048983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.048987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.049991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.049996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.050974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.050999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.051962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.051999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.052966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.052971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.053968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.053973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.054962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.054967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.055992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.055997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.056962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.056967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.057993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.057998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.058984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.058989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.059979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.059983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.060984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.060988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.061952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.061997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.062961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.062965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.063962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.063967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.064978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.064983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.065992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.065997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.066961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.066998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.067964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.067969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.068964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.068969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.069967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.069972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.070960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.070997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.071921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  739.071927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  739.072048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.072116] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.072148] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.072204] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.074712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.074730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.074749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.074765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.074781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.074796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.074810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.074825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.074842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.074858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.074873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.074915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.074935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.074955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.074996] [drm:intel_power_well_disable [i915]] disabling display
>[  739.075020] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.075040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.075054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.076401] [IGT] kms_flip: exiting, ret=0
>[  739.097349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.097366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.097383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.097403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.097420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.097438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.097455] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  739.097473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  739.097490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.097507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.097522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.097526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.097543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.097546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.097562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.097579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.097597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.097614] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  739.097631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.097648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.097665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  739.097683] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  739.097700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  739.097718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.097737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  739.097787] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.097802] [drm:intel_power_well_enable [i915]] enabling display
>[  739.097816] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.097845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.097863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.097880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.097913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.097928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.097944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.097964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.097982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.098001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.098018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.098035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.098053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  739.098070] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.100060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.100075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.100089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.100103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.101610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.101623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.101636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.103133] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.103147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.104957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.107828] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  739.107863] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.107879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  739.107928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.107984] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  739.108006] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  739.124591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.124615] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  739.124649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.124772] Console: switching to colour frame buffer device 240x75
>[  739.271222] Console: switching to colour dummy device 80x25
>[  739.271317] [IGT] kms_flip: executing
>[  739.279347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  739.279371] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  739.280960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.280986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.282947] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.282953] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  739.284995] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.285011] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.287053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.287058] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.287062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  739.287077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  739.287097] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  739.288112] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  739.288997] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  739.289015] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  739.289030] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  739.289044] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  739.290025] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  739.290041] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  739.291099] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  739.291102] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  739.291183] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.291185] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.291189] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  739.291191] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  739.291195] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.291197] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.291204] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  739.291207] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.291210] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.291213] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.291216] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.291218] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.291221] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.291223] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  739.291226] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.291228] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.291231] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.291234] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.291236] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.291239] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  739.291241] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.291243] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.291246] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  739.291249] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.291252] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.291254] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  739.291257] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  739.291259] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  739.291262] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  739.291264] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  739.291267] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  739.291270] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.291272] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.291275] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  739.291277] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.291279] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.291282] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  739.291313] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  739.291330] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  739.292945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.292961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.294945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.294951] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  739.296938] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.296954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.298948] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.298954] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.298958] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  739.300193] [IGT] kms_flip: starting subtest 2x-flip-vs-rmfb-interruptible
>[  739.301552] [IGT] kms_flip: exiting, ret=77
>[  739.324862] Console: switching to colour frame buffer device 240x75
>[  739.475443] Console: switching to colour dummy device 80x25
>[  739.475535] [IGT] kms_flip: executing
>[  739.489482] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  739.489511] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  739.490985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.491006] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.492971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.492977] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  739.494970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.494991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.496972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.496978] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.496982] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  739.496998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  739.497021] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  739.498052] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  739.498965] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  739.498982] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  739.498997] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  739.499014] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  739.500002] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  739.500025] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  739.501109] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  739.501112] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  739.501193] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.501195] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.501200] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  739.501202] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  739.501205] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.501207] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.501215] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  739.501218] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.501221] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.501223] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.501226] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.501228] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.501231] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.501233] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  739.501235] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.501238] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.501240] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.501243] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.501245] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.501248] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  739.501250] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.501252] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.501255] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  739.501257] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.501260] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.501262] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  739.501265] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  739.501267] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  739.501269] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  739.501272] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  739.501274] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  739.501277] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.501279] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.501281] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  739.501284] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.501286] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.501289] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  739.501318] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  739.501336] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  739.502971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.502989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.504973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.504979] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  739.507046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.507065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.509139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.509145] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.509149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  739.509366] [IGT] kms_flip: starting subtest 2x-plain-flip-ts-check
>[  739.511746] [IGT] kms_flip: exiting, ret=77
>[  739.541742] Console: switching to colour frame buffer device 240x75
>[  739.688004] Console: switching to colour dummy device 80x25
>[  739.688096] [IGT] kms_flip: executing
>[  739.702423] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  739.702452] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  739.704532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.704552] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.706626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.706632] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  739.708708] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.708730] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.710804] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.710810] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.710814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  739.710830] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  739.710853] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  739.711878] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  739.712767] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  739.712785] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  739.712803] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  739.712820] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  739.713806] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  739.713823] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  739.714870] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  739.714873] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  739.715007] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.715011] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.715018] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  739.715022] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  739.715028] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.715032] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.715043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  739.715048] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.715051] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.715054] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.715056] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.715059] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.715061] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.715064] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  739.715066] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.715068] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.715071] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.715073] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.715076] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.715078] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  739.715081] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.715083] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.715086] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  739.715088] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.715091] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.715093] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  739.715095] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  739.715098] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  739.715100] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  739.715103] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  739.715105] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  739.715108] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.715110] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.715112] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  739.715115] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.715117] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.715120] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  739.715149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  739.715167] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  739.716984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.717002] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.718991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.718997] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  739.720985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.721005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.722992] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.722998] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.723002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  739.724245] [IGT] kms_flip: starting subtest 2x-blocking-absolute-wf_vblank-interruptible
>[  739.725624] [IGT] kms_flip: exiting, ret=77
>[  739.758617] Console: switching to colour frame buffer device 240x75
>[  739.900908] Console: switching to colour dummy device 80x25
>[  739.901059] [IGT] kms_flip: executing
>[  739.915437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  739.915467] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  739.917548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.917569] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.919645] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  739.919652] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  739.921728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.921747] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  739.923821] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  739.923827] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.923831] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  739.923847] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  739.923870] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  739.924892] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  739.925777] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  739.925794] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  739.925810] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  739.925827] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  739.926811] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  739.926827] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  739.927876] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  739.927879] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  739.928008] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.928012] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.928019] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  739.928022] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  739.928029] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  739.928032] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  739.928044] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  739.928048] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.928053] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.928057] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.928061] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.928065] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  739.928067] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.928070] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  739.928072] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.928075] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  739.928077] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  739.928080] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.928082] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  739.928085] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  739.928087] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.928090] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  739.928092] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  739.928094] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.928097] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  739.928099] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  739.928102] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  739.928104] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  739.928107] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  739.928109] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  739.928112] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  739.928114] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.928116] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  739.928119] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  739.928121] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.928124] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  739.928126] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  739.928155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  739.928173] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  739.929996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.930015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.932004] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  739.932009] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  739.934001] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.934020] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  739.936003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  739.936009] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  739.936013] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  739.936232] [IGT] kms_flip: starting subtest modeset-vs-vblank-race
>[  739.936636] [drm:drm_mode_addfb2] [FB:75]
>[  739.936659] [drm:drm_mode_addfb2] [FB:79]
>[  739.979016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  739.979069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.992050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  739.992077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.992120] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.010985] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.011012] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.011039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.011059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.011077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.011095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.011111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.011126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.011142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.011160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.011177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.011193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.011209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.011223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.011241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.011270] [drm:intel_power_well_disable [i915]] disabling display
>[  740.011293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.011319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.011337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.011376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  740.011449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  740.011516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.011527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.011572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.011592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.011612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.011634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.011653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.011672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.011691] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.011711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.011730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.011749] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.011767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.011771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.011790] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.011793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.011813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.011832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.011851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.011870] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.011889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.011907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.011927] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.011946] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.012013] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.012038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.012064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.014582] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.014597] [drm:intel_power_well_enable [i915]] enabling display
>[  740.014610] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.014637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.014652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.014666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.014680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.014693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.014707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.014726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.014745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.014763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.014781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.014798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.014817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.014834] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.016815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.016832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.016849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.016867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.018376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.018393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.018407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.019903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.019919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.021727] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.024650] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.024684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.024700] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.024722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.024761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.024777] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.041431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.041457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.041491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.058206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.058255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.074790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.074814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.075146] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.092015] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.092037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.092053] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.092075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.092095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.092116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.092136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.092155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.092174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.092196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.092217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.092237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.092258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.092276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.092293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.092320] [drm:intel_power_well_disable [i915]] disabling display
>[  740.092343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.092368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.092386] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.092431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.092440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.092486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.092506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.092526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.092548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.092567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.092586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.092605] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.092624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.092644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.092662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.092681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.092685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.092704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.092708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.092727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.092746] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.092765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.092784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.092809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.092826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.092841] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.092855] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.092869] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.092885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.092902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.092944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.093000] [drm:intel_power_well_enable [i915]] enabling display
>[  740.093025] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.093064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.093088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.093111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.093135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.093157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.093181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.093207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.093232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.093257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.093279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.093301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.093327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.093351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.095351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.095367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.095382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.095397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.096904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.096919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.096933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.098453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.098471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.100303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.103228] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.103260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.103276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.103298] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.103339] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.103358] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.120007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.120033] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.120069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.153392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.153436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.170043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.170067] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.170106] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.188979] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.189001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.189017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.189037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.189053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.189071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.189087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.189101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.189117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.189135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.189152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.189167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.189183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.189197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.189211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.189238] [drm:intel_power_well_disable [i915]] disabling display
>[  740.189259] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.189280] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.189297] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.189339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.189348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.189389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.189405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.189423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.189442] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.189457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.189473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.189489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.189504] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.189519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.189533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.189547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.189551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.189564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.189567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.189581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.189594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.189608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.189621] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.189637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.189651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.189665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.189679] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.189692] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.189708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.189726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.189770] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.189785] [drm:intel_power_well_enable [i915]] enabling display
>[  740.189798] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.189824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.189839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.189854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.189868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.189881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.189896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.189913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.189928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.189944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.189991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.190016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.190045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.190071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.192077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.192093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.192107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.192122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.193626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.193641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.193655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.195153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.195169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.196983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.199918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.200025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.200052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.200089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.200249] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.200267] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.216738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.216763] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.216797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.250124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.250167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.266781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.266806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.266852] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.285677] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.285699] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.285716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.285735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.285752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.285769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.285785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.285799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.285815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.285833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.285849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.285865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.285881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.285895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.285908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.285935] [drm:intel_power_well_disable [i915]] disabling display
>[  740.285956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.286022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.286049] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.286119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.286133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.286201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.286220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.286239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.286258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.286275] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.286292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.286309] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.286325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.286341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.286356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.286371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.286375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.286389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.286392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.286407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.286421] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.286442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.286454] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.286470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.286483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.286497] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.286509] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.286522] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.286537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.286554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.286596] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.286610] [drm:intel_power_well_enable [i915]] enabling display
>[  740.286623] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.286647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.286661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.286675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.286688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.286701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.286715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.286731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.286745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.286759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.286772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.286785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.286801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.286816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.288801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.288817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.288831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.288846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.290353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.290368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.290382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.291905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.291921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.293730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.296667] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.296740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.296766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.296788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.296824] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.296839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.313485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.313510] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.313545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.346882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.346925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.363547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.363570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.363616] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.382488] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.382511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.382531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.382553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.382573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.382594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.382613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.382633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.382652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.382673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.382694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.382714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.382735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.382753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.382772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.382800] [drm:intel_power_well_disable [i915]] disabling display
>[  740.382822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.382855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.382872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.382915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.382924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.382966] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.383024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.383051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.383078] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.383100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.383125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.383148] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.383171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.383193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.383214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.383235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.383242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.383262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.383268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.383290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.383312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.383334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.383355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.383378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.383399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.383422] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.383445] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.383466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.383491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.383517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.383585] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.383610] [drm:intel_power_well_enable [i915]] enabling display
>[  740.383634] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.383673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.383690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.383705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.383720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.383734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.383749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.383766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.383782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.383797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.383811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.383824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.383842] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.383868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.385846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.385862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.385876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.385891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.387400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.387415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.387429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.388925] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.388941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.390750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.393686] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.393760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.393776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.393798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.393836] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.393852] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.410504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.410529] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.410564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.443932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.444077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.460579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.460611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.460675] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.479646] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.479675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.479696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.479722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.479744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.479767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.479787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.479807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.479828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.479851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.479873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.479894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.479915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.479934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.479958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.480055] [drm:intel_power_well_disable [i915]] disabling display
>[  740.480102] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.480147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.480186] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.480259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.480271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.480330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.480353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.480377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.480404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.480424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.480448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.480471] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.480494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.480515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.480536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.480555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.480561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.480580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.480585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.480606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.480625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.480644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.480663] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.480687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.480705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.480725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.480744] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.480763] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.480786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.480811] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.480872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.480893] [drm:intel_power_well_enable [i915]] enabling display
>[  740.480912] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.480947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.480968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.481024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.481056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.481085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.481116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.481150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.481182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.481215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.481243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.481272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.481306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.481338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.483365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.483381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.483397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.483415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.484924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.484940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.484955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.486482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.486498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.488336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.491277] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.491344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.491359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.491379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.491414] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.491429] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.508090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.508115] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.508149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.541473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.541523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.558131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.558154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.558200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.577058] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.577080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.577096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.577116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.577132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.577150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.577166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.577181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.577197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.577214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.577231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.577246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.577262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.577276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.577289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.577316] [drm:intel_power_well_disable [i915]] disabling display
>[  740.577337] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.577357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.577374] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.577409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.577418] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.577460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.577475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.577499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.577517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.577531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.577546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.577563] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.577581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.577599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.577616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.577634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.577637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.577654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.577658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.577675] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.577693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.577710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.577727] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.577745] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.577762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.577780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.577797] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.577814] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.577832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.577851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.577893] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.577908] [drm:intel_power_well_enable [i915]] enabling display
>[  740.577921] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.577948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.577966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.578023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.578046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.578067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.578090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.578113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.578136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.578158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.578177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.578197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.578221] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.578242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.580236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.580253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.580267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.580282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.581788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.581803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.581817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.583315] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.583331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.585140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.588079] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.588149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.588166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.588188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.588226] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.588243] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.604894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.604919] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.604953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.638286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.638331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.654944] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.654966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.655171] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.673674] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.673695] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.673712] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.673732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.673748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.673766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.673781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.673796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.673812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.673830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.673846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.673862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.673878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.673892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.673906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.673933] [drm:intel_power_well_disable [i915]] disabling display
>[  740.673954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.673975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.674036] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.674104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.674119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.674189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.674213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.674232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.674252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.674268] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.674285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.674302] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.674321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.674342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.674362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.674381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.674386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.674405] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.674409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.674428] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.674448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.674467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.674486] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.674507] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.674526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.674546] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.674565] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.674584] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.674605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.674626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.674673] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.674689] [drm:intel_power_well_enable [i915]] enabling display
>[  740.674704] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.674734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.674759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.674775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.674789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.674803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.674818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.674834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.674849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.674864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.674877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.674891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.674907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.674923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.676899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.676915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.676930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.676944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.678451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.678466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.678480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.679978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.680007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.681814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.684751] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.684824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.684841] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.684863] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.684902] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.684918] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.701568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.701594] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.701631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.734957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.735041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.751605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.751629] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.751675] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.769715] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.769738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.769754] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.769773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.769790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.769807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.769822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.769837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.769853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.769871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.769887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.769902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.769918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.769931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.769945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.769971] [drm:intel_power_well_disable [i915]] disabling display
>[  740.770039] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.770075] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.770104] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.770173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.770188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.770262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.770285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.770310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.770337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.770359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.770383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.770407] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.770430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.770452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.770474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.770495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.770501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.770521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.770526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.770548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.770569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.770590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.770612] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.770634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.770655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.770676] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.770698] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.770719] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.770743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.770768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.770832] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.770855] [drm:intel_power_well_enable [i915]] enabling display
>[  740.770877] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.770915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.770938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.770960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.770982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.771025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.771047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.771073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.771098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.771122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.771144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.771167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.771193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.771217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.773211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.773228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.773242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.773257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.774761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.774776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.774791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.776290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.776306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.778114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.781065] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.781123] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.781140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.781162] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.781200] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.781217] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.797868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.797893] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.797928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.831262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.831306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.847909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.847932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.847978] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.866912] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.866934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.866951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.866970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.866987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.867046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.867070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.867095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.867119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.867148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.867174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.867200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.867225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.867246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.867268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.867311] [drm:intel_power_well_disable [i915]] disabling display
>[  740.867344] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.867376] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.867403] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.867472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.867487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.867555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.867578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.867604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.867638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.867659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.867682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.867703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.867725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.867745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.867765] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.867784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.867789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.867809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.867814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.867834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.867853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.867873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.867892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.867914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.867933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.867954] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.867972] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.867993] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.868037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.868060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.868124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.868149] [drm:intel_power_well_enable [i915]] enabling display
>[  740.868171] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.868208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.868230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.868251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.868273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.868292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.868314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.868337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.868360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.868383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.868402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.868422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.868445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.868467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.870477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.870493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.870507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.870522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.872061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.872078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.872095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.873592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.873608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.875418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.878357] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.878427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.878444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.878466] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.878504] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.878521] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.895174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.895199] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.895234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.928557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.928600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.945216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  740.945240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.945286] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  740.964156] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  740.964178] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  740.964194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.964214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.964230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.964248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.964264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.964279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.964298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.964320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.964340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.964361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.964381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.964400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.964417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.964444] [drm:intel_power_well_disable [i915]] disabling display
>[  740.964466] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.964491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.964509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.964553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  740.964563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  740.964608] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.964628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.964648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.964670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.964689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.964708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.964727] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  740.964746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  740.964766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.964784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.964803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.964807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.964826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.964829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.964849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.964875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.964891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.964905] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  740.964921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.964936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.964950] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  740.964963] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  740.964976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  740.964991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.965046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  740.965110] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.965134] [drm:intel_power_well_enable [i915]] enabling display
>[  740.965157] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.965193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.965215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.965238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.965258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.965280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.965301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.965325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.965348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.965372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.965391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.965412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.965437] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  740.965458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.967469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.967485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.967499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.967513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.969035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.969050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.969064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.970569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.970586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.972414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.975349] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  740.975423] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.975440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  740.975462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.975499] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  740.975516] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  740.992169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.992194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  740.992231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.025554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.025597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.042224] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.042249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.042295] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.061154] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.061176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.061192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.061212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.061229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.061246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.061262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.061277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.061293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.061310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.061327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.061342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.061358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.061373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.061387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.061413] [drm:intel_power_well_disable [i915]] disabling display
>[  741.061434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.061458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.061476] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.061522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.061531] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.061577] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.061597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.061617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.061639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.061659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.061678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.061698] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.061717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.061736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.061755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.061774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.061778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.061796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.061800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.061819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.061838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.061857] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.061876] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.061896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.061914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.061933] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.061953] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.061972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.061992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.062012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.062112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.062138] [drm:intel_power_well_enable [i915]] enabling display
>[  741.062163] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.062211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.062234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.062257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.062278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.062301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.062323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.062348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.062373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.062693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.062714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.062735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.062761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.062782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.064779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.064795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.064809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.064824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.066334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.066349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.066362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.067856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.067872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.069682] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.072605] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.072639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.072655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.072680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.072720] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.072740] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.089386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.089411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.089448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.122772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.122815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.139446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.139470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.139515] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.158383] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.158405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.158422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.158441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.158458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.158476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.158491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.158506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.158522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.158539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.158560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.158580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.158600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.158619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.158637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.158665] [drm:intel_power_well_disable [i915]] disabling display
>[  741.158687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.158712] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.158730] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.158775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.158784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.158830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.158850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.158870] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.158892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.158910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.158930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.158949] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.158968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.158988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.159006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.159065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.159074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.159100] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.159107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.159133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.159156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.159181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.159203] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.159229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.159251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.159275] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.159297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.159320] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.159347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.159375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.159733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.159757] [drm:intel_power_well_enable [i915]] enabling display
>[  741.159778] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.159815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.159837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.159859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.159879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.159900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.159921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.159945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.159968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.159992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.160011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.160049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.160076] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.160098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.162275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.162291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.162305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.162319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.163824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.163839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.163853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.165350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.165365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.167175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.170112] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.170184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.170201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.170223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.170261] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.170278] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.186929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.186954] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.186989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.220306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.220350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.236965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.236989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.237127] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.255978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.256000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.256016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.256083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.256111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.256140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.256260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.256276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.256292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.256310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.256327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.256343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.256358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.256372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.256391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.256418] [drm:intel_power_well_disable [i915]] disabling display
>[  741.256440] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.256465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.256483] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.256519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.256528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.256574] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.256594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.256614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.256636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.256655] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.256674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.256694] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.256713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.256732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.256751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.256769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.256773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.256792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.256796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.256815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.256834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.256853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.256872] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.256891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.256910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.256929] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.256948] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.256967] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.256994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.257012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.257099] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.257122] [drm:intel_power_well_enable [i915]] enabling display
>[  741.257145] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.257183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.257209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.257232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.257256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.257278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.257302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.257328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.257353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.257627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.257650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.257672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.257697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.257721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.259718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.259736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.259754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.259772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.261282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.261298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.261313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.262806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.262821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.264631] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.267553] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.267588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.267604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.267625] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.267665] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.267681] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.284334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.284359] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.284396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.317713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.317757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.334371] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.334395] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.334441] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.353310] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.353332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.353352] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.353373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.353393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.353415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.353434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.353453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.353472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.353494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.353515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.353535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.353556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.353575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.353591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.353619] [drm:intel_power_well_disable [i915]] disabling display
>[  741.353641] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.353666] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.353683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.353719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.353728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.353771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.353788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.353807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.353829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.353848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.353868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.353887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.353906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.353926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.353945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.353963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.353967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.353986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.353990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.354009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.354028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.354088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.354117] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.354146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.354173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.354199] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.354224] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.354249] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.354277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.354305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.354379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.354403] [drm:intel_power_well_enable [i915]] enabling display
>[  741.354530] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.354567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.354591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.354613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.354635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.354657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.354681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.354705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.354729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.354753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.354774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.354795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.354820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.354844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.356848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.356866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.356884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.356902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.358421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.358438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.358453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.359972] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.359988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.361798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.364734] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.364808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.364824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.364846] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.364885] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.364902] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.381552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.381577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.381611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.414936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.414980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.431588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.431612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.431650] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.450516] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.450537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.450557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.450578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.450598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.450619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.450639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.450658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.450677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.450698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.450719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.450739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.450760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.450778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.450795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.450822] [drm:intel_power_well_disable [i915]] disabling display
>[  741.450845] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.450869] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.450887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.450930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.450939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.450984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.451004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.451024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.451092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.451121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.451150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.451178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.451204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.451231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.451255] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.451280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.451287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.451310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.451317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.451341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.451365] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.451390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.451413] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.451440] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.451464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.451489] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.451513] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.451537] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.451565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.451593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.451951] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.451974] [drm:intel_power_well_enable [i915]] enabling display
>[  741.451996] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.452036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.452079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.452103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.452127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.452149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.452173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.452271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.452295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.452319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.452340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.452361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.452386] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.452409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.454406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.454422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.454436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.454451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.455978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.455993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.456007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.457503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.457518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.459326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.462255] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.462283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.462300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.462321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.462359] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.462375] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.479030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.479072] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.479106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.512419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.512463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.529066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.529092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.529132] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.547997] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.548019] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.548035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.548102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.548131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.548160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.548185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.548209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.548234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.548263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.548289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.548315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.548341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.548365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.548388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.548431] [drm:intel_power_well_disable [i915]] disabling display
>[  741.548464] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.548496] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.548524] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.548588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.548597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.548640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.548656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.548674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.548693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.548709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.548726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.548742] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.548761] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.548780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.548799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.548818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.548822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.548840] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.548844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.548863] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.548882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.548901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.548920] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.548939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.548958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.548983] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.549001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.549018] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.549036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.549086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.549153] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.549178] [drm:intel_power_well_enable [i915]] enabling display
>[  741.549201] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.549239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.549264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.549287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.549310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.549333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.549354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.549378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.549402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.549426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.549445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.549467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.549492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.549515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.551513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.551529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.551543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.551558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.553092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.553107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.553120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.554625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.554641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.556460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.559403] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.559469] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.559485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.559507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.559546] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.559562] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.576214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.576239] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.576273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.609598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.609641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.626249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.626274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.626312] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.645166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.645189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.645205] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.645224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.645241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.645258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.645273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.645288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.645304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.645321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.645338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.645354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.645370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.645384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.645398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.645424] [drm:intel_power_well_disable [i915]] disabling display
>[  741.645445] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.645466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.645483] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.645525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.645534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.645575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.645591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.645610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.645632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.645651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.645671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.645690] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.645710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.645729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.645748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.645767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.645770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.645789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.645793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.645812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.645832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.645851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.645869] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.645889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.645908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.645927] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.645946] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.645965] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.645985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.646005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.646092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.646121] [drm:intel_power_well_enable [i915]] enabling display
>[  741.646146] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.646188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.646216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.646242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.646274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.646298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.646321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.646347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.646372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.646396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.646418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.646441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.646467] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.646491] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.648506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.648523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.648537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.648552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.650096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.650112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.650125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.651630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.651648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.653464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.656399] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.656472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.656487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.656507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.656552] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.656575] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.673219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.673244] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.673281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.706603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.706647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.723276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.723300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.723346] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.742202] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.742225] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.742245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.742267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.742287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.742308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.742327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.742346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.742366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.742387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.742408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.742428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.742448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.742467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.742486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.742514] [drm:intel_power_well_disable [i915]] disabling display
>[  741.742536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.742561] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.742579] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.742624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.742633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.742678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.742704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.742722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.742740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.742754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.742769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.742785] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.742800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.742814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.742828] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.742841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.742844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.742857] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.742860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.742873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.742886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.742899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.742911] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.742926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.742939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.742951] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.742964] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.742976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.742992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.743008] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.743088] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.743114] [drm:intel_power_well_enable [i915]] enabling display
>[  741.743137] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.743175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.743199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.743222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.743245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.743267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.743291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.743316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.743340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.743365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.743387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.743409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.743435] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.743458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.745459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.745477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.745494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.745512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.747022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.747039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.747087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.748588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.748606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.750488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.753423] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.753498] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.753515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.753537] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.753576] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.753592] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.770242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.770267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.770301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.803628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.803671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.820278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.820303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.820344] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.839208] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.839230] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.839246] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.839265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.839282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.839299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.839315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.839329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.839345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.839363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.839380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.839396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.839412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.839426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.839440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.839466] [drm:intel_power_well_disable [i915]] disabling display
>[  741.839488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.839509] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.839526] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.839570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.839579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.839621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.839637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.839655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.839674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.839691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.839711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.839730] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.839749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.839769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.839788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.839806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.839810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.839829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.839833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.839852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.839871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.839890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.839909] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.839928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.839953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.839970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.839988] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.840005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.840023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.840042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.840134] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.840159] [drm:intel_power_well_enable [i915]] enabling display
>[  741.840182] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.840221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.840246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.840270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.840294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.840317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.840341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.840367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.840391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.840416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.840734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.840757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.840783] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.840806] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.842808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.842824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.842838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.842852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.844361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.844379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.844396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.845891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.845907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.847717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.850640] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.850674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.850691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.850713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.850750] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.850767] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.867408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.867431] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.867464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.900805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.900850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.917456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.917482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.917522] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.936386] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.936410] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.936429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.936451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.936470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.936492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.936511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.936531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.936550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.936571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.936592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.936612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.936632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.936651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.936670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.936697] [drm:intel_power_well_disable [i915]] disabling display
>[  741.936719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.936744] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.936762] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.936807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.936817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.936863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.936883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.936902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.936924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.936943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.936963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.936982] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.937001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.937020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.937039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.937058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.937099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.937128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.937137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.937165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.937197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.937220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.937243] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.937268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.937291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.937314] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.937337] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.937359] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.937385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.937411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.937476] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.937724] [drm:intel_power_well_enable [i915]] enabling display
>[  741.937746] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.937784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.937808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.937832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.937854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.937876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.937899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.937924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.937948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.937972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.937993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.938015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.938040] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.938063] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.940207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.940223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.940237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.940251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.941756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.941771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.941785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.943283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.943299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.945110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.948045] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.948129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.948147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.948169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.948207] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.948224] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.964864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.964889] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.964924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.998242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.998286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.014921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.014945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.014984] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.033851] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.033872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.033888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.033908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.033924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.033941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.033960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.033980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.033999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.034021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.034041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.034062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.034127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.034151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.034174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.034217] [drm:intel_power_well_disable [i915]] disabling display
>[  742.034253] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.034286] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.034315] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.034371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.034385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.034430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.034447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.034466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.034493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.034507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.034523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.034539] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.034553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.034567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.034582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.034594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.034599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.034611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.034615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.034628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.034641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.034654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.034671] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.034689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.034707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.034725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.034742] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.034759] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.034779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.034798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.034841] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.034857] [drm:intel_power_well_enable [i915]] enabling display
>[  742.034871] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.034898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.034916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.034934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.034952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.034969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.034987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.035006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.035026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.035044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.035062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.035106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.035131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.035153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.037149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.037165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.037180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.037194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.038708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.038726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.038740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.040242] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.040258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.042069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.045017] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.045126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.045153] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.045187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.045245] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.045268] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.061841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.061866] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.061901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.095237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.095281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.111880] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.111905] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.111955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.130785] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.130807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.130823] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.130843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.130860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.130877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.130892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.130907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.130923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.130941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.130959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.130980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.131001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.131020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.131037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.131064] [drm:intel_power_well_disable [i915]] disabling display
>[  742.131132] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.131167] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.131196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.131253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.131267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.131336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.131360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.131387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.131416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.131439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.131465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.131489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.131513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.131536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.131559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.131580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.131586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.131607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.131613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.131636] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.131657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.131679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.131699] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.131724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.131745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.131767] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.131788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.131810] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.131833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.131860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.131934] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.131957] [drm:intel_power_well_enable [i915]] enabling display
>[  742.131978] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.132014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.132034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.132055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.132076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.132114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.132137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.132163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.132186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.132211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.132231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.132252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.132278] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.132299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.134305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.134323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.134340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.134358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.135867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.135884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.135898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.137398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.137414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.139223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.142154] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.142180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.142196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.142218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.142266] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.142291] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.158928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.158953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.158988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.192318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.192363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.208987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.209012] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.209064] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.227961] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.227983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.227999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.228019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.228035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.228053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.228068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.228123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.228147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.228178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.228203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.228229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.228247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.228262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.228276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.228303] [drm:intel_power_well_disable [i915]] disabling display
>[  742.228324] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.228346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.228363] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.228405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.228414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.228456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.228472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.228490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.228512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.228532] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.228553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.228572] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.228592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.228612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.228632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.228651] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.228656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.228674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.228679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.228698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.228717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.228737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.228756] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.228776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.228795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.228814] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.228834] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.228853] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.228874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.228895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.228948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.228963] [drm:intel_power_well_enable [i915]] enabling display
>[  742.228976] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.229003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.229019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.229034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.229048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.229062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.229080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.229121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.229145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.229168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.229188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.229208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.229232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.229253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.231248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.231264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.231278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.231293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.232797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.232813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.232826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.234323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.234339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.236148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.239083] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.239158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.239175] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.239197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.239249] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.239273] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.255902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.255927] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.255961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.289295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.289340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.305943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.305966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.306018] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.324863] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.324884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.324901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.324920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.324937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.324955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.324970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.324985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.325004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.325025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.325046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.325066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.325087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.325147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.325171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.325214] [drm:intel_power_well_disable [i915]] disabling display
>[  742.325328] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.325352] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.325370] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.325411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.325421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.325463] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.325480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.325498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.325517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.325534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.325555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.325575] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.325595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.325614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.325634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.325654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.325658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.325677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.325681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.325701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.325721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.325737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.325756] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.325775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.325795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.325814] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.325833] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.325852] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.325873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.325894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.325939] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.325956] [drm:intel_power_well_enable [i915]] enabling display
>[  742.325971] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.326001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.326021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.326040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.326059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.326080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.326129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.326158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.326184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.326217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.326236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.326256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.326281] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.326302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.328297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.328313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.328327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.328342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.329845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.329860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.329874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.331373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.331389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.333197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.336133] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.336207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.336223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.336246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.336294] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.336320] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.352950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.352976] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.353013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.386349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.386393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.403018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.403041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.403093] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.421978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.422002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.422022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.422043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.422063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.422085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.422149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.422172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.422189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.422208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.422225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.422241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.422256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.422271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.422285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.422312] [drm:intel_power_well_disable [i915]] disabling display
>[  742.422333] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.422355] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.422373] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.422417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.422427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.422473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.422493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.422513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.422536] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.422555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.422575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.422595] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.422615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.422641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.422656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.422671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.422674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.422688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.422692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.422705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.422719] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.422732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.422745] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.422761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.422774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.422787] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.422800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.422812] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.422828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.422844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.422886] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.422900] [drm:intel_power_well_enable [i915]] enabling display
>[  742.422913] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.422940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.422958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.422976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.422994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.423012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.423030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.423049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.423068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.423087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.423126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.423148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.423173] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.423195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.425188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.425206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.425224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.425242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.426749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.426765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.426779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.428279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.428295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.430115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.433049] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.433153] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.433181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.433266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.433315] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.433341] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.449868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.449894] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.449930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.483265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.483309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.499932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.499955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.500006] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.518879] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.518901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.518917] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.518936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.518953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.518970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.518985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.519004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.519024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.519045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.519066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.519086] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.519149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.519174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.519197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.519349] [drm:intel_power_well_disable [i915]] disabling display
>[  742.519371] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.519395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.519413] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.519455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.519465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.519507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.519525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.519543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.519564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.519580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.519596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.519613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.519629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.519644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.519658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.519673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.519677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.519690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.519694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.519709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.519723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.519737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.519751] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.519767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.519781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.519796] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.519810] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.519824] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.519843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.519865] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.519916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.519930] [drm:intel_power_well_enable [i915]] enabling display
>[  742.519943] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.519968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.519983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.519998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.520012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.520025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.520039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.520054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.520069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.520083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.520119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.520139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.520163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.520183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.522178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.522194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.522208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.522223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.523726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.523741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.523755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.525252] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.525268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.527128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.530068] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.530165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.530191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.530290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.530336] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.530360] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.546882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.546907] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.546942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.580277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.580320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.596923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.596947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.596997] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.615869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.615891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.615910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.615932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.615952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.615973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.615992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.616011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.616031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.616052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.616073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.616094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.616156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.616180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.616203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.616246] [drm:intel_power_well_disable [i915]] disabling display
>[  742.616274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.616298] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.616315] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.616358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.616367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.616409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.616426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.616444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.616464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.616480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.616497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.616514] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.616529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.616545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.616559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.616574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.616578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.616591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.616595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.616610] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.616624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.616638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.616652] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.616669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.616683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.616697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.616711] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.616725] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.616744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.616766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.616812] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.616829] [drm:intel_power_well_enable [i915]] enabling display
>[  742.616844] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.616874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.616894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.616911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.616931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.616951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.616970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.616992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.617012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.617033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.617053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.617072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.617093] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.617136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.619137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.619153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.619169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.619187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.620698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.620713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.620727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.622228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.622246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.624056] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.626990] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.627066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.627083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.627137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.627325] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.627343] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.643811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.643836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.643871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.677261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.677340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.693904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.693943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.694006] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.712921] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.712943] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.712959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.712979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.712996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.713017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.713037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.713056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.713075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.713096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.713164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.713195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.713223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.713248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.713273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.713350] [drm:intel_power_well_disable [i915]] disabling display
>[  742.713384] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.713417] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.713445] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.713519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.713533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.713596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.713619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.713645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.713672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.713695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.713719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.713743] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.713765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.713788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.713809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.713830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.713835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.713856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.713861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.713883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.713904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.713924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.713945] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.713967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.713988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.714009] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.714028] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.714048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.714070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.714095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.714178] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.714201] [drm:intel_power_well_enable [i915]] enabling display
>[  742.714224] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.714261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.714285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.714308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.714330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.714352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.714373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.714398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.714421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.714445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.714466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.714487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.714512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.714534] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.716529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.716545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.716559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.716573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.718080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.718095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.718141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.719638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.719653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.721472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.724410] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.724481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.724498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.724520] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.724558] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.724575] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.741226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.741251] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.741286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.774604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.774648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.791261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.791286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.791326] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.809664] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.809685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.809705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.809727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.809746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.809768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.809787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.809806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.809825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.809847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.809867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.809888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.809908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.809927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.809944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.809971] [drm:intel_power_well_disable [i915]] disabling display
>[  742.809993] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.810018] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.810035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.810072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.810082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.810168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.810198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.810228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.810259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.810285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.810313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.810340] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.810366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.810392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.810417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.810441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.810447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.810471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.810477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.810502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.810526] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.810550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.810574] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.810600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.810623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.810646] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.810671] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.810701] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.810726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.810750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.810812] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.810835] [drm:intel_power_well_enable [i915]] enabling display
>[  742.810857] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.810894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.810917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.810939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.810961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.810981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.811003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.811027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.811051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.811075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.811096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.811116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.811158] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.811181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.813179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.813195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.813209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.813223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.815811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.815835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.815849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.817347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.817363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.819172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.822084] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.822157] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.822182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.822219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.822369] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.822386] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.838875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.838901] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.838938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.872252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.872295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.888931] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.888956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.889002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  742.906885] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  742.906907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  742.906924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  742.906943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.906960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.906978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.906994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.907009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.907028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.907049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.907070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.907090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.907110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.907171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.907200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.907246] [drm:intel_power_well_disable [i915]] disabling display
>[  742.907467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  742.907502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.907530] [drm:intel_power_well_disable [i915]] disabling always-on
>[  742.907585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.907600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  742.907665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  742.907682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  742.907700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  742.907720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  742.907736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  742.907752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  742.907769] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  742.907784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  742.907799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  742.907814] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  742.907828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  742.907831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.907845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  742.907849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  742.907863] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  742.907882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  742.907901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  742.907921] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  742.907940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  742.907959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  742.907978] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  742.907997] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  742.908016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  742.908036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.908057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  742.908109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  742.908154] [drm:intel_power_well_enable [i915]] enabling display
>[  742.908175] [drm:hsw_set_power_well [i915]] Enabling power well
>[  742.908216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  742.908241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  742.908265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  742.908289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  742.908313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  742.908336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  742.908363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  742.908388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  742.908414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.908436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  742.908458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  742.908485] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  742.908508] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  742.910736] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  742.910752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  742.910766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.910781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  742.912288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  742.912303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  742.912317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  742.913811] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  742.913826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  742.916699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  742.919636] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  742.919708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  742.919725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  742.919747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  742.919785] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  742.919802] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  742.936453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  742.936478] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  742.936513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  742.969838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  742.969882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  742.986489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  742.986514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  742.986555] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.005423] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.005445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.005461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.005481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.005498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.005516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.005532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.005547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.005563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.005581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.005597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.005613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.005629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.005643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.005657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.005684] [drm:intel_power_well_disable [i915]] disabling display
>[  743.005705] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.005725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.005742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.005784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.005793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.005834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.005849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.005867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.005887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.005906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.005926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.005945] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  743.005964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  743.005984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.006002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.006021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.006025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.006044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.006048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.006067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.006086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.006105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.006124] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  743.006186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.006217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.006244] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  743.006270] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  743.006302] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  743.006327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.006353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  743.006418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.006443] [drm:intel_power_well_enable [i915]] enabling display
>[  743.006465] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.006763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.006787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.006810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.006832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.006854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.006875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.006899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.006923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.006947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.006968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.006989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.007015] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  743.007039] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.009037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.009052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.009067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.009081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.010590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.010605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.010618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.012164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.012180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.013986] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.016917] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  743.016944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.016961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  743.016983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.017021] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  743.017038] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  743.033690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.033716] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.033753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.067159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.067233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.083771] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  743.083812] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.083890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.101927] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.101949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.101965] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.101985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.102002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.102020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.102035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.102050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.102066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.102084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.102100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.102116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.102175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.102201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.102227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.102271] [drm:intel_power_well_disable [i915]] disabling display
>[  743.102487] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.102520] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.102548] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.102618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.102627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.102668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.102683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.102700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.102720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.102737] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.102755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.102773] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  743.102791] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  743.102808] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.102825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.102842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.102846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.102863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.102866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.102884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.102902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.102919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.102936] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  743.102953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.102971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.102988] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  743.103005] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  743.103023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  743.103041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.103060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  743.103102] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.103116] [drm:intel_power_well_enable [i915]] enabling display
>[  743.103160] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.103200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.103226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.103250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.103273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.103297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.103321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.103348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.103372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.103397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.103419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.103439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.103465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  743.103489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.105716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.105732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.105746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.105761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.107290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.107308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.107323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.108819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.108836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.110646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.113588] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  743.113654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.113671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  743.113693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.113730] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  743.113756] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  743.130400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.130425] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.130460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.163789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.163833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.180436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  743.180460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.180507] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.199378] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.199400] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.199417] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.199437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.199458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.199479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.199498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.199518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.199537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.199559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.199579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.199600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.199620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.199639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.199655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.199683] [drm:intel_power_well_disable [i915]] disabling display
>[  743.199706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.199730] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.199748] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.199792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.199802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.199847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.199867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.199894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.199912] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.199927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.199943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.199959] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  743.199974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  743.199988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.200002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.200015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.200018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.200031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.200034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.200047] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.200060] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.200073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.200085] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  743.200100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.200113] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.200125] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  743.200176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  743.200197] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  743.200222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.200249] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  743.200313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.200338] [drm:intel_power_well_enable [i915]] enabling display
>[  743.200360] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.200397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.200647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.200671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.200694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.200716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.200739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.200764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.200788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.200812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.200834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.200855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.200880] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  743.200904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.202903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.202919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.202933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.202948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.206658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.206678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.206693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.209358] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.209378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.211192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.214134] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  743.214201] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.214216] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  743.214237] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.214272] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  743.214287] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  743.230945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.230970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.231004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.264330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.264373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.280982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  743.281008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.281048] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.301005] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.301029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.301048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.301070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.301090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.301112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.301131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.301195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.301225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.301257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.301285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.301438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.301465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.301490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.301513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.301553] [drm:intel_power_well_disable [i915]] disabling display
>[  743.301586] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.301619] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.301647] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.301705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.301715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.301758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.301774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.301793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.301812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.301828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.301845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.301862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  743.301877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  743.301893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.301908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.301922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.301926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.301940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.301943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.301958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.301972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.301986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.301999] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  743.302016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.302030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.302048] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  743.302067] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  743.302087] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  743.302107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.302127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  743.302220] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.302246] [drm:intel_power_well_enable [i915]] enabling display
>[  743.302271] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.302314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.302347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.302371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.302392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.302414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.302702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.302728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.302752] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.302777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.302798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.302820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.302845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  743.302868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.304863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.304879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.304893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.304908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.306415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.306431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.306444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.307937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.307953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.309762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.312700] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  743.312771] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.312788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  743.312810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.312848] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  743.312865] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  743.329517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.329542] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.329578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.362902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.362945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.379552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  743.379576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.379614] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.398480] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.398502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.398518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.398538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.398555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.398576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.398596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.398615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.398634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.398656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.398677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.398697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.398717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.398736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.398753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.398780] [drm:intel_power_well_disable [i915]] disabling display
>[  743.398803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.398828] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.398845] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.398890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.398899] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.398944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.398964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.398984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.399006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.399025] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.399044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.399063] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  743.399083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  743.399102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.399120] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.399139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.399180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.399209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.399217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.399245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.399271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.399297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.399322] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  743.399350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.399374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.399399] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  743.399424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  743.399448] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  743.399476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.399505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  743.399576] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.399837] [drm:intel_power_well_enable [i915]] enabling display
>[  743.399859] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.399897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.399921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.399945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.399967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.399989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.400012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.400037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.400061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.400085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.400107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.400128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.400153] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  743.400195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.402302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.402318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.402332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.402346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.403852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.403867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.403883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.405382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.405399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.407209] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.410144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  743.410219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.410236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  743.410258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.410296] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  743.410313] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  743.426963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.426989] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.427026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.460388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.476998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  743.477023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.477062] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  743.494997] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  743.495019] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  743.495036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.495056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.495073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.495091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.495106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.495121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.495137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.495197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.495223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.495250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.495275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.495298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.495322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.495366] [drm:intel_power_well_disable [i915]] disabling display
>[  743.495403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.495429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  743.495447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.495598] [drm:drm_mode_addfb2] [FB:75]
>[  743.495621] [drm:drm_mode_addfb2] [FB:78]
>[  743.518407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  743.518490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.518540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  743.518587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.518597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.518644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.518661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.518679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.518700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.518717] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.518735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.518753] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.518770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.518788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.518805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.518822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.518826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.518843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.518846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.518864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.518881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.518898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.518915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.518933] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.518950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.518968] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.518985] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.519003] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.519021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.519041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.521654] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.521669] [drm:intel_power_well_enable [i915]] enabling display
>[  743.521682] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.521711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.521729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.521747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.521765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.521782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.521799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.521819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.521837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.521856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.521873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.521888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.521907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.521924] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.523921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.523939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.523953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.523968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.525477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.525492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.525506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.527000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.527016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.528825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.531762] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.531835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.531852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.531874] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.548579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.548605] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.548640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.565302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.565346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.565399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.565421] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.565468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.584340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.584359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.584379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.584396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.584413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.584428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.584443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.584459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.584477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.584494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.584509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.584525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.584539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.584552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.584579] [drm:intel_power_well_disable [i915]] disabling display
>[  743.584600] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.584621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.584637] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.584679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.584688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.584732] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.584752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.584772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.584794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.584813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.584833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.584852] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.584877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.584893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.584908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.584921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.584925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.584938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.584941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.584954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.584971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.584989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.585006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.585023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.585040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.585058] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.585075] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.585093] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.585111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.585130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.585210] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.585233] [drm:intel_power_well_enable [i915]] enabling display
>[  743.585255] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.585295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.585320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.585342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.585365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.585386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.585409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.585435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.585459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.585484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.585504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.585525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.585551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.585573] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.587573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.587589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.587605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.587623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.589211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.589227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.589241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.590747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.590765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.592579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.595530] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.595588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.595605] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.595627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.612331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.612357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.612391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.645717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.645760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.645814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.645836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.645876] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.663901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.663920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.663940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.663957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.663974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.663989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.664004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.664020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.664037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.664053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.664069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.664084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.664098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.664111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.664138] [drm:intel_power_well_disable [i915]] disabling display
>[  743.664159] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.664223] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.664249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.664468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.664483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.664551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.664575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.664602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.664631] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.664653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.664678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.664701] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.664725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.664748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.664770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.664798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.664803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.664823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.664828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.664849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.664869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.664889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.664907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.664930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.664949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.664969] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.664988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.665008] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.665031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.665055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.665117] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.665138] [drm:intel_power_well_enable [i915]] enabling display
>[  743.665160] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.665219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.665240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.665264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.665284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.665306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.665327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.665352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.665376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.665401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.665421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.665442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.665468] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.665490] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.667768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.667784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.667798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.667813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.669340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.669357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.669372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.670869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.670886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.672699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.675636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.675708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.675725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.675747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.692450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.692476] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.692511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.725836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.725879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.725932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.725954] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.726000] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.744899] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.744918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.744938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.744955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.744973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.744988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.745002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.745018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.745036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.745052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.745068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.745083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.745097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.745111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.745137] [drm:intel_power_well_disable [i915]] disabling display
>[  743.745158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.745225] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.745249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.745319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.745333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.745376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.745393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.745411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.745430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.745446] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.745462] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.745479] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.745494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.745510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.745524] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.745538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.745543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.745556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.745560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.745574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.745596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.745609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.745621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.745636] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.745648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.745666] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.745684] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.745702] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.745721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.745741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.745785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.745799] [drm:intel_power_well_enable [i915]] enabling display
>[  743.745813] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.745840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.745858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.745876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.745894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.745913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.745930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.745950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.745969] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.745988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.746006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.746024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.746042] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.746061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.748035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.748052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.748066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.748081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.749590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.749605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.749618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.751115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.751133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.752945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.755863] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.755901] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.755916] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.755936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.772645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.772671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.772706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.806045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.806089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.806141] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.806161] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.806341] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.824870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.824889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.824910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.824926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.824944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.824959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.824974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.824990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.825008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.825024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.825040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.825055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.825069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.825087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.825115] [drm:intel_power_well_disable [i915]] disabling display
>[  743.825137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.825162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.825247] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.825321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.825336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.825398] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.825417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.825438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.825460] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.825479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.825499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.825519] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.825539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.825559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.825585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.825601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.825605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.825620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.825624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.825638] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.825652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.825665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.825678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.825694] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.825708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.825721] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.825734] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.825747] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.825763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.825780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.825823] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.825836] [drm:intel_power_well_enable [i915]] enabling display
>[  743.825849] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.825874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.825889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.825902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.825916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.825929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.825943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.825958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.825973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.825987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.826000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.826013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.826029] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.826044] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.828025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.828041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.828058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.828076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.829589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.829605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.829620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.831123] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.831140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.832950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.835890] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.835960] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.835977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.835999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.852702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.852729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.852767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.886101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.886144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.886234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.886268] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.886431] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.904956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.904977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.904999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.905019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.905040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.905060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.905079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.905098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.905120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.905140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.905161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.905181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.905241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.905267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.905309] [drm:intel_power_well_disable [i915]] disabling display
>[  743.905475] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.905506] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.905530] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.905597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.905610] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.905673] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.905696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.905721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.905748] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.905771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.905795] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.905819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.905842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.905864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.905886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.905907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.905913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.905933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.905939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.905961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.905982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.906003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.906024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.906045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.906066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.906087] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.906106] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.906126] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.906148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.906173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.906257] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.906280] [drm:intel_power_well_enable [i915]] enabling display
>[  743.906303] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.906341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.906562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.906577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.906592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.906606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.906620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.906636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.906650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.906665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.906678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.906691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.906707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.906722] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.908728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.908744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.908758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.908773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.910293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.910310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.910326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.911825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.911841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.913652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.916585] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.916659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.916674] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.916694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  743.933412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.933437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.933472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.966811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.966855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.966900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  743.966922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  743.966962] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  743.985828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  743.985847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  743.985867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.985883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.985901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.985916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.985931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.985947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  743.985965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.985981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.985997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.986013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.986027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.986041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.986067] [drm:intel_power_well_disable [i915]] disabling display
>[  743.986089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  743.986114] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  743.986131] [drm:intel_power_well_disable [i915]] disabling always-on
>[  743.986168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  743.986224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  743.986290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  743.986308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  743.986326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  743.986344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  743.986359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  743.986376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  743.986391] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  743.986407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  743.986422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  743.986440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  743.986458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  743.986463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.986480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  743.986484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  743.986502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  743.986521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  743.986540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  743.986558] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  743.986576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  743.986594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  743.986613] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  743.986631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  743.986649] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  743.986669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  743.986690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  743.986725] [drm:intel_power_well_enable [i915]] enabling always-on
>[  743.986741] [drm:intel_power_well_enable [i915]] enabling display
>[  743.986755] [drm:hsw_set_power_well [i915]] Enabling power well
>[  743.986784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  743.986802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  743.986821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  743.986839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  743.986857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  743.986876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  743.986895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  743.986915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  743.986935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  743.986954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  743.986969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  743.986989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  743.987007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  743.989003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  743.989020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  743.989034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.989049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  743.990560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  743.990578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  743.990595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  743.992092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  743.992108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  743.993918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  743.996855] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  743.996928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  743.996945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  743.996967] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.013663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.013690] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.013728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.047054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.047097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.047152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.047174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.047377] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.065961] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.065980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.066000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.066017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.066035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.066050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.066064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.066080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.066097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.066114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.066129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.066145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.066159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.066173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.066244] [drm:intel_power_well_disable [i915]] disabling display
>[  744.066280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.066313] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.066470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.066527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.066541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.066610] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.066636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.066663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.066701] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.066725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.066751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.066776] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.066801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.066826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.066850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.066874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.066880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.066902] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.066908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.066932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.066955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.066978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.067001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.067024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.067047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.067070] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.067092] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.067113] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.067138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.067165] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.067262] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.067286] [drm:intel_power_well_enable [i915]] enabling display
>[  744.067309] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.067347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.067371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.067394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.067621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.067636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.067651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.067667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.067682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.067697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.067711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.067728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.067747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.067764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.069745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.069761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.069775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.069790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.071311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.071328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.071343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.072841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.072857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.075783] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.078722] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.078793] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.078809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.078831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.095533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.095557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.095590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.128933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.128978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.129031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.129055] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.129103] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.147912] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.147930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.147950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.147967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.147985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.148000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.148015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.148031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.148049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.148066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.148081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.148097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.148111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.148125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.148152] [drm:intel_power_well_disable [i915]] disabling display
>[  744.148174] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.148234] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.148264] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.148333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.148349] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.148416] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.148439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.148465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.148494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.148517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.148542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.148565] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.148589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.148612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.148635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.148656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.148662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.148683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.148689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.148711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.148732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.148754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.148775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.148799] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.148820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.148843] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.148863] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.148885] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.148908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.148935] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.149003] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.149027] [drm:intel_power_well_enable [i915]] enabling display
>[  744.149050] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.149090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.149113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.149136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.149157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.149180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.149224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.149257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.149282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.149306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.149326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.149348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.149374] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.149395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.151391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.151409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.151426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.151444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.152947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.152963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.152978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.154477] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.154493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.156305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.159242] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.159314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.159331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.159356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.176058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.176084] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.176118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.209444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.209487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.209541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.209563] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.209602] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.228478] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.228497] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.228517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.228534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.228552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.228567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.228582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.228598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.228616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.228633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.228648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.228664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.228683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.228701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.228728] [drm:intel_power_well_disable [i915]] disabling display
>[  744.228751] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.228775] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.228792] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.228836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.228846] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.228892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.228911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.228931] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.228953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.228972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.228992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.229011] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.229030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.229049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.229068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.229086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.229090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.229109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.229113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.229132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.229151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.229170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.229189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.229257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.229281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.229302] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.229324] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.229344] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.229368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.229392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.229456] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.229478] [drm:intel_power_well_enable [i915]] enabling display
>[  744.229498] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.229535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.229551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.229565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.229579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.229592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.229606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.229622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.229637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.229651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.229664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.229677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.229694] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.229708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.231686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.231703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.231720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.231738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.233322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.233339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.233356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.234853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.234871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.236693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.239622] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.239650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.239669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.239695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.256391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.256417] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.256454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.289793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.289838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.289890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.289911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.289956] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.308830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.308849] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.308869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.308887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.308905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.308920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.308935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.308950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.308968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.308984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.309000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.309016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.309030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.309044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.309071] [drm:intel_power_well_disable [i915]] disabling display
>[  744.309092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.309113] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.309129] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.309172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.309181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.309277] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.309303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.309467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.309489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.309508] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.309528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.309547] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.309567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.309586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.309606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.309625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.309629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.309647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.309651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.309670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.309689] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.309708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.309726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.309745] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.309763] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.309778] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.309797] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.309816] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.309836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.309856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.309901] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.309916] [drm:intel_power_well_enable [i915]] enabling display
>[  744.309931] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.309960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.309979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.309998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.310017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.310036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.310055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.310076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.310096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.310116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.310135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.310154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.310174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.310193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.312214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.312243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.312260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.312279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.313789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.313806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.313820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.315330] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.315348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.317163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.320103] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.320174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.320191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.320258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.336919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.336944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.336979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.370331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.370375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.370420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.370442] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.370489] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.389367] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.389386] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.389406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.389423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.389441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.389457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.389471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.389488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.389505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.389522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.389538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.389553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.389572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.389589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.389617] [drm:intel_power_well_disable [i915]] disabling display
>[  744.389639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.389664] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.389680] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.389725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.389735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.389780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.389799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.389819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.389841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.389860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.389879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.389899] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.389918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.389937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.389956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.389974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.389978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.389996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.390000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.390019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.390038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.390058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.390076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.390103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.390119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.390135] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.390150] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.390163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.390179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.390195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.390285] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.390305] [drm:intel_power_well_enable [i915]] enabling display
>[  744.390328] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.390366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.390388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.390411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.390431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.390454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.390475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.390500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.390524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.390876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.390898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.390917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.390942] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.390963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.392958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.392974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.392988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.393002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.394512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.394527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.394540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.396035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.396050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.397860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.400788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.400817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.400833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.400855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.417567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.417592] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.417627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.450975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.451018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.451072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.451094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.451141] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.469991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.470010] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.470030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.470047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.470065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.470080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.470094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.470110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.470128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.470144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.470160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.470176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.470190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.470203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.470277] [drm:intel_power_well_disable [i915]] disabling display
>[  744.470311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.470343] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.470368] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.470439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.470453] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.470521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.470544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.470570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.470599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.470622] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.470647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.470671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.470695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.470717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.470740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.470761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.470767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.470788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.470794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.470816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.470837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.470859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.470880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.470905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.470925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.470948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.470968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.470990] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.471013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.471040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.471112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.471133] [drm:intel_power_well_enable [i915]] enabling display
>[  744.471155] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.471191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.471211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.471250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.471271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.471293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.471315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.471340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.471364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.471388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.471408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.471429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.471455] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.471477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.473482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.473500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.473514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.473529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.475037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.475053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.475067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.476566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.476582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.478391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.481337] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.481402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.481421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.481447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.498144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.498170] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.498204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.531530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.531574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.531627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.531649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.531695] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.550569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.550588] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.550608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.550625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.550642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.550658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.550673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.550691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.550713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.550733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.550754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.550774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.550793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.550809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.550837] [drm:intel_power_well_disable [i915]] disabling display
>[  744.550859] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.550883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.550900] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.550946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.550955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.551008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.551025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.551042] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.551062] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.551079] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.551097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.551115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.551132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.551149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.551167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.551184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.551187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.551204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.551238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.551265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.551292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.551317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.551341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.551366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.551390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.551413] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.551435] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.551457] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.551483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.551509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.551574] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.551818] [drm:intel_power_well_enable [i915]] enabling display
>[  744.551840] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.551878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.551902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.551924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.551947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.551969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.551992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.552017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.552041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.552065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.552086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.552108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.552134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.552157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.554171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.554188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.554206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.554258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.555772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.555787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.555801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.557365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.557381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.559191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.562126] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.562200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.562224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.562280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.578944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.578970] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.579005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.612322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.612366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.612420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.612442] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.612482] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.631386] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.631405] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.631425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.631442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.631459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.631475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.631489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.631505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.631523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.631539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.631555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.631571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.631585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.631598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.631625] [drm:intel_power_well_disable [i915]] disabling display
>[  744.631646] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.631667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.631682] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.631719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.631728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.631772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.631792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.631812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.631834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.631853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.631873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.631892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.631911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.631931] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.631949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.631968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.631972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.631991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.631995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.632014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.632040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.632057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.632072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.632089] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.632106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.632124] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.632141] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.632159] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.632177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.632195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.632281] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.632305] [drm:intel_power_well_enable [i915]] enabling display
>[  744.632328] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.632367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.632393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.632416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.632440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.632463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.632487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.632513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.632538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.632562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.632585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.632607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.632633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.632657] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.634967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.634983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.634997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.635012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.636521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.636536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.636550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.638044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.638059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.639868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.642790] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.642824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.642840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.642862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.659568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.659594] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.659629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.692948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.692992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.693045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.693068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.693107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.711981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.712000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.712020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.712037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.712055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.712070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.712084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.712100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.712118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.712135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.712151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.712166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.712181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.712194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.712221] [drm:intel_power_well_disable [i915]] disabling display
>[  744.712293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.712328] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.712354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.712412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.712427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.712495] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.712520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.712547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.712576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.712601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.712627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.712653] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.712678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.712703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.712726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.712750] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.712756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.712777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.712783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.712807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.712830] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.712854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.712882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.712905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.712926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.712948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.712969] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.712990] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.713014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.713039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.713103] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.713126] [drm:intel_power_well_enable [i915]] enabling display
>[  744.713148] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.713186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.713209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.713231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.713270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.713292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.713316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.713342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.713367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.713391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.713413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.713436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.713462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.713486] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.715479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.715495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.715509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.715523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.717030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.717045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.717058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.718556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.718571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.720382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.723318] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.723392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.723409] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.723431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.740134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.740160] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.740194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.773519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.773562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.773616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.773638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.773676] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.791997] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.792016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.792036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.792053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.792071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.792086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.792101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.792117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.792134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.792154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.792175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.792195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.792214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.792231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.792306] [drm:intel_power_well_disable [i915]] disabling display
>[  744.792341] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.792554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.792580] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.792649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.792664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.792737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.792761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.792786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.792814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.792836] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.792861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.792885] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.792908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.792930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.792952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.792973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.792978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.792999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.793004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.793025] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.793046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.793065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.793086] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.793109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.793131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.793150] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.793171] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.793192] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.793213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.793238] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.793519] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.793532] [drm:intel_power_well_enable [i915]] enabling display
>[  744.793545] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.793572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.793588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.793602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.793616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.793629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.793644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.793659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.793674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.793688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.793701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.793714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.793730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.793745] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.795719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.795735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.795748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.795763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.797297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.797312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.797329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.798833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.798851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.800666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.803601] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.803675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.803691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.803713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.820425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.820451] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.820485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.853829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.853873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.853919] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.853943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.853995] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.872061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.872080] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.872101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.872117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.872135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.872150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.872164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.872180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.872198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.872214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.872230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.872289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.872312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.872338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.872379] [drm:intel_power_well_disable [i915]] disabling display
>[  744.872571] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.872604] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.872630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.872700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.872713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.872778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.872802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.872827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.872854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.872876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.872900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.872924] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.872947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.872969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.872991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.873010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.873015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.873036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.873041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.873062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.873083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.873102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.873123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.873147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.873168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.873187] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.873208] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.873226] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.873271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.873296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.873363] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.873550] [drm:intel_power_well_enable [i915]] enabling display
>[  744.873563] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.873590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.873605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.873620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.873633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.873646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.873661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.873677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.873691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.873706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.873719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.873731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.873747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.873762] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.875740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.875758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.875775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.875793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.877311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.877327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.877341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.878846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.878862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.880691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.883637] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.883700] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.883717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.883739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.900443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.900469] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.900504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.933821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.933865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.933918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  744.933943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  744.933983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  744.951994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  744.952013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  744.952034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.952051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.952068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.952083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.952098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.952114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.952132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.952148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.952164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.952180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.952194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.952209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.952235] [drm:intel_power_well_disable [i915]] disabling display
>[  744.952305] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  744.952339] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.952366] [drm:intel_power_well_disable [i915]] disabling always-on
>[  744.952573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  744.952594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  744.952657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  744.952681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  744.952706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  744.952733] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  744.952755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  744.952779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  744.952803] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  744.952826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  744.952850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  744.952871] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  744.952892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  744.952898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.952918] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  744.952923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  744.952945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  744.952966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  744.952987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  744.953007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  744.953030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  744.953051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  744.953072] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  744.953092] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  744.953112] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  744.953136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  744.953162] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  744.953226] [drm:intel_power_well_enable [i915]] enabling always-on
>[  744.953270] [drm:intel_power_well_enable [i915]] enabling display
>[  744.953291] [drm:hsw_set_power_well [i915]] Enabling power well
>[  744.953330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  744.953354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  744.953377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  744.953400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  744.953423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  744.953447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  744.953472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  744.953497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  744.953521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  744.953542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  744.953564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  744.953590] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  744.953861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  744.955838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  744.955853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  744.955867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.955881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  744.957398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  744.957422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  744.957440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  744.958938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  744.958957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  744.960769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  744.963694] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  744.963726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  744.963743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  744.963765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  744.980480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  744.980507] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  744.980544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.013883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.013927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.013982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.014004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.014054] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.032948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.032966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.032986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.033003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.033020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.033035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.033050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.033065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.033083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.033099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.033115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.033130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.033149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.033168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.033195] [drm:intel_power_well_disable [i915]] disabling display
>[  745.033218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.033242] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.033305] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.033377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.033392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.033464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.033497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.033523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.033546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.033561] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.033577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.033593] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.033607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.033622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.033635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.033648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.033652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.033665] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.033668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.033681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.033694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.033707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.033720] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.033736] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.033749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.033762] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.033774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.033788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.033802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.033820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.033864] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.033877] [drm:intel_power_well_enable [i915]] enabling display
>[  745.033890] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.033914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.033929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.033943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.033957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.033970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.033984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.033999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.034013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.034027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.034040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.034053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.034069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.034084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.036063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.036081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.036099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.036117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.037626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.037642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.037656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.039150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.039166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.040974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.043898] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.043932] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.043951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.043977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.060675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.060701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.060736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.094077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.094120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.094172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.094193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.094238] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.112956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.112975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.112995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.113012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.113029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.113044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.113059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.113075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.113096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.113117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.113138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.113158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.113177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.113196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.113223] [drm:intel_power_well_disable [i915]] disabling display
>[  745.113246] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.113318] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.113346] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.113568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.113583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.113654] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.113681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.113709] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.113738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.113762] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.113788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.113815] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.113840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.113865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.113889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.113912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.113918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.113941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.113947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.113970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.113993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.114016] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.114037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.114063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.114086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.114109] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.114129] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.114152] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.114177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.114205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.114295] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.114329] [drm:intel_power_well_enable [i915]] enabling display
>[  745.114352] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.114390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.114415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.114438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.114461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.114483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.114506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.114531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.114556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.114580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.114601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.114813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.114832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.114850] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.116831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.116848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.116863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.116878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.118401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.118418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.118433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.119928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.119945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.121755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.124697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.124764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.124784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.124809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.141507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.141533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.141567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.174896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.174939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.174993] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.175018] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.175060] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.193928] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.193946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.193967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.193984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.194004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.194024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.194043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.194062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.194083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.194104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.194124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.194144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.194163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.194179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.194207] [drm:intel_power_well_disable [i915]] disabling display
>[  745.194229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.194254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.194319] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.194394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.194408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.194480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.194506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.194534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.194564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.194589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.194615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.194642] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.194667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.194692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.194715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.194738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.194745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.194767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.194772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.194796] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.194819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.194842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.194866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.194889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.194912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.194936] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.194960] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.194983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.195016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.195042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.195107] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.195129] [drm:intel_power_well_enable [i915]] enabling display
>[  745.195151] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.195189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.195212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.195235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.195257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.195297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.195321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.195347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.195371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.195395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.195417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.195439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.195465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.195489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.197482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.197498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.197512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.197527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.199032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.199050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.199067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.200569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.200585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.202393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.205334] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.205403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.205420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.205442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.222145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.222171] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.222205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.255525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.255568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.255622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.255647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.255687] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.274560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.274579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.274600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.274617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.274634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.274650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.274665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.274681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.274699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.274719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.274740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.274761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.274779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.274797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.274824] [drm:intel_power_well_disable [i915]] disabling display
>[  745.274846] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.274870] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.274887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.274924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.274933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.274979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.274999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.275019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.275047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.275063] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.275079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.275095] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.275112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.275130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.275147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.275164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.275168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.275185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.275188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.275206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.275223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.275240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.275257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.275317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.275344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.275369] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.275393] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.275416] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.275442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.275468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.275533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.275556] [drm:intel_power_well_enable [i915]] enabling display
>[  745.275578] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.275616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.275641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.275664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.275686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.275707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.275730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.275754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.275778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.275801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.275822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.275844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.275867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.275890] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.277889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.277905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.277920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.277934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.279442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.279457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.279470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.280964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.280979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.282788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.285709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.285745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.285762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.285784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.302489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.302515] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.302551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.335872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.335915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.335968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.335992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.336032] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.354899] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.354918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.354938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.354955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.354972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.354987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.355002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.355018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.355036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.355052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.355068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.355084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.355098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.355112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.355139] [drm:intel_power_well_disable [i915]] disabling display
>[  745.355160] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.355181] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.355197] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.355232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.355241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.355334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.355360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.355388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.355417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.355443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.355469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.355496] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.355520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.355545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.355569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.355593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.355600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.355622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.355628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.355651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.355675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.355698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.355721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.355747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.355770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.355793] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.355816] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.355840] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.355865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.355893] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.355964] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.355987] [drm:intel_power_well_enable [i915]] enabling display
>[  745.356009] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.356046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.356068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.356090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.356110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.356131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.356154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.356178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.356202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.356226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.356247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.356266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.356308] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.356332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.358334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.358350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.358365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.358379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.359886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.359901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.359914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.361414] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.361430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.363238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.366180] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.366248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.366264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.366331] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.382990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.383015] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.383052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.416385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.416430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.416482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.416505] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.416553] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.435414] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.435433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.435453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.435469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.435487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.435502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.435516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.435532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.435550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.435566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.435586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.435606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.435625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.435642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.435670] [drm:intel_power_well_disable [i915]] disabling display
>[  745.435692] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.435717] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.435733] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.435777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.435787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.435832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.435858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.435875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.435893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.435907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.435923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.435940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.435958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.435976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.435993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.436010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.436013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.436030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.436034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.436051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.436069] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.436086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.436103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.436121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.436138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.436155] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.436173] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.436190] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.436208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.436227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.436269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.436326] [drm:intel_power_well_enable [i915]] enabling display
>[  745.436352] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.436392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.436417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.436442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.436465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.436488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.436512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.436538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.436563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.436587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.436610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.436632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.436658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.436682] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.438681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.438697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.438711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.438726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.440234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.440249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.440263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.441804] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.441819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.443701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.446629] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.446658] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.446675] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.446696] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.463402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.463428] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.463462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.496788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.496831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.496884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.496909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.496956] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.515830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.515849] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.515869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.515886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.515904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.515919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.515933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.515949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.515967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.515983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.515999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.516015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.516029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.516042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.516069] [drm:intel_power_well_disable [i915]] disabling display
>[  745.516090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.516111] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.516127] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.516169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.516178] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.516219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.516235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.516253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.516272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.516332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.516361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.516389] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.516415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.516441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.516465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.516489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.516496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.516519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.516526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.516549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.516573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.516597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.516621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.516648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.516671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.516703] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.516724] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.516746] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.516771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.516797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.516862] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.516884] [drm:intel_power_well_enable [i915]] enabling display
>[  745.516907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.516944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.516967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.516989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.517011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.517032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.517053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.517077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.517101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.517125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.517146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.517167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.517193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.517216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.519233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.519249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.519262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.519311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.520824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.520842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.520860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.522427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.522445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.524322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.527256] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.527366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.527392] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.527429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.544073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.544099] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.544134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.577469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.577513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.577565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.577586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.577633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.596506] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.596525] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.596545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.596562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.596579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.596594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.596609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.596625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.596643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.596659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.596675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.596690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.596704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.596722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.596750] [drm:intel_power_well_disable [i915]] disabling display
>[  745.596772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.596797] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.596813] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.596858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.596867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.596913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.596932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.596952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.596974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.596993] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.597013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.597032] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.597052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.597071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.597089] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.597108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.597112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.597131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.597134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.597154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.597173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.597192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.597211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.597230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.597248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.597267] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.597332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.597361] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.597391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.597421] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.597492] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.597523] [drm:intel_power_well_enable [i915]] enabling display
>[  745.597546] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.597584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.597608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.597632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.597655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.597677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.597701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.597725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.597749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.597773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.597794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.597815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.597840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.597863] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.599876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.599893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.599908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.599923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.601435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.601453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.601471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.602968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.602985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.604795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.607736] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.607803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.607819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.607840] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.624546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.624573] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.624610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.657931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.657975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.658029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.658054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.658094] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.676966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.676986] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.677006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.677023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.677040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.677055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.677070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.677086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.677104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.677120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.677136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.677152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.677166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.677180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.677207] [drm:intel_power_well_disable [i915]] disabling display
>[  745.677228] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.677249] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.677265] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.677368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.677383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.677453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.677477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.677502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.677529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.677551] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.677575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.677599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.677622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.677645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.677667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.677689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.677694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.677715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.677721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.677742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.677763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.677785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.677806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.677829] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.677851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.677873] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.677894] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.677914] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.677937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.677963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.678028] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.678050] [drm:intel_power_well_enable [i915]] enabling display
>[  745.678072] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.678109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.678132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.678154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.678176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.678198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.678218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.678243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.678266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.678290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.678330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.678353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.678378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.678402] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.680398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.680414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.680428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.680443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.681947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.681962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.681976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.683473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.683489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.685327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.688261] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.688369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.688396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.688433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.705079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.705106] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.705144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.738471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.738514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.738568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.738590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.738636] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.757491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.757510] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.757531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.757547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.757565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.757580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.757595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.757611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.757632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.757653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.757673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.757693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.757712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.757729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.757757] [drm:intel_power_well_disable [i915]] disabling display
>[  745.757779] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.757803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.757820] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.757867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.757876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.757922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.757942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.757962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.757983] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.758002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.758022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.758041] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.758060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.758080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.758098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.758117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.758121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.758140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.758143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.758163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.758182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.758201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.758227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.758244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.758260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.758275] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.758289] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.758341] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.758365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.758392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.758458] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.758481] [drm:intel_power_well_enable [i915]] enabling display
>[  745.758503] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.758541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.758797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.758821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.758844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.758866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.758890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.758915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.758939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.758963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.758985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.759006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.759032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.759055] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.761054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.761071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.761085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.761100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.762610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.762625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.762638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.764132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.764148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.765958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.768881] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.768916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.768935] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.768961] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.785660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.785687] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.785724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.819058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.819101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.819153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.819174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.819219] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.838091] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.838109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.838130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.838147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.838167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.838187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.838207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.838226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.838247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.838268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.838288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.838349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.838375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.838400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.838441] [drm:intel_power_well_disable [i915]] disabling display
>[  745.838475] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.838507] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.838532] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.838605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.838620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.838687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.838710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.838737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.838766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.838788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.838813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.838837] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.838861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.838884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.838907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.838927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.838934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.838955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.838960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.838983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.839003] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.839025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.839052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.839075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.839094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.839114] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.839133] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.839154] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.839175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.839199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.839261] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.839283] [drm:intel_power_well_enable [i915]] enabling display
>[  745.839321] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.839358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.839382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.839403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.839425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.839446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.839468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.839493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.839518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.839542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.839562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.839584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.839607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.839630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.841625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.841641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.841655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.841669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.843175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.843190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.843204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.844701] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.844717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.846528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.849465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.849538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.849555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.849576] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.866278] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.866342] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.866451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.899659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.899702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.899755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.899777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.899823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.918697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.918716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.918736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.918753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.918771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.918786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.918801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.918817] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.918834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.918851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.918866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.918881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.918895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.918909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.918935] [drm:intel_power_well_disable [i915]] disabling display
>[  745.918956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.918977] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.918993] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.919030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.919039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.919084] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.919104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.919124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.919146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.919165] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.919184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  745.919203] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  745.919223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  745.919242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  745.919261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  745.919279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  745.919283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.919302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  745.919337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  745.919367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  745.919392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  745.919418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  745.919441] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  745.919468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  745.919490] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  745.919514] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  745.919536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  745.919559] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  745.919587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.919616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  745.919686] [drm:intel_power_well_enable [i915]] enabling always-on
>[  745.920017] [drm:intel_power_well_enable [i915]] enabling display
>[  745.920039] [drm:hsw_set_power_well [i915]] Enabling power well
>[  745.920077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.920100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.920121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.920143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.920163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.920185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.920210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.920233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.920256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.920276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.920297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.920340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  745.920362] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  745.922486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  745.922502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  745.922516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.922531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  745.924036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  745.924051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  745.924065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  745.925565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  745.925581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  745.927390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  745.930319] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  745.930347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  745.930363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  745.930384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  745.947092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.947117] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.947152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.980471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.980514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  745.980568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  745.980591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  745.980637] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  745.999510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  745.999529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  745.999549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  745.999566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  745.999583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  745.999599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  745.999613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  745.999629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  745.999647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  745.999663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  745.999679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  745.999695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  745.999709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  745.999722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  745.999749] [drm:intel_power_well_disable [i915]] disabling display
>[  745.999770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  745.999790] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  745.999806] [drm:intel_power_well_disable [i915]] disabling always-on
>[  745.999844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  745.999854] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  745.999899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  745.999919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  745.999939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  745.999961] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  745.999980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  745.999999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.000018] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.000037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.000057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.000076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.000094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.000098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.000117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.000121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.000140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.000159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.000178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.000197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.000216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.000234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.000254] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.000273] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.000291] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.000350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.000383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.000453] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.000478] [drm:intel_power_well_enable [i915]] enabling display
>[  746.000503] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.000545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.000572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.000901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.000922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.000944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.000965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.000990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.001013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.001036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.001056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.001076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.001099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.001121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.003119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.003137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.003155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.003173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.004684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.004700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.004715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.006211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.006227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.008036] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.010959] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.010993] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.011009] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.011031] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.027736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.027763] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.027801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.061123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.061167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.061221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.061243] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.061288] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.080181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.080200] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.080220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.080238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.080255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.080271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.080286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.080302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.080363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.080391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.080418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.080444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.080468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.080492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.080535] [drm:intel_power_well_disable [i915]] disabling display
>[  746.080570] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.080602] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.080627] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.080699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.080712] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.080774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.080796] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.080820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.080846] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.080866] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.080889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.080911] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.080932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.080953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.080974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.080993] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.080999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.081018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.081023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.081044] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.081064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.081084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.081103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.081125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.081144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.081164] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.081183] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.081203] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.081227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.081251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.081334] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.081359] [drm:intel_power_well_enable [i915]] enabling display
>[  746.081381] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.081419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.081443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.081465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.081487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.081507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.081530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.081555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.081579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.081604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.081624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.081645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.081671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.081693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.083689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.083705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.083719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.083734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.085254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.085272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.085289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.086818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.086834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.088673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.091613] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.091684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.091703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.091729] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.108425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.108451] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.108485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.141810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.141853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.141905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.141927] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.141974] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.159960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.159978] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.159998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.160015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.160032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.160047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.160062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.160078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.160095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.160111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.160126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.160146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.160165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.160184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.160212] [drm:intel_power_well_disable [i915]] disabling display
>[  746.160234] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.160259] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.160275] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.160350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.160366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.160438] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.160462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.160490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.160519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.160547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.160571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.160593] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.160615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.160636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.160657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.160676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.160682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.160701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.160707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.160728] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.160747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.160768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.160787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.160810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.160829] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.160849] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.160868] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.160888] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.160909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.160933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.160997] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.161019] [drm:intel_power_well_enable [i915]] enabling display
>[  746.161040] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.161077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.161097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.161119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.161139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.161160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.161180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.161203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.161226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.161249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.161268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.161289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.161314] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.161361] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.163358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.163374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.163390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.163409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.164915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.164931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.164945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.166444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.166460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.168266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.171201] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.171275] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.171292] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.171317] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.188019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.188045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.188083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.221404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.221447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.221501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.221523] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.221569] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.240429] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.240448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.240469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.240489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.240511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.240530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.240549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.240568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.240590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.240611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.240631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.240651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.240670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.240689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.240716] [drm:intel_power_well_disable [i915]] disabling display
>[  746.240738] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.240763] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.240779] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.240824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.240834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.240879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.240898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.240918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.240940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.240958] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.240978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.240997] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.241016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.241036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.241054] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.241073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.241077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.241096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.241100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.241119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.241138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.241157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.241176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.241195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.241214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.241233] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.241252] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.241271] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.241291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.241312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.241417] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.241441] [drm:intel_power_well_enable [i915]] enabling display
>[  746.241461] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.241503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.241526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.241549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.241570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.241593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.241614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.241640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.241663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.241687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.241707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.241729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.241752] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.241775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.243786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.243803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.243817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.243832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.245357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.245372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.245386] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.246901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.246918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.248728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.251666] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.251737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.251754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.251776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.268479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.268505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.268540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.301876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.301920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.301972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.301993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.302038] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.320936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.320954] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.320975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.320992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.321010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.321029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.321048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.321067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.321089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.321110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.321131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.321151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.321170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.321186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.321214] [drm:intel_power_well_disable [i915]] disabling display
>[  746.321236] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.321261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.321277] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.321364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.321380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.321446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.321470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.321497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.321525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.321547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.321572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.321595] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.321619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.321640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.321663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.321683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.321689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.321709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.321715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.321737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.321758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.321780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.321800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.321824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.321844] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.321865] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.321886] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.321907] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.321929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.321955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.322021] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.322044] [drm:intel_power_well_enable [i915]] enabling display
>[  746.322067] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.322105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.322127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.322150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.322171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.322193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.322214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.322240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.322264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.322288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.322316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.322354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.322378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.322401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.324399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.324415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.324429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.324444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.325958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.325977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.325994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.327495] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.327513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.329323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.332271] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.332378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.332401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.332425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.349086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.349112] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.349147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.382489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.382532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.382584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.382605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.382656] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.401532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.401550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.401570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.401587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.401604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.401620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.401638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.401658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.401680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.401700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.401721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.401741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.401760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.401776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.401804] [drm:intel_power_well_disable [i915]] disabling display
>[  746.401827] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.401852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.401868] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.401914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.401924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.401969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.401989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.402009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.402031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.402049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.402069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.402088] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.402107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.402127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.402146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.402164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.402168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.402187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.402191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.402210] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.402229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.402248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.402274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.402291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.402308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.402325] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.402378] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.402401] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.402426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.402450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.402513] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.402533] [drm:intel_power_well_enable [i915]] enabling display
>[  746.402555] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.402772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.402788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.402803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.402817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.402830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.402848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.402868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.402887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.402905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.402923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.402941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.402960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.402978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.404955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.404972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.404986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.405001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.406511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.406526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.406540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.408035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.408051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.409862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.412798] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.412871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.412888] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.412910] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.429613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.429639] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.429674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.463002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.463045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.463099] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.463121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.463171] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.481103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.481122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.481142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.481159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.481177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.481192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.481207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.481223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.481241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.481258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.481274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.481290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.481304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.481317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.481387] [drm:intel_power_well_disable [i915]] disabling display
>[  746.481422] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.481544] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.481561] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.481606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.481615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.481658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.481675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.481693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.481713] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.481729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.481746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.481763] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.481779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.481795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.481810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.481825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.481829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.481843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.481847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.481861] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.481875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.481890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.481903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.481921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.481935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.481949] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.481963] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.481978] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.481994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.482013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.482065] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.482078] [drm:intel_power_well_enable [i915]] enabling display
>[  746.482091] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.482116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.482130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.482144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.482157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.482170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.482184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.482199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.482218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.482237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.482254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.482272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.482291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.482309] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.484311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.484327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.484374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.484402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.485913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.485931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.485948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.487449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.487466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.489285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.492206] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.492242] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.492259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.492280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.508979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.509003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.509037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.542369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.542411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.542454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.542475] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.542521] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.561401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.561420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.561440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.561458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.561475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.561494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.561514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.561533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.561555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.561575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.561596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.561616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.561635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.561652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.561679] [drm:intel_power_well_disable [i915]] disabling display
>[  746.561701] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.561726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.561742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.561780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.561789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.561836] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.561856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.561875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.561898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.561916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.561936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.561955] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.561974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.561994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.562012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.562031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.562035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.562053] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.562057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.562076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.562095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.562122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.562139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.562156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.562173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.562190] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.562208] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.562225] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.562243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.562262] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.562305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.562318] [drm:intel_power_well_enable [i915]] enabling display
>[  746.562332] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.562402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.562428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.562453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.562476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.562499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.562523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.562550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.562575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.562600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.562622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.562645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.562671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.562695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.564694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.564710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.564724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.564739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.566245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.566260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.566274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.567771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.567787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.569595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.572525] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.572552] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.572571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.572597] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.589296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.589322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.589405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.622667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.622711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.622764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.622786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.622826] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.641108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.641127] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.641147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.641164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.641182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.641197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.641211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.641227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.641244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.641261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.641276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.641296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.641315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.641332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.641407] [drm:intel_power_well_disable [i915]] disabling display
>[  746.641442] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.641608] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.641634] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.641691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.641705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.641774] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.641800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.641828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.641857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.641882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.641908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.641934] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.641959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.641984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.642015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.642037] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.642043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.642064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.642069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.642091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.642112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.642133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.642152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.642175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.642196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.642218] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.642237] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.642257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.642281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.642305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.642390] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.642413] [drm:intel_power_well_enable [i915]] enabling display
>[  746.642436] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.642474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.642499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.642522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.642545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.642567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.642591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.642617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.642642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.642666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.642688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.642710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.642926] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.642941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.644932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.644949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.644966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.644984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.646500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.646517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.646532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.648028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.648044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.649853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.652797] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.652861] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.652881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.652906] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.669628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.669654] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.669689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.703055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.703136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.703232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.703273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.703344] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.720256] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.720275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.720295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.720312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.720330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.720345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.720404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.720430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.720460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.720488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.720514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.720541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.720564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.720587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.720630] [drm:intel_power_well_disable [i915]] disabling display
>[  746.720664] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.720696] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.720722] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.720790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.720804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.720880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.720903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.720928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.720955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.720978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.721002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.721026] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.721048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.721071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.721092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.721113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.721119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.721140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.721145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.721167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.721187] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.721208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.721227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.721250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.721270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.721290] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.721310] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.721329] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.721352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.721398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.721466] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.721489] [drm:intel_power_well_enable [i915]] enabling display
>[  746.721512] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.721550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.721573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.721596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.721619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.721640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.721663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.721687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.721711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.721734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.721756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.721777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.721802] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.721825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.723820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.723837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.723851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.723866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.725374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.725392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.725409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.726973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.726989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.728799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.731717] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.731756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.731772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.731794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.748500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.748526] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.748561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.781886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.781930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.781983] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.782008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.782049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.800915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.800933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.800954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.800973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.800995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.801014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.801034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.801053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.801074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.801095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.801116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.801136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.801155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.801171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.801199] [drm:intel_power_well_disable [i915]] disabling display
>[  746.801221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.801246] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.801262] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.801307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.801317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.801409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.801438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.801468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.801499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.801525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.801553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.801580] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.801606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.801632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.801656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.801680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.801687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.801710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.801717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.801741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.801771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.801793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.801815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.801839] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.801860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.801881] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.801903] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.801925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.801949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.801974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.802036] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.802058] [drm:intel_power_well_enable [i915]] enabling display
>[  746.802080] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.802118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.802141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.802163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.802185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.802207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.802227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.802251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.802275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.802299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.802321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.802340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.802383] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.802406] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.804403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.804421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.804438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.804456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.805973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.805989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.806003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.807521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.807540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.809403] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.812337] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.812420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.812451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.812486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.829155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.829180] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.829215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.862585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.862653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.862734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.862768] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.862827] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.879706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.879732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.879759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.879784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.879810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.879834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.879858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.879882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.879909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.879934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.879960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.879985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.880009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.880029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.880063] [drm:intel_power_well_disable [i915]] disabling display
>[  746.880090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.880120] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.880141] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.880196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.880208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.880265] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.880289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.880314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.880340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.880364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.880445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.880484] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  746.880517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  746.880551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.880581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.880611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.880620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.880648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.880656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.880687] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.880717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.880746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.880775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.880809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.880839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.880870] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  746.880899] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  746.880929] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  746.880963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.880998] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  746.881086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.881116] [drm:intel_power_well_enable [i915]] enabling display
>[  746.881147] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.881198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.881228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.881258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.881287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.881313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.881343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.881401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.881433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.881467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.881496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.881525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.881558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  746.881590] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.883641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.883663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.883682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.883702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.885246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.885266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.885284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.886820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.886844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.888700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.891697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  746.891764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.891784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  746.891810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  746.908504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.908531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.908568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.941971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.942040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  746.942075] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  746.942132] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  746.958987] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  746.959007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  746.959028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.959046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.959064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.959079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.959094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.959113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  746.959136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.959158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.959179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.959200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.959220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.959240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.959269] [drm:intel_power_well_disable [i915]] disabling display
>[  746.959293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  746.959318] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  746.959336] [drm:intel_power_well_disable [i915]] disabling always-on
>[  746.959607] [drm:drm_mode_addfb2] [FB:75]
>[  746.959647] [drm:drm_mode_addfb2] [FB:78]
>[  746.986297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  746.986428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  746.986508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  746.986565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  746.986575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  746.986623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  746.986640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  746.986657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  746.986676] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  746.986690] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  746.986706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  746.986722] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  746.986737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  746.986751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  746.986764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  746.986777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  746.986780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.986793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  746.986796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  746.986809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  746.986821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  746.986834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  746.986846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  746.986861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  746.986874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  746.986887] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  746.986900] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  746.986912] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  746.986927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  746.986944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  746.989461] [drm:intel_power_well_enable [i915]] enabling always-on
>[  746.989478] [drm:intel_power_well_enable [i915]] enabling display
>[  746.989492] [drm:hsw_set_power_well [i915]] Enabling power well
>[  746.989522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  746.989541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  746.989560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  746.989579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  746.989598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  746.989617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  746.989637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  746.989657] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  746.989677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  746.989695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  746.989711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  746.989732] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  746.989751] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  746.991739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  746.991755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  746.991770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.991785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  746.993310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  746.993325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  746.993339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  746.994837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  746.994852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  746.996662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  746.999596] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  746.999671] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  746.999688] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  746.999710] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.016424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.016450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.016487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.033135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.033186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.033229] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.033251] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.033297] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.051169] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.051188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.051208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.051225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.051243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.051259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.051273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.051290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.051308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.051324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.051340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.051356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.051410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.051434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.051477] [drm:intel_power_well_disable [i915]] disabling display
>[  747.051642] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.051675] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.051701] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.051760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.051775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.051844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.051870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.051897] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.051926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.051951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.051977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.052003] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.052028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.052053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.052077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.052100] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.052106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.052128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.052134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.052158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.052181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.052204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.052227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.052250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.052273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.052296] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.052324] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.052345] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.052366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.052412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.052468] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.052490] [drm:intel_power_well_enable [i915]] enabling display
>[  747.052513] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.052551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.052763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.052778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.052792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.052806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.052820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.052836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.052851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.052865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.052878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.052891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.052907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.052922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.054922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.054938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.054951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.054966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.056477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.056494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.056512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.058008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.058024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.059834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.062783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.062844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.062864] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.062890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.079586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.079612] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.079648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.112972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.113016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.113070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.113092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.113131] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.131999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.132018] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.132038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.132055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.132072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.132087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.132101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.132117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.132134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.132150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.132166] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.132181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.132195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.132209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.132235] [drm:intel_power_well_disable [i915]] disabling display
>[  747.132256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.132277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.132293] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.132334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.132344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.132435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.132462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.132492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.132522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.132547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.132575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.132602] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.132628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.132654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.132679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.132703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.132710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.132732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.132738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.132762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.132787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.132810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.132834] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.132860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.132882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.132906] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.132929] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.132951] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.132977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.133004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.133072] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.133096] [drm:intel_power_well_enable [i915]] enabling display
>[  747.133120] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.133160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.133185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.133209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.133231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.133254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.133278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.133305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.133336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.133360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.133397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.133420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.133445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.133469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.135467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.135483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.135497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.135512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.137017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.137032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.137045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.138545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.138560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.140369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.143306] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.143338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.143354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.143416] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.160081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.160108] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.160146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.193468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.193511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.193564] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.193589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.193637] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.212533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.212552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.212572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.212589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.212607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.212622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.212638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.212654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.212672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.212692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.212712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.212733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.212751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.212768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.212796] [drm:intel_power_well_disable [i915]] disabling display
>[  747.212818] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.212843] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.212859] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.212903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.212914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.212960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.212979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.212999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.213021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.213040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.213060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.213079] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.213098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.213117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.213136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.213155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.213159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.213177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.213181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.213200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.213219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.213238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.213265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.213282] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.213298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.213313] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.213327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.213340] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.213355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.213372] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.213467] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.213490] [drm:intel_power_well_enable [i915]] enabling display
>[  747.213512] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.213550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.213575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.213599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.213622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.213644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.213668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.213694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.213718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.213742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.213763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.213785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.213811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.213834] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.215847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.215863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.215877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.215891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.217414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.217429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.217442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.218959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.218975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.220787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.223730] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.223796] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.223813] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.223835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.240539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.240566] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.240604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.273929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.273972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.274027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.274049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.274088] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.292945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.292964] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.292984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.293001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.293019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.293034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.293049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.293065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.293083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.293100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.293115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.293131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.293145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.293159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.293186] [drm:intel_power_well_disable [i915]] disabling display
>[  747.293207] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.293228] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.293243] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.293286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.293295] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.293336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.293352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.293370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.293436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.293465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.293492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.293521] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.293546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.293572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.293596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.293620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.293627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.293650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.293657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.293681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.293704] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.293729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.293752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.293779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.293803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.293827] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.293851] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.293875] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.293902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.293930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.294000] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.294025] [drm:intel_power_well_enable [i915]] enabling display
>[  747.294048] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.294089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.294114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.294138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.294169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.294189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.294211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.294235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.294258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.294282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.294303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.294324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.294347] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.294370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.296382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.296409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.296423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.296438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.297952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.297967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.297981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.299499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.299517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.301333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.304270] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.304349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.304364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.304416] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.321084] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.321111] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.321149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.354471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.354515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.354568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.354590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.354636] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.373524] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.373543] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.373563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.373580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.373598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.373614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.373628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.373644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.373662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.373678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.373694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.373714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.373733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.373750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.373777] [drm:intel_power_well_disable [i915]] disabling display
>[  747.373800] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.373825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.373841] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.373886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.373896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.373942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.373961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.373981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.374003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.374022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.374048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.374065] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.374080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.374094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.374107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.374119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.374123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.374135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.374138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.374151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.374164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.374176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.374193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.374211] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.374228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.374245] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.374263] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.374280] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.374299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.374317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.374359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.374373] [drm:intel_power_well_enable [i915]] enabling display
>[  747.374429] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.374472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.374497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.374522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.374545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.374568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.374592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.374618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.374643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.374667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.374690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.374712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.374738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.374762] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.376761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.376777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.376791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.376806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.378337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.378352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.378366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.379894] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.379910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.381747] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.384687] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.384757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.384774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.384796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.401499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.401525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.401561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.434886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.434930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.434984] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.435009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.435050] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.453157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.453175] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.453197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.453217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.453238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.453257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.453277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.453296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.453318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.453338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.453358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.453379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.453441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.453469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.453511] [drm:intel_power_well_disable [i915]] disabling display
>[  747.453703] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.453737] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.453763] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.453839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.453852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.453916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.453940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.453965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.453993] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.454016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.454040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.454064] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.454086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.454109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.454130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.454149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.454155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.454175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.454180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.454202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.454223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.454242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.454262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.454286] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.454307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.454327] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.454348] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.454369] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.454392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.454440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.454506] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.454529] [drm:intel_power_well_enable [i915]] enabling display
>[  747.454703] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.454729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.454745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.454760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.454774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.454787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.454802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.454817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.454832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.454847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.454860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.454872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.454888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.454906] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.456885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.456901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.456918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.456936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.458466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.458482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.458496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.460001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.460019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.461836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.464774] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.464846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.464865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.464891] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.481597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.481625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.481662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.515003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.515047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.515092] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.515114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.515163] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.534020] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.534039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.534059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.534076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.534093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.534112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.534132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.534151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.534172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.534193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.534213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.534233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.534252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.534268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.534296] [drm:intel_power_well_disable [i915]] disabling display
>[  747.534318] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.534342] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.534358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.534446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.534461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.534524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.534542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.534561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.534581] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.534597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.534615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.534633] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.534650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.534666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.534681] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.534696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.534700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.534714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.534718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.534733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.534747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.534769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.534782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.534798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.534811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.534825] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.534837] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.534850] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.534869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.534888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.534931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.534946] [drm:intel_power_well_enable [i915]] enabling display
>[  747.534960] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.534988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.535006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.535024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.535042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.535059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.535077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.535096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.535115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.535135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.535152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.535170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.535189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.535207] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.537189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.537206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.537220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.537235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.538745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.538759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.538773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.540268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.540284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.542094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.545033] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.545104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.545120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.545142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.561841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.561867] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.561902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.595216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.595263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.595317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.595342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.595383] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.614287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.614306] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.614326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.614343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.614361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.614376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.614391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.614453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.614486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.614514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.614541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.614734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.614753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.614770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.614797] [drm:intel_power_well_disable [i915]] disabling display
>[  747.614819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.614844] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.614860] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.614897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.614907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.614952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.614972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.614992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.615014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.615033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.615052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.615072] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.615091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.615110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.615129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.615147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.615151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.615170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.615174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.615193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.615212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.615231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.615250] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.615269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.615288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.615307] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.615326] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.615346] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.615365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.615386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.615478] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.615503] [drm:intel_power_well_enable [i915]] enabling display
>[  747.615528] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.615571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.615607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.615631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.615655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.615677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.615702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.615727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.615751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.615775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.615797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.615819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.615844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.615867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.617881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.617897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.617913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.617931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.619466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.619482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.619496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.621001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.621018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.622833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.625785] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.625843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.625860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.625882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.642585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.642611] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.642649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.676005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.676072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.676155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.676191] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.676268] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.693095] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.693114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.693134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.693151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.693170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.693185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.693200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.693217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.693235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.693251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.693267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.693283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.693297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.693311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.693338] [drm:intel_power_well_disable [i915]] disabling display
>[  747.693359] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.693380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.693395] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.693487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.693502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.693572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.693598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.693627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.693656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.693681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.693708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.693734] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.693760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.693785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.693809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.693833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.693839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.693862] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.693868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.693891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.693915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.693938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.693961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.693987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.694010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.694034] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.694055] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.694079] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.694105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.694132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.694203] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.694228] [drm:intel_power_well_enable [i915]] enabling display
>[  747.694252] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.694293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.694317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.694341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.694366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.694388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.694419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.694460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.694486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.694510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.694532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.694554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.694580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.694603] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.696598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.696613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.696627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.696641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.698146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.698164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.698181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.699683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.699700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.701510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.704435] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.704468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.704484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.704506] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.721211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.721237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.721272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.754599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.754662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.754737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.754768] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.754826] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.771655] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.771674] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.771694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.771711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.771729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.771744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.771759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.771775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.771793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.771809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.771825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.771840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.771854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.771868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.771894] [drm:intel_power_well_disable [i915]] disabling display
>[  747.771917] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.771941] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.771958] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.772001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.772010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.772056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.772076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.772096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.772118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.772137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.772157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.772176] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.772195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.772215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.772233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.772258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.772262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.772277] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.772281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.772296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.772310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.772323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.772336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.772351] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.772365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.772378] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.772391] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.772404] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.772458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.772483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.772547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.772570] [drm:intel_power_well_enable [i915]] enabling display
>[  747.772592] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.772630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.772651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.772674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.772693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.772714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.772737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.772762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.772785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.772808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.772827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.772847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.772872] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.772892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.774889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.774905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.774919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.774933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.776467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.776482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.776496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.778000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.778016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.779847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.782783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.782856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.782873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.782895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.799598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.799625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.799660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.833037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.833107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.833193] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.833229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.833291] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.850150] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.850169] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.850189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.850206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.850223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.850239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.850253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.850269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.850287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.850303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.850319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.850335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.850349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.850363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.850389] [drm:intel_power_well_disable [i915]] disabling display
>[  747.850410] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.850478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.850502] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.850565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.850575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.850617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.850637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.850657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.850680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.850700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.850720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.850740] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.850760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.850780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.850800] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.850819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.850823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.850842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.850847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.850866] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.850886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.850905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.850925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.850944] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.850963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.850990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.851006] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.851021] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.851038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.851055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.851097] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.851110] [drm:intel_power_well_enable [i915]] enabling display
>[  747.851122] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.851148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.851163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.851177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.851194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.851213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.851231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.851250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.851269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.851286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.851303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.851321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.851340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.851358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.853335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.853352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.853366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.853381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.854888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.854902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.854916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.856432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.856448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.858257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.861181] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.861215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.861233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.861258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.877957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.877984] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.878019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.911353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.911397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.911539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.911560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.911606] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  747.928458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  747.928476] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  747.928497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.928516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.928538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.928557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.928577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.928596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.928617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.928638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.928658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.928678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.928697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.928716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.928743] [drm:intel_power_well_disable [i915]] disabling display
>[  747.928766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  747.928790] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.928806] [drm:intel_power_well_disable [i915]] disabling always-on
>[  747.928851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.928860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  747.928906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  747.928926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  747.928946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  747.928968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  747.928986] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  747.929006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  747.929025] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  747.929044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  747.929063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  747.929082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  747.929101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  747.929105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.929124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  747.929127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  747.929147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  747.929166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  747.929185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  747.929203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  747.929223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  747.929241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  747.929260] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  747.929279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  747.929298] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  747.929318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.929339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  747.929384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  747.929399] [drm:intel_power_well_enable [i915]] enabling display
>[  747.929414] [drm:hsw_set_power_well [i915]] Enabling power well
>[  747.929482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  747.929507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  747.929531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  747.929554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  747.929577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  747.929600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  747.929626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  747.929652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  747.929676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.929703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  747.929723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  747.929748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  747.929769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  747.931762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  747.931780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  747.931797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.931816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  747.933323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  747.933340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  747.933354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  747.934852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  747.934868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  747.936678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  747.939610] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  747.939688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  747.939704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  747.939726] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  747.956430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  747.956473] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  747.956508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  747.989818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  747.989862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  747.989916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  747.989938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  747.989977] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.008190] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.008209] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.008229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.008246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.008264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.008279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.008294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.008310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.008327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.008343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.008359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.008374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.008389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.008402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.008472] [drm:intel_power_well_disable [i915]] disabling display
>[  748.008508] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.008666] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.008682] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.008724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.008734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.008776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.008794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.008812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.008832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.008847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.008864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.008881] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.008897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.008913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.008927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.008942] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.008946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.008965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.008970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.008990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.009009] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.009029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.009048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.009067] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.009086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.009105] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.009125] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.009144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.009164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.009186] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.009232] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.009247] [drm:intel_power_well_enable [i915]] enabling display
>[  748.009263] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.009294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.009313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.009334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.009354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.009379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.009395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.009412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.009452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.009476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.009496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.009516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.009541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.009563] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.011558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.011575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.011589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.011603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.013107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.013122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.013136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.014632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.014648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.016457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.019394] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.019496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.019524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.019609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.036208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.036234] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.036270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.069612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.069656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.069709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.069729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.069774] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.086659] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.086678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.086698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.086715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.086732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.086747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.086762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.086778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.086796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.086812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.086827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.086843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.086857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.086871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.086898] [drm:intel_power_well_disable [i915]] disabling display
>[  748.086919] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.086940] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.086955] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.086999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.087008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.087049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.087064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.087082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.087101] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.087117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.087133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.087149] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.087164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.087179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.087193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.087207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.087211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.087228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.087232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.087258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.087271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.087284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.087297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.087312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.087325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.087338] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.087350] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.087363] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.087378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.087394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.087466] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.087486] [drm:intel_power_well_enable [i915]] enabling display
>[  748.087506] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.087544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.087565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.087585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.087605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.087625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.087645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.087669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.087692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.087713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.087733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.087752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.087775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.087797] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.089982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.089999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.090013] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.090027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.091539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.091554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.091568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.093063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.093079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.094889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.097833] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.097898] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.097916] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.097938] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.114641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.114667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.114702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.148038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.148081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.148133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.148154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.148198] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.166176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.166195] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.166216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.166236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.166258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.166277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.166297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.166316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.166337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.166358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.166378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.166398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.166417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.166436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.166514] [drm:intel_power_well_disable [i915]] disabling display
>[  748.166551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.166587] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.166614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.166673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.166682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.166727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.166745] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.166763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.166783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.166798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.166815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.166832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.166851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.166871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.166891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.166911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.166915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.166934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.166938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.166958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.166977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.166997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.167017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.167037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.167055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.167076] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.167095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.167121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.167139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.167157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.167199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.167212] [drm:intel_power_well_enable [i915]] enabling display
>[  748.167226] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.167254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.167272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.167290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.167308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.167326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.167344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.167363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.167382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.167402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.167419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.167439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.167483] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.167506] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.169501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.169517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.169531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.169546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.171052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.171067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.171081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.172580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.172596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.174405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.177343] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.177421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.177472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.177507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.194158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.194185] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.194222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.227537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.227582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.227636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.227660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.227702] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.246559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.246579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.246601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.246621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.246643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.246662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.246681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.246700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.246722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.246742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.246763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.246784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.246803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.246819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.246846] [drm:intel_power_well_disable [i915]] disabling display
>[  748.246868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.246893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.246909] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.246945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.246955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.247001] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.247020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.247040] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.247062] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.247080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.247100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.247119] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.247138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.247157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.247176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.247195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.247199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.247224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.247227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.247244] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.247258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.247272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.247285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.247300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.247314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.247327] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.247340] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.247353] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.247368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.247385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.247426] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.247478] [drm:intel_power_well_enable [i915]] enabling display
>[  748.247498] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.247536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.247558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.247579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.247599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.247619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.247640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.247663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.247686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.247708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.247728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.247747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.247771] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.247792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.249789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.249805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.249820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.249835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.251340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.251355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.251369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.252868] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.252883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.254692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.257635] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.257701] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.257718] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.257740] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.274443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.274488] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.274525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.307828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.307877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.307928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.307949] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.307995] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.326856] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.326874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.326895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.326912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.326930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.326949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.326969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.326988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.327010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.327030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.327051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.327071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.327090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.327106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.327134] [drm:intel_power_well_disable [i915]] disabling display
>[  748.327156] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.327180] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.327197] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.327233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.327243] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.327289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.327309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.327328] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.327350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.327369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.327389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.327408] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.327427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.327446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.327508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.327532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.327539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.327562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.327568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.327591] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.327613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.327635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.327657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.327681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.327703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.327725] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.327746] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.327767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.327792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.327818] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.327888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.327913] [drm:intel_power_well_enable [i915]] enabling display
>[  748.327936] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.327978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.328003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.328028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.328051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.328075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.328105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.328128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.328144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.328158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.328171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.328184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.328201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.328216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.330193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.330209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.330223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.330238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.331746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.331761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.331774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.333270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.333286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.335095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.338020] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.338052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.338068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.338090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.354789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.354824] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.354877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.388182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.388226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.388279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.388302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.388340] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.407206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.407225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.407245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.407262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.407279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.407298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.407318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.407337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.407358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.407379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.407400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.407420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.407438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.407503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.407547] [drm:intel_power_well_disable [i915]] disabling display
>[  748.407582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.407616] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.407642] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.407708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.407722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.407792] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.407818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.407845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.407875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.407900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.407926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.407952] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.407985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.408008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.408030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.408051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.408056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.408077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.408083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.408104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.408125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.408145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.408166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.408190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.408211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.408233] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.408254] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.408275] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.408297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.408322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.408386] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.408408] [drm:intel_power_well_enable [i915]] enabling display
>[  748.408431] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.408488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.408512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.408536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.408559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.408581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.408605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.408631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.408656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.408680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.408702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.408724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.408750] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.408774] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.410768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.410784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.410798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.410812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.412317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.412332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.412346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.413843] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.413859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.415667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.418604] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.418677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.418696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.418722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.435419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.435445] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.435536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.468848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.468915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.468998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.469036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.469110] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.485981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.486005] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.486030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.486051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.486073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.486091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.486110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.486129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.486155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.486182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.486207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.486232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.486256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.486279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.486313] [drm:intel_power_well_disable [i915]] disabling display
>[  748.486340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.486370] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.486390] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.486490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.486511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.486599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.486633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.486667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.486705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.486736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.486770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.486802] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.486833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.486865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.486894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.486923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.486931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.486958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.486966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.486995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.487023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.487052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.487080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.487112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.487141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.487170] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.487198] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.487227] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.487256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.487290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.487377] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.487407] [drm:intel_power_well_enable [i915]] enabling display
>[  748.487437] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.487512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.487538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.487563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.487589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.487620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.487646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.487673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.487699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.487725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.487748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.487772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.487799] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.487824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.489823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.489839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.489853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.489867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.491406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.491424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.491441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.492993] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.493010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.494832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.497783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.497845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.497861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.497881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.514584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.514611] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.514649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.547968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.548012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.548065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.548087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.548133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.567003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.567022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.567042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.567059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.567076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.567092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.567106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.567122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.567140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.567156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.567171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.567187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.567201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.567219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.567247] [drm:intel_power_well_disable [i915]] disabling display
>[  748.567269] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.567294] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.567311] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.567355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.567364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.567410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.567430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.567450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.567508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.567535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.567572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.567598] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.567623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.567646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.567670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.567692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.567699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.567720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.567726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.567749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.567771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.567793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.567815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.567840] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.567862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.567884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.567905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.567927] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.567952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.567978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.568043] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.568065] [drm:intel_power_well_enable [i915]] enabling display
>[  748.568088] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.568126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.568149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.568172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.568194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.568213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.568235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.568260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.568283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.568307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.568328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.568349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.568374] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.568398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.570394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.570411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.570425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.570439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.571983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.571998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.572012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.573599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.573615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.575489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.578426] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.578530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.578556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.578594] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.595241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.595267] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.595302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.628629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.628673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.628727] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.628752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.628793] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.647661] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.647679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.647700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.647716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.647734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.647749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.647764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.647780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.647797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.647814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.647829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.647845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.647859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.647872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.647899] [drm:intel_power_well_disable [i915]] disabling display
>[  748.647921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.647946] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.647962] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.648007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.648016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.648062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.648081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.648101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.648123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.648142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.648161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.648180] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.648200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.648219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.648238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.648256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.648260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.648279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.648283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.648302] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.648321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.648340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.648359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.648378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.648397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.648416] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.648434] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.648454] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.648524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.648554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.648620] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.648643] [drm:intel_power_well_enable [i915]] enabling display
>[  748.648666] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.648705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.648729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.648751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.648775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.648797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.648821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.648846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.648870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.648893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.648915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.648936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.648962] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.648984] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.651004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.651020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.651034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.651048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.653721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.653740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.653756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.655256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.655272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.657083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.660021] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.660093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.660112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.660138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.676834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.676860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.676896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.710226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.710269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.710322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.710345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.710391] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.729272] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.729290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.729310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.729327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.729345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.729360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.729374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.729390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.729408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.729424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.729440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.729455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.729513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.729535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.729578] [drm:intel_power_well_disable [i915]] disabling display
>[  748.729614] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.729647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.729673] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.729733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.729742] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.729784] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.729801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.729819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.729840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.729859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.729880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.729899] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.729919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.729938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.729958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.729977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.729982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.730001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.730005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.730024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.730043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.730063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.730082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.730101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.730120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.730140] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.730160] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.730180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.730200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.730221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.730267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.730282] [drm:intel_power_well_enable [i915]] enabling display
>[  748.730298] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.730328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.730354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.730371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.730386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.730401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.730415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.730432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.730448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.730462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.730504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.730526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.730550] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.730571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.732567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.732583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.732597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.732611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.734116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.734131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.734148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.735648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.735665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.737469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.740405] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.740439] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.740455] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.740512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.757183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.757209] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.757244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.790571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.790614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.790667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.790689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.790729] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.809584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.809603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.809623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.809640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.809658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.809673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.809687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.809704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.809722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.809738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.809754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.809769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.809783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.809797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.809823] [drm:intel_power_well_disable [i915]] disabling display
>[  748.809844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.809865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.809881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.809924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.809933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.809974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.809990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.810008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.810030] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.810049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.810068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.810088] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.810107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.810126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.810145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.810164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.810168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.810187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.810190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.810210] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.810229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.810248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.810267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.810293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.810310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.810325] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.810340] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.810353] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.810368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.810385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.810426] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.810439] [drm:intel_power_well_enable [i915]] enabling display
>[  748.810452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.810514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.810536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.810556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.810576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.810596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.810617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.810639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.810662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.810684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.810704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.810723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.810747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.810768] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.812762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.812779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.812796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.812814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.814320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.814338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.814355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.816982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.817000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.818841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.821785] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.821850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.821867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.821890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.838591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.838618] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.838655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.871999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.872046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.872091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.872113] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.872152] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.891016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.891035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.891055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.891072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.891089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.891105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.891119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.891135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.891153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.891169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.891185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.891200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.891215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.891228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.891254] [drm:intel_power_well_disable [i915]] disabling display
>[  748.891275] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.891296] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.891312] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.891347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.891356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.891397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.891412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.891430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.891449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.891464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.891522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.891549] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.891575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.891597] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.891622] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.891644] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.891651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.891673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.891680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.891703] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.891725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.891749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.891770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.891796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.891818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.891841] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.891863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.891886] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.891912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.891940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.891997] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.892020] [drm:intel_power_well_enable [i915]] enabling display
>[  748.892044] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.892084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.892106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.892129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.892150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.892172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.892201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.892224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.892247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.892270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.892288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.892308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.892331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.892353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.894358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.894375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.894390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.894405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.895914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.895929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.895942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.898518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.898538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.900350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.903278] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.903307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.903324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.903346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  748.920051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.920078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.920116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.953421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.953465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.953567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  748.953599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  748.953739] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  748.972173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  748.972192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  748.972212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.972229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.972246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.972261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.972276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.972292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  748.972309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.972326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.972341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.972356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.972370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.972384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.972411] [drm:intel_power_well_disable [i915]] disabling display
>[  748.972432] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  748.972453] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  748.972469] [drm:intel_power_well_disable [i915]] disabling always-on
>[  748.972561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  748.972576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  748.972646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  748.972672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  748.972699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  748.972729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  748.972754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  748.972780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  748.972806] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  748.972831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  748.972855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  748.972879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  748.972903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  748.972909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.972931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  748.972937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  748.972961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  748.972984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  748.973008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  748.973030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  748.973056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  748.973080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  748.973103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  748.973127] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  748.973148] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  748.973180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.973205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  748.973270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  748.973293] [drm:intel_power_well_enable [i915]] enabling display
>[  748.973314] [drm:hsw_set_power_well [i915]] Enabling power well
>[  748.973352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  748.973375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  748.973397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  748.973419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  748.973439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  748.973462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  748.973486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  748.973528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  748.973554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  748.973576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  748.973598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  748.973624] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  748.973648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  748.976742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  748.976761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  748.976778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.976794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  748.978303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  748.978321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  748.978338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  748.979839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  748.979856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  748.981664] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  748.984617] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  748.984674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  748.984691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  748.984713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.001416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.001443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.001480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.034802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.034845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.034898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.034921] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.034960] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.053828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.053847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.053867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.053884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.053902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.053921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.053940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.053960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.053981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.054002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.054022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.054043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.054061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.054080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.054107] [drm:intel_power_well_disable [i915]] disabling display
>[  749.054130] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.054154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.054171] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.054214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.054223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.054268] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.054288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.054307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.054330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.054349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.054368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.054387] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.054406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.054426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.054445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.054463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.054467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.054486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.054528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.054559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.054588] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.054614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.054641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.054668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.054694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.054719] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.054744] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.054768] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.054796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.054824] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.054895] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.054919] [drm:intel_power_well_enable [i915]] enabling display
>[  749.054944] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.054985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.055010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.055035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.055065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.055087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.055110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.055134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.055156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.055180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.055201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.055223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.055248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.055270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.058364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.058383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.058399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.058416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.059931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.059946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.059960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.061457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.061473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.063309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.066247] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.066318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.066342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.066362] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.083061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.083088] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.083126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.116446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.116489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.116592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.116625] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.116683] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.133535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.133554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.133574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.133591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.133609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.133624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.133639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.133655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.133673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.133689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.133704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.133720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.133734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.133748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.133774] [drm:intel_power_well_disable [i915]] disabling display
>[  749.133795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.133815] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.133831] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.133872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.133881] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.133929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.133947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.133966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.133987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.134005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.134024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.134042] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.134060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.134078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.134096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.134114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.134117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.134135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.134138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.134156] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.134174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.134192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.134210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.134228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.134245] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.134263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.134281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.134299] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.134317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.134337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.134379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.134394] [drm:intel_power_well_enable [i915]] enabling display
>[  749.134408] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.134436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.134454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.134472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.134490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.134539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.134566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.134594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.134621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.134647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.134670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.134693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.134720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.134745] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.136748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.136764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.136778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.136793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.138299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.138317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.138334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.140898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.140917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.142728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.145664] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.145737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.145754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.145775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.162480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.162524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.162562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.195867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.195910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.195963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.195986] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.196031] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.214928] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.214947] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.214967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.214984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.215002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.215017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.215031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.215047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.215065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.215081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.215097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.215112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.215127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.215140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.215167] [drm:intel_power_well_disable [i915]] disabling display
>[  749.215188] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.215209] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.215225] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.215267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.215276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.215317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.215332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.215350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.215370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.215386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.215406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.215425] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.215445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.215464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.215483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.215501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.215544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.215573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.215581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.215608] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.215634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.215659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.215690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.215716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.215738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.215761] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.215783] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.215806] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.215831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.215857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.215922] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.215944] [drm:intel_power_well_enable [i915]] enabling display
>[  749.215967] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.216004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.216027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.216049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.216071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.216092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.216115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.216139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.216161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.216184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.216205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.216227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.216251] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.216275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.218273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.218289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.218303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.218318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.220912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.220931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.220947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.223541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.223559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.225368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.228307] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.228378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.228398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.228424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.245119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.245145] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.245180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.278532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.278574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.278626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.278647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.278693] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.297564] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.297582] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.297604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.297624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.297645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.297665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.297684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.297703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.297725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.297746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.297766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.297786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.297805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.297824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.297851] [drm:intel_power_well_disable [i915]] disabling display
>[  749.297873] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.297898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.297914] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.297959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.297968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.298015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.298034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.298054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.298076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.298095] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.298115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.298134] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.298153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.298172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.298191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.298209] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.298213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.298232] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.298235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.298255] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.298274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.298293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.298311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.298331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.298349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.298368] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.298387] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.298406] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.298426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.298446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.298498] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.298550] [drm:intel_power_well_enable [i915]] enabling display
>[  749.298574] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.298614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.298637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.298660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.298681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.298704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.298725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.298751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.298776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.298799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.298822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.298842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.298868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.298890] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.300889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.300906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.300920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.300935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.303541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.303560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.303576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.305075] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.305091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.306900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.309837] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.309910] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.309926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.309948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.326652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.326677] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.326714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.360039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.360083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.360137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.360162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.360210] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.379065] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.379084] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.379105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.379122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.379139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.379154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.379169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.379185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.379202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.379218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.379234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.379249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.379263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.379277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.379303] [drm:intel_power_well_disable [i915]] disabling display
>[  749.379325] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.379345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.379361] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.379407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.379416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.379461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.379481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.379501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.379566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.379591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.379620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.379646] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.379671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.379695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.379720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.379742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.379750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.379772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.379778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.379803] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.379824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.379848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.379869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.379895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.379917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.379941] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.379962] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.379986] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.380013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.380038] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.380107] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.380130] [drm:intel_power_well_enable [i915]] enabling display
>[  749.380154] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.380194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.380217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.380241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.380262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.380285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.380307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.380333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.380358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.380383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.380404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.380426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.380458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.380480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.382491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.382507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.382552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.382578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.384086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.384101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.384114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.385617] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.385635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.387457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.390395] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.390468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.390487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.390551] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.407209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.407235] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.407273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.440596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.440639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.440692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.440715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.440753] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.459186] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.459205] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.459225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.459242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.459259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.459274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.459288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.459304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.459321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.459337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.459353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.459368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.459382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.459395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.459422] [drm:intel_power_well_disable [i915]] disabling display
>[  749.459443] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.459463] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.459479] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.459569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.459585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.459655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.459680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.459708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.459737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.459762] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.459788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.459815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.459840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.459865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.459889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.459912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.459918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.459941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.459947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.459970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.459993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.460016] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.460039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.460064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.460088] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.460111] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.460135] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.460156] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.460181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.460209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.460267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.460291] [drm:intel_power_well_enable [i915]] enabling display
>[  749.460315] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.460362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.460385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.460407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.460429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.460451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.460474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.460499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.460539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.460565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.460586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.460608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.460634] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.460658] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.462652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.462668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.462681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.462696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.464202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.464217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.464230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.465740] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.465758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.467570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.470508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.470578] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.470593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.470614] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.487322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.487348] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.487383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.520701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.520744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.520797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.520819] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.520865] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.539724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.539743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.539763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.539780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.539797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.539812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.539827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.539843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.539861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.539877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.539893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.539908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.539927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.539944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.539972] [drm:intel_power_well_disable [i915]] disabling display
>[  749.539994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.540019] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.540035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.540072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.540081] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.540126] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.540146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.540166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.540188] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.540207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.540234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.540252] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.540267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.540282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.540295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.540308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.540311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.540324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.540327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.540340] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.540353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.540365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.540378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.540393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.540410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.540427] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.540445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.540462] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.540480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.540499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.540589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.540612] [drm:intel_power_well_enable [i915]] enabling display
>[  749.540635] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.540674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.540699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.540721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.540744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.540765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.540789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.540815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.540840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.540864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.540884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.540905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.540930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.540953] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.542947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.542964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.542978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.542994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.544500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.544516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.544560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.546063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.546078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.547909] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.550857] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.550919] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.550936] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.550957] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.567661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.567687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.567722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.601041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.601084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.601137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.601159] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.601197] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.620093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.620112] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.620132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.620149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.620166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.620181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.620195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.620211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.620229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.620245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.620260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.620276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.620289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.620303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.620329] [drm:intel_power_well_disable [i915]] disabling display
>[  749.620351] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.620371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.620387] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.620422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.620431] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.620474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.620489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.620507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.620567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.620592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.620620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.620644] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.620670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.620693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.620718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.620739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.620747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.620769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.620775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.620799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.620821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.620844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.620865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.620891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.620913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.620936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.620958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.620981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.621008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.621036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.621105] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.621136] [drm:intel_power_well_enable [i915]] enabling display
>[  749.621158] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.621195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.621217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.621238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.621259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.621279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.621300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.621324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.621347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.621370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.621389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.621410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.621432] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.621454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.623450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.623467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.623485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.623503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.625042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.625058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.625072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.626594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.626610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.628416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.631342] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.631380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.631395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.631415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.648117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.648143] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.648178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.681510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.681568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.681620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.681641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.681686] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.700567] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.700586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.700606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.700623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.700641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.700656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.700671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.700687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.700705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.700722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.700737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.700753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.700767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.700781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.700808] [drm:intel_power_well_disable [i915]] disabling display
>[  749.700829] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.700850] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.700865] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.700907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.700916] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.700958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.700973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.700991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.701011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.701026] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.701042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.701058] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.701074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.701089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.701103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.701117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.701120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.701134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.701137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.701152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.701165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.701179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.701199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.701214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.701227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.701239] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.701252] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.701264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.701278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.701294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.701335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.701349] [drm:intel_power_well_enable [i915]] enabling display
>[  749.701363] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.701390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.701408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.701426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.701444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.701461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.701479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.701498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.701516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.701573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.701596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.701620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.701647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.701669] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.703666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.703685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.703702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.703720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.705227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.705243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.705257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.706756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.706773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.708581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.711503] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.711571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.711597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.711631] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.728280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.728306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.728341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.761723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.761797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.761889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.761927] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.762007] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.778815] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.778834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.778854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.778871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.778889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.778904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.778919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.778935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.778953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.778969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.778985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.779001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.779015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.779029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.779056] [drm:intel_power_well_disable [i915]] disabling display
>[  749.779077] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.779098] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.779114] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.779158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.779168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.779214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.779233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.779253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.779275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.779294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.779313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.779332] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.779351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.779370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.779389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.779408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.779412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.779430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.779434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.779453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.779472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.779491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.779510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.779529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.779590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.779615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.779642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.779665] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.779692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.779722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.779792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.779817] [drm:intel_power_well_enable [i915]] enabling display
>[  749.779838] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.779879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.779909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.779931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.779951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.779972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.779992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.780016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.780039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.780062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.780081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.780102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.780126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.780147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.782141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.782159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.782176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.782195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.783704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.783720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.783735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.785227] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.785243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.787053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.789987] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.790062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.790079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.790101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.806806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.806832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.806868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.840194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.840238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.840291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.840314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.840360] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.859233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.859252] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.859272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.859289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.859307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.859322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.859336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.859352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.859369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.859386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.859401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.859417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.859431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.859445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.859471] [drm:intel_power_well_disable [i915]] disabling display
>[  749.859492] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.859513] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.859529] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.859634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.859649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.859704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.859721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.859739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.859759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.859775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.859792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.859809] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.859824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.859840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.859855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.859869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.859872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.859886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.859890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.859904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.859919] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.859933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.859957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.859973] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.859986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.859999] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.860012] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.860024] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.860040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.860056] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.860099] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.860112] [drm:intel_power_well_enable [i915]] enabling display
>[  749.860125] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.860150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.860164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.860178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.860191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.860204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.860218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.860233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.860247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.860261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.860274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.860287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.860303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.860317] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.862298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.862314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.862328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.862343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.863851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.863866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.863880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.865374] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.865390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.867200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.870133] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.870210] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.870228] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.870254] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.886952] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.886978] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.887015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.920351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.920395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.920447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  749.920468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  749.920513] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  749.939219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  749.939238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  749.939258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.939275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.939292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.939307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.939327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.939346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.939367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.939388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.939409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.939429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.939448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.939465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.939493] [drm:intel_power_well_disable [i915]] disabling display
>[  749.939515] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  749.939539] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.939592] [drm:intel_power_well_disable [i915]] disabling always-on
>[  749.939667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  749.939682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  749.939753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  749.939777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  749.939804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  749.939833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  749.939856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  749.939888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  749.939910] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  749.939933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  749.939953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  749.939975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  749.939994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  749.940000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.940020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  749.940025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  749.940046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  749.940066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  749.940087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  749.940106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  749.940129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  749.940148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  749.940169] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  749.940188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  749.940209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  749.940230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  749.940254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  749.940318] [drm:intel_power_well_enable [i915]] enabling always-on
>[  749.940340] [drm:intel_power_well_enable [i915]] enabling display
>[  749.940362] [drm:hsw_set_power_well [i915]] Enabling power well
>[  749.940399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  749.940420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  749.940441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  749.940461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  749.940482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  749.940502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  749.940526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  749.940571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  749.940595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  749.940615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  749.940638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  749.940661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  749.940684] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  749.942677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  749.942693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  749.942707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.942721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  749.944226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  749.944241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  749.944254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  749.945752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  749.945767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  749.947578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  749.950515] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  749.950626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  749.950651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  749.950687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  749.967329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  749.967355] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  749.967390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.000719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.000763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.000816] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.000839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.000885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.019787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.019805] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.019826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.019843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.019861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.019876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.019891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.019908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.019926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.019942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.019958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.019974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.019988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.020007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.020034] [drm:intel_power_well_disable [i915]] disabling display
>[  750.020056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.020081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.020097] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.020143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.020152] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  750.020198] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.020218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.020237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.020259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.020278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.020298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.020317] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  750.020336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  750.020356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.020374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.020393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.020397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.020415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.020419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.020438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.020457] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.020476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.020495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  750.020514] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.020533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.020595] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  750.020621] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  750.020647] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  750.020675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.020704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  750.020781] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.020804] [drm:intel_power_well_enable [i915]] enabling display
>[  750.020824] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.020865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.020886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.020908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.020928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.020949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.020970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.020993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.021016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.021039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.021058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.021079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.021104] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  750.021125] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.023137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.023154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.023168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.023183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.024695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.024710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.024724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.026218] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.026234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.028061] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.031010] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  750.031069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.031085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  750.031106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.047813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.047839] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.047874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.081200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.081243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.081296] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.081318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.081364] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.100225] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.100244] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.100264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.100281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.100299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.100318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.100337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.100356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.100378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.100398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.100419] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.100439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.100458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.100474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.100502] [drm:intel_power_well_disable [i915]] disabling display
>[  750.100524] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.100549] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.100609] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.100686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.100700] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  750.100764] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.100786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.100811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.100838] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.100858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.100881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.100903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  750.100925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  750.100946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.100966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.100985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.100991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.101010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.101016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.101037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.101056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.101076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.101095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  750.101118] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.101137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.101158] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  750.101177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  750.101197] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  750.101218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.101242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  750.101305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.101327] [drm:intel_power_well_enable [i915]] enabling display
>[  750.101348] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.101384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.101405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.101426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.101446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.101467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.101488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.101511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.101534] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.101575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.101596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.101618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.101643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  750.101665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.103662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.103678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.103692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.103707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.105211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.105226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.105240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.106738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.106754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.108578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.111515] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  750.111616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.111645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  750.111681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.128329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.128356] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.128394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.161708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.161751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.161805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.161830] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.161878] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.180748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.180767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.180787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.180804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.180821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.180836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.180851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.180867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.180885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.180900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.180916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.180931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.180945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.180958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.180985] [drm:intel_power_well_disable [i915]] disabling display
>[  750.181006] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.181027] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.181042] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.181078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.181087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  750.181128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.181144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.181161] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.181180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.181195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.181211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.181227] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  750.181243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  750.181258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.181272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.181286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.181290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.181304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.181307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.181326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.181345] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.181364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.181383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  750.181402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.181421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.181441] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  750.181459] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  750.181479] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  750.181505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.181523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  750.181603] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.181626] [drm:intel_power_well_enable [i915]] enabling display
>[  750.181649] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.181688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.181712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.181733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.181755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.181776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.181799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.181826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.181851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.181876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.181895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.181917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.181943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  750.181964] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.183963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.183979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.183994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.184009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.185516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.185531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.185545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.187086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.187101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.188925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.191867] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  750.191934] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.191951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  750.191973] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.208676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.208702] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.208738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.242054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.242098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.242151] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.242176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.242223] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.261094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.261115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.261137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.261157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.261178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.261198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.261217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.261236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.261258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.261278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.261299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.261319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.261338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.261357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.261384] [drm:intel_power_well_disable [i915]] disabling display
>[  750.261406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.261431] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.261447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.261484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.261494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  750.261539] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.261559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.261622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.261654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.261678] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.261707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.261733] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  750.261759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  750.261783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.261807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.261829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.261836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.261859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.261865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.261890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.261912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.261935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.261957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  750.261983] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.262005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.262029] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  750.262050] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  750.262074] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  750.262098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.262124] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  750.262194] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.262219] [drm:intel_power_well_enable [i915]] enabling display
>[  750.262243] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.262285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.262311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.262342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.262364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.262385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.262405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.262430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.262453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.262476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.262495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.262516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.262540] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  750.262561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.264590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.264606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.264621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.264635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.266154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.266172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.266190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.267695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.267711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.269522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.272459] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  750.272531] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.272548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  750.272623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.289282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.289308] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.289343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.322658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.322703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.322756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.322779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.322825] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.341707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.341725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.341746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.341762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.341780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.341796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.341814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.341834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.341855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.341876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.341896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.341917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.341936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.341955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.341982] [drm:intel_power_well_disable [i915]] disabling display
>[  750.342004] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.342029] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.342045] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.342088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  750.342097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  750.342143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.342162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.342182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.342204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.342223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.342243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.342262] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  750.342281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  750.342301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.342320] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.342338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.342350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.342367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.342370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.342386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.342400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.342414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.342428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  750.342443] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.342456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.342470] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  750.342483] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  750.342495] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  750.342511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.342527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  750.342600] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.342625] [drm:intel_power_well_enable [i915]] enabling display
>[  750.342648] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.342685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.342707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.342730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.342751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.342773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.342794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.342819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.342843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.342868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.342888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.342909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.342935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  750.342957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.344954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.344971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.344985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.344999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.346512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.346529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.346546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.348077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.348094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.349930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.352867] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  750.352940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.352957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  750.352979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.369681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.369708] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.369745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.403091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.403137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  750.403160] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  750.403197] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  750.422060] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  750.422079] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  750.422099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.422115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.422133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.422148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.422162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.422178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.422196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.422212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.422232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.422253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.422272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.422291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.422319] [drm:intel_power_well_disable [i915]] disabling display
>[  750.422342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  750.422367] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  750.422384] [drm:intel_power_well_disable [i915]] disabling always-on
>[  750.424918] [IGT] kms_flip: exiting, ret=0
>[  750.441070] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  750.441091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  750.441112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  750.441135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  750.441155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  750.441176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  750.441196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  750.441215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  750.441235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  750.441255] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  750.441272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  750.441276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.441295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  750.441299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.441319] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  750.441339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  750.441358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  750.441378] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  750.441398] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  750.441417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  750.441437] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  750.441456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  750.441483] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  750.441502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  750.441522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  750.441586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  750.441602] [drm:intel_power_well_enable [i915]] enabling display
>[  750.441617] [drm:hsw_set_power_well [i915]] Enabling power well
>[  750.441648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  750.441667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  750.441685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  750.441704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  750.441722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  750.441740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  750.441760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  750.441780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  750.441799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.441817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  750.441835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  750.441854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  750.441873] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  750.443882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  750.443899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  750.443916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.443934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  750.445452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  750.445466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  750.445480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  750.446983] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  750.446997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  750.448816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  750.451861] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  750.451925] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  750.451940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  750.451964] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  750.452009] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  750.452026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  750.468675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  750.468699] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  750.468736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  750.468861] Console: switching to colour frame buffer device 240x75
>[  750.599902] Console: switching to colour dummy device 80x25
>[  750.599993] [IGT] kms_flip: executing
>[  750.611078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  750.611103] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  750.612651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  750.612671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  750.614640] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  750.614647] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  750.616640] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  750.616660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  750.618642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  750.618648] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  750.618652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  750.618670] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  750.618693] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  750.619722] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  750.620623] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  750.620648] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  750.620663] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  750.620677] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  750.621659] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  750.621675] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  750.622740] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  750.622742] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  750.622823] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  750.622826] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  750.622830] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  750.622832] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  750.622836] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  750.622838] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  750.622845] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  750.622848] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.622850] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.622853] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.622855] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  750.622858] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  750.622860] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  750.622862] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  750.622865] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.622867] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.622870] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  750.622872] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  750.622875] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  750.622877] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  750.622879] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  750.622882] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  750.622884] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  750.622887] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  750.622889] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  750.622891] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  750.622894] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  750.622896] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  750.622899] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  750.622901] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  750.622904] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  750.622906] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  750.622908] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  750.622911] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  750.622913] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  750.622916] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  750.622918] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  750.622948] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  750.622965] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  750.624632] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  750.624649] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  750.626648] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  750.626654] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  750.628641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  750.628661] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  750.630648] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  750.630653] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  750.630657] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  750.631899] [IGT] kms_flip: starting subtest 2x-plain-flip-interruptible
>[  750.633215] [IGT] kms_flip: exiting, ret=77
>[  750.668947] Console: switching to colour frame buffer device 240x75
>[  750.802480] Console: switching to colour dummy device 80x25
>[  750.802571] [IGT] kms_flip: executing
>[  750.814077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  750.814107] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  750.815665] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  750.815685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  750.817652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  750.817659] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  750.819654] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  750.819674] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  750.821655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  750.821661] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  750.821666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  750.821682] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  750.821706] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  750.822741] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  750.823638] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  750.823657] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  750.823672] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  750.823686] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  750.824676] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  750.824701] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  750.825755] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  750.825758] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  750.825836] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  750.825839] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  750.825843] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  750.825845] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  750.825849] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  750.825851] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  750.825858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  750.825861] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  750.825863] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.825866] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.825868] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  750.825871] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  750.825873] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  750.825876] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  750.825878] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.825881] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  750.825883] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  750.825885] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  750.825888] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  750.825890] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  750.825893] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  750.825895] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  750.825898] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  750.825900] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  750.825902] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  750.825905] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  750.825907] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  750.825910] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  750.825912] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  750.825915] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  750.825917] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  750.825919] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  750.825922] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  750.825924] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  750.825927] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  750.825929] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  750.825931] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  750.825961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  750.825979] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  750.827652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  750.827672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  750.829729] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  750.829734] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  750.831652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  750.831674] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  750.833657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  750.833662] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  750.833666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  750.833886] [IGT] kms_flip: starting subtest 2x-vblank-vs-dpms-suspend
>[  750.836172] [IGT] kms_flip: exiting, ret=77
>[  750.869108] Console: switching to colour frame buffer device 240x75
>[  751.004722] Console: switching to colour dummy device 80x25
>[  751.004816] [IGT] kms_flip: executing
>[  751.025844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  751.025873] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  751.027663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  751.027684] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  751.029669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  751.029675] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  751.031664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  751.031685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  751.033710] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  751.033716] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  751.033720] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  751.033736] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  751.033759] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  751.034785] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  751.035700] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  751.035725] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  751.035741] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  751.035755] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  751.036750] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  751.036768] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  751.037822] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  751.037825] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  751.037906] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  751.037908] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  751.037912] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  751.037914] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  751.037918] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  751.037920] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  751.037927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  751.037930] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  751.037932] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  751.037935] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  751.037937] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  751.037940] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  751.037942] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  751.037945] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  751.037947] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  751.037950] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  751.037952] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  751.037954] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  751.037957] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  751.037959] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  751.037962] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  751.037964] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  751.037967] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  751.037969] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  751.037971] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  751.037974] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  751.037976] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  751.037979] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  751.037981] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  751.037984] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  751.037986] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  751.037988] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  751.037991] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  751.037993] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  751.037996] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  751.037998] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  751.038000] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  751.038030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  751.038048] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  751.039635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  751.039652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  751.041666] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  751.041672] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  751.043665] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  751.043684] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  751.045664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  751.045670] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  751.045674] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  751.045889] [IGT] kms_flip: starting subtest nonexisting-fb
>[  751.046297] [drm:drm_mode_addfb2] [FB:77]
>[  751.046319] [drm:drm_mode_addfb2] [FB:79]
>[  751.088580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.088682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  751.102568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  751.102593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  751.102684] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  751.121550] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  751.121573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  751.121590] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  751.121610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  751.121673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  751.121699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  751.121719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  751.121739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  751.121759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  751.121781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  751.121802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  751.121824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  751.121845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.121864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  751.121884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  751.121912] [drm:intel_power_well_disable [i915]] disabling display
>[  751.121935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  751.121960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  751.121979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  751.122027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.122096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  751.122155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.122167] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  751.122212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  751.122232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  751.122259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  751.122279] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  751.122294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  751.122310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  751.122326] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  751.122341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  751.122355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  751.122368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  751.122381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  751.122385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  751.122398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  751.122401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  751.122414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  751.122427] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  751.122440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  751.122452] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  751.122467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  751.122481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  751.122494] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  751.122507] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  751.122519] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  751.122535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  751.122551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  751.125051] [drm:intel_power_well_enable [i915]] enabling always-on
>[  751.125065] [drm:intel_power_well_enable [i915]] enabling display
>[  751.125078] [drm:hsw_set_power_well [i915]] Enabling power well
>[  751.125104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  751.125120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  751.125134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  751.125147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  751.125160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  751.125174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  751.125190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  751.125204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  751.125218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.125231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  751.125243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  751.125259] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  751.125274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  751.127249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  751.127266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  751.127280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  751.127295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  751.128802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  751.128820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  751.128837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  751.130331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  751.130348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  751.132153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  751.135090] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  751.135162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  751.135179] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  751.135202] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  751.135242] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  751.135262] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  751.151896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  751.151918] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  751.151952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.168592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.168983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.168998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.169980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.169985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.170986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.170990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.171964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.171968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.172961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.172965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.173981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.173986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.174990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.174994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.175972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.175996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.176986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.176990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.177992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.177996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.178995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.178999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.179967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.179971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.180961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.180965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.181983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.181987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.182980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.182985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.183961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.183998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.184982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.184986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.185986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.185990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.186965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.186969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.187983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.187987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.188982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.188986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.189965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.189969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.190990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.190993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.191962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.191966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.192974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.192998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.193987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.193991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.194961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.194965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.195986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.195990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.196985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.196989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.197960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.197965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.198980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.198984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.199986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.199990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.200959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.200996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.201975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.201979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.202972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.202976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.203960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.203998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.204976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.204980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.205991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.205995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.206990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.206994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.207977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.207981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.208985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.208988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.209984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.209988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.210978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.210982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.211960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.211996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.212984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.212988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.213973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.213998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.214962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.214966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.215978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.215982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.216967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.216971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.217971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.217975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.218993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.218997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.219968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.219972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.220976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.220980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.221976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.221980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.222993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.222996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.223975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.223979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.224978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.224982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.225991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.225995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.226974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.226978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.227974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.227978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.228988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.228992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.229964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.229967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.230988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.230992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.231967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.231971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.232978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.232982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.233963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.233966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.234987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.234991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.235973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.235976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.236988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.236992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.237987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.237991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.238965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.238970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.239995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.239998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.240974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.240978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.241972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.241996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.242964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.242968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.243973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.243977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.244985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.244989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.245992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.245996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.246960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.246964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.247976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.247980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.248975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.248999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.249975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.249979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.250990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.250994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.251968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.251972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.252972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.252976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.253994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.253998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.254967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.254971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.255973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.255977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.256970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.256974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.257980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.257984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.258992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.258996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.259980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.259984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.260960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.260997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.261979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.261983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.262991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.262996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.263960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.263998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.264969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.264973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.265990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.265995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.266969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.266973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.267977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.267981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.268963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.268967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.269972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.269976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.270993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.270997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.271963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.271998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.272978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.272983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.273986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.273991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.274976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.274980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.275988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.275992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.276975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.276999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.277990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.277994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.278981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.278985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.279962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.279966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.280988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.280992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.281973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.281977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.282977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.282981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.283974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.283978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.284975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.284978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.285969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.285972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.286969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.286973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.287973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.287977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.288960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.288996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.289977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.289982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.290980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.290984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.291994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.291998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.292970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.292974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.293985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.293989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.294959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.294996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.295963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.295967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.296995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.296999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.297981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.297985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.298989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.298993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.299990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.299994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.300991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.300995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.301958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.301996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.302965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.302969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.303983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.303987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.304979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.304983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.305962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.305966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.306980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.306984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.307995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.307999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.308971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.308996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.309980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.309984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.310977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.310981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.311971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.311975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.312969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.312973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.313971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.313975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.314967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.314971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.315972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.315976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.316985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.316989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.317962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.317965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.318968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.318973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.319978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.319982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.320987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.320991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.321963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.321967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.322986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.322990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.323961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.323965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.324963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.324998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.325993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.325997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.326960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.326998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.327970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.327974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.328986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.328990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.329973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.329977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.330960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.330963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.331977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.331981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.332986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.332990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.333993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.333997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.334966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.334970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.335993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.335997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.336974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.336977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.337991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.337995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.338988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.338993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.339993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.339997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.340994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.340998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.341972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.341976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.342963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.342998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.343979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.343984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.344976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.344980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.345962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.345997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.346988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.346992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.347977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.347981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.348991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.348995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.349984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.349989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.350984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.350988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.351986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.351990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.352963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.352967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.353993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.353997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.354751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.354755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.355992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.355994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.356980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.356984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.357992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.357996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.358975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.358979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.359973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.359978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.360980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.360984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.361966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.361970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.362978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.362983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.363985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.363989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.364989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.364993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.365977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.365981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.366971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.366975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.367986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.367990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.368968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.368972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.369976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.369980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.370986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.370990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.371992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.371996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.372972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.372977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.373972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.373975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.374974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.374978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.375982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.375987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.376985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.376988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.377972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.377976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.378971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.378975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.379991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.379995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.380977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.380982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.381987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.381990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.382964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.382968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.383976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.383980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.384985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.384989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.385970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.385974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.386977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.386981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.387978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.387982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.388966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.388970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.389980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.389984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.390985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.390988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.391962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.391966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.392964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.392968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.393985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.393989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.394986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.394989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.395984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.395988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.396962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.396966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.397972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.397997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.398959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.398963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.399964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.399999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.400973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.400977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.401974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.401998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.402988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.402992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.403967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.403971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.404983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.404987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.405982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.405986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.406991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.406996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.407963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.407967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.408974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.408978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.409982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.409986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.410960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.410996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.411985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.411989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.412961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.412965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.413960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.413996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.414963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.414967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.415982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.415986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.416980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.416984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.417961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.417996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.418966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.418970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.419982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.419986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.420994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.420999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.421964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.421968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.422971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.422975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.423988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.423992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.424973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.424977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.425961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.425965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.426964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.426969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.427976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.427980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.428993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.428997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.429986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.429990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.430974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.430977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.431964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.431969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.432973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.432977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.433974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.433978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.434971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.434975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.435995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.435999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.436973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.436998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.437989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.437993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.438980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.438984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.439973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.439977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.440991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.440995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.441980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.441985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.442986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.442990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.443978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.443982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.444962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.444966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.445982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.445986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.446970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.446974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.447992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.447996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.448962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.448966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.449982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.449987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.450971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.450975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.451975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.451979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.452968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.452972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.453976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.453999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.454962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.454966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.455982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.455986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.456963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.456967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.457992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.457996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.458979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.458983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.459972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.459996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.460960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.460965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.461960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.461964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.462966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.462970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.463984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.463988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.464983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.464987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.465989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.465993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.466959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.466995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.467976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.467980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.468968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.468972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.469993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.469997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.470983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.470987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.471961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.471998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.472961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.472997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.473972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.473976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.474991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.474995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.475978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.475982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.476982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.476986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.477965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.477969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.478982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.478986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.479971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.479975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.480955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.480958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.481975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.481979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.482987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.482991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.483961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.483965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.484964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.484968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.485981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.485985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.486972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.486976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.487989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.487994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.488974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.488978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.489960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.489996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.490982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.490986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.491964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.491968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.492976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.492980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.493971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.493975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.494982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.494986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.495986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.495990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.496984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.496988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.497964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.497968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.498985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.498989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.499988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.499991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.500974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.500978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.501973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.501977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.502979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.502983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.503964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.503999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.504973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.504997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.505988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.505992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.506975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.506979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.507994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.507998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.508981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.508985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.509961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.509965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.510995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.510999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.511992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.511996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.512977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.512981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.513962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.513996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.514994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.514998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.515972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.515976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.516986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.516990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.517964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.517968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.518981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.518985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.519971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.519975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.520986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.520990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.521975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.521978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.522980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.522984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.523989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.523993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.524987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.524991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.525977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.525981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.526966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.526970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.527981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.527985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.528992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.528996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.529972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.529976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.530990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.530994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.531981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.531985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.532971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.532975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.533974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.533998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.534984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.534988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.535964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.535999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.536984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.536988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.537973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.537977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.538987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.538991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.539989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.539993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.540982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.540986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.541966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.541971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.542961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.542996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.543976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.543980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.544988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.544992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.545995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.545999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.546988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.546993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.547969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.547973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.548986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.548990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.549973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.549977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.550976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.550999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.551990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.551994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.552959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.552964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.553974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.553978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.554982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.554986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.555970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.555974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.556967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.556971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.557967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.557971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.558994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.558998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.559988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.559992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.560977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.560982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.561973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.561977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.562973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.562996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.563982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.563986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.564964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.564968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.565988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.565993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.566975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.566979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.567990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.567994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.568988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.568992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.569992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.569996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.570980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.570984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.571986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.571990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.572978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.572982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.573974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.573997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.574960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.574996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.575980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.575984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.576995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.576999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.577980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.577984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.578970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.578974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.579981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.579985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.580960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.580997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.581977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.581981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.582976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.582980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.583964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.583968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.584976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.584980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.585974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.585998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.586971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.586976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.587975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.587980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.588993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.588997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.589994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.589998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.590965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.590999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.591973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.591997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.592982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.592985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.593962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.593998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.594991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.594995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.595969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.595973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.596963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.596967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.597972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.597996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.598977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.598981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.599963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.599967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.600975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.600979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.601963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.601967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.602984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.602988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.603986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.603990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.604980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.604984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.605966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.605970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.606994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.606998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.607976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.607980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.608983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.608987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.609987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.609991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.610994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.610998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.611969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.611973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.612962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.612996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.613973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.613977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.614983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.614987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.615991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.615995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.616991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.616996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.617988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.617992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.618964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.618999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.619981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.619985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.620993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.620997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.621985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.621989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.622980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.622983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.623990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.623995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.624989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.624993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.625971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.625975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.626993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.626997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.627982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.627987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.628984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.628988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.629963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.629999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.630973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.630977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.631993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.631997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.632979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.632984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.633973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.633997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.634988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.634992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.635963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.635998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.636964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.636968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.637966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.637999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.638980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.638983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.639987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.639991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.640972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.640976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.641993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.641997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.642984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.642988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.643994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.643997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.644983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.644987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.645977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.645981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.646961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.646965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.647988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.647992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.648972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.648975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.649992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.649996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.650977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.650981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.651974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.651997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.652963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.652967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.653995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.653999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.654969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.654973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.655986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.655990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.656979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.656983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.657967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.657971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.658983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.658987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.659967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.659971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.660984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.660988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.661990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.661994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.662995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.662999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.663962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.663999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.664964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.664968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.665968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.665972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.666993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.666997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.667963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.667997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.668613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.668737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  751.669014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  751.669046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  751.669092] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  751.687819] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  751.687842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  751.687861] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  751.687882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  751.687901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  751.687921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  751.687939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  751.687958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  751.687976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  751.687996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  751.688016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  751.688035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  751.688054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.688072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  751.688090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  751.688118] [drm:intel_power_well_disable [i915]] disabling display
>[  751.688139] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  751.688163] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  751.688181] [drm:intel_power_well_disable [i915]] disabling always-on
>[  751.688339] [drm:drm_mode_addfb2] [FB:77]
>[  751.688361] [drm:drm_mode_addfb2] [FB:78]
>[  751.715608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  751.715729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.715807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  751.715857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.715868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  751.715915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  751.715933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  751.715952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  751.715970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  751.715985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  751.716000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  751.716017] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  751.716032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  751.716047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  751.716061] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  751.716074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  751.716078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  751.716091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  751.716095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  751.716109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  751.716122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  751.716135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  751.716148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  751.716163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  751.716177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  751.716190] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  751.716203] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  751.716215] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  751.716231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  751.716248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  751.718750] [drm:intel_power_well_enable [i915]] enabling always-on
>[  751.718764] [drm:intel_power_well_enable [i915]] enabling display
>[  751.718777] [drm:hsw_set_power_well [i915]] Enabling power well
>[  751.718806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  751.718822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  751.718838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  751.718852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  751.718865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  751.718880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  751.718897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  751.718912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  751.718930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.718947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  751.718965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  751.718985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  751.719003] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  751.720981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  751.720997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  751.721012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  751.721027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  751.722528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  751.722543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  751.722557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  751.724050] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  751.724066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  751.725867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  751.728765] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  751.728825] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  751.728840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  751.728865] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  751.745547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  751.745569] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  751.745602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  751.762257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.762993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.762995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.763986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.763990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.764975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.764979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.765985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.765990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.766965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.766969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.767988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.767992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.768970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.768974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.769972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.769976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.770971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.770975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.771990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.771994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.772962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.772966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.773982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.773986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.774991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.774994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.775977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.775981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.776961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.776965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.777979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.777983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.778986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.778990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.779960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.779964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.780992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.780996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.781966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.781971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.782965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.782969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.783979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.783983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.784976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.784980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.785963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.785967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.786992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.786997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.787968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.787972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.788969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.788973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.789982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.789986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.790973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.790977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.791973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.791977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.792970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.792974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.793971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.793975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.794987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.794991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.795959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.795963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.796979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.796983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.797992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.797996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.798981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.798985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.799978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.799982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.800994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.800998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.801970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.801974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.802972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.802976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.803989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.803993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.804982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.804986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.805958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.805996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.806992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.806997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.807962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.807966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.808987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.808991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.809978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.809982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.810963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.810999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.811973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.811977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.812975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.812979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.813967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.813971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.814965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.814968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.815981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.815984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.816966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.816970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.817988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.817992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.818977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.818980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.819976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.819980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.820995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.820999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.821979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.821983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.822978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.822982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.823961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.823965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.824989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.824993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.825978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.825982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.826964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.826968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.827980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.827984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.828978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.828982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.829972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.829997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.830981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.830985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.831991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.831996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.832975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.832979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.833965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.833969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.834995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.834999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.835967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.835971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.836973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.836977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.837990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.837994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.838976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.838980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.839979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.839983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.840959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.840996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.841973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.841977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.842995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.842999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.843958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.843963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.844981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.844985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.845963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.845967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.846992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.846996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.847976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.847979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.848995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.848999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.849992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.849996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.850966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.850970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.851973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.851977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.852995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.852999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.853993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.853997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.854991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.854995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.855995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.855998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.856990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.856994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.857981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.857985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.858992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.858996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.859975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.859979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.860981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.860985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.861977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.861981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.862986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.862990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.863991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.863994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.864971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.864975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.865964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.865999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.866976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.866980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.867975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.867978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.868971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.868975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.869970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.869974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.870959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.870997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.871965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.871969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.872972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.872976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.873975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.873979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.874994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.874998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.875986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.875990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.876995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.876999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.877968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.877972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.878963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.878997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.879984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.879988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.880965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.880969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.881966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.881970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.882988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.882992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.883983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.883987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.884992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.884996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.885973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.885977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.886975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.886979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.887967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.887970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.888964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.888998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.889980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.889984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.890970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.890974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.891978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.891982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.892982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.892986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.893982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.893986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.894968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.894972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.895962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.895966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.896959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.896997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.897975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.897979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.898962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.898965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.899972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.899996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.900982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.900986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.901993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.901997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.902965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.902969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.903981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.903985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.904964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.904967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.905992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.905996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.906971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.906996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.907987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.907991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.908994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.908998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.909977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.909981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.910993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.910997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.911977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.911981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.912994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.912998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.913975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.913979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.914985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.914989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.915977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.915981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.916981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.916985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.917992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.917996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.918991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.918995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.919970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.919974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.920995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.920999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.921991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.921995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.922978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.922982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.923991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.923996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.924990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.924993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.925982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.925986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.926992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.926995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.927990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.927994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.928981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.928985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.929984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.929988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.930973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.930978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.931988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.931992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.932970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.932974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.933995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.933999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.934985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.934989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.935981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.935985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.936960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.936964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.937991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.937995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.938973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.938977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.939981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.939985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.940986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.940990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.941974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.941978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.942966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.942971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.943985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.943989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.944967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.944971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.945972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.945977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.946961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.946998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.947983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.947987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.948977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.948981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.949986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.949991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.950986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.950990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.951967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.951970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.952992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.952995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.953985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.953989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.954813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.954818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.955993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.955996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.956961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.956996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.957975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.957979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.958977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.958981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.959994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.959997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.960987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.960992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.961973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.961977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.962962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.962966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.963962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.963966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.964995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.964999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.965967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.965971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.966982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.966986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.967991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.967995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.968980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.968984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.969975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.969998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.970986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.970989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.971972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.971976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.972994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.972998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.973967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.973971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.974980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.974985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.975963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.975967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.976989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.976993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.977975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.977979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.978988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.978992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.979978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.979982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.980979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.980983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.981967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.981972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.982963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.982967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.983977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.983981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.984960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.984964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.985985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.985989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.986985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.986989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.987962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.987965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.988980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.988984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.989974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.989999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.990978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.990982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.991964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.991967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.992985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.992988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.993985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.993989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.994995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.994999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.995974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.995978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.996988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.996992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.997981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.997985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.998963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.998998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  751.999981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  751.999985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.000983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.000987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.001977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.001981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.002991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.002994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.003975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.003979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.004985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.004989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.005976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.005980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.006988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.006992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.007995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.007998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.008963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.008998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.009978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.009982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.010971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.010995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.011962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.011999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.012983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.012987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.013963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.013967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.014982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.014986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.015991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.015995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.016963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.016967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.017982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.017986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.018988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.018992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.019993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.019997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.020980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.020984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.021980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.021984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.022961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.022965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.023981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.023985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.024976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.024980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.025960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.025996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.026981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.026985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.027962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.027966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.028976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.028980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.029975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.029978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.030962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.030995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.031991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.031995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.032962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.032966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.033968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.033972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.034983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.034986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.035985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.035989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.036962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.036998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.037979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.037982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.038973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.038977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.039989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.039993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.040982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.040986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.041970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.041974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.042975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.042999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.043984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.043988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.044962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.044996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.045972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.045976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.046988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.046992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.047991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.047995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.048980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.048984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.049975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.049979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.050990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.050994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.051972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.051976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.052978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.052982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.053959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.053963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.054962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.054966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.055986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.055989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.056962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.056966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.057985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.057989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.058966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.058970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.059993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.059998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.060988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.060992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.061974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.061978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.062978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.062982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.063976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.063980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.064978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.064982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.065985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.065990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.066989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.066993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.067963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.067999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.068985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.068990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.069974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.069978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.070937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.070941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.071969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.071973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.072990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.072994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.073978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.073982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.074989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.074994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.075970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.075974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.076974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.076978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.077989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.077993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.078966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.078970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.079989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.079993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.080985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.080989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.081990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.081993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.082968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.082972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.083978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.083982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.084992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.084996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.085966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.085970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.086984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.086988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.087985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.087989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.088990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.088994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.089980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.089984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.090971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.090975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.091978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.091982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.092966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.092970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.093992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.093996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.094962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.094967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.095962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.095967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.096974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.096978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.097975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.097979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.098961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.098997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.099963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.099967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.100978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.100981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.101984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.101989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.102965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.102969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.103978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.103982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.104981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.104984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.105995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.105999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.106974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.106978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.107978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.107982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.108984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.108988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.109987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.109991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.110966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.110970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.111990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.111994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.112984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.112988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.113989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.113993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.114972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.114976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.115969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.115973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.116980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.116984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.117973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.117977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.118973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.118997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.119978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.119982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.120963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.120997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.121972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.121976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.122985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.122989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.123990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.123994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.124995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.124999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.125991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.125995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.126989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.126994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.127969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.127973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.128993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.128996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.129993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.129997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.130962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.130966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.131950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.131954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.132973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.132977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.133962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.133966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.134961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.134965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.135980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.135983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.136989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.136993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.137970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.137974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.138978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.138982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.139990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.139994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.140991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.140995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.141993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.141997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.142979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.142983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.143984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.143988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.144964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.144999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.145976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.145980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.146994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.146999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.147971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.147974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.148970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.148974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.149983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.149987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.150973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.150978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.151962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.151999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.152970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.152974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.153994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.153998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.154961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.154998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.155992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.155996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.156985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.156989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.157973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.157977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.158963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.158999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.159974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.159978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.160973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.160977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.161962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.161998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.162971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.162975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.163995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.163999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.164994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.164998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.165967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.165971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.166994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.166998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.167985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.167989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.168965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.168969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.169988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.169992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.170987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.170991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.171995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.171999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.172964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.172998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.173986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.173990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.174959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.174996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.175964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.175968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.176985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.176989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.177994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.177998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.178990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.178994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.179966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.179970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.180978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.180982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.181981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.181985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.182984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.182989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.183995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.183999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.184984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.184988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.185972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.185976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.186987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.186991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.187968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.187972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.188984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.188989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.189991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.189995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.190965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.190969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.191982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.191986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.192962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.192999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.193962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.193997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.194975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.195986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.195990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.196960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.196996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.197962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.197966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.198987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.198990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.199983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.199987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.200963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.200967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.201982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.201986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.202975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.202979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.203961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.203997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.204977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.204981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.205964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.205999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.206976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.206980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.207962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.207965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.208975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.208979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.209992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.209996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.210988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.210992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.211967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.211971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.212985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.212989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.213979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.213983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.214964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.214968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.215975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.215979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.216963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.216967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.217960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.217998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.218975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.218978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.219993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.219997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.220989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.220993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.221971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.221975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.222991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.222995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.223977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.223981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.224974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.224978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.225992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.225996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.226976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.226980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.227991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.227995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.228976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.228980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.229962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.229998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.230975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.230979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.231975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.231979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.232970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.232974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.233926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.233968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.234903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.234998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.235991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.235995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.236774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.236965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.237936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.237979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.238962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.238997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.239904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.239991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.240960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.240964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.241975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.241979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.242859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.242976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.243875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.243962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.244941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.244983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.245986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.245991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.246992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.246996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.247995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.247999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.248962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.248996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.249987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.249991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.250992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.250996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.251978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.251982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.252993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.252997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.253970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.253997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.254960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.254997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.255990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.255994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.256900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.256998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.257961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.257998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.258939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.258981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.259975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.259980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.260980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.260984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.261754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.261977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.262248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.262327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.262375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  752.262396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  752.262445] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  752.264949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  752.264966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  752.264986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.265018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.265046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.265060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.265078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.265108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.265136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.265196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  752.265215] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  752.265230] [drm:intel_power_well_disable [i915]] disabling always-on
>[  752.265378] [drm:drm_mode_addfb2] [FB:77]
>[  752.265400] [drm:drm_mode_addfb2] [FB:78]
>[  752.291836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.291902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  752.291949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  752.291985] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  752.292004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  752.292019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  752.292037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  752.292055] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  752.292073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  752.292092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  752.292110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  752.292125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  752.292129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.292146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  752.292150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.292168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  752.292186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  752.292204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  752.292221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  752.292240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  752.292258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  752.292276] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  752.292294] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  752.292312] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  752.292331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.292351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  752.294867] [drm:intel_power_well_enable [i915]] enabling always-on
>[  752.294883] [drm:intel_power_well_enable [i915]] enabling display
>[  752.294897] [drm:hsw_set_power_well [i915]] Enabling power well
>[  752.294926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.294942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  752.294957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.294971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  752.294986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.295000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.295017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  752.295032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.295046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.295059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.295072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  752.295089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  752.295104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  752.297090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  752.297106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  752.297120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.297135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  752.298642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  752.298660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  752.298677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.300196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  752.302038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  752.304924] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  752.304996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  752.305012] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  752.321719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.321744] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  752.321778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.338431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.338860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.338998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.339780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.339961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.340860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.340979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.341761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.341980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.342754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.342976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.343774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.343969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.344660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.344967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.345964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.345968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.346807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.346998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.347653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.347990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.348763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.348981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.349786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.349978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.350805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.350965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.351847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.351991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.352911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.352968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.353968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.353996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.354773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.354831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.355821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.355987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.356668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.356976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.357937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.357977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.358851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.358969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.359969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.359972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.360993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.360997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.361952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.361992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.362709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.362971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.363967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.363995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.364798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.364994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.365995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.365999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.366960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.366964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.367921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.367963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.368956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.368996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.369974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.369978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.370971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.370999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.371819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.371966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.372968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.372972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.373971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.373999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.374669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.374976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.375692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.375993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.376959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.376997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.377895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.377937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.378872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.378990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.379866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.379972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.380935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.380992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.381650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.381980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.382701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.382963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.383976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.383980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.384772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.384972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.385941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.385981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.386966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.386970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.387745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.387976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.388932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.388937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.389846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.389994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.390780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.390962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.391738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.391981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.392726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.392984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.393958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.393962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.394669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.394978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.395890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.395971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.396860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.396978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.397713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.397972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.398971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.398999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.399838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.399959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.400816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.400962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.401975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.401980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.402699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.402998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.403786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.403980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.404664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.404967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.405747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.405969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.406929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.406974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.407742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.407967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.408676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.408987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.409886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.409983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.410969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.410997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.411821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.411979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.412883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.412989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.413915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.413973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.414959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.414963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.415946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.415985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.416676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.416992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.417937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.417983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.418960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.418999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.419726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.419986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.420975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.420999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.421879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.421961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.422915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.422992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.423909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.423967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.424884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.424996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.425870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.425988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.426923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.426962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.427943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.427972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.428809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.428969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.429907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.429986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.430734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.430995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.431836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.431988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.432974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.432978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.433927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.433966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.434963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.434991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.435900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.435942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.436822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.436968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.437962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.437966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.438930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.438988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.439867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.439987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.440874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.440991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.441928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.441967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.442970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.442998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.443945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.443985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.444783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.444996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.445719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.445980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.446833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.446997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.447768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.447984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.448954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.448992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.449923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.449981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.450714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.450969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.451843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.451989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.452696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.452995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.453968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.453996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.454977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.454981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.455739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.455998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.456974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.456998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.457931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.457973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.458799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.458974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.459798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.459979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.460738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.460998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.461956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.461960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.462968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.462972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.463921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.463989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.464944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.464989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.465802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.465987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.466860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.466968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.467848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.467986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.468889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.468972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.469911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.469991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.470959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.470997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.471938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.471983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.472969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.472973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.473952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.473990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.474858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.474996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.475940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.475944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.476912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.476992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.477925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.477964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.478882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.478981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.479930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.479968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.480878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.480996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.481909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.481977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.482959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.482996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.483930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.483970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.484991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.484995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.485982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.485985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.486917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.486959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.487960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.487964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.488918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.488995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.489897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.489996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.490981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.490984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.491918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.491997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.492939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.492977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.493972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.493976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.494945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.494986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.495959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.495997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.496939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.496964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.497989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.497992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.498976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.498979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.499985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.499989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.500964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.500968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.501959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.501996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.502986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.502990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.503984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.503988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.504972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.504996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.505990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.505994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.506964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.506969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.507985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.507989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.508813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.508996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.509809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.509967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.510663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.510961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.511719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.511981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.512824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.512986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.513864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.513986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.514746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.514966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.515958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.515985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.516870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.516993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.517865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.517984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.518741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.518999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.519918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.519979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.520931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.520972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.521874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.521992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.522780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.522998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.523891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.523977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.524787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.524978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.525786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.525964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.526793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.526975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.527882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.527964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.528945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.528981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.529883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.529990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.530822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.530975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.531792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.531994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.532872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.532990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.533800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.533943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.534970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.534998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.535901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.535981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.536946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.536981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.537862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.537999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.538819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.538983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.539956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.539996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.540793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.540974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.541925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.541987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.542868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.542992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.543883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.543963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.544940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.544978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.545810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.545991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.546944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.546984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.547933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.547972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.548883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.548980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.549853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.549978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.550832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.550955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.551895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.551977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.552840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.552981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.553939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.553977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.554836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.554840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.555784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.555853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.555996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.556673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.556990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.557858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.557979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.558858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.558977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.559907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.559974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.560817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.560971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.561938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.561979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.562860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.562968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.563944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.563979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.564899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.564941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.565837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.565999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.566933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.566972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.567939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.567996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.568746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.568939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.569849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.569968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.570845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.570983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.571870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.571994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.572861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.572980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.573957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.573992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.574961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.574986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.575926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.575967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.576857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.576978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.577887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.577996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.578919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.578990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.579879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.579960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.580942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.580981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.581930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.581998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.582930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.582972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.583954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.583994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.584924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.584964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.585934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.585991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.586942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.586978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.587943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.587979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.588938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.588978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.589957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.589985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.590926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.590963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.591979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.591983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.592986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.592990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.593987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.593991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.594962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.594966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.595977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.595981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.596980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.596984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.597981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.597985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.598965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.598969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.599974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.599978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.600985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.600989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.601980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.601984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.602970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.602974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.603981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.603985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.604977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.604982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.605972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.605977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.606964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.606969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.607990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.607994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.608971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.608975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.609988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.609992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.610992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.610996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.611974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.611978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.612974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.612978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.613979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.613983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.614990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.614994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.615959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.615996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.616983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.616987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.617992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.617996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.618975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.618999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.619991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.619995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.620967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.620971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.621980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.621984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.622973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.622997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.623960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.623965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.624967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.624971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.625994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.625998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.626981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.626985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.627963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.627999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.628970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.628974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.629992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.629996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.630959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.630996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.631991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.631995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.632962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.632967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.633976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.633999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.634963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.634999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.635972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.635976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.636994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.636998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.637987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.637991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.638960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.638997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.639969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.639973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.640981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.640985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.641978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.641982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.642962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.642997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.643972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.643976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.644973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.644977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.645986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.645990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.646989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.646993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.647982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.647986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.648987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.648991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.649966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.649970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.650982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.650986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.651993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.651997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.652993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.652997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.653994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.653997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.654971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.654975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.655959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.655996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.656985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.656989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.657973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.657977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.658995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.658999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.659985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.659989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.660992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.660996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.661986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.661990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.662980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.662984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.663974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.663978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.664994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.664998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.665964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.665998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.666987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.666990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.667971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.667975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.668985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.668989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.669993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.669997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.670986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.670990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.671977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.671981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.672994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.672998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.673996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.673999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.674987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.674991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.675974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.675979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.676982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.676986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.677973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.677977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.678983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.678987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.679967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.679971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.680976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.680980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.681994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.681998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.682975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.682979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.683967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.683971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.684989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.684994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.685986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.685990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.686971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.686975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.687967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.687971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.688995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.688999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.689992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.689996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.690981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.690985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.691962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.691966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.692975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.692979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.693977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.693981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.694984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.694988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.695994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.695998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.696989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.696993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.697993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.697997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.698964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.698968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.699978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.699982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.700965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.700969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.701982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.701986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.702995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.702999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.703975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.703999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.704958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.704962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.705970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.705974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.706965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.706969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.707977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.707981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.708989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.708993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.709962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.709998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.710980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.710984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.711973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.711998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.712986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.712990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.713966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.713970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.714977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.714981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.715973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.715997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.716986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.716990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.717986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.717990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.718964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.718968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.719996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.719999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.720962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.720966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.721963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.721967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.722967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.722971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.723992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.723996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.724992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.724996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.725985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.725989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.726982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.726986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.727986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.727990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.728960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.728964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.729990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.729994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.730987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.730991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.731984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.731988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.732959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.732997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.733985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.733989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.734986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.734991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.735991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.735995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.736971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.736975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.737973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.737978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.738980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.738984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.739980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.739984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.740991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.740994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.741961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.741996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.742985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.742989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.743981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.743985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744970] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.744980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.744984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.744993] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.745019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745331] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.745335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745348] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.745357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745368] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.745378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745690] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.745723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.745985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.745989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746027] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.746028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746343] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.746351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746359] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.746367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746693] systemd-journald[277]: /dev/kmsg buffer overrun, some messages lost.
>[  752.746696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.746979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.746983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.747969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.747973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.748975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.748979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.749989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.749993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.750972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.750976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.751970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.751974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.752979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.752983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.753995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.753999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.754972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.754996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.755984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.755988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.756965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.756968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.757986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.757990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.758962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.758966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.759962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.759999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.760967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.760971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.761963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.761967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.762993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.762997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.763970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.763974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.764995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.764999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.765992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.765996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.766982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.766986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.767992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.767996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.768993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.768997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.769963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.769998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.770984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.770988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.771958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.771962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.772980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.772984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.773988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.773992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.774984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.774988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.775989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.775993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.776989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.776994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.777980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.777984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.778971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.778975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.779964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.779968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.780965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.780969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.781992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.781996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.782959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.782996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.783982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.783986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.784988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.784992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.785979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.785983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.786988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.786992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.787967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.787971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.788974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.788978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.789978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.789982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.790959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.790962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.791994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.791998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.792964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.792968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.793973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.793976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.794959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.794996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.795978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.795982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.796986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.796991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.797974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.797978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.798994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.798998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.799986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.799990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.800962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.800996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.801994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.801998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.802992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.802996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.803994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.803998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.804964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.804998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.805979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.805983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.806987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.806991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.807969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.807973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.808979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.808983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.809987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.809991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.810967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.810971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.811974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.811978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.812983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.812987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.813981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.813985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.814969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.814973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.815975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.815979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.816986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.816990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.817973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.817977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.818971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.818975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.819990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.819994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.820963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.820998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.821973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.821998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.822991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.822995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.823960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.823964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.824982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.824987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.825985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.825989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.826961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.826965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.827986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.827990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.828984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.828988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.829996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.829999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.830987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.830991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.831993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.831997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.832991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.832995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.833993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.833997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.834977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.834981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.835977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.835981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.836985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.836989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.837980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.837984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.838434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  752.838518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.838566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  752.838587] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  752.838636] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  752.841151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  752.841168] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  752.841188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.841203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  752.841220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.841234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  752.841248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.841262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.841279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.841295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  752.841310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.841324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.841337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.841350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  752.841377] [drm:intel_power_well_disable [i915]] disabling display
>[  752.841398] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  752.841418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  752.841433] [drm:intel_power_well_disable [i915]] disabling always-on
>[  752.843668] [IGT] kms_flip: exiting, ret=0
>[  752.870290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  752.870307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  752.870324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  752.870342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  752.870356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  752.870371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  752.870387] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  752.870401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  752.870415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  752.870428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  752.870441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  752.870445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.870462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  752.870465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.870484] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  752.870499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  752.870516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  752.870533] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  752.870550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  752.870567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  752.870585] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  752.870602] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  752.870619] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  752.870638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.870657] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  752.870708] [drm:intel_power_well_enable [i915]] enabling always-on
>[  752.870739] [drm:intel_power_well_enable [i915]] enabling display
>[  752.870754] [drm:hsw_set_power_well [i915]] Enabling power well
>[  752.870783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.870798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  752.870812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.870826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  752.870839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.870853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.870869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  752.870883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.870897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.870910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.870923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  752.870938] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  752.870952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  752.872952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  752.872967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  752.872980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.872995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  752.874505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  752.874518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  752.874531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.876030] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  752.876044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  752.877858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  752.880838] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  752.880865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  752.880880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  752.880901] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  752.880953] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  752.880975] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  752.897600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.897624] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  752.897661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.897803] Console: switching to colour frame buffer device 240x75
>[  753.045697] Console: switching to colour dummy device 80x25
>[  753.045858] [IGT] kms_flip: executing
>[  753.067932] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  753.067955] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  753.069775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  753.069792] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  753.071771] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  753.071777] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  753.073773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  753.073790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  753.075773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  753.075779] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  753.075783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  753.075798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  753.075818] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  753.076846] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  753.077735] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  753.077771] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  753.077834] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  753.077849] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  753.078838] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  753.078854] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  753.079991] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  753.079994] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  753.080074] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  753.080076] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  753.080081] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  753.080084] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  753.080088] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  753.080089] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  753.080097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  753.080100] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.080102] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  753.080105] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  753.080108] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  753.080110] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  753.080113] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  753.080116] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  753.080118] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  753.080121] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  753.080123] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  753.080126] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  753.080128] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  753.080131] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  753.080134] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  753.080137] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  753.080139] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  753.080142] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  753.080144] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  753.080146] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  753.080149] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  753.080152] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  753.080155] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  753.080157] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  753.080159] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  753.080162] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  753.080164] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  753.080167] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  753.080170] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  753.080172] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  753.080175] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  753.080205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  753.080222] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  753.081762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  753.081778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  753.083759] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  753.083764] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  753.085771] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  753.085790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  753.087773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  753.087779] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  753.087782] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  753.089060] [IGT] kms_flip: starting subtest dpms-vs-vblank-race-interruptible
>[  753.089530] [drm:drm_mode_addfb2] [FB:75]
>[  753.089552] [drm:drm_mode_addfb2] [FB:79]
>[  753.132680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  753.132734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.147826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.147851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.147895] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.166382] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.166404] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.166419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.166438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.166453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.166470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.166484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.166498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.166513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.166530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.166545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.166560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.166574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.166587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.166600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.166627] [drm:intel_power_well_disable [i915]] disabling display
>[  753.166648] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.166669] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.166685] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.166767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  753.166877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  753.166967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  753.166978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  753.167017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.167034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.167051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.167070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.167086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.167105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.167123] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.167141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.167159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.167178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.167195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.167199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.167216] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.167220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.167237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.167255] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.167273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.167290] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.167309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.167326] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.167344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  753.167362] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.167380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.167399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.167419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.169924] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.169939] [drm:intel_power_well_enable [i915]] enabling display
>[  753.169952] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.169980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.169996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.170011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.170029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.170047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.170065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.170085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.170104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.170123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.170141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.170158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.170177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.170195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.172170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.172187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.172202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.172216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.173726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.173757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.173773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.175270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.175287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.177095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.179986] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.180053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.180070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.180091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.180139] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.180163] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.196801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.196827] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.196861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.213627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.213649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.213671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.213694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.213714] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.213735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.213797] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.213823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.213850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.213872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.213897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.213905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.213928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.213934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.213957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.213980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.214003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.214025] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.214050] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.214071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.214096] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.214117] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.214140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.214166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.214194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.230164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.230189] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.230233] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.248139] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.248161] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.248177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.248197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.248214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.248231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.248246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.248261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.248277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.248294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.248310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.248326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.248341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.248355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.248381] [drm:intel_power_well_disable [i915]] disabling display
>[  753.248403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.248418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.248435] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.248452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.248467] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.248576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.248592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.248609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.248628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.248644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.248660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.248677] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.248692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.248707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.248726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.248783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.248792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.248815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.248822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.248846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.248868] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.248892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.248914] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.248940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.248962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.248988] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.249010] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.249033] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.249060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.249094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.249161] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.249184] [drm:intel_power_well_enable [i915]] enabling display
>[  753.249206] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.249243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.249266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.249286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.249308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.249327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.249349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.249373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.249396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.249420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.249439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.249459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.249482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.249504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.251501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.251518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.251531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.251548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.253057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.253075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.253092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.254587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.254604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.256416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.259361] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.259425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.259441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.259463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.259511] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.259536] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.259602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.259627] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.259658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.309594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.309614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.309634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.309655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.309672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.309692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.309713] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.309733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.309791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.309818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.309843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.309850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.309875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.309881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.309906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.309928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.309952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.309974] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.310227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.310250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.310275] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.310297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.310319] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.310345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.310373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.326207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.326231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.326276] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.345140] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.345162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.345178] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.345198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.345215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.345230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.345246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.345260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.345279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.345300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.345320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.345341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.345360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.345377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.345405] [drm:intel_power_well_disable [i915]] disabling display
>[  753.345427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.345447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.345467] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.345489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.345504] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.345749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.345811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.345838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.345867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.345890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.345915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.345939] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.345962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.345985] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.346008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.346029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.346036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.346057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.346063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.346086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.346286] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.346304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.346321] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.346339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.346356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.346375] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.346393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.346410] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.346429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.346448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.346491] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.346506] [drm:intel_power_well_enable [i915]] enabling display
>[  753.346520] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.346548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.346566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.346585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.346603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.346621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.346638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.346658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.346677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.346696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.346714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.346732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.346773] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.346796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.348790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.348806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.348820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.348835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.350350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.350368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.350385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.351884] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.351901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.353704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.355871] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.355904] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.355923] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.355950] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.355991] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.356011] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.356055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.356079] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.356114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.406051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.406072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.406092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.406113] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.406132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.406153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.406174] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.406195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.406216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.406236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.406256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.406260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.406280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.406284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.406304] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.406324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.406345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.406365] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.406385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.406405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.406426] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.406446] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.406467] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.406488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.406510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.422687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.422711] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.422756] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.441625] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.441647] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.441663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.441684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.441704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.441724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.441743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.441804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.441830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.441859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.441886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.441913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.442099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.442117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.442144] [drm:intel_power_well_disable [i915]] disabling display
>[  753.442167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.442187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.442208] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.442230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.442245] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.442471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.442491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.442518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.442537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.442552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.442569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.442584] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.442599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.442614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.442627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.442641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.442644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.442657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.442661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.442674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.442687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.442700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.442712] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.442727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.442740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.442782] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.442805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.442825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.442851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.442877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.442941] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.443198] [drm:intel_power_well_enable [i915]] enabling display
>[  753.443220] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.443257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.443278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.443300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.443320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.443341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.443361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.443384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.443408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.443431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.443450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.443471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.443496] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.443517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.445513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.445529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.445543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.445558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.447065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.447080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.447094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.448588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.448604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.450412] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.453336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.453370] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.453389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.453415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.453465] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.453492] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.453560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.453586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.453619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.503544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.503564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.503585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.503609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.503629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.503650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.503670] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.503691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.503711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.503731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.503751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.503792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.503822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.503828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.503857] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.503880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.503906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.503928] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.503956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.503978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.504004] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.504026] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.504238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.504264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.504292] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.520153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.520177] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.520221] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.539094] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.539116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.539132] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.539151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.539168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.539184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.539202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.539222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.539241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.539262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.539282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.539302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.539321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.539340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.539368] [drm:intel_power_well_disable [i915]] disabling display
>[  753.539390] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.539410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.539430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.539452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.539468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.539704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.539721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.539738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.539758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.539813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.539839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.539862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.539884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.539905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.539925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.539945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.539951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.539970] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.539976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.539996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.540015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.540035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.540054] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.540076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.540096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.540118] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.540313] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.540331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.540350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.540370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.540413] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.540428] [drm:intel_power_well_enable [i915]] enabling display
>[  753.540442] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.540470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.540488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.540507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.540524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.540543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.540561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.540580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.540600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.540618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.540636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.540653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.540672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.540690] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.542667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.542684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.542699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.542714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.544219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.544236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.544253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.545750] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.545781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.547585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.550520] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.550595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.550615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.550640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.550681] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.550701] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.550749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.550804] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.550861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.600750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.600788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.600808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.600830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.600849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.600869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.600888] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.600907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.600926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.600945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.600964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.600968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.600987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.600990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.601010] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.601029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.601048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.601067] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.601086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.601105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.601125] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.601144] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.601163] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.601183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.601203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.617376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.617398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.617433] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.636287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.636309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.636325] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.636345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.636361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.636377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.636392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.636407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.636423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.636440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.636456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.636472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.636486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.636500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.636527] [drm:intel_power_well_disable [i915]] disabling display
>[  753.636548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.636564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.636580] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.636598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.636612] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.637146] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.637163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.637180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.637198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.637213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.637229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.637246] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.637263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.637281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.637299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.637316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.637319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.637336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.637340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.637358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.637375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.637393] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.637410] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.637427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.637444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.637462] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.637480] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.637498] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.637516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.637538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.637588] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.637602] [drm:intel_power_well_enable [i915]] enabling display
>[  753.637614] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.637640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.637656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.637671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.637684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.637698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.637712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.637731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.637750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.637799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.637826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.637847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.637873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.637894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.639883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.639900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.639914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.639930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.641432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.641448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.641461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.642952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.642968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.644785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.647694] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.647744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.647761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.647824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.647886] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.647911] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.647976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.648008] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.648058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.697913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.697935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.697956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.697980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.698000] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.698021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.698041] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.698061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.698082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.698102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.698122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.698126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.698146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.698150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.698171] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.698191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.698211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.698231] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.698252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.698272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.698293] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.698313] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.698334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.698355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.698377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.714526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.714550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.714586] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.732531] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.732553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.732572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.732594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.732614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.732633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.732653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.732672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.732691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.732712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.732732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.732752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.732771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.732833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.732877] [drm:intel_power_well_disable [i915]] disabling display
>[  753.732912] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.732940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.732968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.732999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.733023] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.733322] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.733338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.733355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.733373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.733391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.733409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.733427] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.733444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.733462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.733479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.733496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.733500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.733517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.733520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.733538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.733555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.733572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.733589] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.733607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.733624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.733642] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.733659] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.733677] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.733695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.733714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.733756] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.733801] [drm:intel_power_well_enable [i915]] enabling display
>[  753.733823] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.733863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.733888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.733913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.733936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.733959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.733983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.734010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.734035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.734060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.734082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.734104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.734131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.734154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.736152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.736168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.736183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.736202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.737718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.737734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.737748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.739275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.739290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.741125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.744072] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.744135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.744152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.744173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.744211] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.744228] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.744273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.744307] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.744338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.794299] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.794321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.794342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.794366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.794386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.794406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.794427] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.794447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.794467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.794487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.794507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.794512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.794532] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.794535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.794556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.794576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.794596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.794617] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.794637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.794657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.794678] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.794698] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.794718] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.794739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.794761] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.810916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.810942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.810979] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.829834] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.829858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.829878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.829900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.829919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.829939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.829958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.829977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.829996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.830017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.830038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.830058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.830077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.830093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.830121] [drm:intel_power_well_disable [i915]] disabling display
>[  753.830143] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.830163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.830184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.830206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.830221] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.830459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.830477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.830494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.830512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.830526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.830542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.830557] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.830571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.830585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.830598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.830611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.830615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.830631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.830635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.830653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.830670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.830688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.830705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.830722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.830739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.830757] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.830775] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.830831] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.830860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.830887] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.830953] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.830978] [drm:intel_power_well_enable [i915]] enabling display
>[  753.831001] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.831038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.831309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.831332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.831356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.831378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.831401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.831426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.831450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.831474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.831496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.831518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.831543] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.831566] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.833565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.833581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.833595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.833609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.835117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.835132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.835146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.836640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.836657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.838469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.841391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.841426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.841443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.841465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.841503] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.841527] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.841568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.841587] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.841617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.891587] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.891607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.891627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.891651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.891671] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.891692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.891713] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.891733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.891753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.891773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.891838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.891848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.891875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.891881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.891908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.891934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.891960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.891984] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.892012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.892037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.892063] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.892089] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.892113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.892141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.892169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.908208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  753.908232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  753.908268] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  753.926546] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  753.926568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  753.926584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  753.926604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.926621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.926640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.926659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.926679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.926698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.926718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.926739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.926759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.926778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.926844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.926886] [drm:intel_power_well_disable [i915]] disabling display
>[  753.926921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  753.927129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.927157] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.927187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.927212] [drm:intel_power_well_disable [i915]] disabling always-on
>[  753.927480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.927498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.927516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.927542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.927558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.927576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.927594] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.927611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.927629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.927646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.927663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.927667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.927684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.927687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.927705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.927723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.927740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.927757] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.927775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.927824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.927848] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.927873] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.927896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.927922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.927949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  753.928199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  753.928223] [drm:intel_power_well_enable [i915]] enabling display
>[  753.928244] [drm:hsw_set_power_well [i915]] Enabling power well
>[  753.928282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  753.928305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  753.928328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  753.928351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  753.928373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  753.928397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  753.928421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  753.928445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  753.928469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.928490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  753.928512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  753.928536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  753.928560] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  753.930552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  753.930567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  753.930581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.930595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  753.932102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  753.932117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  753.932131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  753.933624] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  753.933640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  753.935451] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  753.938387] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  753.938460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  753.938477] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  753.938499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  753.938537] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  753.938554] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  753.938597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  753.938618] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  753.938650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  753.988624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  753.988645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  753.988665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  753.988689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  753.988709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  753.988730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  753.988750] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  753.988771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  753.988831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  753.988857] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  753.988884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  753.988892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.988917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  753.988924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  753.988949] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  753.988974] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  753.989000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  753.989023] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  753.989186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  753.989213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  753.989239] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  753.989264] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  753.989288] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  753.989315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  753.989343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.005242] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.005266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.005301] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.023543] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.023565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.023581] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.023600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.023617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.023633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.023648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.023663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.023679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.023696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.023712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.023728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.023743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.023757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.023783] [drm:intel_power_well_disable [i915]] disabling display
>[  754.023854] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.023882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.023910] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.023940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.023965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.024440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.024458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.024477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.024496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.024511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.024531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.024550] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.024570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.024589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.024608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.024627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.024631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.024649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.024653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.024672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.024692] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.024710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.024729] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.024748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.024767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.024787] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.024850] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.024876] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.024903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.024931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.025162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.025185] [drm:intel_power_well_enable [i915]] enabling display
>[  754.025208] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.025245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.025269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.025292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.025314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.025337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.025360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.025385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.025407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.025432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.025453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.025474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.025497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.025520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.027516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.027532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.027546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.027560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.029067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.029082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.029096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.030589] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.030605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.032417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.035354] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.035426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.035442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.035464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.035502] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.035518] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.035560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.035581] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.035613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.085572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.085594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.085616] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.085639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.085659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.085680] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.085700] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.085721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.085741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.085761] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.085781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.085830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.085856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.085862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.085891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.085914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.085938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.085961] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.085982] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.085997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.086013] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.086028] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.086043] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.086060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.086079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.102209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.102234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.102269] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.121122] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.121143] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.121160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.121179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.121196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.121211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.121226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.121241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.121257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.121274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.121290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.121306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.121320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.121334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.121361] [drm:intel_power_well_disable [i915]] disabling display
>[  754.121383] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.121398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.121415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.121432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.121447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.121729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.121746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.121767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.121797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.121858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.121883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.121907] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.121930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.121952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.121973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.121994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.122001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.122022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.122028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.122050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.122071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.122092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.122112] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.122143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.122162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.122183] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.122204] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.122225] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.122246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.122270] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.122321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.122334] [drm:intel_power_well_enable [i915]] enabling display
>[  754.122348] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.122376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.122394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.122412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.122430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.122447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.122465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.122484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.122503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.122522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.122539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.122554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.122573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.122591] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.124573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.124589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.124604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.124618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.126124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.126139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.126153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.127646] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.127662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.129472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.132429] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.132480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.132495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.132516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.132551] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.132566] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.132607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.132626] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.132655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.182657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.182678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.182698] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.182719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.182735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.182756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.182777] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.182797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.182858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.182883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.182906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.182913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.182936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.182942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.182965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.182987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.183011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.183029] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.183047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.183061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.183076] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.183091] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.183105] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.183123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.183141] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.199264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.199288] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.199323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.218187] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.218209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.218225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.218245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.218262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.218278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.218297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.218317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.218336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.218357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.218377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.218398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.218416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.218435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.218463] [drm:intel_power_well_disable [i915]] disabling display
>[  754.218485] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.218506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.218526] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.218548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.218563] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.218936] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.218964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.218993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.219023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.219040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.219058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.219076] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.219092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.219108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.219123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.219137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.219141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.219155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.219159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.219173] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.219192] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.219212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.219232] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.219252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.219271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.219292] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.219311] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.219331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.219352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.219373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.219420] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.219443] [drm:intel_power_well_enable [i915]] enabling display
>[  754.219456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.219483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.219499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.219513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.219527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.219541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.219556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.219571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.219586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.219600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.219613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.219626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.219643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.219657] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.221630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.221647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.221661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.221675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.223181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.223199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.223216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.224712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.224729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.226538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.229466] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.229496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.229513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.229535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.229574] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.229590] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.229633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.229654] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.229686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.279648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.279667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.279686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.279706] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.279721] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.279738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.279755] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.279771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.279787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.279802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.279853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.279863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.279887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.279894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.279920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.279943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.279967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.279989] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.280016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.280037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.280062] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.280083] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.280106] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.280130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.280157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.296278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.296302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.296338] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.314666] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.314688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.314704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.314724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.314741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.314756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.314771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.314786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.314802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.314864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.314892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.314917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.314941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.314958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.314985] [drm:intel_power_well_disable [i915]] disabling display
>[  754.315007] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.315028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.315049] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.315072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.315088] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.315403] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.315421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.315440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.315459] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.315475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.315492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.315509] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.315527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.315547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.315566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.315585] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.315589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.315607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.315611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.315630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.315649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.315669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.315688] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.315707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.315725] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.315745] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.315764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.315783] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.315809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.315861] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.315904] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.315919] [drm:intel_power_well_enable [i915]] enabling display
>[  754.315932] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.315958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.315974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.315992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.316010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.316027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.316045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.316065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.316083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.316103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.316120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.316138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.316157] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.316175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.318147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.318163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.318177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.318192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.319693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.319709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.319723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.321218] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.321234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.323038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.325970] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.326044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.326059] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.326079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.326116] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.326134] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.326176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.326198] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.326231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.376216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.376238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.376259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.376283] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.376303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.376324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.376345] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.376365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.376386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.376406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.376425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.376430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.376449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.376453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.376474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.376494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.376514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.376534] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.376555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.376574] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.376596] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.376616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.376636] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.376658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.376679] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.392843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.392867] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.392902] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.411762] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.411784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.411800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.411864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.411889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.411916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.411939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.411962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.411987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.412014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.412039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.412065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.412086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.412109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.412149] [drm:intel_power_well_disable [i915]] disabling display
>[  754.412182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.412206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.412233] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.412260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.412284] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.412554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.412572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.412590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.412609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.412624] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.412641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.412658] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.412674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.412689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.412703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.412717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.412721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.412735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.412738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.412753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.412767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.412780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.412793] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.412810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.412854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.412879] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.412901] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.412925] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.412952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.412980] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.413050] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.413083] [drm:intel_power_well_enable [i915]] enabling display
>[  754.413105] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.413142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.413163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.413186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.413205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.413226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.413247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.413270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.413293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.413316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.413335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.413356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.413378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.413400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.415402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.415420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.415434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.415449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.416969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.416986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.417003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.418498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.418515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.420322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.422738] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.422774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.422790] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.422845] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.422906] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.422932] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.422995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.423028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.423062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.472940] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.472962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.472983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.473007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.473027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.473047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.473068] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.473088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.473109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.473129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.473149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.473153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.473173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.473177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.473198] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.473218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.473238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.473258] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.473278] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.473298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.473320] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.473340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.473360] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.473381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.473403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.489557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.489581] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.489618] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.508474] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.508496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.508512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.508531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.508548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.508564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.508580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.508595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.508611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.508628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.508644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.508661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.508675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.508689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.508716] [drm:intel_power_well_disable [i915]] disabling display
>[  754.508737] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.508753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.508770] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.508788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.508802] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.509213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.509231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.509250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.509270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.509287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.509304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.509321] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.509337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.509356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.509377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.509396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.509401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.509420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.509424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.509450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.509465] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.509480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.509494] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.509514] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.509534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.509551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.509564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.509577] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.509593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.509610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.509651] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.509666] [drm:intel_power_well_enable [i915]] enabling display
>[  754.509679] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.509703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.509717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.509731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.509744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.509757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.509771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.509790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.509811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.509854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.509876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.509895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.509919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.509941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.511933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.511949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.511963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.511977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.513480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.513495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.513509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.515003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.515019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.516836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.519753] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.519794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.519811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.519877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.519934] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.519958] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.520022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.520053] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.520104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.569964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.569987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.570008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.570031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.570051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.570072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.570093] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.570113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.570133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.570153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.570173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.570177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.570197] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.570201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.570221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.570242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.570262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.570282] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.570302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.570322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.570343] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.570363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.570383] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.570405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.570426] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.586575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.586600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.586635] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.605497] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.605519] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.605535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.605555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.605571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.605587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.605602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.605617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.605633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.605649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.605665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.605681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.605699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.605717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.605744] [drm:intel_power_well_disable [i915]] disabling display
>[  754.605766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.605787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.605807] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.605871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.605895] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.606198] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.606220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.606246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.606267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.606283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.606300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.606317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.606333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.606350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.606365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.606379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.606383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.606397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.606401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.606420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.606439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.606459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.606478] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.606498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.606517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.606544] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.606560] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.606575] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.606591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.606609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.606650] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.606663] [drm:intel_power_well_enable [i915]] enabling display
>[  754.606676] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.606701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.606716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.606729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.606743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.606756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.606770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.606786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.606801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.606819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.606861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.606882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.606907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.606928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.608921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.608937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.608951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.608969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.610473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.610489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.610502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.611997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.612015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.613823] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.616770] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.616875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.616892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.616914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.616960] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.616985] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.617047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.617072] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.617103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.667018] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.667039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.667057] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.667077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.667093] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.667110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.667127] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.667143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.667158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.667173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.667187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.667191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.667204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.667208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.667222] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.667236] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.667250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.667263] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.667279] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.667293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.667308] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.667321] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.667340] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.667361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.667382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.683621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.683645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.683689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.702558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.702580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.702597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.702616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.702633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.702649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.702664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.702679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.702695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.702713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.702729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.702745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.702760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.702774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.702800] [drm:intel_power_well_disable [i915]] disabling display
>[  754.702822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.702881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.702907] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.702934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.702956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.703335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.703364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.703392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.703423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.703448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.703476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.703504] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.703529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.703555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.703578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.703602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.703608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.703626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.703630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.703645] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.703659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.703673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.703686] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.703703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.703717] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.703736] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.703756] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.703781] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.703797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.703814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.703901] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.703922] [drm:intel_power_well_enable [i915]] enabling display
>[  754.703942] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.703981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.704004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.704025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.704048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.704069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.704092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.704116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.704141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.704164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.704185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.704206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.704225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.704242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.706216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.706232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.706246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.706261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.707775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.707790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.707803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.709296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.709312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.711116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.714047] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.714074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.714091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.714112] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.714162] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.714187] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.714254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.714285] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.714318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.764231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.764252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.764272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.764293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.764313] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.764334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.764354] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.764375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.764395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.764416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.764436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.764440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.764460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.764464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.764485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.764505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.764525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.764545] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.764565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.764585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.764606] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.764626] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.764647] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.764668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.764690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.780866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.780891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.780936] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.799797] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.799819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.799880] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.799904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.799921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.799938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.799953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.799967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.799983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.800001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.800017] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.800034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.800048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.800063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.800090] [drm:intel_power_well_disable [i915]] disabling display
>[  754.800112] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.800128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.800145] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.800163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.800177] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.800472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.800490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.800508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.800528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.800543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.800560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.800576] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.800592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.800611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.800630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.800649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.800653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.800672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.800675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.800695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.800714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.800733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.800752] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.800771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.800790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.800809] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.800831] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.800886] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.800913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.800940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.801014] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.801035] [drm:intel_power_well_enable [i915]] enabling display
>[  754.801057] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.801096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.801117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.801140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.801154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.801168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.801182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.801198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.801213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.801227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.801240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.801253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.801269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.801284] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.803256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.803274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.803291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.803309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.804816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.804839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.804887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.806388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.806404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.808281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.811230] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.811290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.811306] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.811328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.811375] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.811400] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.811466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.811491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.811523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.861456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.861476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.861496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.861520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.861540] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.861561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.861582] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.861602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.861623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.861643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.861663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.861667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.861687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.861691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.861711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.861732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.861752] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.861772] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.861793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.861813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.861834] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.861895] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.861921] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.861947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.861974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.878072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.878096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.878140] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.897008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.897030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.897047] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.897066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.897083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.897099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.897114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.897129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.897145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.897162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.897179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.897195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.897209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.897223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.897250] [drm:intel_power_well_disable [i915]] disabling display
>[  754.897273] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.897293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.897313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.897335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.897351] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.897597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.897617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.897637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.897658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.897677] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.897697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.897717] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.897735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.897755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.897774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.897793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.897797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.897816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.897819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.897839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.897905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.897933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.897959] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.897987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.898012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.898040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.898071] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.898094] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.898119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.898145] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.898211] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.898234] [drm:intel_power_well_enable [i915]] enabling display
>[  754.898257] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.898293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.898316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.898339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.898360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.898381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.898402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.898427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.898450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.898474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.898496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.898515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.898539] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.898562] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.900560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.900577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.900595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.900613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.902122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.902138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.902153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.903649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  754.903665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  754.905471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  754.908396] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  754.908428] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  754.908444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  754.908466] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  754.908513] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  754.908539] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  754.908606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.908631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.908664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.958583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.958604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.958625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.958646] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.958664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.958686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.958706] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.958727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.958747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.958767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.958787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.958791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.958811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.958815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.958836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.958902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.958927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.958950] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.958978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.959002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.959028] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.959051] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.959075] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.959103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.959132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.975212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  754.975236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  754.975281] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  754.994149] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  754.994171] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  754.994188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  754.994209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.994229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.994249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.994268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.994288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.994307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.994328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.994348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.994369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.994387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.994406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.994434] [drm:intel_power_well_disable [i915]] disabling display
>[  754.994456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  754.994477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  754.994497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  754.994519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.994534] [drm:intel_power_well_disable [i915]] disabling always-on
>[  754.994783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  754.994803] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  754.994823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  754.994845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  754.994907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  754.994934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  754.994960] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  754.994983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  754.995007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  754.995028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  754.995050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  754.995057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.995078] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  754.995084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  754.995106] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  754.995127] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  754.995149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  754.995170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  754.995194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  754.995215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  754.995240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  754.995451] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  754.995465] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  754.995481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  754.995498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  754.995540] [drm:intel_power_well_enable [i915]] enabling always-on
>[  754.995554] [drm:intel_power_well_enable [i915]] enabling display
>[  754.995568] [drm:hsw_set_power_well [i915]] Enabling power well
>[  754.995595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  754.995614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  754.995632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  754.995651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  754.995666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  754.995684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  754.995704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  754.995723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  754.995742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  754.995760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  754.995777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  754.995796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  754.995814] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  754.997814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  754.997831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  754.997845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  754.997892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  754.999405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  754.999420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  754.999434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.000934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.000951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.002752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.004765] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.004799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.004816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.004838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.005042] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.005059] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.005103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.005124] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.005157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.054989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.055009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.055027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.055047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.055063] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.055080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.055097] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.055113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.055128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.055143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.055158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.055162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.055180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.055184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.055203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.055223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.055242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.055261] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.055280] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.055299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.055318] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.055337] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.055356] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.055377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.055397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.071583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.071607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.071648] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.090512] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.090534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.090551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.090570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.090587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.090603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.090619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.090634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.090653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.090674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.090695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.090716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.090735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.090751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.090779] [drm:intel_power_well_disable [i915]] disabling display
>[  755.090802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.090822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.090842] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.090909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.090931] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.091361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.091379] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.091398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.091420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.091439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.091459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.091478] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.091497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.091517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.091536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.091554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.091558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.091577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.091581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.091600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.091619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.091646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.091662] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.091679] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.091694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.091708] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.091722] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.091735] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.091751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.091768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.091808] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.091822] [drm:intel_power_well_enable [i915]] enabling display
>[  755.091836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.091901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.091923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.091944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.091965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.091985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.092006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.092030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.092052] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.092074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.092094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.092114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.092137] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.092159] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.094338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.094354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.094369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.094387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.095963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.095979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.095993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.097487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.097503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.099312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.102245] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.102322] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.102341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.102367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.102408] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.102427] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.102473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.102497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.102532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.152478] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.152500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.152522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.152545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.152566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.152586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.152607] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.152627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.152648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.152668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.152688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.152692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.152711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.152715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.152736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.152756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.152776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.152796] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.152817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.152837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.152858] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.152917] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.152944] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.152973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.152999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.169103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.169129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.169166] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.188026] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.188048] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.188064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.188084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.188100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.188116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.188131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.188146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.188161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.188178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.188194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.188211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.188225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.188239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.188266] [drm:intel_power_well_disable [i915]] disabling display
>[  755.188287] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.188302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.188319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.188340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.188356] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.188593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.188612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.188632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.188660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.188675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.188691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.188707] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.188724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.188742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.188759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.188776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.188780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.188797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.188801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.188819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.188836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.188853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.188907] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.188931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.188954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.188976] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.188997] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.189017] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.189040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.189065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.189129] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.189152] [drm:intel_power_well_enable [i915]] enabling display
>[  755.189172] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.189208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.189230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.189250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.189271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.189291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.189312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.189336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.189359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.189381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.189401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.189421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.189443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.189465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.191462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.191479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.191493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.191507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.193014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.193029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.193042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.194535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.194551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.196378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.199318] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.199387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.199403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.199425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.199464] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.199480] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.199523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.199544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.199575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.249555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.249576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.249596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.249617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.249635] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.249653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.249671] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.249688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.249704] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.249720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.249735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.249739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.249755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.249758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.249774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.249789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.249809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.249829] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.249850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.249909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.249935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.249956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.249978] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.250003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.250030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.266169] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.266195] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.266231] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.285097] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.285121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.285140] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.285162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.285182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.285201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.285220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.285240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.285259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.285280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.285300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.285321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.285339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.285356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.285383] [drm:intel_power_well_disable [i915]] disabling display
>[  755.285406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.285426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.285446] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.285468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.285483] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.285765] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.285784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.285803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.285822] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.285837] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.285856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.285916] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.285940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.285970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.285991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.286011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.286018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.286036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.286042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.286062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.286082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.286101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.286120] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.286142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.286161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.286182] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.286201] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.286220] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.286243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.286268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.286501] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.286515] [drm:intel_power_well_enable [i915]] enabling display
>[  755.286528] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.286553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.286569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.286584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.286598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.286612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.286627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.286643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.286658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.286673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.286689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.286708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.286726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.286745] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.288719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.288737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.288755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.288773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.290280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.290298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.290315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.291817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.291834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.293646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.296569] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.296603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.296622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.296648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.296688] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.296707] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.296753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.296777] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.296812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.346767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.346787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.346808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.346831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.346852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.346872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.346938] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.347023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.347039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.347055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.347070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.347074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.347088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.347092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.347111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.347131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.347150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.347170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.347190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.347209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.347229] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.347249] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.347268] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.347289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.347311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.363386] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.363410] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.363446] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.382303] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.382325] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.382341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.382361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.382378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.382394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.382409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.382424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.382439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.382456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.382472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.382488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.382502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.382516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.382543] [drm:intel_power_well_disable [i915]] disabling display
>[  755.382566] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.382586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.382607] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.382629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.382644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.382922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.382948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.382975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.383003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.383026] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.383051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.383075] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.383101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.383254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.383270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.383284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.383289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.383303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.383306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.383322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.383336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.383357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.383369] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.383385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.383398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.383416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.383434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.383452] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.383471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.383490] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.383533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.383548] [drm:intel_power_well_enable [i915]] enabling display
>[  755.383562] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.383590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.383608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.383626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.383644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.383662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.383680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.383700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.383728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.383751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.383766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.383780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.383797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.383812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.385792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.385813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.385828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.385843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.387361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.387376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.387389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.388899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.388917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.390726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.393663] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.393736] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.393752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.393775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.393813] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.393830] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.393917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.393952] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.394003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.443913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.443933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.443953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.443975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.443991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.444009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.444027] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.444044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.444061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.444077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.444092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.444096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.444111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.444115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.444130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.444145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.444160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.444174] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.444192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.444207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.444223] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.444238] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.444252] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.444270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.444288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.460513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.460539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.460578] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.478609] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.478630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.478646] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.478665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.478682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.478698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.478713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.478727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.478742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.478760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.478776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.478792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.478806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.478825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.478853] [drm:intel_power_well_disable [i915]] disabling display
>[  755.478915] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.478941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.478967] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.478995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.479020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.479342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.479360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.479380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.479402] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.479421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.479448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.479465] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.479480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.479495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.479509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.479522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.479526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.479538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.479542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.479555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.479568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.479582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.479594] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.479609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.479622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.479636] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.479649] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.479662] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.479677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.479694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.479727] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.479742] [drm:intel_power_well_enable [i915]] enabling display
>[  755.479756] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.479784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.479802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.479820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.479838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.479856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.479878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.479925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.479949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.479973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.479993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.480013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.480036] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.480058] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.482064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.482081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.482096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.482111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.483618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.483633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.483647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.485144] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.485160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.486965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.489915] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.489975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.489992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.490014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.490062] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.490088] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.490155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.490182] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.490214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.540139] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.540159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.540180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.540201] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.540218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.540236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.540254] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.540271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.540288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.540304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.540319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.540323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.540338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.540342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.540357] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.540373] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.540392] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.540413] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.540433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.540453] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.540474] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.540495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.540515] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.540536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.540558] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.556755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.556779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.556823] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.574713] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.574735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.574751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.574771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.574787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.574803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.574818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.574833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.574849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.574866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.574923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.574951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.574974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.574998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.575039] [drm:intel_power_well_disable [i915]] disabling display
>[  755.575218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.575245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.575272] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.575301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.575325] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.575591] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.575611] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.575631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.575653] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.575672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.575691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.575711] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.575729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.575749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.575768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.575786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.575790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.575809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.575812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.575839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.575856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.575871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.575913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.575939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.575961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.575985] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.576006] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.576028] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.576054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.576080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.576352] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.576375] [drm:intel_power_well_enable [i915]] enabling display
>[  755.576397] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.576435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.576456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.576478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.576498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.576518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.576539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.576571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.576595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.576618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.576637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.576657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.576680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.576703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.578695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.578712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.578726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.578742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.580249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.580267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.580284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.581780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.581797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.583607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.586542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.586616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.586633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.586655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.586704] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.586730] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.586797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.586824] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.586857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.636748] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.636767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.636786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.636806] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.636822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.636839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.636856] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.636872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.636929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.636954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.636978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.636985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.637009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.637016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.637040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.637062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.637085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.637351] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.637370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.637386] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.637403] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.637417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.637432] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.637449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.637467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.653397] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.653422] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.653466] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.671504] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.671526] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.671543] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.671563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.671580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.671596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.671612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.671627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.671643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.671661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.671677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.671693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.671708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.671722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.671748] [drm:intel_power_well_disable [i915]] disabling display
>[  755.671769] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.671785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.671801] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.671819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.671833] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.672203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.672229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.672257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.672286] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.672311] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.672337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.672363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.672388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.672413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.672436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.672460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.672466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.672489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.672495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.672519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.672542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.672566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.672589] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.672615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.672638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.672660] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.672683] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.672714] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.672738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.672763] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.672826] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.672849] [drm:intel_power_well_enable [i915]] enabling display
>[  755.672871] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.672927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.672953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.672977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.673000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.673022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.673046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.673073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.673097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.673122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.673144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.673167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.673192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.673216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.675210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.675226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.675240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.675255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.676765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.676783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.676797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.678288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.678304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.680107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.683045] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.683117] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.683136] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.683162] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.683213] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.683240] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.683308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.683333] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.683365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.733282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.733305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.733326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.733349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.733369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.733390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.733411] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.733431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.733451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.733472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.733491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.733496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.733516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.733519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.733540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.733561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.733581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.733601] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.733621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.733641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.733662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.733683] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.733703] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.733724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.733746] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.749897] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.749938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.749982] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.767850] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.767873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.767893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.767958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.767984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.768010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.768034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.768057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.768081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.768108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.768134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.768160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.768181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.768204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.768246] [drm:intel_power_well_disable [i915]] disabling display
>[  755.768279] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.768304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.768330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.768357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.768381] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.768716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.768734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.768753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.768772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.768788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.768805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.768822] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.768841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.768860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.768879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.768926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.768932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.768958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.768972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.768995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.769016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.769038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.769058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.769083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.769103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.769126] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.769146] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.769168] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.769191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.769216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.769280] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.769304] [drm:intel_power_well_enable [i915]] enabling display
>[  755.769326] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.769361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.769382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.769404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.769423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.769444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.769464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.769487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.769510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.769533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.769552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.769572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.769594] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.769616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.771619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.771636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.771650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.771665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.773172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.773188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.773201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.774696] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.774712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.776523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.779460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.779533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.779550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.779572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.779621] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.779647] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.779713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.779740] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.779772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.829716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.829738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.829760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.829783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.829803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.829824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.829845] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.829865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.829886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.829976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.830092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.830099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.830124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.830130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.830154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.830179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.830203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.830224] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.830251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.830275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.830300] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.830324] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.830347] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.830374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.830402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.846347] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.846372] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.846408] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.864662] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.864683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.864700] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.864720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.864737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.864753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.864769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.864784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.864803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.864824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.864845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.864865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.864884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.864946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.864989] [drm:intel_power_well_disable [i915]] disabling display
>[  755.865024] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.865150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.865178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.865208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.865233] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.865527] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.865543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.865560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.865578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.865592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.865607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.865622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.865637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.865651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.865664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.865677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.865680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.865697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.865700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.865718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.865736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.865753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.865770] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.865788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.865805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.865823] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.865840] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.865858] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.865876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.865895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.865981] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.866005] [drm:intel_power_well_enable [i915]] enabling display
>[  755.866028] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.866068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.866093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.866117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.866141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.866163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.866188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.866413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.866437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.866462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.866484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.866505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.866530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.866554] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.868546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.868563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.868578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.868593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.870092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.870108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.870121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.871615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.871631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.873437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.876374] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.876447] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.876464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.876486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.876533] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.876559] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.876632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.876657] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.876687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.926615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.926636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.926656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.926678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.926698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.926719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.926739] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.926760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.926780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.926801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.926821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.926825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.926845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.926849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.926869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.926889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.926952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.926978] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.927006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.927029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.927055] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.927078] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.927103] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.927128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.927156] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.943227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  755.943253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  755.943299] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  755.961784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  755.961806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  755.961822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  755.961842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.961858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.961874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.961889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.961951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.961975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.962005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.962032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.962059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.962082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.962106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.962151] [drm:intel_power_well_disable [i915]] disabling display
>[  755.962185] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  755.962210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.962236] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.962265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.962289] [drm:intel_power_well_disable [i915]] disabling always-on
>[  755.962623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  755.962650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  755.962678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  755.962708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  755.962738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  755.962762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  755.962786] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  755.962809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  755.962832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  755.962854] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  755.962883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  755.962889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.962934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  755.962941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  755.962965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  755.962987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  755.963010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  755.963029] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  755.963054] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  755.963076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  755.963099] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  755.963119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  755.963141] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  755.963166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  755.963191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  755.963258] [drm:intel_power_well_enable [i915]] enabling always-on
>[  755.963281] [drm:intel_power_well_enable [i915]] enabling display
>[  755.963303] [drm:hsw_set_power_well [i915]] Enabling power well
>[  755.963339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  755.963362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  755.963384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  755.963407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  755.963428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  755.963450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  755.963475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  755.963498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  755.963522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  755.963543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  755.963565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  755.963589] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  755.963612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  755.965611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  755.965628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  755.965644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.965663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  755.967173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  755.967191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  755.967208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  755.968703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  755.968720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  755.970531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  755.973480] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  755.973540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  755.973557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  755.973579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  755.973628] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  755.973654] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  755.973720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  755.973746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  755.973779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.023729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.023748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.023767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.023789] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.023808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.023828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.023847] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.023866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.023885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.023904] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.023966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.023973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.023997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.024004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.024030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.024053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.024076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.024099] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.024119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.024134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.024150] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.024165] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.024179] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.024196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.024215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.040322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.040346] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.040390] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.059259] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.059283] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.059302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.059325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.059344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.059363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.059383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.059402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.059421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.059442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.059462] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.059483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.059501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.059518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.059545] [drm:intel_power_well_disable [i915]] disabling display
>[  756.059568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.059588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.059608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.059630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.059645] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.059882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.059899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.059959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.059985] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.060006] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.060029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.060052] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.060073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.060094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.060115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.060134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.060141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.060160] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.060165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.060185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.060206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.060227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.060246] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.060269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.060289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.060311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.060332] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.060353] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.060377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.060402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.060468] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.060491] [drm:intel_power_well_enable [i915]] enabling display
>[  756.060513] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.060545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.060560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.060574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.060587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.060600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.060615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.060630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.060645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.060659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.060672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.060685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.060702] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.060716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.062693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.062710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.062727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.062746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.064256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.064272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.064287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.065781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.065797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.067608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.070536] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.070565] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.070582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.070603] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.070651] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.070677] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.070743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.070771] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.070807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.120734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.120754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.120775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.120798] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.120819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.120839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.120860] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.120880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.120901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.120961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.120986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.120992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.121016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.121023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.121048] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.121071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.121094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.121117] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.121138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.121158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.121178] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.121198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.121217] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.121237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.121259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.137350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.137376] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.137421] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.156262] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.156284] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.156300] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.156320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.156336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.156352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.156367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.156382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.156398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.156415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.156431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.156447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.156461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.156476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.156502] [drm:intel_power_well_disable [i915]] disabling display
>[  756.156525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.156546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.156566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.156589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.156604] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.156884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.156902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.156964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.156991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.157012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.157035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.157058] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.157080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.157101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.157121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.157141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.157147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.157166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.157172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.157192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.157211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.157231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.157250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.157272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.157291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.157312] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.157333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.157354] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.157377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.157400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.157450] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.157464] [drm:intel_power_well_enable [i915]] enabling display
>[  756.157477] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.157501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.157515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.157529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.157542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.157555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.157569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.157584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.157599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.157614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.157627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.157640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.157655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.157671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.159643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.159660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.159674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.159689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.161194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.161209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.161223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.162717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.162732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.164541] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.167465] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.167499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.167515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.167537] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.167585] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.167611] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.167677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.167703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.167735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.217663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.217684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.217705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.217725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.217742] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.217760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.217780] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.217801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.217821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.217842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.217862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.217866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.217886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.217890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.217910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.217968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.217993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.218017] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.218042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.218065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.218089] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.218112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.218133] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.218158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.218186] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.234281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.234305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.234349] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.253216] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.253237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.253257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.253278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.253298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.253317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.253337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.253356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.253375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.253396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.253417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.253437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.253456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.253475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.253503] [drm:intel_power_well_disable [i915]] disabling display
>[  756.253525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.253545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.253566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.253588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.253603] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.253856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.253876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.253896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.253918] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.253983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.254014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.254042] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.254069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.254100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.254121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.254143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.254150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.254172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.254178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.254200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.254222] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.254244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.254266] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.254291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.254313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.254337] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.254358] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.254380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.254405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.254430] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.254496] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.254520] [drm:intel_power_well_enable [i915]] enabling display
>[  756.254542] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.254579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.254602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.254624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.254646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.254668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.254690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.254715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.254737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.254761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.254782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.254803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.254829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.254852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.256856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.256872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.256886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.256902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.258436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.258452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.258466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.260075] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.260091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.261960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.264895] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.265003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.265029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.265067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.265195] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.265221] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.265289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.265324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.265355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.315125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.315146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.315166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.315187] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.315204] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.315222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.315240] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.315257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.315277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.315299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.315319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.315323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.315343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.315346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.315367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.315388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.315408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.315428] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.315448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.315468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.315489] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.315510] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.315530] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.315551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.315573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.331752] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.331776] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.331820] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.350708] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.350730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.350746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.350766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.350782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.350798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.350812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.350827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.350843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.350860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.350876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.350891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.350905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.350919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.350994] [drm:intel_power_well_disable [i915]] disabling display
>[  756.351030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.351056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.351084] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.351113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.351137] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.351488] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.351504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.351521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.351539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.351555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.351573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.351591] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.351608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.351626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.351644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.351661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.351664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.351682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.351685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.351703] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.351720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.351737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.351754] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.351772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.351789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.351807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.351824] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.351842] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.351860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.351879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.351921] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.351969] [drm:intel_power_well_enable [i915]] enabling display
>[  756.351994] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.352035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.352061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.352085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.352108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.352131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.352155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.352181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.352206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.352231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.352253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.352273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.352299] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.352322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.354320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.354336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.354350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.354365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.355883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.355906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.355927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.357463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.357479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.359292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.362238] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.362301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.362318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.362340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.362380] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.362397] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.362441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.362462] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.362494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.412468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.412489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.412509] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.412530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.412547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.412565] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.412583] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.412600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.412617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.412636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.412657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.412661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.412681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.412685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.412706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.412726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.412746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.412766] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.412787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.412807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.412828] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.412848] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.412868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.412890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.412911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.429081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.429104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.429139] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.447994] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.448016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.448032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.448051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.448068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.448083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.448098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.448113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.448129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.448146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.448166] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.448187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.448206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.448225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.448253] [drm:intel_power_well_disable [i915]] disabling display
>[  756.448275] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.448296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.448316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.448338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.448354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.448603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.448629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.448647] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.448666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.448680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.448696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.448712] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.448726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.448741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.448754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.448767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.448771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.448784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.448787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.448800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.448813] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.448825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.448837] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.448855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.448872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.448890] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.448908] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.448925] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.448981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.449007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.449071] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.449095] [drm:intel_power_well_enable [i915]] enabling display
>[  756.449118] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.449155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.449176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.449199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.449220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.449241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.449261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.449286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.449311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.449334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.449353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.449373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.449396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.449418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.451417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.451435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.451453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.451471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.453001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.453017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.453032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.454529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.454545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.456353] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.459303] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.459362] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.459379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.459401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.459439] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.459456] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.459500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.459521] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.459553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.509508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.509528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.509546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.509566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.509581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.509598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.509615] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.509631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.509646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.509661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.509674] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.509678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.509692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.509696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.509710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.509724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.509737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.509751] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.509767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.509781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.509795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.509809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.509823] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.509839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.509856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.526144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.526167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.526202] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.545062] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.545084] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.545100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.545122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.545142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.545161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.545181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.545200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.545219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.545240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.545261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.545281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.545300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.545316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.545344] [drm:intel_power_well_disable [i915]] disabling display
>[  756.545367] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.545387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.545407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.545430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.545445] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.545684] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.545704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.545724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.545745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.545764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.545784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.545803] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.545822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.545842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.545861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.545886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.545890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.545905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.545908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.545923] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.545937] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.545995] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.546016] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.546041] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.546062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.546086] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.546106] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.546128] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.546153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.546179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.546242] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.546265] [drm:intel_power_well_enable [i915]] enabling display
>[  756.546287] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.546323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.546344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.546366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.546385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.546406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.546426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.546449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.546472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.546495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.546514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.546534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.546556] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  756.546578] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.548586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.548603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.548617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.548632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.550141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.550157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.550171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.551665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.551681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.553492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.556430] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  756.556500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.556515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  756.556535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.556570] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  756.556586] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  756.556626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.556645] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.556675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.606666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.606687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.606707] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.606728] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.606745] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.606763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.606782] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  756.606800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  756.606821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.606841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.606861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.606865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.606885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.606889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.606909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.606930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.606992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.607017] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  756.607042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.607066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.607091] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.607113] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  756.607136] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  756.607161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.607189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  756.623287] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  756.623313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.623350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  756.642207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  756.642228] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  756.642244] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.642263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.642280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.642295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.642310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.642325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.642341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.642357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.642373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.642389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.642403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.642417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.642444] [drm:intel_power_well_disable [i915]] disabling display
>[  756.642465] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.642481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.642498] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.642515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.642529] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.642633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.642666] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.642684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.642699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.642715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.642729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.642743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.642758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.642774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.642790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.642806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.642821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.642835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.642849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.642870] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  756.642886] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.643110] [drm:drm_mode_addfb2] [FB:75]
>[  756.643133] [drm:drm_mode_addfb2] [FB:78]
>[  756.666021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  756.666099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  756.666149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  756.666196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  756.666205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  756.666251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.666268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.666286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.666304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.666319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.666334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.666350] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.666364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.666378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.666395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.666413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.666417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.666434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.666437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.666455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.666472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.666490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.666507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.666525] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.666542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.666560] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  756.666577] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.666594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.666613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.666633] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.669258] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.669275] [drm:intel_power_well_enable [i915]] enabling display
>[  756.669291] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.669322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.669342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.669361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.669380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.669398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.669417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.669438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.669458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.669478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.669498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.669522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.669541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  756.669556] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.671555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.671572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.671593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.671608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.673110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.673125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.673139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.674633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.674649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.676460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.679396] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  756.679470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.679487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  756.679510] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.696214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.696240] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.696278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.713039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.713058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.713077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.713096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.713112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.713129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.713146] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.713165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.713184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.713203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.713222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.713226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.713245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.713249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.713268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.713288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.713306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.713325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.713344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.713363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.713383] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.713402] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.713421] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.713450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.713475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.713530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  756.713551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.713597] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  756.730423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  756.730442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.730463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.730480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.730496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.730511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.730526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.730542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.730559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.730575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.730591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.730605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.730619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.730646] [drm:intel_power_well_disable [i915]] disabling display
>[  756.730668] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.730683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.730700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.730715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.730729] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.730840] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.730856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.730874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.730893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.730909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.730925] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.730942] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.731000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.731025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.731058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.731080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.731087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.731108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.731114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.731136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.731158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.731181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.731202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.731227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.731248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.731272] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.731294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.731316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.731341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.731366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.731433] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.731455] [drm:intel_power_well_enable [i915]] enabling display
>[  756.731477] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.731515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.731538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.731559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.731580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.731600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.731622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.731646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.731670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.731694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.731715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.731734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.731759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  756.731782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.733780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.733796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.733810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.733825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.735346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.735363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.735378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.736905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.736922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.738735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.741671] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  756.741745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.741762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  756.741784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.741843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.741865] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.741898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.791914] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.791936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.791957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.792022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.792045] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.792065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.792085] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.792104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.792124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.792143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.792163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.792168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.792187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.792191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.792211] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.792230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.792250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.792270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.792290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.792308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.792328] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.792348] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.792368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.792389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.792410] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.792467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  756.792492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.792539] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  756.809364] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  756.809383] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.809403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.809420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.809439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.809459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.809478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.809497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.809518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.809538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.809558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.809577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.809596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.809623] [drm:intel_power_well_disable [i915]] disabling display
>[  756.809645] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.809665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.809685] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.809706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.809721] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.810194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.810212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.810230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.810249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.810267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.810286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.810304] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.810320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.810338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.810356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.810373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.810377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.810392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.810395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.810413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.810431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.810449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.810466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.810485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.810501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.810521] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.810538] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.810556] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.810575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.810594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.810637] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.810651] [drm:intel_power_well_enable [i915]] enabling display
>[  756.810665] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.810693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.810711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.810730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.810748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.810765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.810783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.810803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.810823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.810842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.810859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.810877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.810895] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  756.810913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.812907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.812924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.812938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.812957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.814562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.814577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.814591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.816084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.816100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.817898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.819887] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  756.819946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.819995] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  756.820033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.820116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.820148] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.820203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.870111] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.870132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.870152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.870176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.870196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.870217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.870237] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.870258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.870278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.870299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.870319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.870323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.870343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.870347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.870367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.870388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.870408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.870428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.870448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.870468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.870489] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.870510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.870530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.870551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.870573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.870631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  756.870656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.870692] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  756.887532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  756.887551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.887571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.887588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.887604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.887619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.887633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.887649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.887667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.887682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.887698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.887712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.887726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.887753] [drm:intel_power_well_disable [i915]] disabling display
>[  756.887774] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.887790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.887806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.887822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.887836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.888417] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.888437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.888457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.888478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.888496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.888515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.888534] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.888552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.888571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.888590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.888608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.888612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.888630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.888634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.888652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.888671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.888689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.888708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.888726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.888744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.888763] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.888782] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.888800] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.888819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.888839] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.888882] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.888896] [drm:intel_power_well_enable [i915]] enabling display
>[  756.888911] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.888947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.888989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.889013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.889035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.889055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.889078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.889102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.889125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.889148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.889167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.889188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.889212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  756.889233] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.891228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.891244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.891258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.891273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.892775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.892790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.892803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.894300] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.894316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.896128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.899078] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  756.899136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.899152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  756.899172] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.899225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.899245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.899275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.949308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.949330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.949352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.949375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.949395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.949416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.949436] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.949456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.949477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.949497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.949517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.949521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.949541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.949545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.949566] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.949586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.949606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.949626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.949646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.949666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.949687] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.949707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.949727] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.949748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.949770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.949827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  756.949851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  756.949888] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  756.966729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  756.966748] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  756.966769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.966786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.966801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.966816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.966831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.966847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.966864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.966880] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.966899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.966918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.966937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.967005] [drm:intel_power_well_disable [i915]] disabling display
>[  756.967042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  756.967071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.967098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.967126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.967143] [drm:intel_power_well_disable [i915]] disabling always-on
>[  756.967351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  756.967369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  756.967387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  756.967407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  756.967423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  756.967439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  756.967456] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  756.967471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  756.967486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  756.967501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  756.967519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  756.967524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.967543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  756.967547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  756.967567] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  756.967586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  756.967606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  756.967625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  756.967644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  756.967663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  756.967683] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  756.967702] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  756.967729] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  756.967747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  756.967766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  756.967808] [drm:intel_power_well_enable [i915]] enabling always-on
>[  756.967822] [drm:intel_power_well_enable [i915]] enabling display
>[  756.967836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  756.967864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  756.967882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  756.967900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  756.967919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  756.967937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  756.967955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  756.967999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  756.968024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  756.968048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  756.968068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  756.968087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  756.968111] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  756.968133] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  756.970129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  756.970146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  756.970160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.970175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  756.971679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  756.971694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  756.971708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  756.973205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  756.973221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  756.975029] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  756.977956] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  756.978039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  756.978056] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  756.978077] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  756.978138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  756.978160] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  756.978193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.028204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.028224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.028244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.028268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.028289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.028310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.028330] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.028350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.028371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.028391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.028411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.028415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.028435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.028439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.028460] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.028480] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.028500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.028520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.028540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.028560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.028581] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.028602] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.028622] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.028643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.028666] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.028726] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.028751] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.028788] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.045622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.045641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.045661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.045678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.045694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.045709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.045724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.045740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.045760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.045781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.045801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.045820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.045837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.045864] [drm:intel_power_well_disable [i915]] disabling display
>[  757.045887] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.045906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.045927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.045948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.045963] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.046341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.046360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.046379] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.046401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.046421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.046442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.046461] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.046487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.046502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.046517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.046531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.046535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.046549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.046552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.046565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.046579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.046591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.046604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.046619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.046633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.046646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.046659] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.046672] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.046687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.046705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.046755] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.046769] [drm:intel_power_well_enable [i915]] enabling display
>[  757.046782] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.046807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.046822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.046836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.046849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.046862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.046876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.046892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.046906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.046921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.046934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.046946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.046965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.047009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.049002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.049018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.049032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.049047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.050551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.050567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.050581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.052094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.052112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.053921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.056867] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.056931] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.056948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.056969] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.057194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.057217] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.057250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.107087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.107108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.107129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.107152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.107172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.107193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.107214] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.107234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.107255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.107275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.107295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.107299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.107319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.107323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.107344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.107364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.107384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.107404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.107425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.107444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.107465] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.107486] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.107506] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.107535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.107562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.107616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.107637] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.107671] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.125740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.125758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.125778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.125796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.125811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.125826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.125841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.125856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.125873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.125889] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.125905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.125919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.125933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.125959] [drm:intel_power_well_disable [i915]] disabling display
>[  757.126023] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.126051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.126079] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.126107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.126132] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.126549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.126566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.126583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.126601] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.126615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.126631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.126646] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.126660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.126675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.126688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.126701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.126705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.126718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.126721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.126734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.126747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.126760] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.126772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.126787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.126800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.126814] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.126827] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.126839] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.126854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.126870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.126909] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.126922] [drm:intel_power_well_enable [i915]] enabling display
>[  757.126935] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.126959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.126999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.127019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.127043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.127063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.127086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.127112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.127137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.127161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.127181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.127202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.127228] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.127250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.129529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.129545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.129559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.129575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.131103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.131120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.131135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.132635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.132651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.134474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.137411] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.137488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.137504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.137524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.137577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.137597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.137627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.187648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.187669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.187688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.187709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.187726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.187744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.187762] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.187779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.187795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.187811] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.187830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.187835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.187855] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.187859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.187880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.187900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.187920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.187940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.187961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.187981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.188041] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.188068] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.188094] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.188120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.188148] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.188234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.188265] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.188317] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.205140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.205159] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.205179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.205197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.205216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.205235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.205255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.205274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.205295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.205315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.205336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.205355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.205371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.205398] [drm:intel_power_well_disable [i915]] disabling display
>[  757.205421] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.205440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.205461] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.205482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.205497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.205749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.205769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.205788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.205810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.205829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.205849] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.205868] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.205887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.205907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.205925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.205944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.205948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.205967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.206013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.206041] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.206064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.206088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.206109] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.206134] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.206155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.206178] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.206199] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.206221] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.206246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.206272] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.206338] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.206360] [drm:intel_power_well_enable [i915]] enabling display
>[  757.206382] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.206419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.206441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.206461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.206482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.206501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.206523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.206547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.206570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.206593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.206612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.206632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.206655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.206677] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.208671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.208688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.208703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.208718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.210223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.210238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.210252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.211747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.211763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.213573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.216519] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.216582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.216599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.216621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.216675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.216697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.216730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.266744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.266764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.266785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.266806] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.266823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.266841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.266859] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.266879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.266900] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.266920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.266940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.266944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.266964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.266968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.267027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.267052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.267075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.267097] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.267122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.267145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.267169] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.267191] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.267212] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.267237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.267265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.267327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.267347] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.267393] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.283990] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.284027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.284048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.284065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.284080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.284095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.284110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.284128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.284149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.284170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.284191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.284210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.284228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.284256] [drm:intel_power_well_disable [i915]] disabling display
>[  757.284279] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.284298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.284319] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.284340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.284355] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.284600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.284620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.284640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.284662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.284681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.284701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.284720] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.284739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.284758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.284777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.284796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.284800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.284818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.284822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.284841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.284867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.284884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.284898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.284914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.284928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.284943] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.284956] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.284969] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.285014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.285039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.285106] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.285129] [drm:intel_power_well_enable [i915]] enabling display
>[  757.285152] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.285190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.285214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.285238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.285261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.285284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.285306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.285332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.285356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.285380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.285401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.285423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.285447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.285471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.287477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.287493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.287507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.287522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.289049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.289063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.289077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.290581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.290599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.292409] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.294693] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.294762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.294778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.294800] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.294857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.294879] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.294911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.344927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.344948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.344968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.344989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.345046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.345073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.345103] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.345129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.345155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.345327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.345343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.345347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.345361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.345365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.345380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.345394] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.345409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.345422] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.345439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.345453] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.345468] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.345486] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.345506] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.345526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.345547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.345603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.345626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.345661] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.363751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.363770] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.363790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.363807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.363826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.363845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.363865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.363884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.363905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.363925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.363945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.363964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.363981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.364056] [drm:intel_power_well_disable [i915]] disabling display
>[  757.364091] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.364280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.364310] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.364338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.364362] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.364640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.364657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.364674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.364692] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.364706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.364721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.364736] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.364751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.364768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.364785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.364803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.364807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.364824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.364827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.364845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.364862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.364879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.364897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.364914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.364931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.364950] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.364967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.364985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.365037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.365065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.365130] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.365338] [drm:intel_power_well_enable [i915]] enabling display
>[  757.365360] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.365400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.365424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.365447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.365470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.365492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.365515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.365541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.365565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.365590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.365611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.365633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.365658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.365681] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.367674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.367692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.367706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.367722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.369242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.369260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.369274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.370770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.370786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.372597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.375534] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.375607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.375624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.375646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.375703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.375725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.375757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.425764] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.425784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.425805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.425826] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.425843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.425863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.425884] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.425904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.425925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.425945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.425965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.425969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.425989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.426031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.426062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.426090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.426117] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.426143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.426171] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.426196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.426224] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.426248] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.426273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.426302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.426330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.426624] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.426656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.426707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.443529] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.443548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.443569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.443585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.443601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.443616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.443630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.443646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.443663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.443680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.443696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.443710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.443724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.443750] [drm:intel_power_well_disable [i915]] disabling display
>[  757.443772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.443788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.443805] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.443821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.443835] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.444372] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.444400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.444427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.444457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.444481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.444507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.444539] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.444562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.444585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.444606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.444628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.444634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.444654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.444660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.444681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.444702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.444722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.444742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.444765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.444787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.444809] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.444831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.444850] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.444873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.444898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.444963] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.444985] [drm:intel_power_well_enable [i915]] enabling display
>[  757.445029] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.445068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.445092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.445116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.445138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.445161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.445185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.445210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.445235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.445259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.445281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.445303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.445329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.445526] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.447536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.447552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.447565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.447580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.449105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.449123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.449137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.450635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.450652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.452461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.455407] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.455470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.455487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.455509] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.455568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.455592] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.455628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.505627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.505648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.505668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.505689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.505706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.505724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.505742] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.505759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.505776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.505792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.505807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.505811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.505826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.505830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.505845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.505860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.505875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.505890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.505907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.505926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.505948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.505968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.505988] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.506050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.506078] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.506355] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.506386] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.506438] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.522703] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.522721] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.522742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.522759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.522775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.522790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.522805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.522821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.522838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.522854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.522870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.522884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.522898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.522924] [drm:intel_power_well_disable [i915]] disabling display
>[  757.522945] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.522961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.522977] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.522997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.523057] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.523558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.523574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.523591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.523610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.523627] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.523645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.523662] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.523680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.523698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.523715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.523732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.523736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.523753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.523756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.523774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.523792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.523809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.523826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.523844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.523861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.523879] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.523896] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.523914] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.523932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.523950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.523991] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.524038] [drm:intel_power_well_enable [i915]] enabling display
>[  757.524061] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.524102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.524127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.524153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.524176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.524199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.524224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.524250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.524275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.524299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.524322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.524343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.524581] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.524605] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.526600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.526616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.526630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.526645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.528160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.528177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.528192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.529690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.529707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.531518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.534466] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.534527] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.534544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.534565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.534643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.534674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.534720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.584725] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.584746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.584766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.584787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.584803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.584821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.584839] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.584856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.584873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.584888] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.584904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.584908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.584923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.584926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.584942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.584957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.584975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.584995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.585056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.585080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.585104] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.585126] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.585147] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.585172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.585198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.585282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.585304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.585347] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.602162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.602181] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.602202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.602219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.602234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.602249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.602264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.602283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.602304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.602324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.602345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.602363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.602382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.602410] [drm:intel_power_well_disable [i915]] disabling display
>[  757.602432] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.602452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.602472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.602493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.602508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.602750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.602770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.602790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.602812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.602831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.602850] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.602869] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.602888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.602908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.602927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.602945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.602949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.602968] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.602972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.602991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.603059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.603082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.603103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.603126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.603147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.603170] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.603190] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.603210] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.603233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.603257] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.603508] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.603523] [drm:intel_power_well_enable [i915]] enabling display
>[  757.603537] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.603565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.603583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.603601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.603619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.603636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.603654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.603674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.603693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.603713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.603730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.603748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.603767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.603785] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.605767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.605784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.605799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.605814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.607316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.607334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.607351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.608848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.608865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.610675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.613600] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.613632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.613649] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.613671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.613728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.613752] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.613788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.663796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.663817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.663837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.663858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.663875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.663893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.663911] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.663928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.663944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.663960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.663975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.663979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.663994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.664036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.664064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.664089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.664114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.664138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.664163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.664187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.664214] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.664238] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.664262] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.664290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.664318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.664401] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.664432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.664483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.681304] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.681323] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.681343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.681360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.681376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.681395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.681415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.681434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.681455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.681475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.681496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.681515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.681531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.681559] [drm:intel_power_well_disable [i915]] disabling display
>[  757.681581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.681601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.681621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.681642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.681657] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.681871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.681888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.681905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.681925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.681942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.681960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.681978] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.681995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.682057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.682080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.682105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.682111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.682134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.682140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.682163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.682186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.682209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.682231] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.682256] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.682278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.682302] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.682324] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.682346] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.682371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.682397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.682708] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.682732] [drm:intel_power_well_enable [i915]] enabling display
>[  757.682754] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.682792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.682816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.682838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.682861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.682880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.682903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.682928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.682952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.682976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.682997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.683037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.683062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.683086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.685206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.685222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.685236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.685251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.686757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.686773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.686787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.688284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.688300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.690102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.693047] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.693110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.693126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.693147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.693200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.693220] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.693250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.743276] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.743296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.743316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.743337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.743353] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.743372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.743390] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.743407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.743424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.743440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.743456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.743460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.743475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.743478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.743494] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.743509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.743524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.743538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.743556] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.743571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.743587] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.743602] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.743616] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.743634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.743655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.743714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.743739] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.743776] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.761784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.761803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.761823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.761840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.761856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.761871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.761885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.761901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.761918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.761935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.761951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.761965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.761979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.762005] [drm:intel_power_well_disable [i915]] disabling display
>[  757.762075] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.762104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.762132] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.762159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.762184] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.762646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.762662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.762679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.762696] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.762711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.762726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.762741] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.762756] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.762770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.762783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.762795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.762799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.762812] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.762815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.762828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.762840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.762857] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.762875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.762893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.762910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.762928] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.762945] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.762963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.762981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.763000] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.763086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.763109] [drm:intel_power_well_enable [i915]] enabling display
>[  757.763132] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.763172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.763388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.763413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.763436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.763459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.763482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.763508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.763532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.763556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.763578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.763600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.763625] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.763648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.765658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.765675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.765690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.765707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.767218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.767236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.767253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.768749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.768766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.770578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.773516] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.773587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.773604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.773626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.773690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.773710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.773740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.823733] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.823755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.823777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.823800] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.823820] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.823841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.823862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.823882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.823902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.823922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.823942] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.823946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.823966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.823970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.823990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.824011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.824072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.824102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.824132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.824159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.824187] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.824212] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.824238] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.824266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.824295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.824377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.824407] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.824458] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.841280] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.841299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.841319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.841336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.841352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.841367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.841382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.841398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.841414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.841430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.841446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.841460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.841475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.841501] [drm:intel_power_well_disable [i915]] disabling display
>[  757.841523] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.841543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.841563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.841584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.841599] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.841838] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.841858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.841878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.841900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.841919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.841939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.841958] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.841977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.841996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.842015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.842078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.842085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.842112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.842119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.842146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.842171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.842197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.842221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.842249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.842274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.842299] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.842323] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.842348] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.842375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.842404] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.842724] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.842747] [drm:intel_power_well_enable [i915]] enabling display
>[  757.842769] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.842808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.842831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.842854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.842877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.842899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.842920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.842944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.842968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.842992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.843013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.843054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.843078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.843103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.845271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.845289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.845306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.845324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.846831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.846849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.846866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.848365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.848381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.850189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.853134] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.853200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.853219] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.853245] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.853306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.853330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.853366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.903365] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.903387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.903409] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.903432] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.903452] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.903473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.903494] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.903514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.903534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.903554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.903574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.903578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.903598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.903602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.903622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.903643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.903663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.903683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.903703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.903723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.903744] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.903764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.903784] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.903805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.903827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.903885] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.903909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.903947] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  757.920786] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  757.920805] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  757.920825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.920842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.920857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.920872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.920887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.920903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.920921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.920937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.920953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.920967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.920982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.921008] [drm:intel_power_well_disable [i915]] disabling display
>[  757.921080] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  757.921108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.921136] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.921163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.921188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  757.921534] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.921550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.921567] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.921585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.921602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.921620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.921637] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.921655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.921672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.921690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.921707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.921711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.921728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.921731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.921749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.921766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.921784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.921801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.921819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.921836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.921854] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.921871] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.921889] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.921907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.921926] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.921967] [drm:intel_power_well_enable [i915]] enabling always-on
>[  757.921981] [drm:intel_power_well_enable [i915]] enabling display
>[  757.921995] [drm:hsw_set_power_well [i915]] Enabling power well
>[  757.922022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  757.922073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  757.922099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  757.922124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  757.922147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  757.922172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  757.922198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  757.922224] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  757.922248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.922271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  757.922290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  757.922317] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  757.922341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  757.924339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  757.924355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  757.924370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.924385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  757.925889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  757.925905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  757.925918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  757.927415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  757.927431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  757.929238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  757.932160] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  757.932195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  757.932211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  757.932233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  757.932290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  757.932312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  757.932344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  757.982348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  757.982370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  757.982391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  757.982415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  757.982435] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  757.982456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  757.982476] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  757.982497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  757.982517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  757.982537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  757.982557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  757.982561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.982581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  757.982585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  757.982606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  757.982626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  757.982646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  757.982666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  757.982687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  757.982706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  757.982728] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  757.982748] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  757.982768] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  757.982789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  757.982811] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  757.982870] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  757.982894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  757.982932] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.000703] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.000722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.000742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.000759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.000775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.000790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.000805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.000821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.000838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.000854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.000869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.000884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.000898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.000924] [drm:intel_power_well_disable [i915]] disabling display
>[  758.000945] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.000961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.000978] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.000994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.001008] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.001421] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.001444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.001470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.001497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.001519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.001543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.001567] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.001590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.001613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.001635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.001656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.001661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.001682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.001687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.001709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.001730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.001751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.001772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.001796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.001817] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.001839] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.001860] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.001881] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.001905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.001929] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.001993] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.002016] [drm:intel_power_well_enable [i915]] enabling display
>[  758.002060] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.002098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.002122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.002146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.002168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.002191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.002215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.002241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.002266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.002290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.002312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.002334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.002360] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.002383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.004374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.004390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.004404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.004422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.005928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.005943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.005957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.007451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.007466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.009271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.011675] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.011722] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.011739] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.011761] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.011838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.011872] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.011923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.061919] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.061940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.061960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.061984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.062004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.062025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.062085] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.062110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.062134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.062159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.062178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.062183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.062198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.062201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.062216] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.062230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.062244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.062258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.062275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.062289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.062304] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.062318] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.062331] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.062348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.062366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.062420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.062440] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.062482] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.079308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.079327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.079348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.079364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.079380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.079394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.079408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.079424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.079441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.079457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.079472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.079487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.079501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.079527] [drm:intel_power_well_disable [i915]] disabling display
>[  758.079549] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.079565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.079581] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.079598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.079612] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.079814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.079834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.079854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.079876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.079895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.079915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.079940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.079955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.079970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.079983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.079996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.079999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.080012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.080015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.080028] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.080084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.080104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.080123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.080146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.080165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.080186] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.080206] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.080225] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.080248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.080271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.080337] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.080359] [drm:intel_power_well_enable [i915]] enabling display
>[  758.080379] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.080414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.080429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.080443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.080457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.080469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.080483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.080498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.080513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.080527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.080540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.080553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.080568] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.080583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.082569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.082585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.082599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.082614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.084119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.084133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.084147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.085648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.085666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.087475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.090410] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.090485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.090501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.090523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.090599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.090633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.090684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.140630] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.140649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.140668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.140687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.140703] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.140720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.140737] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.140754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.140769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.140784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.140798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.140802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.140815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.140819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.140833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.140852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.140871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.140890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.140910] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.140928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.140948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.140968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.140986] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.141006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.141027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.141137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.141168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.141222] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.158023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.158053] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.158073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.158090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.158106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.158122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.158136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.158152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.158170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.158186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.158202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.158216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.158230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.158258] [drm:intel_power_well_disable [i915]] disabling display
>[  758.158281] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.158301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.158322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.158343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.158358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.158603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.158620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.158638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.158657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.158672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.158688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.158705] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.158720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.158735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.158749] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.158762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.158766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.158780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.158783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.158797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.158811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.158825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.158838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.158854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.158867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.158881] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.158895] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.158908] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.158923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.158940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.158983] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.158996] [drm:intel_power_well_enable [i915]] enabling display
>[  758.159009] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.159035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.159086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.159110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.159134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.159159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.159183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.159210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.159237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.159263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.159286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.159310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.159337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.159362] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.161369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.161385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.161402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.161421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.162929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.162945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.162959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.164455] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.164471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.166281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.169263] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.169291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.169308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.169330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.169391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.169412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.169445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.219462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.219483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.219503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.219524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.219541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.219559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.219577] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.219594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.219610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.219626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.219641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.219645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.219661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.219664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.219679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.219695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.219710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.219724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.219744] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.219765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.219786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.219806] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.219827] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.219848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.219871] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.219928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.219953] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.219991] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.236813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.236832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.236852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.236868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.236887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.236907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.236926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.236945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.236966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.236986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.237007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.237026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.237044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.237121] [drm:intel_power_well_disable [i915]] disabling display
>[  758.237157] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.237187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.237223] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.237250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.237269] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.237536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.237553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.237570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.237591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.237609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.237627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.237645] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.237663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.237681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.237699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.237717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.237720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.237738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.237742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.237760] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.237778] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.237796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.237813] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.237831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.237849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.237868] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.237886] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.237904] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.237923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.237942] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.237985] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.237999] [drm:intel_power_well_enable [i915]] enabling display
>[  758.238013] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.238048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.238095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.238118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.238140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.238161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.238183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.238208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.238239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.238262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.238281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.238301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.238325] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.238346] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.240337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.240355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.240373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.240391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.241897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.241913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.241928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.243422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.243438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.245243] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.248188] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.248253] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.248270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.248292] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.248349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.248371] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.248406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.298418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.298439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.298459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.298480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.298498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.298519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.298539] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.298560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.298581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.298601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.298621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.298625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.298645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.298649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.298669] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.298689] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.298710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.298730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.298750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.298770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.298792] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.298812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.298832] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.298854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.298876] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.298933] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.298958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.298995] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.315807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.315826] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.315846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.315863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.315879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.315894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.315909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.315930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.315956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.315972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.315988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.316002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.316016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.316043] [drm:intel_power_well_disable [i915]] disabling display
>[  758.316114] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.316139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.316167] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.316193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.316218] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.316548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.316569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.316589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.316611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.316630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.316649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.316669] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.316688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.316707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.316726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.316745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.316749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.316767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.316771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.316790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.316810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.316829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.316847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.316866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.316885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.316905] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.316925] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.316944] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.316964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.316985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.317036] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.317083] [drm:intel_power_well_enable [i915]] enabling display
>[  758.317104] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.317144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.317166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.317188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.317209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.317229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.317251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.317275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.317297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.317320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.317339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.317358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.317384] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.317407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.319399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.319417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.319434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.319452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.320958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.320976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.320993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.322490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.322508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.324315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.327266] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.327324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.327340] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.327362] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.327418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.327439] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.327471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.377480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.377501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.377521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.377545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.377565] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.377586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.377607] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.377627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.377647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.377667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.377687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.377691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.377711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.377715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.377736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.377756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.377776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.377796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.377817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.377837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.377858] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.377878] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.377898] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.377919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.377941] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.377998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.378023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.378097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.394922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.394940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.394960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.394977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.394993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.395008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.395023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.395038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.395093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.395120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.395145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.395167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.395190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.395234] [drm:intel_power_well_disable [i915]] disabling display
>[  758.395269] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.395293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.395312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.395329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.395344] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.395648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.395669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.395688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.395715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.395729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.395744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.395760] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.395774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.395788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.395801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.395814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.395818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.395831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.395834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.395851] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.395869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.395886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.395903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.395921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.395938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.395956] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.395973] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.395991] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.396009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.396028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.396116] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.396136] [drm:intel_power_well_enable [i915]] enabling display
>[  758.396157] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.396197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.396219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.396240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.396261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.396283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.396306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.396329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.396354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.396378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.396399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.396420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.396446] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.396469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.398461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.398478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.398492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.398506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.400014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.400032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.400054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.401583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.401601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.403489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.406414] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.406446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.406463] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.406485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.406542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.406563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.406595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.456612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.456632] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.456652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.456676] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.456696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.456717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.456737] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.456757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.456778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.456798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.456818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.456822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.456842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.456846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.456866] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.456887] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.456907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.456927] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.456947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.456967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.456988] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.457008] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.457029] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.457050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.457112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.457194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.457449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.457499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.473748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.473766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.473787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.473804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.473820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.473835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.473850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.473868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.473890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.473911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.473931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.473950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.473966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.473994] [drm:intel_power_well_disable [i915]] disabling display
>[  758.474017] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.474037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.474057] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.474118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.474146] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.474516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.474532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.474549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.474570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.474587] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.474605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.474623] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.474640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.474658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.474675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.474692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.474696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.474713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.474717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.474734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.474752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.474769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.474786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.474804] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.474821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.474839] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.474856] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.474874] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.474892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.474911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.474953] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.474967] [drm:intel_power_well_enable [i915]] enabling display
>[  758.474981] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.475009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.475027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.475044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.475087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.475114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.475137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.475163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.475189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.475214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.475234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.475256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.475282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.475304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.477301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.477318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.477335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.477353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.478860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.478877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.478891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.480390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.480406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.482214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.485123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.485172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.485188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.485210] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.485268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.485289] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.485321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.535320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.535340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.535360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.535381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.535398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.535416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.535434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.535451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.535468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.535484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.535499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.535503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.535518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.535522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.535540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.535561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.535581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.535601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.535622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.535642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.535663] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.535683] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.535704] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.535725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.535747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.535804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.535829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.535866] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.552683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.552703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.552723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.552740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.552756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.552772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.552787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.552803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.552820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.552835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.552851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.552865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.552879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.552905] [drm:intel_power_well_disable [i915]] disabling display
>[  758.552926] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.552942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.552959] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.552974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.552989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.553515] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.553532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.553549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.553567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.553581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.553597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.553612] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.553627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.553641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.553654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.553671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.553675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.553692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.553695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.553713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.553731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.553748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.553765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.553783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.553800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.553818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.553835] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.553853] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.553871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.553889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.553931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.553945] [drm:intel_power_well_enable [i915]] enabling display
>[  758.553958] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.553986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.554004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.554021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.554039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.554056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.554102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.554130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.554157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.554181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.554202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.554224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.554250] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.554272] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.556274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.556291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.556305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.556320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.557827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.557842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.557856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.559353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.559369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.561178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.564110] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.564187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.564203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.564225] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.564282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.564304] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.564336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.614351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.614372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.614392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.614413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.614430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.614449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.614467] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.614484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.614500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.614516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.614532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.614536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.614551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.614555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.614570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.614586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.614605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.614625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.614646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.614666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.614687] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.614707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.614728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.614749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.614771] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.614830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.614855] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.614892] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.632833] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.632854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.632875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.632895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.632915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.632934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.632953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.632972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.632993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.633013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.633033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.633052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.633112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.633155] [drm:intel_power_well_disable [i915]] disabling display
>[  758.633189] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.633383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.633412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.633439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.633463] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.633716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.633736] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.633756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.633778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.633797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.633817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.633836] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.633855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.633874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.633893] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.633912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.633916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.633935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.633938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.633957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.633977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.633996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.634015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.634034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.634053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.634101] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.634129] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.634161] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.634186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.634213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.634277] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.634502] [drm:intel_power_well_enable [i915]] enabling display
>[  758.634523] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.634561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.634583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.634605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.634625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.634646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.634666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.634690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.634713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.634736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.634755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.634775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.634801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.634821] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.636815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.636831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.636845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.636859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.638369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.638387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.638404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.639900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.639917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.641726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.644648] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.644682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.644699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.644720] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.644777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.644798] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.644833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.694842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.694863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.694884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.694908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.694928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.694948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.694969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.694989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.695010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.695030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.695050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.695054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.695108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.695118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.695146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.695170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.695196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.695219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.695246] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.695269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.695295] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.695317] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.695341] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.695368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.695631] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.695715] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.695743] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.695788] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.712613] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.712631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.712651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.712668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.712684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.712699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.712713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.712729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.712746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.712762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.712778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.712792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.712810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.712838] [drm:intel_power_well_disable [i915]] disabling display
>[  758.712860] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.712880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.712901] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.712922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.712936] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.713278] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.713302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.713327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.713355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.713376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.713400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.713423] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.713446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.713467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.713489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.713509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.713515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.713535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.713541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.713562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.713582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.713602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.713622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.713645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.713665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.713687] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.713707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.713728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.713750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.713776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.713839] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.713862] [drm:intel_power_well_enable [i915]] enabling display
>[  758.713884] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.713922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.713945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.713966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.713988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.714008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.714038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.714062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.714096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.714119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.714140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.714162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.714186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.714210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.716204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.716222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.716240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.716258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.717765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.717781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.717796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.719293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.719309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.721118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.724054] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.724133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.724208] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.724235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.724295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.724320] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.724361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.774297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.774317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.774337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.774358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.774375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.774393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.774411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.774428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.774444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.774464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.774484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.774488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.774508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.774512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.774532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.774553] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.774573] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.774593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.774614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.774634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.774655] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.774675] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.774696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.774717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.774739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.774796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.774821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.774858] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.791679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.791698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.791719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.791739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.791759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.791778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.791798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.791817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.791838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.791858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.791879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.791898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.791914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.791941] [drm:intel_power_well_disable [i915]] disabling display
>[  758.791964] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.791984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.792004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.792025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.792040] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.792381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.792400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.792419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.792439] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.792457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.792476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.792496] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.792515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.792535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.792554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.792572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.792576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.792595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.792599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.792619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.792638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.792657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.792676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.792695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.792714] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.792734] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.792753] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.792772] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.792792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.792814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.792859] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.792874] [drm:intel_power_well_enable [i915]] enabling display
>[  758.792889] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.792919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.792939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.792959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.792978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.793005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.793022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.793040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.793055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.793076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.793118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.793139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.793163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.793184] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.795177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.795193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.795207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.795221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.796722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.796739] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.796756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.798256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.798274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.800105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.803005] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.803065] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.803116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.803158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.803334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.803357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.803390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.853489] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.853510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.853530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.853552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.853569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.853587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.853606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.853623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.853640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.853656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.853672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.853677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.853692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.853695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.853711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.853726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.853741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.853755] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.853773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.853788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.853805] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.853819] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.853834] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.853852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.853872] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.853938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.853960] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.853999] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.870783] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.870803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.870823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.870840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.870856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.870872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.870887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.870903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.870921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.870937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.870953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.870968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.870982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.871010] [drm:intel_power_well_disable [i915]] disabling display
>[  758.871031] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.871047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.871064] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.871125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.871153] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.871604] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.871623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.871641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.871662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.871679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.871697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.871715] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.871732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.871750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.871767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.871784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.871788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.871805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.871809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.871826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.871844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.871861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.871878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.871896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.871913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.871931] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.871949] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.871966] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.871985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.872004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.872047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.872061] [drm:intel_power_well_enable [i915]] enabling display
>[  758.872075] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.872167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.872193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.872217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.872240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.872264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.872288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.872314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.872340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.872366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.872388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.872410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.872437] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.872461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.874711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.874728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.874746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.874764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.876472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.876488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.876502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.878163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.878180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.880154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.883054] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.883218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.883243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.883266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.883331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.883353] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.883389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.933286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.933309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.933331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.933354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.933374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.933396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.933416] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.933436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.933457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.933477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.933497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.933502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.933522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.933525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.933546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.933566] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.933587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.933607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.933628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.933647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.933669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.933689] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.933709] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.933731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.933753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.933819] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  758.933845] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  758.933885] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  758.950678] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  758.950697] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  758.950717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.950734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.950753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.950772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.950792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.950811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.950833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.950853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.950874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.950893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.950909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.950938] [drm:intel_power_well_disable [i915]] disabling display
>[  758.950961] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  758.950980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.951001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.951022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.951037] [drm:intel_power_well_disable [i915]] disabling always-on
>[  758.951553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  758.951570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  758.951587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  758.951605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  758.951619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  758.951635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  758.951651] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  758.951665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  758.951680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  758.951693] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  758.951706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  758.951710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.951723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  758.951726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  758.951739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  758.951752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  758.951764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  758.951777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  758.951792] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  758.951805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  758.951818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  758.951831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  758.951843] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  758.951858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  758.951875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  758.951916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  758.951929] [drm:intel_power_well_enable [i915]] enabling display
>[  758.951941] [drm:hsw_set_power_well [i915]] Enabling power well
>[  758.951966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  758.951981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  758.951994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  758.952007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  758.952019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  758.952033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  758.952048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  758.952062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  758.952076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  758.952125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  758.952145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  758.952173] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  758.952196] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  758.954192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  758.954208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  758.954222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.954236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  758.955744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  758.955766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  758.955787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  758.957280] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  758.957296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  758.959118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  758.962066] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  758.962138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  758.962229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  758.962253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  758.962315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  758.962338] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  758.962371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.012294] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.012314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.012334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.012355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.012372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.012390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.012409] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.012429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.012450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.012470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.012490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.012495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.012515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.012519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.012539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.012560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.012580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.012600] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.012620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.012640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.012661] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.012682] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.012702] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.012723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.012745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.012804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.012829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.012866] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.030859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.030878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.030898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.030914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.030930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.030945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.030960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.030976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.030993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.031009] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.031025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.031039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.031053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.031080] [drm:intel_power_well_disable [i915]] disabling display
>[  759.031147] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.031171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.031199] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.031226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.031251] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.031716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.031734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.031752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.031772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.031788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.031805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.031824] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.031843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.031862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.031881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.031900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.031904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.031923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.031926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.031946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.031965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.031984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.032002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.032022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.032040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.032060] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.032079] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.032136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.032164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.032191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.032257] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.032476] [drm:intel_power_well_enable [i915]] enabling display
>[  759.032498] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.032537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.032558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.032580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.032600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.032621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.032642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.032665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.032689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.032712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.032731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.032752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.032774] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.032797] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.034788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.034806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.034823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.034847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.036365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.036384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.036401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.037898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.037915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.039727] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.042659] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.042737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.042757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.042783] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.042844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.042868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.042904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.092882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.092904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.092926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.092949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.092970] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.092990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.093011] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.093031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.093052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.093072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.093092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.093135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.093162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.093168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.093193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.093216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.093241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.093264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.093290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.093314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.093334] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.093348] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.093364] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.093381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.093400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.093454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.093474] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.093517] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.110339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.110358] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.110378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.110395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.110411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.110426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.110441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.110457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.110474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.110490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.110506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.110520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.110538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.110566] [drm:intel_power_well_disable [i915]] disabling display
>[  759.110589] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.110609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.110629] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.110650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.110665] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.110966] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.110983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.111000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.111019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.111037] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.111055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.111073] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.111094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.111152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.111174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.111195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.111201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.111221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.111226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.111247] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.111267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.111287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.111306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.111329] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.111348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.111369] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.111388] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.111408] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.111430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.111454] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.111673] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.111687] [drm:intel_power_well_enable [i915]] enabling display
>[  759.111700] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.111726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.111741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.111756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.111769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.111783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.111797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.111813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.111828] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.111846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.111863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.111882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.111900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.111918] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.113894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.113910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.113925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.113940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.115446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.115461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.115475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.116968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.116984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.118793] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.121731] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.121803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.121820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.121842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.121920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.121955] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.122003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.171970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.171992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.172013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.172037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.172057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.172078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.172098] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.172161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.172187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.172212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.172236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.172243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.172265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.172271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.172294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.172318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.172335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.172349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.172366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.172385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.172405] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.172425] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.172445] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.172465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.172486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.172543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.172566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.172612] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.189433] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.189452] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.189472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.189489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.189505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.189520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.189539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.189558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.189580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.189600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.189621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.189639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.189658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.189686] [drm:intel_power_well_disable [i915]] disabling display
>[  759.189708] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.189728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.189749] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.189770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.189785] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.190100] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.190501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.190521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.190541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.190556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.190573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.190591] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.190607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.190623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.190646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.190659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.190662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.190675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.190678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.190696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.190714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.190731] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.190749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.190766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.190783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.190801] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.190819] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.190836] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.190855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.190873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.190917] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.190931] [drm:intel_power_well_enable [i915]] enabling display
>[  759.190945] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.190973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.190990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.191008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.191026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.191043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.191061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.191080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.191104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.191151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.191176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.191198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.191223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.191247] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.193241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.193257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.193271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.193286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.194787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.194802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.194816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.196313] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.196331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.198134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.201052] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.201092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.201138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.201176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.201263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.201295] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.201346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.251244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.251265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.251285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.251306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.251323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.251341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.251359] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.251380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.251401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.251421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.251441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.251445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.251465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.251469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.251489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.251510] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.251530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.251550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.251570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.251590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.251612] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.251632] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.251652] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.251673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.251695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.251754] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.251778] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.251823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.268644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.268663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.268683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.268700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.268715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.268730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.268745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.268761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.268778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.268793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.268813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.268832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.268849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.268877] [drm:intel_power_well_disable [i915]] disabling display
>[  759.268900] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.268919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.268940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.268960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.268975] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.269494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.269511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.269528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.269546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.269562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.269580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.269597] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.269615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.269633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.269650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.269667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.269671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.269688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.269692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.269709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.269727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.269744] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.269761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.269779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.269796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.269814] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.269831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.269849] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.269867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.269886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.269926] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.269940] [drm:intel_power_well_enable [i915]] enabling display
>[  759.269954] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.269981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.269999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.270017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.270035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.270052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.270070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.270089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.270134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.270159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.270181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.270202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.270226] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.270248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.272241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.272256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.272270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.272285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.273792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.273807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.273821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.275317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.275333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.277140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.280078] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.280186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.280208] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.280232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.280311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.280345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.280394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.330326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.330346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.330366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.330387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.330404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.330425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.330446] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.330466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.330487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.330507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.330527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.330531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.330551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.330555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.330576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.330596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.330616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.330636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.330657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.330677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.330698] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.330718] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.330738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.330760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.330782] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.330840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.330864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.330910] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.347732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.347751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.347771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.347789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.347805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.347820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.347835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.347851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.347869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.347885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.347901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.347915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.347929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.347956] [drm:intel_power_well_disable [i915]] disabling display
>[  759.347977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.347993] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.348010] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.348026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.348040] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.348367] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.348393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.348417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.348436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.348450] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.348466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.348482] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.348496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.348511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.348524] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.348537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.348541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.348553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.348557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.348570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.348583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.348596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.348609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.348624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.348641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.348660] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.348678] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.348696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.348715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.348735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.348778] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.348793] [drm:intel_power_well_enable [i915]] enabling display
>[  759.348806] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.348834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.348853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.348870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.348886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.348904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.348922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.348941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.348960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.348978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.348996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.349014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.349033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.349051] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.351026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.351043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.351058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.351072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.352577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.352592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.352606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.354103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.354131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.355947] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.358885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.358958] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.358974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.358996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.359076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.359110] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.359199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.409138] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.409160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.409182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.409205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.409225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.409246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.409267] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.409287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.409307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.409327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.409347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.409351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.409371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.409375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.409396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.409416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.409436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.409456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.409476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.409496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.409517] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.409537] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.409557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.409579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.409601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.409658] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.409683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.409730] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.426551] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.426570] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.426590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.426607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.426623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.426638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.426657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.426677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.426698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.426718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.426739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.426757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.426773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.426801] [drm:intel_power_well_disable [i915]] disabling display
>[  759.426823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.426843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.426864] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.426884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.426899] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.427210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.427230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.427250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.427269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.427285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.427302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.427320] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.427336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.427352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.427367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.427385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.427390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.427409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.427413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.427433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.427452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.427472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.427492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.427512] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.427531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.427552] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.427572] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.427591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.427612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.427634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.427680] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.427696] [drm:intel_power_well_enable [i915]] enabling display
>[  759.427712] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.427742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.427762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.427781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.427801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.427820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.427840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.427862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.427883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.427903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.427930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.427947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.427966] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.427981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.429959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.429976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.429992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.430010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.431519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.431535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.431549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.433064] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.433080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.434889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.437825] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.437898] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.437915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.437937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.438015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.438050] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.438099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.488067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.488088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.488107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.488173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.488250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.488268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.488286] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.488302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.488318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.488332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.488347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.488351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.488365] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.488369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.488384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.488398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.488413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.488427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.488444] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.488458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.488473] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.488487] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.488502] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.488518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.488536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.488589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.488612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.488655] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.505478] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.505496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.505516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.505533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.505549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.505564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.505583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.505602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.505623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.505644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.505664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.505683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.505702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.505730] [drm:intel_power_well_disable [i915]] disabling display
>[  759.505752] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.505771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.505792] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.505813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.505828] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.506117] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.506183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.506210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.506239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.506262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.506288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.506313] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.506336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.506360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.506384] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.506548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.506552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.506568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.506572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.506588] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.506602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.506617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.506631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.506649] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.506664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.506680] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.506694] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.506708] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.506725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.506744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.506796] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.506809] [drm:intel_power_well_enable [i915]] enabling display
>[  759.506823] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.506848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.506862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.506876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.506890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.506903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.506917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.506933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.506947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.506962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.506974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.506991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.507010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.507029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.509015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.509031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.509046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.509060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.510565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.510580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.510593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.512089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.512105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.513937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.516876] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.516947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.516971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.516992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.517065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.517096] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.517163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.567166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.567186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.567205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.567224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.567240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.567258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.567275] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.567293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.567313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.567332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.567351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.567355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.567374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.567378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.567397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.567416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.567436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.567454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.567473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.567492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.567512] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.567531] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.567550] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.567570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.567591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.567648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.567671] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.567717] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.584538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.584557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.584577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.584594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.584610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.584625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.584640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.584656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.584673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.584688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.584704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.584717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.584731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.584758] [drm:intel_power_well_disable [i915]] disabling display
>[  759.584779] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.584794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.584811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.584827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.584842] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.585082] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.585099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.585117] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.585183] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.585207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.585232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.585256] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.585279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.585302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.585324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.585345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.585352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.585373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.585379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.585401] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.585422] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.585445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.585467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.585491] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.585512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.585538] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.585560] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.585582] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.585608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.585635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.585712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.585735] [drm:intel_power_well_enable [i915]] enabling display
>[  759.585757] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.585784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.585799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.585813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.585826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.585844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.585864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.585888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.585904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.585919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.585932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.585945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.585961] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.585978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.587958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.587974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.587988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.588003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.589512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.589527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.589541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.591037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.591053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.592866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.595800] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.595884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.595899] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.595920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.595993] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.596023] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.596072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.646036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.646058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.646080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.646103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.646123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.646188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.646216] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.646242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.646269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.646292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.646308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.646312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.646327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.646330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.646345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.646359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.646373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.646387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.646404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.646418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.646434] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.646448] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.646463] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.646479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.646498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.646551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.646571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.646614] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.663431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.663450] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.663470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.663487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.663502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.663517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.663532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.663548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.663565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.663581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.663597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.663611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.663625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.663651] [drm:intel_power_well_disable [i915]] disabling display
>[  759.663673] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.663688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.663705] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.663721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.663736] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.663953] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.663970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.663988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.664007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.664023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.664040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.664056] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.664071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.664090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.664110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.664129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.664171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.664195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.664201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.664227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.664249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.664271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.664292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.664317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.664339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.664362] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.664383] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.664404] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.664430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.664462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.664526] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.664546] [drm:intel_power_well_enable [i915]] enabling display
>[  759.664560] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.664585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.664600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.664614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.664628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.664641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.664655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.664670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.664685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.664699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.664712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.664724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.664742] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.664760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.666735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.666752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.666766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.666781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.668293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.668309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.668323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.669815] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.669830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.671635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.674579] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.674653] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.674669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.674690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.674745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.674766] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.674795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.724808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.724829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.724849] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.724869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.724886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.724904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.724923] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.724940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.724956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.724972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.724988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.724992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.725009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.725013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.725034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.725054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.725074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.725095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.725115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.725135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.725201] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.725231] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.725258] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.725288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.725317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.725400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.725431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.725482] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.743345] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.743363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.743383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.743400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.743415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.743430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.743445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.743463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.743484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.743505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.743525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.743544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.743561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.743588] [drm:intel_power_well_disable [i915]] disabling display
>[  759.743611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.743630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.743650] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.743671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.743686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.743994] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.744014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.744035] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.744057] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.744075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.744101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.744118] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.744177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.744202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.744223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.744245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.744252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.744273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.744279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.744301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.744322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.744344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.744363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.744387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.744407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.744431] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.744451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.744473] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.744498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.744523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.744840] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.744862] [drm:intel_power_well_enable [i915]] enabling display
>[  759.744884] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.744922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.744943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.744965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.744985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.745006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.745027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.745059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.745083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.745106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.745125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.745165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.745191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.745212] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.747371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.747387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.747401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.747415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.748918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.748936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.748953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.750449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.750466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.752271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.755209] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.755280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.755296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.755337] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.755417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.755446] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.755492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.805430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.805451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.805471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.805492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.805511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.805532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.805553] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.805573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.805594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.805614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.805634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.805639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.805659] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.805662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.805683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.805704] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.805724] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.805744] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.805764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.805785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.805806] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.805826] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.805847] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.805868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.805890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.805949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.805974] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.806012] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.822802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.822823] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.822845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.822865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.822884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.822904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.822923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.822943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.822964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.822984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.823005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.823023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.823042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.823070] [drm:intel_power_well_disable [i915]] disabling display
>[  759.823093] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.823113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.823133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.823196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.823220] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.823605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.823624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.823643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.823662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.823678] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.823695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.823712] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.823729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.823745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.823760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.823774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.823778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.823792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.823796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.823811] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.823829] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.823851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.823864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.823880] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.823893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.823907] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.823920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.823932] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.823947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.823963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.824004] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.824017] [drm:intel_power_well_enable [i915]] enabling display
>[  759.824030] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.824055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.824069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.824083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.824096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.824109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.824126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.824168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.824193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.824218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.824239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.824261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.824287] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.824309] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.826305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.826321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.826338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.826357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.827865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.827881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.827895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.829392] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.829408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.831214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.834165] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.834224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.834241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.834263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.834322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.834343] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.834375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.884393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.884414] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.884434] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.884455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.884471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.884489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.884508] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.884525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.884541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.884557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.884572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.884576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.884596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.884600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.884621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.884641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.884661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.884682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.884702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.884722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.884743] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.884764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.884784] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.884805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.884827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.884886] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.884910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.884948] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.901762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.901783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.901805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.901825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.901845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.901864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.901883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.901902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.901923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.901944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.901964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.901983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.901999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.902027] [drm:intel_power_well_disable [i915]] disabling display
>[  759.902049] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.902068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.902089] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.902110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.902125] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.902534] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.902558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.902584] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.902611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.902632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.902656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.902677] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.902700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.902721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.902743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.902762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.902768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.902787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.902793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.902814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.902834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.902854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.902873] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.902896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.902915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.902936] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.902955] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.902976] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.902997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.903020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.903083] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.903105] [drm:intel_power_well_enable [i915]] enabling display
>[  759.903127] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.903191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.903214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.903237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.903257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.903279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.903301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.903327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.903352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.903377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.903397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.903418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.903444] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.903466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.905460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.905476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.905490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.905505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.907009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.907025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.907038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.908534] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.908550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.910356] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.913267] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.913312] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.913329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.913351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.913408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.913430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.913462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.963473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.963493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.963513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.963535] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.963555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.963576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.963597] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.963617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.963638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.963658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.963678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.963682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.963702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.963706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.963727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.963747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.963767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.963787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.963807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.963827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.963848] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.963868] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.963888] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.963910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.963931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.963989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  759.964013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  759.964050] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  759.982452] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  759.982471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  759.982492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.982512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.982532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.982551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.982571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.982590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.982611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.982631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.982652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.982671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.982690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.982717] [drm:intel_power_well_disable [i915]] disabling display
>[  759.982740] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  759.982759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.982780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.982801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.982816] [drm:intel_power_well_disable [i915]] disabling always-on
>[  759.983127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  759.983151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  759.983218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  759.983249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  759.983272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  759.983300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  759.983332] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  759.983356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  759.983378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  759.983400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  759.983420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  759.983427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.983448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  759.983454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  759.983476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  759.983496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  759.983518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  759.983538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  759.983562] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  759.983582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  759.983605] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  759.983623] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  759.983643] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  759.983667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  759.983692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  759.983758] [drm:intel_power_well_enable [i915]] enabling always-on
>[  759.983780] [drm:intel_power_well_enable [i915]] enabling display
>[  759.983801] [drm:hsw_set_power_well [i915]] Enabling power well
>[  759.983837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  759.983858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  759.983880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  759.983900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  759.983921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  759.983941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  759.983964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  759.983987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  759.984010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  759.984029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  759.984049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  759.984074] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  759.984095] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  759.986107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  759.986123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  759.986140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.986185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  759.987695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  759.987713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  759.987730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  759.989302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  759.989320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  759.991128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  759.994091] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  759.994136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  759.994195] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  759.994231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  759.994393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  759.994416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  759.994448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.044306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.044327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.044347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.044368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.044385] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.044403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.044421] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  760.044438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  760.044454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.044470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.044485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.044489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.044504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.044508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.044523] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.044538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.044558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.044578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.044599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.044619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.044640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.044660] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  760.044680] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  760.044701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.044723] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  760.044780] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  760.044805] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.044842] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  760.061657] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  760.061678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.061700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.061720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.061739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.061759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.061778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.061797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.061818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.061838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.061859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.061877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.061894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.061922] [drm:intel_power_well_disable [i915]] disabling display
>[  760.061944] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.061963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.061984] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  760.062005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.062020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.062135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.062210] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.062238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.062261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.062286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.062309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.062331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.062355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.062379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.062399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.062414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.062429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.062443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.062456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.062477] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  760.062492] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.062628] [drm:drm_mode_addfb2] [FB:75]
>[  760.062651] [drm:drm_mode_addfb2] [FB:78]
>[  760.088170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  760.088288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  760.088358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  760.088411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  760.088422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  760.088468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.088485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.088503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.088521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.088536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.088552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.088567] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.088583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.088597] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.088614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.088631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.088635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.088652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.088656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.088673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.088691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.088708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.088726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.088743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.088761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.088778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  760.088795] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.088813] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.088831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.088851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.091377] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.091394] [drm:intel_power_well_enable [i915]] enabling display
>[  760.091409] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.091440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.091460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.091479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.091498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.091517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.091535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.091556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.091576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.091596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.091614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.091632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.091652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.091671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.093696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.093714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.093732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.093750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.095264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.095281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.095299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.096794] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.096811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.098622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.101574] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.101632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.101648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.101671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.118374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.118401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.118439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.135197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.135217] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.135235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.135255] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.135271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.135288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.135305] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.135321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.135337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.135352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.135366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.135370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.135388] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.135392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.135412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.135431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.135450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.135469] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.135488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.135507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.135527] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.135546] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.135565] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.135585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.135606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.135653] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.135676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.135725] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.152559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.152578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.152598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.152615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.152631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.152650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.152669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.152688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.152709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.152730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.152750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.152769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.152786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.152813] [drm:intel_power_well_disable [i915]] disabling display
>[  760.152836] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.152856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.152876] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.152897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.152912] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.153033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.153053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.153072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.153094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.153113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.153133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.153152] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.153218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.153248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.153274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.153299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.153307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.153330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.153336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.153361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.153385] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.153409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.153432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.153460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.153484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.153510] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.153534] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.153558] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.153585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.153613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.153688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.153713] [drm:intel_power_well_enable [i915]] enabling display
>[  760.153737] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.153778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.153803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.153829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.153853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.153877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.153902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.153935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.153960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.153983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.154005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.154026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.154051] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.154075] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.156081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.156104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.156126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.156147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.157696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.157711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.157725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.159230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.159246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.161052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.163995] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.164061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.164078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.164100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.164165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.164270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.164320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.214248] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.214268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.214288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.214309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.214326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.214345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.214363] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.214380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.214397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.214413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.214428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.214432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.214447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.214450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.214468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.214489] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.214509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.214530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.214550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.214570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.214591] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.214612] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.214633] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.214654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.214676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.214734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.214759] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.214796] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.231603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.231621] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.231642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.231658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.231677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.231697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.231716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.231735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.231756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.231777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.231797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.231816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.231832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.231860] [drm:intel_power_well_disable [i915]] disabling display
>[  760.231882] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.231902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.231923] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.231943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.231958] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.232227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.232255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.232286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.232316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.232341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.232370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.232396] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.232422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.232447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.232471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.232494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.232501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.232523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.232529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.232553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.232576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.232600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.232623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.232648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.232672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.232697] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.232720] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.232743] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.232770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.232797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.232868] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.232900] [drm:intel_power_well_enable [i915]] enabling display
>[  760.232922] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.232960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.232983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.233005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.233027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.233049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.233069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.233094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.233118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.233142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.233163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.233203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.233230] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.233253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.235249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.235265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.235279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.235294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.236799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.236814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.236828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.238323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.238341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.240151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.242624] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.242665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.242684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.242710] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.242771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.242795] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.242831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.292828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.292848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.292869] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.292889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.292906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.292924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.292943] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.292960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.292976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.292992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.293007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.293011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.293025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.293029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.293044] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.293059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.293074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.293088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.293106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.293121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.293141] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.293162] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.293221] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.293247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.293278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.293361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.293392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.293443] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.310268] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.310287] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.310308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.310325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.310341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.310356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.310371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.310386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.310404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.310423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.310444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.310463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.310480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.310507] [drm:intel_power_well_disable [i915]] disabling display
>[  760.310529] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.310550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.310570] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.310590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.310606] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.310860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.310878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.310896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.310916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.310933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.310951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.310969] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.310991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.311016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.311032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.311046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.311049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.311062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.311065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.311079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.311092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.311104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.311117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.311132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.311145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.311158] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.311212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.311234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.311260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.311286] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.311352] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.311375] [drm:intel_power_well_enable [i915]] enabling display
>[  760.311398] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.311436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.311459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.311483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.311505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.311527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.311549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.311574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.311598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.311621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.311642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.311663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.311689] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.311711] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.313715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.313731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.313745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.313760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.315278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.315293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.315307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.316800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.316818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.318630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.321597] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.321639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.321657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.321678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.321736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.321758] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.321791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.371817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.371837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.371855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.371875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.371890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.371907] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.371923] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.371939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.371955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.371969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.371984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.371988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.372002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.372005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.372020] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.372034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.372048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.372062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.372078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.372092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.372107] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.372121] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.372135] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.372151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.372168] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.372285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.372310] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.372354] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.389169] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.389206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.389226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.389243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.389259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.389274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.389288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.389304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.389321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.389337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.389353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.389367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.389380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.389407] [drm:intel_power_well_disable [i915]] disabling display
>[  760.389428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.389444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.389460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.389476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.389490] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.389711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.389727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.389745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.389765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.389783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.389803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.389822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.389841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.389861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.389880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.389898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.389902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.389921] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.389925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.389944] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.389963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.389982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.390001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.390020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.390038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.390058] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.390077] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.390096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.390116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.390136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.390213] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.390235] [drm:intel_power_well_enable [i915]] enabling display
>[  760.390257] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.390300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.390324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.390348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.390370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.390393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.390416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.390449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.390472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.390495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.390514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.390534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.390559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.390580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.392761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.392779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.392796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.392814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.394326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.394343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.394358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.395853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.395870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.397680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.400645] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.400687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.400705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.400729] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.400807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.400841] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.400887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.450857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.450879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.450900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.450924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.450944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.450964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.450985] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.451005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.451026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.451046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.451066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.451070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.451090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.451094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.451114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.451135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.451155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.451175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.451237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.451263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.451289] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.451312] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.451334] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.451360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.451387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.451468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.451494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.451537] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.468332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.468351] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.468371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.468388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.468404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.468419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.468434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.468450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.468471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.468491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.468512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.468531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.468548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.468576] [drm:intel_power_well_disable [i915]] disabling display
>[  760.468598] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.468618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.468639] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.468659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.468674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.468980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.468999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.469017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.469036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.469052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.469069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.469086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.469102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.469121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.469140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.469159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.469163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.469232] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.469239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.469261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.469282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.469303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.469323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.469345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.469365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.469387] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.469407] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.469427] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.469450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.469473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.469699] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.469713] [drm:intel_power_well_enable [i915]] enabling display
>[  760.469725] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.469752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.469767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.469782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.469796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.469810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.469825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.469840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.469855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.469873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.469891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.469908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.469928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.469945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.471918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.471935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.471949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.471964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.473469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.473484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.473498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.474991] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.475007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.476815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.479755] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.479825] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.479842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.479864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.479942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.479977] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.480027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.529970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.529992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.530013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.530037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.530057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.530078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.530098] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.530119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.530139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.530159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.530179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.530221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.530248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.530254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.530280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.530304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.530328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.530484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.530502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.530518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.530535] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.530550] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.530564] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.530581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.530600] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.530653] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.530674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.530715] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.547536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.547555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.547575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.547592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.547608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.547623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.547642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.547661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.547682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.547702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.547723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.547742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.547765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.547799] [drm:intel_power_well_disable [i915]] disabling display
>[  760.547821] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.547840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.547861] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.547881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.547896] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.548140] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.548160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.548180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.548245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.548271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.548297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.548322] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.548346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.548369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.548391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.548412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.548419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.548440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.548446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.548468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.548491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.548686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.548701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.548718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.548733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.548749] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.548763] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.548777] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.548794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.548812] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.548858] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.548880] [drm:intel_power_well_enable [i915]] enabling display
>[  760.548893] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.548918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.548932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.548946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.548960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.548973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.548986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.549002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.549017] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.549031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.549044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.549056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.549072] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.549087] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.551064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.551081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.551095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.551110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.552617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.552632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.552646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.554145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.554161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.556008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.558950] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.559019] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.559047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.559070] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.559144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.559177] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.559257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.609186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.609225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.609246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.609270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.609290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.609311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.609332] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.609352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.609373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.609393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.609412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.609417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.609437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.609440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.609461] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.609481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.609502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.609522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.609542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.609562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.609583] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.609603] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.609624] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.609645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.609666] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.609724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.609748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.609794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.626613] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.626631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.626653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.626673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.626693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.626712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.626731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.626750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.626771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.626792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.626812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.626831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.626847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.626875] [drm:intel_power_well_disable [i915]] disabling display
>[  760.626897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.626917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.626938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.626958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.626973] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.627557] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.627575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.627593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.627611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.627626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.627645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.627663] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.627680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.627698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.627715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.627732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.627736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.627753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.627756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.627774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.627791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.627808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.627826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.627843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.627860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.627878] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.627896] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.627913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.627931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.627949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.627992] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.628006] [drm:intel_power_well_enable [i915]] enabling display
>[  760.628019] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.628047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.628065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.628082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.628100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.628118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.628135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.628154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.628173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.628219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.628245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.628267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.628294] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.628316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.630310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.630326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.630340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.630355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.631862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.631878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.631892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.633388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.633404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.635216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.638155] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.638255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.638284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.638319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.638408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.638443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.638485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.688382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.688402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.688422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.688446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.688466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.688487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.688508] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.688528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.688548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.688568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.688588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.688593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.688612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.688616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.688637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.688657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.688677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.688697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.688717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.688737] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.688758] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.688779] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.688799] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.688820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.688841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.688900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.688925] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.688961] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.705794] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.705814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.705835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.705855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.705875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.705894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.705914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.705933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.705954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.705974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.705995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.706014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.706030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.706057] [drm:intel_power_well_disable [i915]] disabling display
>[  760.706080] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.706100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.706120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.706141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.706156] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.706552] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.706577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.706602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.706629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.706650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.706674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.706697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.706720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.706741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.706764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.706784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.706789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.706810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.706815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.706837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.706857] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.706878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.706897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.706921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.706944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.706964] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.706986] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.707005] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.707029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.707055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.707119] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.707142] [drm:intel_power_well_enable [i915]] enabling display
>[  760.707165] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.707222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.707251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.707276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.707297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.707319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.707340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.707365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.707390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.707415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.707435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.707456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.707482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.707503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.709497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.709513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.709527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.709542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.711047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.711063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.711077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.712574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.712590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.714395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.717347] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.717412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.717428] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.717448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.717502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.717522] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.717552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.767573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.767593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.767614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.767638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.767659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.767680] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.767700] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.767721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.767741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.767762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.767782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.767786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.767806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.767810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.767830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.767851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.767871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.767891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.767911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.767931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.767952] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.767972] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.767992] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.768014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.768036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.768093] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.768118] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.768155] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.784682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.784701] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.784721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.784738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.784753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.784768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.784783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.784799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.784816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.784832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.784848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.784862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.784876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.784902] [drm:intel_power_well_disable [i915]] disabling display
>[  760.784923] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.784939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.784956] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.784972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.784986] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.785240] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.785266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.785292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.785319] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.785341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.785364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.785386] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.785408] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.785429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.785451] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.785470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.785476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.785495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.785500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.785522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.785540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.785561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.785579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.785603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.785621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.785643] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.785662] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.785681] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.785702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.785726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.785790] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.785811] [drm:intel_power_well_enable [i915]] enabling display
>[  760.785833] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.785870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.785891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.785912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.785932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.785952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.785972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.785996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.786019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.786043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.786062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.786082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.786106] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.786127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.788124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.788141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.788155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.788169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.789708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.789723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.789737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.791258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.791276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.793083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.795136] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.795181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.795225] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.795263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.795357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.795388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.795429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.845301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.845321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.845341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.845362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.845379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.845397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.845415] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.845432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.845453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.845473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.845493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.845497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.845517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.845521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.845542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.845562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.845582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.845602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.845623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.845643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.845664] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.845684] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.845704] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.845725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.845747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.845804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.845829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.845866] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.862678] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.862697] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.862717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.862734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.862750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.862765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.862780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.862796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.862813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.862829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.862844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.862858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.862872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.862898] [drm:intel_power_well_disable [i915]] disabling display
>[  760.862919] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.862935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.862952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.862967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.862982] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.863376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.863401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.863428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.863457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.863480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.863506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.863530] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.863553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.863576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.863599] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.863620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.863627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.863650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.863655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.863678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.863699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.863722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.863742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.863767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.863788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.863811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.863832] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.863860] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.863881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.863905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.863970] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.863992] [drm:intel_power_well_enable [i915]] enabling display
>[  760.864013] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.864050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.864070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.864093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.864112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.864133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.864153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.864176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.864200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.864242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.864262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.864283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.864309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.864331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.866322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.866338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.866352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.866367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.867869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.867884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.867898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.869393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.869410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.871231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.874152] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.874189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.874235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.874274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.874362] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.874397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.874447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.924355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.924376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.924396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.924417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.924434] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.924452] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.924470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.924487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.924508] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.924528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.924548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.924552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.924572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.924576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.924597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.924617] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.924637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.924657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.924678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.924697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.924719] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.924739] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.924759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.924780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.924806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.924873] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  760.924895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  760.924928] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  760.941740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  760.941759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  760.941779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.941796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.941812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.941827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.941842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.941858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.941875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.941891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.941907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.941921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.941935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.941963] [drm:intel_power_well_disable [i915]] disabling display
>[  760.941985] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  760.942005] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.942026] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.942047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.942062] [drm:intel_power_well_disable [i915]] disabling always-on
>[  760.942634] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  760.942652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  760.942669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  760.942689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  760.942707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  760.942725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  760.942742] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  760.942760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  760.942777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  760.942795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  760.942812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  760.942815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.942832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  760.942836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  760.942854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  760.942871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  760.942888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  760.942905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  760.942923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  760.942940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  760.942958] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  760.942976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  760.942993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  760.943011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  760.943029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  760.943072] [drm:intel_power_well_enable [i915]] enabling always-on
>[  760.943085] [drm:intel_power_well_enable [i915]] enabling display
>[  760.943099] [drm:hsw_set_power_well [i915]] Enabling power well
>[  760.943127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  760.943145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  760.943162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  760.943180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  760.943197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  760.943243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  760.943268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  760.943294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  760.943317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  760.943337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  760.943358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  760.943382] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  760.943403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  760.945396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  760.945412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  760.945426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.945441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  760.946943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  760.946961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  760.946978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  760.948476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  760.948492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  760.950298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  760.952830] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  760.952903] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  760.952920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  760.952942] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  760.953016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  760.953051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  760.953104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.003066] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.003088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.003109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.003133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.003153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.003174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.003194] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.003256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.003282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.003305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.003329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.003336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.003359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.003366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.003388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.003410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.003434] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.003452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.003469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.003484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.003499] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.003513] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.003527] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.003544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.003563] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.003618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.003639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.003683] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.021556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.021575] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.021595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.021613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.021629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.021644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.021659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.021675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.021692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.021708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.021724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.021738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.021752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.021779] [drm:intel_power_well_disable [i915]] disabling display
>[  761.021800] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.021815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.021832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.021848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.021862] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.022102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.022119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.022137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.022156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.022172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.022188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.022205] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.022580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.022596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.022613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.022630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.022634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.022651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.022655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.022673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.022690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.022707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.022725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.022742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.022759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.022778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.022795] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.022813] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.022831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.022849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.022892] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.022906] [drm:intel_power_well_enable [i915]] enabling display
>[  761.022920] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.022948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.022966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.022984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.023002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.023019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.023037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.023056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.023075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.023093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.023111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.023128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.023146] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.023164] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.025140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.025157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.025171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.025186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.026724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.026740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.026753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.028269] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.028285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.030091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.033030] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.033101] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.033120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.033146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.033254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.033291] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.033337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.083263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.083285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.083306] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.083330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.083350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.083371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.083391] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.083411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.083432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.083452] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.083472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.083476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.083496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.083500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.083521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.083541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.083561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.083581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.083601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.083621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.083642] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.083663] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.083683] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.083704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.083726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.083784] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.083808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.083854] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.100691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.100710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.100739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.100760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.100776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.100791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.100806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.100822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.100842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.100863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.100884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.100903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.100920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.100947] [drm:intel_power_well_disable [i915]] disabling display
>[  761.100970] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.100990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.101010] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.101030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.101046] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.101363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.101391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.101417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.101445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.101468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.101494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.101518] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.101542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.101564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.101587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.101608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.101614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.101636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.101642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.101665] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.101687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.101709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.101730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.101755] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.101775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.101799] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.101820] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.101842] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.101865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.101891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.101961] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.101984] [drm:intel_power_well_enable [i915]] enabling display
>[  761.102014] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.102051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.102072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.102094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.102113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.102135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.102155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.102179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.102202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.102237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.102258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.102277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.102301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.102322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.104320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.104338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.104355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.104373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.105881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.105897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.105914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.107411] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.107429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.109247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.112191] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.112285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.112312] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.112391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.112467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.112501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.112547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.162424] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.162444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.162465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.162488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.162509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.162530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.162550] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.162570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.162591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.162611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.162631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.162636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.162656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.162659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.162680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.162700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.162720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.162740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.162761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.162780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.162802] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.162822] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.162842] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.162863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.162884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.162942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.162966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.163012] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.179833] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.179852] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.179872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.179889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.179904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.179919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.179934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.179950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.179967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.179983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.179998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.180017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.180034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.180062] [drm:intel_power_well_disable [i915]] disabling display
>[  761.180085] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.180105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.180125] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.180146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.180161] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.180598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.180617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.180645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.180665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.180679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.180696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.180712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.180729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.180748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.180765] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.180783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.180787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.180805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.180808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.180827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.180845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.180863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.180880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.180899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.180916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.180935] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.180952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.180971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.180989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.181009] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.181050] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.181064] [drm:intel_power_well_enable [i915]] enabling display
>[  761.181079] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.181106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.181125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.181143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.181161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.181179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.181197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.181217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.181263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.181288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.181309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.181330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.181355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.181377] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.183371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.183387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.183401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.183416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.184920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.184938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.184955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.186452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.186469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.188275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.191205] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.191285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.191302] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.191324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.191402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.191437] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.191487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.241434] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.241455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.241476] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.241500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.241520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.241541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.241561] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.241582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.241603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.241623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.241643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.241647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.241667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.241670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.241691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.241711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.241731] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.241752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.241772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.241792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.241813] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.241833] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.241853] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.241874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.241896] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.241954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.241979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.242025] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.258849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.258868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.258888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.258905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.258920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.258935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.258950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.258966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.258983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.258998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.259014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.259029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.259043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.259070] [drm:intel_power_well_disable [i915]] disabling display
>[  761.259090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.259106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.259126] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.259147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.259162] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.259513] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.259530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.259548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.259565] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.259580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.259598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.259617] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.259635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.259653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.259671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.259688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.259693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.259710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.259714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.259732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.259750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.259768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.259785] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.259803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.259821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.259839] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.259857] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.259874] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.259892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.259912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.259966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.259981] [drm:intel_power_well_enable [i915]] enabling display
>[  761.259994] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.260022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.260038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.260055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.260073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.260091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.260108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.260125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.260144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.260164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.260181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.260199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.260222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.260269] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.262262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.262278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.262292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.262306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.263811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.263828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.263845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.265340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.265357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.267172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.270140] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.270181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.270198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.270220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.270480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.270503] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.270536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.320351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.320372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.320393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.320416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.320437] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.320457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.320478] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.320498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.320519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.320539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.320559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.320563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.320583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.320586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.320607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.320627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.320648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.320668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.320688] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.320708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.320729] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.320751] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.320779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.320803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.320823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.320877] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.320897] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.320931] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.338995] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.339016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.339038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.339057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.339077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.339096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.339115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.339135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.339156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.339176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.339196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.339215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.339277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.339320] [drm:intel_power_well_disable [i915]] disabling display
>[  761.339452] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.339471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.339491] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.339510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.339525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.339820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.339838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.339857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.339879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.339898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.339918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.339945] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.339962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.339977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.339990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.340003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.340007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.340019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.340023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.340040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.340058] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.340075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.340092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.340110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.340127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.340145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.340163] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.340181] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.340199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.340217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.340305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.340325] [drm:intel_power_well_enable [i915]] enabling display
>[  761.340345] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.340386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.340552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.340568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.340583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.340596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.340611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.340629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.340644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.340663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.340681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.340699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.340718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.340736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.342709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.342725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.342739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.342754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.344285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.344300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.344313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.345810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.345832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.347639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.350586] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.350649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.350666] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.350688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.350747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.350769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.350802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.400808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.400829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.400849] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.400870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.400886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.400904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.400923] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.400940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.400956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.400974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.400994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.400998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.401018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.401022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.401043] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.401063] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.401083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.401103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.401124] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.401144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.401165] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.401185] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.401206] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.401227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.401291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.401525] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.401548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.401594] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.418423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.418442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.418462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.418479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.418495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.418514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.418533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.418553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.418574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.418594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.418615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.418634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.418650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.418678] [drm:intel_power_well_disable [i915]] disabling display
>[  761.418700] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.418720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.418741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.418761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.418776] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.419083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.419101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.419120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.419139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.419157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.419177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.419197] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.419216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.419241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.419306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.419329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.419337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.419362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.419368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.419391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.419416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.419438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.419462] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.419487] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.419510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.419536] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.419558] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.419582] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.419610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.419638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.420044] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.420067] [drm:intel_power_well_enable [i915]] enabling display
>[  761.420088] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.420126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.420148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.420170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.420190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.420211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.420232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.420274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.420299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.420324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.420344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.420366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.420507] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.420529] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.422522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.422540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.422557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.422576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.424079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.424095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.424111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.425607] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.425623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.427427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.430382] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.430437] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.430456] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.430482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.430564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.430600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.430649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.480605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.480625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.480646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.480670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.480690] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.480711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.480731] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.480751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.480772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.480792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.480812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.480816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.480836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.480839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.480860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.480880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.480900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.480920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.480941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.480961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.480982] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.481002] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.481022] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.481043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.481065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.481124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.481149] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.481194] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.497963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.497982] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.498002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.498019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.498034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.498049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.498064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.498080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.498098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.498114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.498130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.498145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.498159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.498186] [drm:intel_power_well_disable [i915]] disabling display
>[  761.498207] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.498222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.498281] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.498306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.498329] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.498599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.498615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.498633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.498651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.498665] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.498682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.498697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.498716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.498734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.498752] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.498770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.498774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.498791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.498795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.498813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.498831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.498849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.498867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.498885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.498902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.498926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.498951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.498967] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.498983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.499000] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.499041] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.499054] [drm:intel_power_well_enable [i915]] enabling display
>[  761.499067] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.499092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.499107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.499121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.499135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.499148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.499163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.499178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.499193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.499211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.499229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.499273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.499300] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.499322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.501317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.501333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.501350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.501369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.502872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.502890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.502907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.504406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.504424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.506235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.509158] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.509203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.509219] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.509281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.509472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.509496] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.509530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.559369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.559391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.559413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.559436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.559456] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.559477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.559497] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.559518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.559538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.559559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.559579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.559583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.559603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.559606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.559627] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.559647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.559667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.559688] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.559708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.559728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.559749] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.559769] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.559789] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.559811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.559833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.559890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.559914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.559952] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.578006] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.578024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.578045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.578062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.578077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.578096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.578116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.578135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.578156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.578176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.578197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.578215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.578232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.578307] [drm:intel_power_well_disable [i915]] disabling display
>[  761.578429] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.578450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.578471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.578493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.578509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.578828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.578847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.578866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.578885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.578901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.578918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.578935] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.578951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.578967] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.578982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.578996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.579000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.579014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.579017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.579032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.579046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.579065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.579084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.579103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.579122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.579142] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.579161] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.579180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.579208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.579226] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.579315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.579336] [drm:intel_power_well_enable [i915]] enabling display
>[  761.579356] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.579397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.579565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.579580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.579595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.579609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.579625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.579642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.579657] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.579672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.579685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.579699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.579715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.579730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.581719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.581735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.581749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.581765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.583295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.583310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.583324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.584826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.584843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.586655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.589606] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.589665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.589682] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.589704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.589762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.589785] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.589820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.639817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.639839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.639861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.639884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.639904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.639925] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.639946] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.639966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.639987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.640007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.640027] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.640031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.640051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.640054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.640075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.640095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.640115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.640135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.640156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.640176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.640197] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.640217] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.640237] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.640301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.640329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.640549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.640571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.640618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.657443] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.657463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.657483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.657501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.657516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.657532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.657547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.657565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.657586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.657607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.657627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.657646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.657662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.657689] [drm:intel_power_well_disable [i915]] disabling display
>[  761.657712] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.657732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.657752] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.657773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.657788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.658075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.658092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.658109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.658127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.658141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.658156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.658172] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.658186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.658200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.658217] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.658234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.658271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.658294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.658299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.658322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.658344] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.658365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.658385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.658407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.658428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.658449] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.658469] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.658488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.658511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.658535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.658756] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.658770] [drm:intel_power_well_enable [i915]] enabling display
>[  761.658782] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.658809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.658824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.658839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.658852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.658866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.658880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.658896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.658910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.658925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.658938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.658951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.658967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.658982] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.660948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.660965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.660983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.661001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.662510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.662528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.662546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.664042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.664059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.665867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.668806] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.668877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.668894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.668916] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.668995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.669030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.669078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.719044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.719064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.719084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.719105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.719122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.719141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.719159] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.719176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.719193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.719209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.719224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.719228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.719243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.719281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.719304] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.719326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.719347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.719368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.719393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.719415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.719437] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.719458] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.719480] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.719506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.719691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.719745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.719766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.719809] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.736625] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.736644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.736664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.736683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.736703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.736722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.736742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.736761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.736782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.736802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.736822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.736841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.736857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.736885] [drm:intel_power_well_disable [i915]] disabling display
>[  761.736907] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.736927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.736948] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.736968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.736983] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.737443] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.737463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.737482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.737502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.737517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.737535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.737552] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.737569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.737585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.737601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.737615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.737620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.737634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.737638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.737653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.737675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.737688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.737705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.737723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.737741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.737759] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.737777] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.737796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.737814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.737833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.737875] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.737889] [drm:intel_power_well_enable [i915]] enabling display
>[  761.737904] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.737931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.737950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.737970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.737996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.738012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.738029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.738046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.738061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.738077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.738090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.738103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.738119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.738134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.740105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.740124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.740141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.740159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.741666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.741683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.741697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.743199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.743215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.745023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.747950] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.747980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.747997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.748018] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.748097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.748131] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.748180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.798130] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.798151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.798171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.798192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.798208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.798227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.798245] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.798304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.798328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.798353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.798375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.798382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.798405] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.798411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.798427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.798441] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.798455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.798468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.798485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.798499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.798514] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.798527] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.798541] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.798558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.798577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.798630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.798650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.798692] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.816834] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.816853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.816873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.816890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.816906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.816921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.816940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.816959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.816981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.817001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.817022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.817041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.817057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.817085] [drm:intel_power_well_disable [i915]] disabling display
>[  761.817107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.817128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.817148] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.817169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.817184] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.817552] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.817577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.817603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.817630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.817654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.817679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.817703] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.817726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.817750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.817772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.817793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.817799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.817820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.817826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.817848] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.817869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.817890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.817911] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.817935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.817957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.817979] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.818000] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.818019] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.818042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.818067] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.818118] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.818140] [drm:intel_power_well_enable [i915]] enabling display
>[  761.818162] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.818199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.818222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.818244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.818284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.818307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.818332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.818358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.818383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.818407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.818429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.818451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.818477] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.818500] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.820493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.820509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.820523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.820537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.822039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.822054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.822067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.823558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.823573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.825382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.828180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.828241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.828260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.828324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.828478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.828502] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.828535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.878420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.878443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.878462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.878482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.878497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.878514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.878531] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.878547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.878563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.878578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.878592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.878596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.878610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.878613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.878628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.878641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.878655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.878669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.878685] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.878699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.878714] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.878728] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.878742] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.878758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.878779] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.878835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.878858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.878895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.895703] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.895722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.895743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.895763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.895783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.895802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.895822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.895841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.895862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.895882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.895903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.895921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.895938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.895966] [drm:intel_power_well_disable [i915]] disabling display
>[  761.895988] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.896008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.896028] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.896049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.896064] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.896394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.896417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.896442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.896469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.896489] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.896513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.896535] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.896558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.896578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.896600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.896619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.896625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.896646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.896651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.896673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.896692] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.896713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.896732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.896755] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.896775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.896797] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.896816] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.896837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.896858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.896882] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.896946] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.896968] [drm:intel_power_well_enable [i915]] enabling display
>[  761.896989] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.897026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.897047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.897068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.897088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.897109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.897129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.897153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.897177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.897200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.897219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.897240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.897263] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.897305] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.899299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.899315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.899330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.899344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.900861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.900879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.900895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.902397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.902414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.904223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.906607] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.906678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.906694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.906717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.906776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.906798] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.906831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.956823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.956842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.956861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.956880] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.956895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.956911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.956928] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.956943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.956958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.956973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.956989] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.956993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.957011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.957014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.957033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.957052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.957070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.957089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.957107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.957126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.957145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.957163] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.957182] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.957201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.957221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.957308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  761.957337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  761.957525] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  761.973962] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  761.973981] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  761.974002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.974019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.974034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.974050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.974064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.974080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.974097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.974113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.974129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.974143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.974157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.974184] [drm:intel_power_well_disable [i915]] disabling display
>[  761.974205] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  761.974224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.974245] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.974266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.974321] [drm:intel_power_well_disable [i915]] disabling always-on
>[  761.974660] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  761.974678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  761.974698] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  761.974717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  761.974733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  761.974757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  761.974772] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  761.974788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  761.974802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  761.974816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  761.974829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  761.974833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.974846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  761.974850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  761.974863] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  761.974876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  761.974890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  761.974902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  761.974918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  761.974931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  761.974945] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  761.974961] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  761.974981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  761.974997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  761.975013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  761.975054] [drm:intel_power_well_enable [i915]] enabling always-on
>[  761.975067] [drm:intel_power_well_enable [i915]] enabling display
>[  761.975081] [drm:hsw_set_power_well [i915]] Enabling power well
>[  761.975105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  761.975119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  761.975134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  761.975147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  761.975161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  761.975174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  761.975194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  761.975214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  761.975233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  761.975251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  761.975294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  761.975319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  761.975341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  761.977333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  761.977351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  761.977368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.977386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  761.978890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  761.978908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  761.978925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  761.980420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  761.980437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  761.982268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  761.985170] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  761.985234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  761.985254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  761.985319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  761.985446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  761.985471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  761.985507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.035402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.035423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.035443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.035465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.035482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.035500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.035518] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.035535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.035552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.035568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.035583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.035587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.035602] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.035606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.035621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.035637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.035652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.035666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.035685] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.035708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.035731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.035746] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.035759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.035776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.035794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.035846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.035866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.035898] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.054033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.054052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.054072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.054089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.054104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.054119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.054134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.054150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.054167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.054183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.054199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.054213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.054226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.054254] [drm:intel_power_well_disable [i915]] disabling display
>[  762.054315] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.054340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.054365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.054391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.054416] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.054823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.054840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.054857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.054875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.054889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.054904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.054920] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.054935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.054949] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.054962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.054975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.054978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.054991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.054994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.055007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.055019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.055031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.055044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.055058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.055071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.055084] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.055097] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.055109] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.055124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.055140] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.055179] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.055192] [drm:intel_power_well_enable [i915]] enabling display
>[  762.055205] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.055230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.055244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.055257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.055306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.055328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.055349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.055372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.055395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.055417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.055437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.055456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.055480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.055501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.057653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.057670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.057684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.057699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.059218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.059234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.059250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.060778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.060794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.062671] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.065619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.065680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.065697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.065719] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.065780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.065801] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.065831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.115842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.115865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.115886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.115909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.115930] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.115950] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.115971] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.115991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.116012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.116032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.116052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.116056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.116076] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.116080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.116101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.116121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.116141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.116161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.116182] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.116201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.116222] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.116243] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.116263] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.116317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.116346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.116549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.116571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.116616] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.133441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.133460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.133480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.133497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.133513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.133528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.133547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.133567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.133588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.133608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.133629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.133647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.133664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.133691] [drm:intel_power_well_disable [i915]] disabling display
>[  762.133714] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.133734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.133754] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.133775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.133790] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.134100] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.134119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.134138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.134158] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.134174] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.134194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.134213] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.134232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.134252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.134276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.134340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.134347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.134369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.134375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.134396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.134417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.134437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.134457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.134479] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.134499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.134521] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.134540] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.134560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.134583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.134607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.134855] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.134869] [drm:intel_power_well_enable [i915]] enabling display
>[  762.134882] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.134908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.134924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.134939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.134953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.134967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.134981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.134997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.135012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.135027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.135040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.135054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.135070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.135085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.137057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.137073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.137087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.137101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.138606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.138621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.138634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.140125] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.140141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.141948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.144888] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.144959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.144978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.145004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.145085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.145122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.145170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.195073] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.195094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.195114] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.195134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.195151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.195172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.195192] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.195213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.195234] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.195254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.195274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.195315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.195342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.195348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.195373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.195397] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.195420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.195442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.195469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.195592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.195609] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.195624] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.195639] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.195656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.195675] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.195730] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.195751] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.195794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.212610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.212629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.212649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.212666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.212681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.212696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.212711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.212727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.212744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.212760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.212776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.212790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.212805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.212832] [drm:intel_power_well_disable [i915]] disabling display
>[  762.212853] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.212869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.212885] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.212901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.212915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.213197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.213215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.213233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.213254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.213273] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.213331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.213357] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.213379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.213400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.213421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.213440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.213447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.213466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.213471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.213491] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.213511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.213530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.213550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.213572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.213591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.213614] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.213801] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.213820] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.213838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.213858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.213901] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.213915] [drm:intel_power_well_enable [i915]] enabling display
>[  762.213929] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.213958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.213976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.213994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.214012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.214030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.214048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.214068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.214088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.214106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.214124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.214141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.214161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.214178] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.216154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.216170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.216185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.216200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.217707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.217722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.217736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.219327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.219345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.221154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.224095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.224171] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.224189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.224212] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.224291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.224384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.224472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.274346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.274367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.274387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.274408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.274427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.274448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.274468] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.274489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.274514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.274540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.274556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.274560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.274574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.274577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.274592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.274606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.274620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.274633] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.274650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.274664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.274683] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.274702] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.274721] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.274741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.274762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.274818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.274841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.274887] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.291694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.291713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.291733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.291750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.291766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.291781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.291796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.291814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.291835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.291855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.291876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.291895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.291911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.291939] [drm:intel_power_well_disable [i915]] disabling display
>[  762.291961] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.291981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.292001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.292022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.292037] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.292285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.292346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.292374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.292403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.292426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.292451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.292475] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.292499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.292522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.292544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.292566] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.292573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.292595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.292759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.292780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.292806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.292822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.292836] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.292853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.292867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.292883] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.292897] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.292911] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.292927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.292944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.292986] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.292999] [drm:intel_power_well_enable [i915]] enabling display
>[  762.293012] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.293037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.293052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.293065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.293083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.293101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.293119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.293139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.293159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.293178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.293195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.293213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.293232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.293250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.295246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.295263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.295277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.295325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.296847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.296866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.296883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.298390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.298409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.300230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.302526] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.302583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.302600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.302622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.302680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.302705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.302741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.352762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.352783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.352803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.352824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.352840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.352859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.352877] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.352895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.352912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.352927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.352943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.352947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.352962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.352966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.352981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.352997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.353012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.353026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.353043] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.353058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.353074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.353089] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.353104] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.353121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.353142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.353192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.353217] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.353254] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.370083] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.370101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.370121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.370141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.370160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.370180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.370199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.370218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.370239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.370259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.370280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.370341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.370366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.370409] [drm:intel_power_well_disable [i915]] disabling display
>[  762.370437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.370455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.370474] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.370491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.370507] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.370804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.370822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.370840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.370860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.370876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.370894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.370911] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.370928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.370944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.370960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.370974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.370979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.370993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.370996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.371012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.371026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.371040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.371054] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.371071] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.371085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.371100] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.371114] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.371134] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.371154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.371175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.371210] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.371226] [drm:intel_power_well_enable [i915]] enabling display
>[  762.371241] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.371271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.371297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.371346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.371369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.371393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.371422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.371446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.371469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.371491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.371511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.371530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.371554] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.371575] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.373568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.373585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.373600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.373618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.375125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.375142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.375160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.376658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.376676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.378484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.381432] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.381493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.381509] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.381531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.381615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.381647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.381693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.431664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.431686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.431708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.431731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.431751] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.431772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.431793] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.431813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.431834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.431854] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.431873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.431878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.431897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.431901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.431922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.431942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.431962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.431982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.432002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.432022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.432043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.432063] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.432083] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.432104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.432126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.432185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.432209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.432255] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.449021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.449040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.449060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.449077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.449093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.449109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.449124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.449140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.449158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.449174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.449190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.449204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.449218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.449245] [drm:intel_power_well_disable [i915]] disabling display
>[  762.449266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.449282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.449342] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.449370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.449395] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.449757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.449775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.449793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.449813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.449828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.449845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.449862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.449878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.449894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.449908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.449923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.449926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.449945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.449949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.449968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.449987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.450006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.450025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.450045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.450063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.450083] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.450102] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.450121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.450141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.450162] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.450215] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.450229] [drm:intel_power_well_enable [i915]] enabling display
>[  762.450242] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.450270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.450287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.450335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.450358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.450381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.450404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.450430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.450455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.450479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.450500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.450521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.450547] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.450569] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.452568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.452584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.452599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.452615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.454124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.454139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.454153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.455650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.455666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.457474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.460418] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.460482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.460497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.460517] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.460592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.460625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.460669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.510638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.510658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.510680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.510703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.510723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.510744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.510764] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.510785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.510805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.510825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.510845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.510849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.510869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.510873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.510894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.510914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.510934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.510954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.510974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.510994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.511016] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.511036] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.511056] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.511077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.511099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.511157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.511182] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.511228] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.528028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.528046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.528067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.528084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.528099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.528114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.528129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.528148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.528169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.528189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.528210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.528229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.528245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.528273] [drm:intel_power_well_disable [i915]] disabling display
>[  762.528295] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.528358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.528387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.528416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.528442] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.528833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.528868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.528894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.528922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.528938] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.528956] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.528974] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.528991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.529009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.529026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.529043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.529047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.529064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.529068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.529085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.529103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.529120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.529137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.529155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.529172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.529190] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.529208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.529225] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.529243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.529261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.529327] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.529349] [drm:intel_power_well_enable [i915]] enabling display
>[  762.529373] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.529412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.529435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.529459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.529479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.529502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.529523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.529548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.529573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.529598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.529618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.529640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.529665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.529690] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.531687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.531703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.531719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.531737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.533247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.533263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.533278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.534805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.534821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.536655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.539242] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.539349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.539374] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.539412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.539493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.539515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.539549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.589512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.589533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.589554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.589578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.589598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.589618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.589639] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.589659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.589680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.589700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.589720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.589724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.589744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.589748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.589769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.589789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.589809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.589829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.589850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.589870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.589891] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.589911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.589931] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.589951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.589974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.590023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.590048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.590086] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.608109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.608128] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.608149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.608165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.608181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.608196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.608211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.608227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.608245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.608261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.608277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.608291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.608349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.608393] [drm:intel_power_well_disable [i915]] disabling display
>[  762.608420] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.608437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.608455] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.608472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.608487] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.608769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.608785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.608803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.608821] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.608835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.608851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.608867] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.608882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.608896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.608910] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.608923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.608928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.608940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.608943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.608962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.608979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.608998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.609015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.609033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.609050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.609069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.609087] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.609105] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.609124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.609144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.609185] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.609199] [drm:intel_power_well_enable [i915]] enabling display
>[  762.609214] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.609241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.609259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.609278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.609297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.609340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.609363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.609388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.609411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.609434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.609454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.609474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.609498] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.609520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.611513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.611529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.611543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.611561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.613064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.613080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.613094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.614590] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.614608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.616412] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.619368] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.619422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.619442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.619468] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.619549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.619586] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.619635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.669585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.669606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.669626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.669647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.669664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.669682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.669700] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.669717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.669734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.669750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.669765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.669769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.669788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.669792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.669813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.669833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.669854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.669874] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.669895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.669915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.669936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.669956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.669977] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.669998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.670020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.670077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.670102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.670148] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.686975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.686994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.687014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.687034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.687053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.687073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.687092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.687112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.687132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.687152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.687178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.687203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.687219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.687246] [drm:intel_power_well_disable [i915]] disabling display
>[  762.687268] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.687285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.687303] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.687365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.687388] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.687723] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.687742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.687761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.687783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.687802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.687822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.687842] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.687861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.687881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.687900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.687919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.687923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.687942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.687946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.687967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.687986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.688006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.688025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.688045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.688064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.688084] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.688104] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.688123] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.688144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.688164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.688210] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.688227] [drm:intel_power_well_enable [i915]] enabling display
>[  762.688242] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.688272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.688292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.688318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.688373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.688395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.688417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.688440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.688464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.688487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.688506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.688526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.688549] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.688571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.690560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.690576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.690590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.690605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.692109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.692124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.692138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.693634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.693650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.695455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.698396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.698464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.698483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.698510] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.698594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.698627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.698672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.748633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.748653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.748673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.748695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.748711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.748730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.748751] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.748771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.748792] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.748812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.748832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.748836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.748856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.748860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.748880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.748901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.748921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.748941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.748962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.748981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.749003] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.749023] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.749043] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.749064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.749086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.749144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.749168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.749214] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.766053] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.766072] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.766094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.766113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.766133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.766152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.766172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.766191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.766212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.766232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.766252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.766271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.766287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.766355] [drm:intel_power_well_disable [i915]] disabling display
>[  762.766392] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.766420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.766449] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.766469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.766483] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.766692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.766709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.766728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.766757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.766779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.766797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.766814] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.766831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.766847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.766863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.766877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.766881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.766896] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.766899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.766919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.766938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.766957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.766977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.766996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.767016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.767037] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.767055] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.767080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.767098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.767115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.767157] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.767170] [drm:intel_power_well_enable [i915]] enabling display
>[  762.767183] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.767209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.767223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.767238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.767251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.767265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.767279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.767296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.767311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.767352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.767373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.767392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.767416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.767437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.769431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.769448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.769465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.769483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.770992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.771010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.771027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.772527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.772544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.774354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.777297] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.777418] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.777435] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.777458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.777537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.777571] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.777621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.827554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.827573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.827592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.827612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.827627] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.827644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.827661] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.827677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.827696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.827716] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.827734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.827739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.827758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.827761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.827781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.827800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.827819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.827838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.827857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.827876] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.827896] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.827915] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.827934] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.827954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.827974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.828029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.828052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.828098] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.844919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.844938] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.844959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.844979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.844998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.845018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.845037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.845056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.845076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.845097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.845117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.845136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.845153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.845181] [drm:intel_power_well_disable [i915]] disabling display
>[  762.845203] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.845223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.845244] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.845264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.845279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.845674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.845694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.845715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.845738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.845758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.845784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.845802] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.845817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.845832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.845845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.845858] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.845862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.845875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.845878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.845892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.845904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.845917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.845930] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.845947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.845964] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.845984] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.846002] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.846020] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.846039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.846058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.846100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.846115] [drm:intel_power_well_enable [i915]] enabling display
>[  762.846128] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.846156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.846175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.846192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.846211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.846226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.846244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.846263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.846282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.846306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.846350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.846372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.846396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.846418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.848415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.848431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.848446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.848461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.849963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.849981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.849999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.851497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.851515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.853324] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.856254] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.856292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.856309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.856379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.856459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.856494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.856543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.906451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.906472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.906492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.906514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.906532] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.906552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.906572] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.906591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.906610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.906629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.906648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.906652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.906671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.906675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.906694] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.906713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.906732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.906751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.906770] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.906789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.906808] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.906828] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.906847] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.906867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.906887] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.906944] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.906967] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.907014] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  762.923834] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  762.923853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.923873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.923890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.923909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.923929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.923948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.923967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.923988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.924008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.924029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.924047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.924064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.924091] [drm:intel_power_well_disable [i915]] disabling display
>[  762.924113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.924134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.924154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.924175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.924190] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.924865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.924882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.924899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.924917] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.924931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.924947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.924963] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.924978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.924992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.925006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.925022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.925026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.925043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.925047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.925065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.925082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.925100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.925117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.925135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.925152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.925170] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.925188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.925205] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.925223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.925242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.925284] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.925298] [drm:intel_power_well_enable [i915]] enabling display
>[  762.925311] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.925374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.925399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.925424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.925448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.925471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.925496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.925522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.925547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.925572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.925594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.925617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.925643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.925667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.927665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.927681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.927695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.927709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.929214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.929231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.929249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.930746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.930764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.932572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.935120] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.935176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.935192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.935214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.935293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.935327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.935485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.985361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.985381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.985402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.985426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.985446] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.985467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.985488] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.985508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.985529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.985549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.985569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.985573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.985593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.985597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.985617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.985638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.985658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.985678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.985698] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.985718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.985739] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  762.985760] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.985780] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.985801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.985823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.985882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  762.985906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.985953] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.003803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.003821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.003842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.003859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.003874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.003889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.003903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.003919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.003936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.003952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.003967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.003982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.003996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.004023] [drm:intel_power_well_disable [i915]] disabling display
>[  763.004044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.004060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.004076] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.004093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.004108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.004500] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.004527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.004553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.004583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.004606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.004632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.004656] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.004680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.004702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.004725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.004746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.004752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.004774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.004779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.004802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.004823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.004845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.004866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.004891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.004911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.004935] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.004956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.004978] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.005001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.005028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.005100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.005121] [drm:intel_power_well_enable [i915]] enabling display
>[  763.005143] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.005179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.005200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.005221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.005241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.005262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.005282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.005305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.005329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.005371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.005392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.005413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.005440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.005461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.007453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.007469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.007483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.007497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.008997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.009012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.009025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.010517] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.010533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.012351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.014723] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.014752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.014768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.014790] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.014869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.014904] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.014954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.064899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.064919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.064939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.064960] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.064977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.064995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.065013] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.065033] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.065054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.065074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.065094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.065098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.065118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.065122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.065142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.065162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.065183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.065203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.065223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.065243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.065265] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.065285] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.065305] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.065326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.065396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.065478] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.065509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.065560] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.082299] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.082317] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.082374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.082401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.082426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.082448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.082472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.082495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.082521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.082546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.082572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.082593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.082615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.082655] [drm:intel_power_well_disable [i915]] disabling display
>[  763.082687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.082712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.082738] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.082764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.082788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.083097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.083115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.083133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.083152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.083168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.083185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.083202] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.083218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.083233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.083247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.083261] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.083265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.083278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.083282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.083296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.083314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.083334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.083383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.083408] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.083433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.083460] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.083482] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.083506] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.083534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.083560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.083629] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.083660] [drm:intel_power_well_enable [i915]] enabling display
>[  763.083683] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.083720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.083741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.083762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.083782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.083803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.083823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.083847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.083870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.083893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.083912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.083932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.083954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.083977] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.085961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.085976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.085990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.086005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.087502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.087517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.087532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.089023] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.089039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.090843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.093231] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.093295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.093311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.093333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.093533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.093556] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.093589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.143462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.143483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.143503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.143524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.143541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.143559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.143577] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.143595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.143612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.143630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.143650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.143654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.143674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.143678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.143699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.143719] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.143739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.143760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.143780] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.143800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.143821] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.143842] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.143862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.143883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.143905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.143962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.143986] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.144024] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.161970] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.161989] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.162009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.162029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.162048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.162068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.162087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.162107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.162127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.162148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.162169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.162188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.162204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.162232] [drm:intel_power_well_disable [i915]] disabling display
>[  763.162255] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.162275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.162295] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.162316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.162331] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.162721] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.162747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.162774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.162803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.162826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.162852] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.162876] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.162901] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.162923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.162946] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.162967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.162973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.162996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.163001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.163032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.163051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.163072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.163091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.163113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.163132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.163154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.163173] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.163193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.163215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.163239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.163301] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.163323] [drm:intel_power_well_enable [i915]] enabling display
>[  763.163369] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.163407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.163428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.163452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.163473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.163495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.163516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.163541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.163565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.163590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.163610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.163632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.163658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.163679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.165672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.165688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.165702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.165720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.167227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.167243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.167257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.168755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.168771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.170576] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.173492] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.173534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.173550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.173572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.173633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.173655] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.173687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.223691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.223712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.223732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.223753] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.223770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.223788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.223806] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.223822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.223839] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.223854] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.223870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.223874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.223889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.223892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.223910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.223931] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.223952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.223972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.223992] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.224012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.224033] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.224054] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.224074] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.224095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.224117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.224175] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.224200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.224237] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.241071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.241089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.241110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.241126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.241142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.241157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.241172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.241188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.241206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.241222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.241238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.241253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.241267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.241293] [drm:intel_power_well_disable [i915]] disabling display
>[  763.241314] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.241330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.241387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.241415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.241441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.241812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.241837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.241863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.241890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.241905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.241921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.241936] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.241951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.241965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.241979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.241992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.241996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.242008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.242011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.242024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.242037] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.242049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.242062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.242077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.242090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.242103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.242115] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.242128] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.242142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.242158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.242199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.242212] [drm:intel_power_well_enable [i915]] enabling display
>[  763.242225] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.242250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.242264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.242277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.242290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.242303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.242316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.242331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.242373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.242396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.242417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.242439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.242461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.242485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.244481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.244498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.244512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.244527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.246032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.246047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.246060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.247558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.247576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.249387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.252323] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.252434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.252462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.252497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.252585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.252618] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.252651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.302565] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.302585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.302605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.302627] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.302644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.302662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.302682] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.302702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.302723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.302743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.302763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.302767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.302788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.302792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.302813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.302833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.302854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.302874] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.302894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.302914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.302935] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.302956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.302976] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.302997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.303019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.303076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.303101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.303138] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.319969] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.319988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.320008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.320025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.320041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.320056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.320071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.320087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.320105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.320121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.320137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.320151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.320165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.320192] [drm:intel_power_well_disable [i915]] disabling display
>[  763.320213] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.320228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.320249] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.320270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.320285] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.320621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.320649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.320678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.320708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.320734] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.320762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.320788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.320815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.320842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.320866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.320890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.320897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.320919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.320927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.320956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.320977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.320997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.321017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.321040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.321059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.321080] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.321100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.321121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.321143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.321168] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.321234] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.321256] [drm:intel_power_well_enable [i915]] enabling display
>[  763.321279] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.321319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.321343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.321384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.321406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.321425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.321446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.321470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.321494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.321518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.321540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.321561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.321586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.321610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.323593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.323610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.323627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.323646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.325151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.325168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.325181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.326675] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.326691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.328496] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.331445] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.331506] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.331523] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.331545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.331604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.331626] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.331659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.381672] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.381693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.381713] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.381734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.381751] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.381770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.381791] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.381811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.381832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.381852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.381872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.381876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.381896] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.381900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.381921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.381941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.381961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.381981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.382002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.382022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.382043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.382063] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.382084] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.382105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.382126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.382185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.382209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.382247] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.399087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.399106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.399126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.399144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.399160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.399175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.399190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.399206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.399224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.399240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.399256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.399270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.399284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.399311] [drm:intel_power_well_disable [i915]] disabling display
>[  763.399332] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.399348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.399409] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.399435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.399465] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.399796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.399816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.399836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.399858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.399876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.399896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.399914] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.399934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.399953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.399972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.399990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.399995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.400013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.400017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.400036] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.400055] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.400073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.400092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.400111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.400129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.400149] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.400168] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.400187] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.400206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.400227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.400270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.400286] [drm:intel_power_well_enable [i915]] enabling display
>[  763.400301] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.400331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.400355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.400404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.400428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.400451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.400474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.400506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.400530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.400553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.400573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.400593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.400617] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  763.400638] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.402626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.402642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.402656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.402671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.404175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.404191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.404204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.405699] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.405717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.407522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.410475] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  763.410532] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.410549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  763.410571] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.410631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.410656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.410699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.460694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.460715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.460736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.460757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.460774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.460794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.460815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  763.460836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  763.460856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.460877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.460896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.460900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.460920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.460924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.460945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.460965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.460986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.461006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  763.461026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.461046] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.461067] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  763.461088] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  763.461108] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  763.461129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.461151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  763.461208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  763.461232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  763.461269] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  763.478095] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  763.478114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  763.478134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.478151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.478166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.478181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.478196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.478212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.478229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.478245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.478261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.478275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.478288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.478315] [drm:intel_power_well_disable [i915]] disabling display
>[  763.478336] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  763.478351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.478412] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.478437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.478463] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.478586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.478619] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.478641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.478661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.478682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.478702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.478722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.478742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.478763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.478784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.478805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.478827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.478846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.478866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.478893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  763.478910] [drm:intel_power_well_disable [i915]] disabling always-on
>[  763.480193] [IGT] kms_flip: exiting, ret=0
>[  763.500875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  763.500894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  763.500914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  763.500935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  763.500951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  763.500971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  763.500992] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  763.501012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  763.501032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  763.501051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  763.501071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  763.501076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.501095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  763.501098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.501118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  763.501138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  763.501158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  763.501177] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  763.501198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  763.501217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  763.501237] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  763.501256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  763.501276] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  763.501297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  763.501319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  763.501398] [drm:intel_power_well_enable [i915]] enabling always-on
>[  763.501416] [drm:intel_power_well_enable [i915]] enabling display
>[  763.501432] [drm:hsw_set_power_well [i915]] Enabling power well
>[  763.501465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  763.501485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  763.501506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  763.501525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  763.501552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  763.501570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  763.501589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  763.501605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  763.501624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.501642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  763.501659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  763.501679] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  763.501697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  763.503690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  763.503706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  763.503720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.503734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  763.505244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  763.505258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  763.505270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  763.506772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  763.506786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  763.508603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  763.511653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  763.511712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  763.511727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  763.511748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  763.511790] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  763.511804] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  763.528469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  763.528494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  763.528530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  763.528655] Console: switching to colour frame buffer device 240x75
>[  763.656707] Console: switching to colour dummy device 80x25
>[  763.656798] [IGT] kms_flip: executing
>[  763.670874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  763.670899] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  763.672441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  763.672462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  763.674427] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  763.674434] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  763.676431] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  763.676453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  763.678428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  763.678434] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  763.678438] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  763.678454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  763.678477] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  763.679504] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  763.680420] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  763.680445] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  763.680469] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  763.680486] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  763.681474] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  763.681497] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  763.682563] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  763.682566] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  763.682645] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  763.682648] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  763.682652] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  763.682654] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  763.682658] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  763.682660] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  763.682667] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  763.682670] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.682672] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.682674] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.682677] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  763.682679] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  763.682682] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  763.682684] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  763.682687] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.682689] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.682692] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  763.682694] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  763.682696] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  763.682699] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  763.682701] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  763.682704] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  763.682706] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  763.682709] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  763.682711] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  763.682714] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  763.682716] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  763.682719] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  763.682721] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  763.682723] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  763.682726] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  763.682728] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  763.682731] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  763.682733] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  763.682735] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  763.682738] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  763.682740] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  763.682770] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  763.682787] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  763.684416] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  763.684433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  763.686428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  763.686434] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  763.688418] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  763.688437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  763.690425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  763.690431] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  763.690435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  763.690666] [IGT] kms_flip: starting subtest 2x-flip-vs-blocking-wf-vblank
>[  763.692948] [IGT] kms_flip: exiting, ret=77
>[  763.728727] Console: switching to colour frame buffer device 240x75
>[  763.858346] Console: switching to colour dummy device 80x25
>[  763.858507] [IGT] kms_flip: executing
>[  763.872910] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  763.872939] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  763.874433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  763.874451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  763.876444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  763.876450] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  763.878437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  763.878457] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  763.880440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  763.880446] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  763.880450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  763.880466] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  763.880489] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  763.881525] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  763.882421] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  763.882445] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  763.882467] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  763.882484] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  763.883478] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  763.883501] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  763.884588] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  763.884592] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  763.884672] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  763.884674] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  763.884678] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  763.884680] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  763.884684] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  763.884686] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  763.884693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  763.884696] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  763.884699] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.884701] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.884703] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  763.884706] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  763.884708] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  763.884711] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  763.884713] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.884716] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  763.884718] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  763.884721] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  763.884723] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  763.884725] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  763.884728] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  763.884730] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  763.884733] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  763.884735] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  763.884738] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  763.884740] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  763.884743] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  763.884745] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  763.884747] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  763.884750] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  763.884752] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  763.884755] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  763.884757] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  763.884760] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  763.884762] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  763.884764] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  763.884767] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  763.884797] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  763.884815] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  763.886419] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  763.886438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  763.888444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  763.888449] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  763.890428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  763.890455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  763.892444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  763.892450] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  763.892454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  763.893729] [IGT] kms_flip: starting subtest 2x-modeset-vs-vblank-race-interruptible
>[  763.895063] [IGT] kms_flip: exiting, ret=77
>[  763.928942] Console: switching to colour frame buffer device 240x75
>[  764.058450] Console: switching to colour dummy device 80x25
>[  764.058544] [IGT] kms_flip: executing
>[  764.068919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  764.068948] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  764.070442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  764.070459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  764.072438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  764.072443] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  764.074451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  764.074471] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  764.076457] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  764.076463] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  764.076468] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  764.076484] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  764.076508] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  764.077540] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  764.078441] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  764.078459] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  764.078474] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  764.078488] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  764.079476] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  764.079499] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  764.080557] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  764.080560] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  764.080640] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  764.080642] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  764.080646] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  764.080648] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  764.080652] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  764.080654] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  764.080661] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  764.080664] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  764.080667] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.080669] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.080672] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  764.080674] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  764.080677] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  764.080679] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  764.080681] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.080684] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.080686] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  764.080689] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  764.080691] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  764.080693] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  764.080696] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  764.080698] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  764.080701] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  764.080703] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  764.080706] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  764.080708] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  764.080710] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  764.080713] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  764.080715] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  764.080718] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  764.080720] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  764.080723] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  764.080725] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  764.080727] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  764.080730] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  764.080732] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  764.080735] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  764.080764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  764.080782] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  764.082449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  764.082469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  764.084454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  764.084460] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  764.086455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  764.086474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  764.088450] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  764.088456] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  764.088459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  764.088666] [IGT] kms_flip: starting subtest 2x-plain-flip
>[  764.090988] [IGT] kms_flip: exiting, ret=77
>[  764.129094] Console: switching to colour frame buffer device 240x75
>[  764.259527] Console: switching to colour dummy device 80x25
>[  764.259624] [IGT] kms_flip: executing
>[  764.269945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  764.269974] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  764.271454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  764.271471] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  764.273466] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  764.273472] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  764.275464] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  764.275484] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  764.277463] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  764.277469] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  764.277473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  764.277490] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  764.277514] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  764.278550] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  764.279449] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  764.279473] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  764.279495] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  764.279516] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  764.280508] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  764.280532] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  764.281587] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  764.281589] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  764.281669] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  764.281672] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  764.281676] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  764.281678] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  764.281681] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  764.281683] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  764.281691] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  764.281694] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  764.281696] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.281699] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.281701] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  764.281704] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  764.281706] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  764.281709] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  764.281711] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.281713] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  764.281716] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  764.281718] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  764.281721] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  764.281723] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  764.281725] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  764.281728] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  764.281730] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  764.281733] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  764.281735] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  764.281738] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  764.281740] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  764.281742] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  764.281745] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  764.281747] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  764.281750] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  764.281752] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  764.281755] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  764.281757] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  764.281759] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  764.281762] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  764.281764] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  764.281794] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  764.281811] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  764.283427] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  764.283444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  764.285461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  764.285467] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  764.287468] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  764.287489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  764.289469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  764.289474] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  764.289479] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  764.289683] [IGT] kms_flip: starting subtest wf_vblank-ts-check
>[  764.290089] [drm:drm_mode_addfb2] [FB:75]
>[  764.290111] [drm:drm_mode_addfb2] [FB:79]
>[  764.332184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  764.332237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  764.345853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  764.345880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  764.345929] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  764.364772] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  764.364795] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  764.364812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  764.364832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  764.364848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  764.364866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  764.364881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  764.364896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  764.364912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  764.364930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  764.364946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  764.364961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  764.364977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  764.364991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  764.365005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  764.365032] [drm:intel_power_well_disable [i915]] disabling display
>[  764.365054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  764.365074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  764.365091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  764.365137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  764.365208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  764.365269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  764.365280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  764.365321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  764.365338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  764.365356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  764.365376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  764.365392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  764.365409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  764.365468] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  764.365492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  764.365515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  764.365537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  764.365558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  764.365565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  764.365586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  764.365592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  764.365614] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  764.365635] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  764.365656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  764.365683] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  764.365705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  764.365724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  764.365744] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  764.365763] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  764.365782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  764.365805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  764.365828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  764.368340] [drm:intel_power_well_enable [i915]] enabling always-on
>[  764.368356] [drm:intel_power_well_enable [i915]] enabling display
>[  764.368370] [drm:hsw_set_power_well [i915]] Enabling power well
>[  764.368398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  764.368452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  764.368477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  764.368500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  764.368521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  764.368545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  764.368570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  764.368594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  764.368618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  764.368638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  764.368659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  764.368683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  764.368704] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  764.370692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  764.370708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  764.370723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  764.370737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  764.372240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  764.372255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  764.372269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  764.373764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  764.373780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  764.375584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  764.378550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  764.378592] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  764.378610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  764.378632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  764.378672] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  764.378688] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  764.395334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  764.395358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  764.395391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.704923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.721308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  774.721351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.721416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  774.738323] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  774.738346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  774.738363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.738383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.738400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.738418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.738434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.738449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.738465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.738483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.738500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.738516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.738532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.738547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.738561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.738589] [drm:intel_power_well_disable [i915]] disabling display
>[  774.738611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.738632] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  774.738649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.738852] [drm:drm_mode_addfb2] [FB:75]
>[  774.738876] [drm:drm_mode_addfb2] [FB:78]
>[  774.764534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  774.764616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.764672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.764724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.764735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.764781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.764799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.764818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.764839] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.764856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.764874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.764892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.764909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.764927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.764944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.764961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.764965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.764982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.764986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.765003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.765021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.765072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.765095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.765120] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.765141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.765162] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.765183] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.765203] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.765226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.765251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.767863] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.767878] [drm:intel_power_well_enable [i915]] enabling display
>[  774.767891] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.767919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.767934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.767948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.767965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.767983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.768001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.768020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.768075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.768103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.768124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.768147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.768174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.768195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.770197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.770213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.770226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.770241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.771747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.771762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.771776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.773276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.773292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.775103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.778040] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.778113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.778130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.778153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.794863] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.794889] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.794927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.104482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  785.104661] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  785.104937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  785.105156] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  785.121650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  785.121714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  785.121749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  785.121778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  785.121809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  785.121836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  785.121862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  785.121889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  785.121920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  785.121948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  785.121983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  785.122019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.122052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  785.122085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  785.122134] [drm:intel_power_well_disable [i915]] disabling display
>[  785.122172] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  785.122216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  785.122244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  785.122552] [drm:drm_mode_addfb2] [FB:75]
>[  785.122593] [drm:drm_mode_addfb2] [FB:78]
>[  785.145925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  785.146013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  785.146072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  785.146127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  785.146137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  785.146184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  785.146201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  785.146218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  785.146236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  785.146251] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  785.146266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  785.146282] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  785.146296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  785.146310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  785.146324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  785.146340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  785.146344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  785.146361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  785.146364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  785.146382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  785.146399] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  785.146417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  785.146434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  785.146452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  785.146469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  785.146486] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  785.146504] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  785.146521] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  785.146540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  785.146559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  785.149083] [drm:intel_power_well_enable [i915]] enabling always-on
>[  785.149100] [drm:intel_power_well_enable [i915]] enabling display
>[  785.149116] [drm:hsw_set_power_well [i915]] Enabling power well
>[  785.149148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  785.149167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  785.149186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  785.149205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  785.149223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  785.149242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  785.149262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  785.149282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  785.149302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.149320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  785.149336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  785.149356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  785.149375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  785.151383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  785.151401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  785.151416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  785.151431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  785.152942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  785.152958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  785.152972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  785.154469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  785.154485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  785.156295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  785.158563] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  785.158596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  785.158615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  785.158641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  785.175349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  785.175376] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  785.175414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.484937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.485115] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  795.485203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  795.485511] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  795.502451] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  795.502473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  795.502497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.502517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.502537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.502554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.502571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.502589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.502610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.502629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.502647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.502665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.502686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.502708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.502741] [drm:intel_power_well_disable [i915]] disabling display
>[  795.502768] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  795.502797] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  795.502816] [drm:intel_power_well_disable [i915]] disabling always-on
>[  795.505372] [IGT] kms_flip: exiting, ret=0
>[  795.524780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.524798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.524817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.524836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.524853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.524872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.524891] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  795.524910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  795.524928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.524947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.524965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.524969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.524987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.524990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.525009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.525027] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.525046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.525064] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  795.525083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.525101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.525119] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  795.525138] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  795.525156] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  795.525175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.525196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  795.525251] [drm:intel_power_well_enable [i915]] enabling always-on
>[  795.525267] [drm:intel_power_well_enable [i915]] enabling display
>[  795.525282] [drm:hsw_set_power_well [i915]] Enabling power well
>[  795.525336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.525355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.525374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.525393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.525412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.525438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.525456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.525472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.525490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.525507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.525523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.525542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  795.525559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  795.527556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  795.527571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  795.527585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.527599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  795.529110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  795.529124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  795.529136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.530635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  795.530649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  795.532464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  795.535496] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  795.535525] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  795.535541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  795.535563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  795.535610] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  795.535625] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  795.552259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.552281] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.552333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.552457] Console: switching to colour frame buffer device 240x75
>[  795.685908] Console: switching to colour dummy device 80x25
>[  795.685999] [IGT] kms_flip: executing
>[  795.695839] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  795.695868] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  795.697353] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  795.697375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  795.699357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  795.699363] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  795.701352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  795.701372] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  795.703354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  795.703360] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  795.703364] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  795.703380] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  795.703404] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  795.704432] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  795.705337] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  795.705354] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  795.705368] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  795.705382] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  795.706381] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  795.706407] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  795.707463] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  795.707466] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  795.707545] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  795.707547] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  795.707551] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  795.707553] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  795.707557] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  795.707559] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  795.707566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  795.707569] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.707572] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  795.707574] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  795.707577] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  795.707579] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  795.707582] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  795.707584] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  795.707587] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  795.707589] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  795.707591] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  795.707594] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  795.707596] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  795.707599] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  795.707601] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  795.707604] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  795.707606] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  795.707608] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  795.707611] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  795.707613] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  795.707616] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  795.707618] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  795.707621] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  795.707623] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  795.707625] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  795.707628] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  795.707630] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  795.707633] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  795.707635] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  795.707638] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  795.707640] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  795.707670] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  795.707688] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  795.709342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  795.709359] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  795.711356] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  795.711362] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  795.713351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  795.713373] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  795.715359] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  795.715365] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  795.715369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  795.715586] [IGT] kms_flip: starting subtest single-buffer-flip-vs-dpms-off-vs-modeset
>[  795.715991] [drm:drm_mode_addfb2] [FB:77]
>[  795.716014] [drm:drm_mode_addfb2] [FB:79]
>[  795.758274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.758384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.769127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  795.769153] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  795.769193] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  795.788048] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  795.788071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  795.788088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  795.788109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.788126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.788144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.788159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.788174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.788193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.788215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.788236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.788256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.788277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.788295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.788355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.788414] [drm:intel_power_well_disable [i915]] disabling display
>[  795.788449] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  795.788485] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.788514] [drm:intel_power_well_disable [i915]] disabling always-on
>[  795.788586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  795.788692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  795.788785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.788801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  795.788869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.788889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.788909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.788931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.788950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.788970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.788989] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  795.789008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  795.789028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.789047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.789066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.789070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.789088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.789092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.789111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.789130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.789149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.789168] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  795.789196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.789213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.789227] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  795.789241] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  795.789255] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  795.789270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.789287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  795.791907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  795.791923] [drm:intel_power_well_enable [i915]] enabling display
>[  795.791938] [drm:hsw_set_power_well [i915]] Enabling power well
>[  795.791966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.791984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.792000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.792015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.792030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.792048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.792068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.792088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.792108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.792126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.792142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.792162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  795.792181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  795.794166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  795.794183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  795.794197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.794212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  795.795724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  795.795739] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  795.795752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.797251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  795.797269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  795.799081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  795.802022] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  795.802091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  795.802108] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  795.802130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  795.802178] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  795.802204] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  795.818860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.818885] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.818920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.835602] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.835623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.835643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.835664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.835680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.835698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.835717] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  795.835733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  795.835750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.835766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.835781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.835785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.835800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.835803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.835818] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.835834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.835853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.835873] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  795.835894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.835914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.835935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  795.835956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  795.835976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  795.835997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.836019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  795.852225] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  795.852249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  795.852295] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  795.870474] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  795.870496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  795.870513] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  795.870532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.870549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.870565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.870584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.870603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.870622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.870643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.870663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.870684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.870702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.870719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.870746] [drm:intel_power_well_disable [i915]] disabling display
>[  795.870768] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  795.870788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.870808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.870830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.870846] [drm:intel_power_well_disable [i915]] disabling always-on
>[  795.870892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.870901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  795.870948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.870967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.870987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.871017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.871034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.871051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.871067] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  795.871083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  795.871097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.871110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.871123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.871127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.871139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.871142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.871155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.871168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.871180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.871193] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  795.871208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.871220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.871233] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  795.871246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  795.871258] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  795.871274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.871290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  795.871377] [drm:intel_power_well_enable [i915]] enabling always-on
>[  795.871401] [drm:intel_power_well_enable [i915]] enabling display
>[  795.871424] [drm:hsw_set_power_well [i915]] Enabling power well
>[  795.871461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.871485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.871509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.871532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.871555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.871578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.871604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.871629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.871653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.871977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.872000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.872026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  795.872050] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  795.874049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  795.874065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  795.874079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.874093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  795.875601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  795.875616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  795.875630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.877123] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  795.877139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  795.878948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  795.881870] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  795.881905] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  795.881921] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  795.881943] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  795.881981] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  795.881997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  795.882040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.882066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.882098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.898713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.898755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.932008] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  795.932032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  795.932067] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  795.950930] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  795.950951] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  795.950967] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  795.950987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.951003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.951021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.951036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.951051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.951067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.951084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.951100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.951116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.951131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.951145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.951158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.951184] [drm:intel_power_well_disable [i915]] disabling display
>[  795.951206] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  795.951226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.951243] [drm:intel_power_well_disable [i915]] disabling always-on
>[  795.951393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.951407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  795.951477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.951503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.951531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.951560] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.951585] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.951611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.951637] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  795.951662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  795.951686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.951710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.951733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.951740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.951762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.951768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.951791] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.951814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.951837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.951860] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  795.951886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.951909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.951939] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  795.951958] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  795.951979] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  795.952003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.952028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  795.952092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  795.952115] [drm:intel_power_well_enable [i915]] enabling display
>[  795.952137] [drm:hsw_set_power_well [i915]] Enabling power well
>[  795.952174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.952197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.952219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.952242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.952261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.952284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.952309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.952355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.952381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.952403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.952425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.952452] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  795.952476] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  795.954471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  795.954488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  795.954502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.954517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  795.956021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  795.956036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  795.956050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.957547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  795.957562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  795.959369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  795.962305] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  795.962380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  795.962397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  795.962419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  795.962457] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  795.962474] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  795.979123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.979148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  795.979183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.979282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.979366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.012479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  796.012504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.012539] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  796.031438] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  796.031461] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  796.031481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.031503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.031522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.031544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.031563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.031583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.031602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.031623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.031644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.031664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.031685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.031703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.031720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.031747] [drm:intel_power_well_disable [i915]] disabling display
>[  796.031769] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.031794] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.031812] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.031918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.031927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.031968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.031987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.032006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.032026] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.032044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.032062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.032080] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  796.032098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  796.032117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.032134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.032152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.032155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.032173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.032176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.032194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.032212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.032230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.032248] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  796.032266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.032283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.032301] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  796.032363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  796.032392] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  796.032419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.032447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  796.032513] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.032537] [drm:intel_power_well_enable [i915]] enabling display
>[  796.032561] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.032600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.032624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.032648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.032671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.032695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.032718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.032743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.032768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.032792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.032814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.032836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.032869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  796.032892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.035004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.035021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.035035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.035050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.036557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.036572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.036587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.038080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.038096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.039903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.042824] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  796.042860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.042876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  796.042898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.042935] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  796.042952] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  796.059606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.059631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.059666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.059765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.059805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.092963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  796.092987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.093022] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  796.111081] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  796.111103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  796.111119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.111139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.111155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.111173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.111188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.111203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.111218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.111236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.111253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.111269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.111285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.111299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.111313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.111387] [drm:intel_power_well_disable [i915]] disabling display
>[  796.111422] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.111655] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.111683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.111834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.111847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.111903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.111919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.111935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.111953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.111967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.111982] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.111998] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  796.112012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  796.112026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.112039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.112052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.112055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.112068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.112071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.112085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.112098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.112110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.112123] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  796.112138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.112151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.112163] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  796.112176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  796.112189] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  796.112203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.112220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  796.112262] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.112275] [drm:intel_power_well_enable [i915]] enabling display
>[  796.112288] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.112312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.112357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.112379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.112402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.112425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.112449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.112474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.112499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.112523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.112545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.112568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.112595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  796.112618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.114864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.114880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.114896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.114914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.116434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.116451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.116465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.117970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.117988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.119817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.122755] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  796.122827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.122847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  796.122873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.122913] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  796.122932] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  796.139570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.139595] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.139629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.139719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.139759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.172928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  796.172954] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.172991] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  796.190881] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  796.190902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  796.190918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.190937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.190954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.190971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.190986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.191001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.191017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.191034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.191051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.191067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.191082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.191096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.191110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.191136] [drm:intel_power_well_disable [i915]] disabling display
>[  796.191158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.191178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.191195] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.191296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.191304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.191394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.191422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.191452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.191483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.191509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.191537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.191564] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  796.191590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  796.191616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.191646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.191668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.191675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.191695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.191702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.191723] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.191745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.191766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.191787] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  796.191810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.191831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.191852] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  796.191873] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  796.191894] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  796.191919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.191944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  796.192007] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.192030] [drm:intel_power_well_enable [i915]] enabling display
>[  796.192052] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.192088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.192111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.192133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.192155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.192174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.192197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.192221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.192245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.192269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.192290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.192309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.192351] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  796.192375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.194372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.194387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.194402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.194416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.195923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.195938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.195953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.197454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.197470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.199278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.202213] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  796.202288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.202305] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  796.202361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.202495] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  796.202513] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  796.219031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.219057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.219094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.219194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.219236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.252387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  796.252412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.252447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  796.271314] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  796.271354] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  796.271370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.271389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.271406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.271424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.271439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.271454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.271470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.271487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.271504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.271520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.271535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.271554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.271572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.271599] [drm:intel_power_well_disable [i915]] disabling display
>[  796.271622] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.271646] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.271664] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.271774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.271783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.271828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.271848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.271868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.271891] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.271910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.271929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.271948] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  796.271967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  796.271987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.272005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.272024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.272028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.272047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.272050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.272070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.272089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.272108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.272127] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  796.272146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.272164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.272183] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  796.272202] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  796.272221] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  796.272241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.272262] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  796.272307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.272323] [drm:intel_power_well_enable [i915]] enabling display
>[  796.272374] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.272418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.272446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.272473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.272498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.272523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.272557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.272584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.272608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.272633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.272655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.272678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.272704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  796.272728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.274726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.274741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.274755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.274773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.276281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.276296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.276310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.277842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.277858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.279697] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.282630] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  796.282706] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.282722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  796.282752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.282787] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  796.282802] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  796.299450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.299476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.299510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.299610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.299649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.332807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  796.332833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.332870] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  796.351803] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  796.351825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  796.351841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.351860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.351876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.351898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.351917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.351937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.351956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.351977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.351998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.352018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.352038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.352057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.352073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.352100] [drm:intel_power_well_disable [i915]] disabling display
>[  796.352123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.352147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  796.352165] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.352367] [drm:drm_mode_addfb2] [FB:77]
>[  796.352410] [drm:drm_mode_addfb2] [FB:78]
>[  796.375521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.375609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.375665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  796.375720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.375731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.375779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.375798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.375817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.375838] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.375856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.375874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.375892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.375909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.375927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.375944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.375961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.375965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.375982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.375986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.376004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.376021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.376038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.376056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.376074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.376091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.376108] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.376126] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.376143] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.376162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.376181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.378803] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.378820] [drm:intel_power_well_enable [i915]] enabling display
>[  796.378836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.378868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.378887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.378906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.378925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.378944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.378962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.378983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.379003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.379023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.379041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.379059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.379079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.379098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.381079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.381098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.381115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.381133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.382644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.382661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.382675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.384166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.384182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.385992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.388929] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.389009] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.389025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.389045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.405745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.405771] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.405808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.422492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.422513] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.422534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.422556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.422575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.422595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.422614] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.422634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.422653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.422672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.422691] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.422695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.422714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.422717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.422737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.422756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.422775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.422794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.422813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.422831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.422851] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  796.422871] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.422890] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.422910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.422929] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.422979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.423002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.423039] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.439851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.439870] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.439890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.439907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.439923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.439938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.439953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.439968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.439985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.440001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.440017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.440031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.440045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.440072] [drm:intel_power_well_disable [i915]] disabling display
>[  796.440093] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.440108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.440129] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.440149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.440165] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.440210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.440219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.440269] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.440286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.440303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.440321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.440336] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.440391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.440417] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.440441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.440464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.440486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.440507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.440514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.440535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.440541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.440563] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.440583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.440605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.440625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.440650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.440670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.440693] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  796.440713] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.440735] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.440762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.440788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.440846] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.440869] [drm:intel_power_well_enable [i915]] enabling display
>[  796.440892] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.440933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.440956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.440979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.441001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.441023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.441047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.441072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.441097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.441121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.441140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.441161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.441186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.441208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.443206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.443222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.443237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.443251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.444756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.444771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.444785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.446287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.446303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.448105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.451027] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.451063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.451079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.451101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.451159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.451185] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.451218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.467877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.467918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.484486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.484509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.484543] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.503418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.503437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.503457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.503474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.503491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.503506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.503521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.503537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.503554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.503575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.503595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.503616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.503635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.503651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.503679] [drm:intel_power_well_disable [i915]] disabling display
>[  796.503701] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.503725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.503742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.503850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.503858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.503900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.503917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.503934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.503952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.503967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.503983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.503998] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.504013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.504027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.504041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.504054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.504058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.504071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.504074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.504088] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.504101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.504114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.504127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.504142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.504156] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.504169] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.504182] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.504195] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.504211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.504227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.504270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.504283] [drm:intel_power_well_enable [i915]] enabling display
>[  796.504296] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.504321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.504339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.504395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.504417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.504438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.504459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.504482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.504505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.504529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.504548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.504568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.504592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.504614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.506614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.506631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.506645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.506663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.508168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.508184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.508198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.509694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.509710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.511519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.514462] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.514528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.514544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.514566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.531270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.531296] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.531330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.531506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.531561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.547968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.547992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.548029] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.566278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.566296] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.566316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.566333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.566391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.566415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.566440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.566464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.566493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.566518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.566545] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.566570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.566591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.566614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.566654] [drm:intel_power_well_disable [i915]] disabling display
>[  796.566687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.566718] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.566743] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.566895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.566905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.566948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.566965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.566983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.567002] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.567017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.567034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.567051] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.567074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.567089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.567104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.567118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.567122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.567135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.567139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.567158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.567184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.567198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.567215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.567232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.567249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.567267] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.567284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.567302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.567320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.567339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.567419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.567442] [drm:intel_power_well_enable [i915]] enabling display
>[  796.567465] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.567505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.567528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.567551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.567573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.567595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.567617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.567642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.567666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.567690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.567712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.567732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.567756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.567778] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.569775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.569793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.569810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.569828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.571341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.571370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.571385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.572955] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.572971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.574790] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.577740] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.577800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.577816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.577838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.594559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.594585] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.594620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.594712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.594751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.611239] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.611264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.611303] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.630159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.630177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.630198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.630214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.630232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.630247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.630262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.630277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.630298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.630319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.630340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.630404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.630433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.630459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.630500] [drm:intel_power_well_disable [i915]] disabling display
>[  796.630534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.630566] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.630599] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.630758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.630771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.630836] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.630860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.630885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.630912] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.630935] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.630958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.630983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.631006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.631028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.631050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.631070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.631076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.631097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.631102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.631123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.631144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.631163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.631184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.631207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.631228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.631247] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.631268] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.631287] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.631310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.631335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.631406] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.631430] [drm:intel_power_well_enable [i915]] enabling display
>[  796.631452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.631490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.631514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.631538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.631560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.631583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.631606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.631631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.631655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.631678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.631700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.631721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.631746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.631768] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.633775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.633792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.633806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.633822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.635329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.635347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.635396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.636899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.636917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.638730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.641664] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.641738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.641754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.641776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.658470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.658494] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.658527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.658626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.658664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.675182] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.675208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.675246] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.694109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.694127] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.694148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.694164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.694182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.694197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.694211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.694227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.694245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.694261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.694277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.694292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.694306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.694320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.694346] [drm:intel_power_well_disable [i915]] disabling display
>[  796.694413] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.694447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.694474] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.694612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.694626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.694695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.694720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.694745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.694774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.694796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.694822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.694845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.694870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.694892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.694915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.694936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.694942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.694963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.694969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.694992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.695013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.695035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.695063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.695085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.695104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.695125] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.695144] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.695164] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.695185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.695209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.695272] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.695294] [drm:intel_power_well_enable [i915]] enabling display
>[  796.695316] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.695353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.695392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.695415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.695435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.695457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.695478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.695503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.695528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.695553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.695573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.695595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.695620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.695642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.697637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.697654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.697668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.697683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.699187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.699202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.699216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.700715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.700733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.702543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.705486] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.705552] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.705569] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.705592] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.722295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.722321] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.722359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.722544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.722589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.738995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.739019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.739055] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.757462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.757481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.757502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.757519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.757537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.757552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.757567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.757583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.757601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.757617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.757633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.757648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.757662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.757676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.757702] [drm:intel_power_well_disable [i915]] disabling display
>[  796.757724] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.757744] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.757759] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.757859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.757868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.757910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.757926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.757944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.757963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.757979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.757995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.758012] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.758028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.758043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.758062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.758081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.758085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.758103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.758107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.758127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.758146] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.758165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.758184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.758203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.758222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.758241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.758260] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.758279] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.758299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.758320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.759025] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.759040] [drm:intel_power_well_enable [i915]] enabling display
>[  796.759053] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.759080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.759099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.759116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.759134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.759152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.759169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.759188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.759207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.759226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.759243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.759257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.759276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.759294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.761277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.761294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.761309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.761324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.762830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.762846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.762859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.764348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.764417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.766224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.769147] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.769181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.769198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.769220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.785926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.785952] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.785988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.786090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.786132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.802606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.802630] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.802674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.821535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.821554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.821574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.821591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.821608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.821623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.821638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.821656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.821678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.821699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.821719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.821739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.821758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.821775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.821802] [drm:intel_power_well_disable [i915]] disabling display
>[  796.821824] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.821849] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.821865] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.821976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.821985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.822031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.822051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.822070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.822092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.822111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.822139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.822156] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.822172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.822186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.822200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.822212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.822216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.822229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.822232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.822245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.822258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.822270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.822282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.822297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.822310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.822322] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.822334] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.822352] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.822408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.822432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.822495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.822515] [drm:intel_power_well_enable [i915]] enabling display
>[  796.822534] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.822573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.822596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.822618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.822640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.822656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.822671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.822687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.822702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.822717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.822730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.822743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.822759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.822773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.824751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.824767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.824781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.824796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.826309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.826325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.826338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.827834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.827850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.829658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.832586] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.832615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.832631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.832653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.849359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.849402] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.849439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.849532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.849574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.866059] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.866085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.866123] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.884140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.884159] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.884179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.884196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.884214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.884229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.884244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.884262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.884284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.884305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.884325] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.884346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.884364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.884423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.884466] [drm:intel_power_well_disable [i915]] disabling display
>[  796.884587] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.884611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.884635] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.884709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.884717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.884757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.884773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.884790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.884808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.884823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.884838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.884854] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  796.884868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  796.884883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.884897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.884910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.884914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.884927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.884930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.884944] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.884956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.884974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.884991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.885009] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.885026] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.885044] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  796.885062] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  796.885079] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  796.885098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.885117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  796.885159] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.885173] [drm:intel_power_well_enable [i915]] enabling display
>[  796.885188] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.885216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.885234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.885252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.885270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.885289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.885306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.885326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.885344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.885364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.885407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.885431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.885457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  796.885478] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.887473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.887489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.887503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.887518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.889022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.889040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.889057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.890556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.890573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.892399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.895334] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  796.895438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.895466] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  796.895549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  796.912142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.912167] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.912200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.912296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.912335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.928831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  796.928855] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  796.928899] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  796.947754] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  796.947773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  796.947793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.947810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.947828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.947843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.947858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.947874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  796.947892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.947908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.947924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.947939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.947953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.947967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.947994] [drm:intel_power_well_disable [i915]] disabling display
>[  796.948015] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  796.948035] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  796.948051] [drm:intel_power_well_disable [i915]] disabling always-on
>[  796.948206] [drm:drm_mode_addfb2] [FB:77]
>[  796.948230] [drm:drm_mode_addfb2] [FB:78]
>[  796.971141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  796.971229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  796.971287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  796.971340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  796.971350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  796.971452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  796.971475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  796.971503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  796.971532] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  796.971555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  796.971579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  796.971603] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  796.971627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  796.971649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  796.971669] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  796.971690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  796.971697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.971718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  796.971723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  796.971745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  796.971767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  796.971788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  796.971809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  796.971831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  796.971852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  796.971874] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  796.971895] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  796.971917] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  796.971941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  796.971968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  796.974589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  796.974604] [drm:intel_power_well_enable [i915]] enabling display
>[  796.974618] [drm:hsw_set_power_well [i915]] Enabling power well
>[  796.974646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  796.974662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  796.974677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  796.974691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  796.974708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  796.974726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  796.974745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  796.974764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  796.974783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  796.974800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  796.974815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  796.974834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  796.974852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  796.976848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  796.976865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  796.976880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.976895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  796.978434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  796.978450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  796.978464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  796.979962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  796.979979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  796.981788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  796.984741] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  796.984798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  796.984815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  796.984837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.001528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.001552] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.001585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.018283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.018301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.018320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.018340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.018357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.018377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.018436] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.018461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.018486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.018508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.018530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.018538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.018559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.018566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.018591] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.018614] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.018637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.018661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.018687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.018710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.018735] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  797.018758] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.018772] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.018789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.018808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.018853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.018874] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.018916] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.035739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.035758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.035778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.035795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.035811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.035826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.035841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.035859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.035880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.035901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.035921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.035940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.035956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.035984] [drm:intel_power_well_disable [i915]] disabling display
>[  797.036006] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.036026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.036047] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.036067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.036083] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.036121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.036131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.036177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.036197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.036216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.036238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.036257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.036277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.036296] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.036315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.036334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.036353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.036372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.036415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.036442] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.036448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.036473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.036496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.036518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.036540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.036565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.036587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.036610] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  797.036632] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.036653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.036678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.036704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.036764] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.036787] [drm:intel_power_well_enable [i915]] enabling display
>[  797.036812] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.036848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.036863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.036877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.036890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.036904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.036918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.036933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.036948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.036963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.036976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.036989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.037005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.037023] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.039007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.039023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.039038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.039052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.040560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.040575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.040589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.042081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.042097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.043907] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.046845] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.046916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.046933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.046955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.047012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.047039] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.047078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.063718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.063758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.080339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.080363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.080581] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.099147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.099165] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.099185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.099202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.099220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.099235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.099250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.099266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.099283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.099299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.099315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.099330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.099344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.099357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.099424] [drm:intel_power_well_disable [i915]] disabling display
>[  797.099460] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.099493] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.099519] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.099821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.099830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.099875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.099893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.099911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.099931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.099947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.099963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.099980] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.099996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.100011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.100025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.100039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.100043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.100057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.100061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.100075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.100089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.100102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.100116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.100132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.100146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.100160] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.100174] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.100187] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.100203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.100221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.100265] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.100279] [drm:intel_power_well_enable [i915]] enabling display
>[  797.100293] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.100325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.100339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.100353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.100365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.100405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.100430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.100455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.100479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.100504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.100524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.100546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.100572] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.100593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.102591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.102607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.102621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.102636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.104140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.104155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.104169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.105667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.105683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.107491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.110438] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.110508] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.110524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.110544] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.127244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.127269] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.127305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.127519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.127559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.143944] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.143968] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.144004] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.162072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.162093] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.162115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.162135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.162156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.162175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.162195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.162214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.162236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.162256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.162277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.162297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.162316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.162332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.162359] [drm:intel_power_well_disable [i915]] disabling display
>[  797.162422] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.162461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.162488] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.162665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.162679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.162749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.162774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.162805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.162832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.162853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.162876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.162898] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.162920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.162940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.162961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.162980] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.162985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.163004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.163009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.163030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.163049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.163070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.163088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.163111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.163130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.163151] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.163169] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.163189] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.163210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.163234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.163297] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.163319] [drm:intel_power_well_enable [i915]] enabling display
>[  797.163340] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.163377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.163420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.163445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.163465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.163487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.163509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.163534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.163559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.163583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.163603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.163625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.163650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.163672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.165666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.165684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.165702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.165720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.167226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.167243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.167257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.168760] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.168777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.170587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.173534] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.173598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.173617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.173643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.190339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.190365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.190447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.190599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.190639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.207039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.207063] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.207100] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.225973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.225992] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.226013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.226029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.226047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.226062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.226076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.226095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.226116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.226137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.226158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.226178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.226197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.226216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.226243] [drm:intel_power_well_disable [i915]] disabling display
>[  797.226265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.226290] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.226306] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.226428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.226443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.226513] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.226537] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.226564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.226594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.226617] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.226643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.226667] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.226691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.226714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.226737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.226758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.226764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.226785] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.226791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.226815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.226836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.226858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.226879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.226904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.226925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.226948] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.226969] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.226991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.227014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.227040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.227109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.227134] [drm:intel_power_well_enable [i915]] enabling display
>[  797.227158] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.227203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.227224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.227245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.227265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.227286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.227306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.227330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.227353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.227376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.227413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.227435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.227459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.227483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.229496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.229521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.229543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.229567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.231091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.231114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.231136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.232652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.232676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.234504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.237698] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.237776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.237799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.237832] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.254516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.254542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.254579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.254698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.254739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.271191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.271218] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.271256] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.290096] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.290115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.290136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.290153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.290170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.290185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.290200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.290216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.290233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.290250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.290266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.290281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.290296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.290309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.290336] [drm:intel_power_well_disable [i915]] disabling display
>[  797.290358] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.290379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.290435] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.290609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.290625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.290698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.290720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.290744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.290771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.290791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.290814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.290836] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.290858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.290878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.290899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.290918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.290924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.290943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.290948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.290969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.290988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.291008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.291026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.291048] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.291067] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.291087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.291106] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.291126] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.291147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.291171] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.291233] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.291255] [drm:intel_power_well_enable [i915]] enabling display
>[  797.291276] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.291314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.291335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.291356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.291375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.291413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.291435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.291459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.291484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.291509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.291529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.291550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.291576] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.291597] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.293592] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.293607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.293621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.293636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.295141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.295157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.295171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.296670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.296686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.298494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.301441] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.301504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.301521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.301543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.318247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.318273] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.318308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.318521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.318562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.334946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.334970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.335007] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.353484] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.353502] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.353522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.353539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.353557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.353572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.353586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.353602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.353623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.353644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.353665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.353685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.353704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.353721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.353748] [drm:intel_power_well_disable [i915]] disabling display
>[  797.353771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.353795] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.353812] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.353924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.353933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.353979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.353999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.354019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.354041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.354060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.354086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.354102] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.354118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.354132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.354146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.354158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.354162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.354174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.354178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.354191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.354204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.354216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.354228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.354243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.354256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.354269] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.354281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.354294] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.354308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.354325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.354366] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.354379] [drm:intel_power_well_enable [i915]] enabling display
>[  797.354427] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.354465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.354486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.354507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.354528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.354548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.354568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.354592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.354614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.354637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.354656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.354676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.354699] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.354720] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.356942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.356959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.356977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.356995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.358514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.358538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.358560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.360057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.360073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.361896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.364855] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.364906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.364923] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.364945] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.381648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.381675] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.381713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.381807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.381849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.398344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.398369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.398449] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.417395] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.417432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.417452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.417469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.417487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.417502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.417516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.417533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.417551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.417567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.417583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.417599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.417613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.417627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.417653] [drm:intel_power_well_disable [i915]] disabling display
>[  797.417675] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.417695] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.417711] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.417796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.417806] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.417848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.417864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.417881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.417900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.417917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.417937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.417956] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.417975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.417995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.418014] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.418032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.418037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.418055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.418059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.418079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.418098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.418117] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.418136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.418155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.418174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.418193] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.418212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.418231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.418251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.418272] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.418319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.418334] [drm:intel_power_well_enable [i915]] enabling display
>[  797.418349] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.418379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.418398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.418451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.418479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.418514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.418539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.418565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.418591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.418616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.418638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.418661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.418687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.418711] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.420725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.420743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.420761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.420779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.422287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.422304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.422319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.423817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.423835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.425645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.428591] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.428654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.428673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.428706] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.445397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.445440] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.445478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.445578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.445619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.462077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.462101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.462145] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.481009] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.481028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.481048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.481066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.481083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.481098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.481113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.481129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.481147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.481163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.481183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.481204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.481223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.481240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.481267] [drm:intel_power_well_disable [i915]] disabling display
>[  797.481289] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.481314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.481330] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.481503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.481518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  797.481590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.481618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.481646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.481675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.481698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.481724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.481748] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  797.481772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  797.481795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.481817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.481838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.481844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.481865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.481871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.481893] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.481914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.481943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.481962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  797.481984] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.482003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.482023] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  797.482042] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  797.482062] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  797.482083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.482107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  797.482169] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.482190] [drm:intel_power_well_enable [i915]] enabling display
>[  797.482212] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.482249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.482270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.482290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.482311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.482330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.482351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.482375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.482398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.482439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.482458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.482479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.482505] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  797.482527] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.484526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.484543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.484557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.484572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.486076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.486094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.486111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.487610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.487627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.489435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.492371] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  797.492471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.492498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  797.492534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.509186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.509213] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.509251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.509353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  797.509394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.525887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  797.525910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  797.525947] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  797.544819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  797.544838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  797.544858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.544878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.544899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.544919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.544938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.544957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.544979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.544999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.545020] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.545040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.545059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.545075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.545102] [drm:intel_power_well_disable [i915]] disabling display
>[  797.545124] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  797.545149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  797.545165] [drm:intel_power_well_disable [i915]] disabling always-on
>[  797.547611] [IGT] kms_flip: exiting, ret=0
>[  797.566976] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  797.566996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  797.567016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  797.567040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  797.567058] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  797.567078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  797.567098] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  797.567118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  797.567138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  797.567158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  797.567177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  797.567182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.567201] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  797.567204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.567224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  797.567244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  797.567263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  797.567283] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  797.567303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  797.567322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  797.567342] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  797.567361] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  797.567381] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  797.567402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  797.567438] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  797.567504] [drm:intel_power_well_enable [i915]] enabling always-on
>[  797.567521] [drm:intel_power_well_enable [i915]] enabling display
>[  797.567537] [drm:hsw_set_power_well [i915]] Enabling power well
>[  797.567570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  797.567590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  797.567611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  797.567631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  797.567651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  797.567670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  797.567693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  797.567715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  797.567736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.567755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  797.567774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  797.567796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  797.567815] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  797.569811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  797.569827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  797.569840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.569855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  797.571363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  797.571376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  797.571389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  797.572908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  797.572922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  797.574735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  797.577760] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  797.577794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  797.577811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  797.577834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  797.577881] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  797.577900] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  797.594544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  797.594569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  797.594606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  797.594734] Console: switching to colour frame buffer device 240x75
>[  797.725537] Console: switching to colour dummy device 80x25
>[  797.725632] [IGT] kms_flip: executing
>[  797.739919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  797.739948] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  797.741483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  797.741504] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  797.743478] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  797.743485] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  797.745476] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  797.745496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  797.747483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  797.747490] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  797.747495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  797.747512] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  797.747535] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  797.748567] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  797.749468] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  797.749494] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  797.749515] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  797.749538] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  797.750531] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  797.750554] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  797.751602] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  797.751605] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  797.751685] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  797.751687] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  797.751691] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  797.751693] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  797.751697] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  797.751699] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  797.751707] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  797.751709] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.751712] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.751714] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.751717] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  797.751719] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  797.751722] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  797.751724] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  797.751727] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.751729] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.751731] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  797.751734] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  797.751736] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  797.751739] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  797.751741] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  797.751744] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  797.751746] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  797.751748] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  797.751751] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  797.751753] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  797.751756] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  797.751758] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  797.751760] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  797.751763] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  797.751765] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  797.751768] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  797.751770] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  797.751773] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  797.751775] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  797.751777] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  797.751780] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  797.751811] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  797.751829] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  797.753479] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  797.753499] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  797.755556] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  797.755562] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  797.757475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  797.757495] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  797.759478] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  797.759483] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  797.759487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  797.759694] [IGT] kms_flip: starting subtest 2x-flip-vs-modeset
>[  797.762062] [IGT] kms_flip: exiting, ret=77
>[  797.794781] Console: switching to colour frame buffer device 240x75
>[  797.923211] Console: switching to colour dummy device 80x25
>[  797.923304] [IGT] kms_flip: executing
>[  797.933945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  797.933974] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  797.935495] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  797.935515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  797.937487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  797.937493] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  797.939493] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  797.939513] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  797.941489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  797.941496] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  797.941500] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  797.941516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  797.941538] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  797.942566] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  797.943471] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  797.943488] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  797.943503] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  797.943516] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  797.944498] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  797.944514] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  797.945586] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  797.945589] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  797.945669] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  797.945671] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  797.945675] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  797.945677] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  797.945681] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  797.945683] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  797.945690] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  797.945693] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  797.945695] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.945698] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.945700] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  797.945703] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  797.945705] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  797.945708] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  797.945710] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.945713] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  797.945715] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  797.945717] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  797.945720] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  797.945722] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  797.945725] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  797.945727] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  797.945730] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  797.945732] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  797.945734] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  797.945737] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  797.945739] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  797.945742] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  797.945744] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  797.945747] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  797.945749] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  797.945751] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  797.945754] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  797.945756] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  797.945759] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  797.945761] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  797.945763] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  797.945793] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  797.945810] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  797.947480] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  797.947496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  797.949487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  797.949492] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  797.951487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  797.951507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  797.953487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  797.953493] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  797.953497] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  797.954747] [IGT] kms_flip: starting subtest 2x-absolute-wf_vblank-interruptible
>[  797.956122] [IGT] kms_flip: exiting, ret=77
>[  797.994996] Console: switching to colour frame buffer device 240x75
>[  798.125171] Console: switching to colour dummy device 80x25
>[  798.125263] [IGT] kms_flip: executing
>[  798.138991] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  798.139019] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  798.140503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  798.140524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  798.142498] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  798.142505] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  798.144499] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  798.144519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  798.146506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  798.146512] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  798.146516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  798.146532] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  798.146554] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  798.147582] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  798.148490] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  798.148515] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  798.148538] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  798.148553] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  798.149541] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  798.149564] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  798.150615] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  798.150618] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  798.150697] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  798.150699] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  798.150703] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  798.150705] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  798.150710] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  798.150712] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  798.150719] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  798.150722] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  798.150725] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  798.150727] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  798.150729] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  798.150732] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  798.150734] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  798.150737] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  798.150739] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  798.150742] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  798.150744] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  798.150747] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  798.150749] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  798.150751] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  798.150754] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  798.150756] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  798.150759] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  798.150761] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  798.150764] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  798.150766] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  798.150768] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  798.150771] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  798.150773] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  798.150776] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  798.150778] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  798.150780] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  798.150783] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  798.150785] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  798.150788] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  798.150790] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  798.150792] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  798.150822] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  798.150839] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  798.152489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  798.152508] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  798.154512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  798.154518] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  798.156505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  798.156526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  798.158487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  798.158493] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  798.158497] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  798.159667] [IGT] kms_flip: starting subtest absolute-wf_vblank-interruptible
>[  798.160065] [drm:drm_mode_addfb2] [FB:75]
>[  798.160086] [drm:drm_mode_addfb2] [FB:79]
>[  798.202507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  798.202559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  798.211755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  798.211781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  798.211821] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  798.230215] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  798.230239] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  798.230259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  798.230282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  798.230301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  798.230323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  798.230343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  798.230362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  798.230381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  798.230403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  798.230424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  798.230444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  798.230507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  798.230542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  798.230565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  798.230609] [drm:intel_power_well_disable [i915]] disabling display
>[  798.230646] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  798.230681] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  798.230710] [drm:intel_power_well_disable [i915]] disabling always-on
>[  798.230764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  798.230845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  798.230923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  798.230942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  798.230982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  798.230998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  798.231016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  798.231036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  798.231054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  798.231073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  798.231091] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  798.231109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  798.231127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  798.231145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  798.231162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  798.231167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  798.231184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  798.231187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  798.231204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  798.231222] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  798.231240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  798.231257] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  798.231276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  798.231293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  798.231311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  798.231329] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  798.231347] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  798.231366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  798.231385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  798.233888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  798.233903] [drm:intel_power_well_enable [i915]] enabling display
>[  798.233916] [drm:hsw_set_power_well [i915]] Enabling power well
>[  798.233943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  798.233959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  798.233974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  798.233988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  798.234001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  798.234018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  798.234038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  798.234057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  798.234075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  798.234092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  798.234107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  798.234126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  798.234143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  798.236115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  798.236132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  798.236146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  798.236161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  798.237667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  798.237682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  798.237696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  798.239186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  798.239202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  798.241005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  798.243927] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  798.243962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  798.243978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  798.244001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  798.244039] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  798.244055] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  798.260705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  798.260730] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  798.260763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  808.286416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  808.303000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  808.303026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  808.303110] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  808.321971] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  808.321994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  808.322011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  808.322042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  808.322104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  808.322134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  808.322157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  808.322182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  808.322205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  808.322234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  808.322261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  808.322286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  808.322311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  808.322332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  808.322354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  808.322397] [drm:intel_power_well_disable [i915]] disabling display
>[  808.322431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  808.322463] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  808.322490] [drm:intel_power_well_disable [i915]] disabling always-on
>[  808.322701] [drm:drm_mode_addfb2] [FB:75]
>[  808.322725] [drm:drm_mode_addfb2] [FB:78]
>[  808.345373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  808.345459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  808.345516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  808.345564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  808.345574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  808.345624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  808.345642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  808.345661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  808.345681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  808.345696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  808.345713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  808.345730] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  808.345745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  808.345761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  808.345778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  808.345797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  808.345801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  808.345819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  808.345822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  808.345841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  808.345860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  808.345879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  808.345897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  808.345916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  808.345934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  808.345953] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  808.345972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  808.345990] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  808.346010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  808.346031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  808.348562] [drm:intel_power_well_enable [i915]] enabling always-on
>[  808.348579] [drm:intel_power_well_enable [i915]] enabling display
>[  808.348593] [drm:hsw_set_power_well [i915]] Enabling power well
>[  808.348623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  808.348640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  808.348659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  808.348678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  808.348697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  808.348715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  808.348736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  808.348755] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  808.348775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  808.348794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  808.348810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  808.348830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  808.348849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  808.350836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  808.350853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  808.350868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  808.350883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  808.352390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  808.352406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  808.352420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  808.353913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  808.353929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  808.355737] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  808.358375] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  808.358443] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  808.358460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  808.358483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  808.375185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  808.375211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  808.375246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  818.400868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  818.400920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  818.400945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  818.400986] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  818.419827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  818.419846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  818.419867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  818.419884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  818.419903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  818.419918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  818.419934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  818.419950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  818.419968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  818.419985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  818.420001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  818.420020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  818.420040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  818.420059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  818.420088] [drm:intel_power_well_disable [i915]] disabling display
>[  818.420111] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  818.420137] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  818.420154] [drm:intel_power_well_disable [i915]] disabling always-on
>[  818.420369] [drm:drm_mode_addfb2] [FB:75]
>[  818.420392] [drm:drm_mode_addfb2] [FB:78]
>[  818.443712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  818.443803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  818.443864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  818.443919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  818.443929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  818.443980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  818.443999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  818.444019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  818.444040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  818.444056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  818.444073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  818.444092] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  818.444111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  818.444131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  818.444149] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  818.444168] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  818.444171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  818.444190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  818.444193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  818.444212] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  818.444230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  818.444249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  818.444267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  818.444286] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  818.444304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  818.444323] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  818.444342] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  818.444361] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  818.444380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  818.444401] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  818.446928] [drm:intel_power_well_enable [i915]] enabling always-on
>[  818.446945] [drm:intel_power_well_enable [i915]] enabling display
>[  818.446959] [drm:hsw_set_power_well [i915]] Enabling power well
>[  818.446990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  818.447007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  818.447023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  818.447038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  818.447053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  818.447069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  818.447085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  818.447101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  818.447117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  818.447131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  818.447149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  818.447169] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  818.447197] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  818.449208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  818.449225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  818.449239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  818.449254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  818.450778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  818.450795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  818.450810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  818.452305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  818.452322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  818.454128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  818.457074] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  818.457138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  818.457155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  818.457177] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  818.473881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  818.473907] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  818.473943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.499567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  828.499618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  828.499642] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  828.499682] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  828.518547] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  828.518566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  828.518587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  828.518604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  828.518622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  828.518637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  828.518653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  828.518669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  828.518687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  828.518703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  828.518719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  828.518735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.518749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  828.518763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  828.518791] [drm:intel_power_well_disable [i915]] disabling display
>[  828.518813] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  828.518835] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  828.518851] [drm:intel_power_well_disable [i915]] disabling always-on
>[  828.520350] [IGT] kms_flip: exiting, ret=0
>[  828.544698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  828.544717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  828.544737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  828.544758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  828.544774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  828.544792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  828.544810] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  828.544826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  828.544842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  828.544857] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  828.544872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  828.544877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  828.544892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  828.544894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  828.544914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  828.544934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  828.544954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  828.544973] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  828.544994] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  828.545013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  828.545033] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  828.545052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  828.545072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  828.545093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  828.545115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  828.545182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  828.545199] [drm:intel_power_well_enable [i915]] enabling display
>[  828.545215] [drm:hsw_set_power_well [i915]] Enabling power well
>[  828.545249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  828.545269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  828.545303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  828.545323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  828.545343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  828.545362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  828.545385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  828.545406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  828.545427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.545446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  828.545466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  828.545487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  828.545507] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  828.547518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  828.547535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  828.547552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  828.547570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  828.549088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  828.549103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  828.549117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  828.550620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  828.550636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  828.552456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  828.555501] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  828.555566] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  828.555582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  828.555605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  828.555652] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  828.555671] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  828.572316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  828.572340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  828.572377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.572502] Console: switching to colour frame buffer device 240x75
>[  828.877949] Console: switching to colour dummy device 80x25
>[  828.878042] [IGT] kms_flip: executing
>[  828.887848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  828.887877] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  828.889351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  828.889371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  828.891354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  828.891360] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  828.893350] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  828.893370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  828.895350] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  828.895356] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  828.895361] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  828.895377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  828.895399] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  828.896429] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  828.897334] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  828.897360] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  828.897383] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  828.897399] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  828.898387] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  828.898410] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  828.899479] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  828.899482] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  828.899561] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  828.899563] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  828.899567] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  828.899569] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  828.899574] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  828.899576] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  828.899583] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  828.899586] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  828.899588] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  828.899591] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  828.899593] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  828.899596] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  828.899598] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  828.899601] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  828.899603] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  828.899606] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  828.899608] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  828.899610] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  828.899613] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  828.899615] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  828.899618] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  828.899620] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  828.899623] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  828.899625] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  828.899627] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  828.899630] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  828.899632] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  828.899635] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  828.899637] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  828.899640] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  828.899642] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  828.899644] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  828.899647] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  828.899649] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  828.899652] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  828.899654] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  828.899656] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  828.899686] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  828.899703] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  828.901352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  828.901376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  828.903360] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  828.903366] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  828.905342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  828.905360] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  828.907342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  828.907347] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  828.907352] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  828.907559] [IGT] kms_flip: starting subtest blocking-absolute-wf_vblank
>[  828.907963] [drm:drm_mode_addfb2] [FB:77]
>[  828.907985] [drm:drm_mode_addfb2] [FB:79]
>[  828.950409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  828.950462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  828.955990] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  828.956016] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  828.956056] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  828.974915] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  828.974938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  828.974955] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  828.974976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  828.974993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  828.975011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  828.975027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  828.975042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  828.975058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  828.975075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  828.975092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  828.975108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  828.975124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.975138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  828.975152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  828.975180] [drm:intel_power_well_disable [i915]] disabling display
>[  828.975202] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  828.975225] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  828.975243] [drm:intel_power_well_disable [i915]] disabling always-on
>[  828.975284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  828.975419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  828.975481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  828.975492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  828.975536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  828.975554] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  828.975572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  828.975593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  828.975608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  828.975625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  828.975643] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  828.975659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  828.975675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  828.975690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  828.975705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  828.975709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  828.975724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  828.975728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  828.975742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  828.975761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  828.975780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  828.975800] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  828.975820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  828.975839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  828.975859] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  828.975878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  828.975898] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  828.975918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  828.975939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  828.978454] [drm:intel_power_well_enable [i915]] enabling always-on
>[  828.978468] [drm:intel_power_well_enable [i915]] enabling display
>[  828.978481] [drm:hsw_set_power_well [i915]] Enabling power well
>[  828.978508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  828.978524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  828.978539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  828.978553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  828.978566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  828.978581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  828.978596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  828.978611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  828.978625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  828.978638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  828.978651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  828.978667] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  828.978682] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  828.980652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  828.980668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  828.980682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  828.980697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  828.982199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  828.982217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  828.982234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  828.983732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  828.983748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  828.985551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  828.988485] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  828.988559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  828.988575] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  828.988598] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  828.988639] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  828.988657] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  829.005304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  829.005346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  829.005381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  839.031294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  839.047603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  839.047631] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  839.047674] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  839.066570] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  839.066595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  839.066613] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  839.066636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  839.066654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  839.066674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  839.066691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  839.066707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  839.066725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  839.066745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  839.066763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  839.066780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  839.066797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  839.066813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  839.066828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  839.066859] [drm:intel_power_well_disable [i915]] disabling display
>[  839.066883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  839.066954] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  839.066985] [drm:intel_power_well_disable [i915]] disabling always-on
>[  839.067183] [drm:drm_mode_addfb2] [FB:77]
>[  839.067208] [drm:drm_mode_addfb2] [FB:78]
>[  839.092579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  839.092667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  839.092723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  839.092777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  839.092787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  839.092837] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  839.092855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  839.092873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  839.092894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  839.092945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  839.092972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  839.092996] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  839.093021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  839.093045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  839.093068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  839.093090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  839.093097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  839.093119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  839.093125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  839.093147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  839.093168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  839.093189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  839.093211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  839.093234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  839.093254] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  839.093276] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  839.093298] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  839.093321] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  839.093344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  839.093371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  839.095991] [drm:intel_power_well_enable [i915]] enabling always-on
>[  839.096006] [drm:intel_power_well_enable [i915]] enabling display
>[  839.096020] [drm:hsw_set_power_well [i915]] Enabling power well
>[  839.096049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  839.096067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  839.096085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  839.096103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  839.096121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  839.096138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  839.096158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  839.096177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  839.096196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  839.096213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  839.096228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  839.096247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  839.096265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  839.098262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  839.098279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  839.098294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  839.098309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  839.099816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  839.099832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  839.099845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  839.102424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  839.102445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  839.104294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  839.107244] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  839.107304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  839.107321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  839.107344] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  839.124046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  839.124072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  839.124107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  849.149801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  849.149882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  849.149922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  849.149988] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  849.166807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  849.166827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  849.166847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  849.166864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  849.166886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  849.166906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  849.166925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  849.166944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  849.166966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  849.166987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  849.167008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  849.167028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  849.167047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  849.167066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  849.167096] [drm:intel_power_well_disable [i915]] disabling display
>[  849.167119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  849.167144] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  849.167160] [drm:intel_power_well_disable [i915]] disabling always-on
>[  849.167363] [drm:drm_mode_addfb2] [FB:77]
>[  849.167385] [drm:drm_mode_addfb2] [FB:78]
>[  849.190415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  849.190497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  849.190613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  849.190678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  849.190687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  849.190734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  849.190753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  849.190773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  849.190794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  849.190811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  849.190830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  849.190848] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  849.190866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  849.190884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  849.190901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  849.190918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  849.190922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  849.190940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  849.190943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  849.190961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  849.190978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  849.190996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  849.191013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  849.191031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  849.191048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  849.191066] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  849.191084] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  849.191101] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  849.191119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  849.191139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  849.193683] [drm:intel_power_well_enable [i915]] enabling always-on
>[  849.193700] [drm:intel_power_well_enable [i915]] enabling display
>[  849.193716] [drm:hsw_set_power_well [i915]] Enabling power well
>[  849.193747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  849.193766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  849.193785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  849.193804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  849.193823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  849.193842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  849.193862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  849.193882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  849.193902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  849.193920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  849.193936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  849.193957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  849.193976] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  849.195979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  849.195996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  849.196010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  849.196025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  849.197547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  849.197564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  849.197579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  849.199081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  849.199098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  849.200922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  849.203869] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  849.203940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  849.203956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  849.203977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  849.220676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  849.220703] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  849.220741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.246487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  859.246594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  859.246644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  859.246728] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  859.263681] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  859.263701] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  859.263722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  859.263739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  859.263760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  859.263780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  859.263800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  859.263819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  859.263841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  859.263862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  859.263883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  859.263904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.263923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  859.263942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  859.263971] [drm:intel_power_well_disable [i915]] disabling display
>[  859.263995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  859.264020] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  859.264037] [drm:intel_power_well_disable [i915]] disabling always-on
>[  859.266462] [IGT] kms_flip: exiting, ret=0
>[  859.286625] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  859.286645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  859.286665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  859.286689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  859.286708] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  859.286729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  859.286749] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  859.286769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  859.286789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  859.286809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  859.286828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  859.286833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  859.286852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  859.286855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  859.286875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  859.286895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  859.286914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  859.286934] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  859.286954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  859.286973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  859.286993] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  859.287013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  859.287032] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  859.287054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  859.287076] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  859.287155] [drm:intel_power_well_enable [i915]] enabling always-on
>[  859.287172] [drm:intel_power_well_enable [i915]] enabling display
>[  859.287189] [drm:hsw_set_power_well [i915]] Enabling power well
>[  859.287222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  859.287243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  859.287263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  859.287283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  859.287303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  859.287322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  859.287344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  859.287366] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  859.287387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.287407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  859.287426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  859.287447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  859.287467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  859.289479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  859.289495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  859.289511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  859.289530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  859.291062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  859.291077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  859.291091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  859.292595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  859.292611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  859.294428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  859.297460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  859.297489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  859.297508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  859.297534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  859.297582] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  859.297601] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  859.314237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  859.314261] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  859.314298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.314423] Console: switching to colour frame buffer device 240x75
>[  859.623229] Console: switching to colour dummy device 80x25
>[  859.623329] [IGT] kms_flip: executing
>[  859.633682] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  859.633710] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  859.635200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  859.635220] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  859.637204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  859.637210] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  859.639200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  859.639219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  859.641200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  859.641205] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  859.641210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  859.641226] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  859.641249] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  859.642287] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  859.643206] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  859.643223] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  859.643238] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  859.643252] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  859.644239] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  859.644261] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  859.645316] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  859.645318] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  859.645398] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  859.645400] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  859.645404] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  859.645406] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  859.645410] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  859.645412] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  859.645419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  859.645422] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  859.645425] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  859.645427] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  859.645430] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  859.645432] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  859.645435] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  859.645437] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  859.645439] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  859.645442] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  859.645444] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  859.645447] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  859.645449] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  859.645452] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  859.645454] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  859.645456] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  859.645459] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  859.645461] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  859.645464] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  859.645466] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  859.645469] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  859.645471] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  859.645474] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  859.645476] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  859.645478] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  859.645481] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  859.645483] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  859.645486] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  859.645488] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  859.645490] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  859.645493] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  859.645523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  859.645540] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  859.647171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  859.647189] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  859.649246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  859.649252] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  859.651320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  859.651340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  859.653406] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  859.653412] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  859.653416] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  859.654687] [IGT] kms_flip: starting subtest dpms-off-confusion-interruptible
>[  859.655195] [drm:drm_mode_addfb2] [FB:75]
>[  859.655218] [drm:drm_mode_addfb2] [FB:79]
>[  859.698150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  859.698201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  859.714589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  859.714615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  859.714655] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  859.733525] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  859.733548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  859.733565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  859.733585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  859.733602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  859.733620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  859.733636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  859.733651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  859.733667] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  859.733688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  859.733708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  859.733729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  859.733749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.733768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  859.733786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  859.733814] [drm:intel_power_well_disable [i915]] disabling display
>[  859.733837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  859.733862] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  859.733881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  859.733935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  859.734010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  859.734069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  859.734079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  859.734124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  859.734144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  859.734208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  859.734245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  859.734266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  859.734290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  859.734312] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  859.734335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  859.734356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  859.734377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  859.734397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  859.734402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  859.734422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  859.734427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  859.734447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  859.734467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  859.734487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  859.734505] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  859.734528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  859.734547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  859.734568] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  859.734587] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  859.734607] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  859.734628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  859.734652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  859.737175] [drm:intel_power_well_enable [i915]] enabling always-on
>[  859.737190] [drm:intel_power_well_enable [i915]] enabling display
>[  859.737203] [drm:hsw_set_power_well [i915]] Enabling power well
>[  859.737229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  859.737245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  859.737259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  859.737273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  859.737286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  859.737303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  859.737322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  859.737341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  859.737360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  859.737377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  859.737392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  859.737411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  859.737428] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  859.739401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  859.739417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  859.739432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  859.739447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  859.740955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  859.740971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  859.740985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  859.742483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  859.742499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  859.744309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  859.747258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  859.747318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  859.747335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  859.747357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  859.747396] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  859.747413] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  859.764062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  859.764087] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  859.764122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  869.789757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  869.806346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  869.806371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  869.806411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  869.825286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  869.825309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  869.825326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  869.825346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  869.825363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  869.825382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  869.825398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  869.825413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  869.825429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  869.825448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  869.825464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  869.825481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  869.825497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  869.825511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  869.825525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  869.825553] [drm:intel_power_well_disable [i915]] disabling display
>[  869.825575] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  869.825597] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  869.825614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  869.825855] [drm:drm_mode_addfb2] [FB:75]
>[  869.825896] [drm:drm_mode_addfb2] [FB:78]
>[  869.851570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  869.851657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  869.851715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  869.851799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  869.851815] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  869.851886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  869.851909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  869.851935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  869.851962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  869.851982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  869.852006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  869.852028] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  869.852051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  869.852071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  869.852093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  869.852113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  869.852118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  869.852138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  869.852143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  869.852165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  869.852184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  869.852204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  869.852222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  869.852245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  869.852264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  869.852285] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  869.852305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  869.852325] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  869.852346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  869.852370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  869.854998] [drm:intel_power_well_enable [i915]] enabling always-on
>[  869.855015] [drm:intel_power_well_enable [i915]] enabling display
>[  869.855029] [drm:hsw_set_power_well [i915]] Enabling power well
>[  869.855059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  869.855077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  869.855093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  869.855109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  869.855123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  869.855139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  869.855155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  869.855171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  869.855187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  869.855203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  869.855221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  869.855241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  869.855260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  869.857248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  869.857264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  869.857278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  869.857293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  869.858825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  869.858840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  869.858853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  869.860353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  869.860370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  869.862184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  869.865141] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  869.865195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  869.865211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  869.865233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  869.881936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  869.881961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  869.881994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  879.907635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  879.907680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  879.907703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  879.907743] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  879.926600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  879.926619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  879.926640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  879.926657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  879.926675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  879.926690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  879.926705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  879.926721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  879.926739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  879.926755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  879.926771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  879.926787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  879.926801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  879.926815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  879.926843] [drm:intel_power_well_disable [i915]] disabling display
>[  879.926865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  879.926886] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  879.926902] [drm:intel_power_well_disable [i915]] disabling always-on
>[  879.927106] [drm:drm_mode_addfb2] [FB:75]
>[  879.927130] [drm:drm_mode_addfb2] [FB:78]
>[  879.950244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  879.950331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  879.950445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  879.950516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  879.950527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  879.950576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  879.950592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  879.950610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  879.950628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  879.950642] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  879.950657] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  879.950672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  879.950687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  879.950701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  879.950714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  879.950727] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  879.950730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  879.950743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  879.950746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  879.950759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  879.950772] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  879.950784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  879.950796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  879.950812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  879.950824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  879.950837] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  879.950849] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  879.950862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  879.950877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  879.950894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  879.953410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  879.953426] [drm:intel_power_well_enable [i915]] enabling display
>[  879.953441] [drm:hsw_set_power_well [i915]] Enabling power well
>[  879.953471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  879.953490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  879.953510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  879.953528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  879.953547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  879.953566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  879.953586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  879.953606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  879.953626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  879.953645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  879.953661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  879.953681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  879.953700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  879.955692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  879.955709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  879.955723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  879.955738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  879.957244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  879.957259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  879.957272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  879.958771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  879.958787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  879.960595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  879.963769] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  879.963806] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  879.963823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  879.963846] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  879.980559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  879.980586] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  879.980621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.006246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  890.006291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  890.006314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  890.006353] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  890.024572] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  890.024591] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  890.024612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  890.024629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  890.024647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  890.024662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  890.024677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  890.024694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  890.024712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  890.024729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  890.024744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  890.024760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.024774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  890.024788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  890.024816] [drm:intel_power_well_disable [i915]] disabling display
>[  890.024838] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  890.024862] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  890.024879] [drm:intel_power_well_disable [i915]] disabling always-on
>[  890.026287] [IGT] kms_flip: exiting, ret=0
>[  890.044447] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  890.044466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  890.044484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  890.044504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  890.044522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  890.044542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  890.044561] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  890.044579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  890.044598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  890.044616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  890.044634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  890.044639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.044657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  890.044660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.044678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  890.044697] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  890.044714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  890.044732] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  890.044751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  890.044769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  890.044788] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  890.044806] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  890.044824] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  890.044844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  890.044864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  890.044931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  890.044947] [drm:intel_power_well_enable [i915]] enabling display
>[  890.044965] [drm:hsw_set_power_well [i915]] Enabling power well
>[  890.045022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  890.045039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  890.045054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  890.045069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  890.045083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  890.045098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  890.045115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  890.045131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  890.045147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.045161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  890.045174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  890.045192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  890.045207] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  890.047195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  890.047210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  890.047223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  890.047237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  890.048750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  890.048763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  890.048776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  890.050278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  890.050293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  890.052108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  890.055146] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  890.055219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  890.055235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  890.055258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  890.055313] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  890.055337] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  890.071975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  890.072019] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  890.072057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.072183] Console: switching to colour frame buffer device 240x75
>[  890.376163] Console: switching to colour dummy device 80x25
>[  890.376257] [IGT] kms_flip: executing
>[  890.390528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  890.390557] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  890.392050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  890.392072] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  890.394048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  890.394054] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  890.396048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  890.396068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  890.398055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  890.398061] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  890.398065] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  890.398082] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  890.398105] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  890.399142] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  890.400036] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  890.400060] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  890.400083] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  890.400104] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  890.401097] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  890.401121] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  890.402187] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  890.402190] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  890.402268] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  890.402271] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  890.402275] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  890.402277] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  890.402280] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  890.402282] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  890.402289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  890.402292] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.402295] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.402297] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.402300] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  890.402302] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  890.402305] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  890.402307] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  890.402310] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.402312] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.402315] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  890.402317] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  890.402319] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  890.402322] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  890.402324] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  890.402326] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  890.402329] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  890.402331] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  890.402334] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  890.402336] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  890.402339] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  890.402341] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  890.402343] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  890.402346] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  890.402348] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  890.402351] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  890.402353] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  890.402356] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  890.402358] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  890.402360] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  890.402363] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  890.402392] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  890.402409] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  890.404047] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  890.404066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  890.406053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  890.406058] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  890.408048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  890.408069] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  890.410049] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  890.410054] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  890.410058] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  890.410277] [IGT] kms_flip: starting subtest 2x-single-buffer-flip-vs-dpms-off-vs-modeset
>[  890.412614] [IGT] kms_flip: exiting, ret=77
>[  890.439066] Console: switching to colour frame buffer device 240x75
>[  890.567184] Console: switching to colour dummy device 80x25
>[  890.567277] [IGT] kms_flip: executing
>[  890.578511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  890.578540] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  890.580052] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  890.580072] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  890.582050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  890.582055] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  890.584061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  890.584082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  890.586067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  890.586073] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  890.586077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  890.586092] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  890.586115] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  890.587149] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  890.588066] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  890.588083] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  890.588099] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  890.588116] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  890.589108] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  890.589126] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  890.590191] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  890.590194] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  890.590274] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  890.590276] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  890.590281] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  890.590283] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  890.590287] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  890.590289] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  890.590296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  890.590299] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.590301] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.590304] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.590306] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  890.590309] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  890.590311] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  890.590314] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  890.590316] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.590318] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  890.590321] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  890.590323] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  890.590326] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  890.590328] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  890.590331] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  890.590333] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  890.590335] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  890.590338] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  890.590340] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  890.590343] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  890.590345] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  890.590348] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  890.590350] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  890.590353] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  890.590355] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  890.590357] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  890.590360] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  890.590362] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  890.590365] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  890.590367] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  890.590369] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  890.590399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  890.590417] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  890.592066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  890.592085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  890.594065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  890.594073] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  890.596060] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  890.596078] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  890.598061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  890.598067] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  890.598071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  890.599349] [IGT] kms_flip: starting subtest flip-vs-expired-vblank-interruptible
>[  890.599848] [drm:drm_mode_addfb2] [FB:75]
>[  890.599871] [drm:drm_mode_addfb2] [FB:79]
>[  890.642573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  890.642626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  890.655809] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  890.655833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  890.655881] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  890.674694] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  890.674717] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  890.674733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  890.674753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  890.674770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  890.674788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  890.674804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  890.674818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  890.674835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  890.674853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  890.674869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  890.674885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  890.674901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.674915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  890.674929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  890.674957] [drm:intel_power_well_disable [i915]] disabling display
>[  890.674980] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  890.675006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  890.675069] [drm:intel_power_well_disable [i915]] disabling always-on
>[  890.675140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  890.675222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  890.675283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  890.675293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  890.675337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  890.675355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  890.675374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  890.675395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  890.675415] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  890.675436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  890.675456] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  890.675475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  890.675496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  890.675515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  890.675535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  890.675540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.675556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  890.675560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  890.675579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  890.675599] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  890.675619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  890.675639] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  890.675659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  890.675678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  890.675698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  890.675717] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  890.675737] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  890.675757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  890.675788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  890.678418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  890.678434] [drm:intel_power_well_enable [i915]] enabling display
>[  890.678449] [drm:hsw_set_power_well [i915]] Enabling power well
>[  890.678478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  890.678498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  890.678517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  890.678536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  890.678554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  890.678573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  890.678593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  890.678613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  890.678633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  890.678651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  890.678667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  890.678687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  890.678705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  890.680694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  890.680712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  890.680726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  890.680741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  890.682252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  890.682268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  890.682282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  890.683781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  890.683797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  890.685606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  890.688531] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  890.688564] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  890.688580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  890.688605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  890.688647] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  890.688667] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  890.705317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  890.705344] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  890.705381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.730998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.747656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  900.747682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  900.747723] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  900.766557] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  900.766580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  900.766596] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  900.766616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.766679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.766708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.766732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.766757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.766781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.766801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.766819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.766835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.766856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.766876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.766895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.766924] [drm:intel_power_well_disable [i915]] disabling display
>[  900.766948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.766973] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.766992] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.767174] [drm:drm_mode_addfb2] [FB:75]
>[  900.767204] [drm:drm_mode_addfb2] [FB:78]
>[  900.790261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  900.790340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  900.790395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  900.790449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  900.790458] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  900.790506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.790524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.790543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.790563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.790581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.790599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.790616] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  900.790669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  900.790695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.790719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.790741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.790749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.790770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.790777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.790799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.790822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.790845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.790867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  900.790889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.790910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.790933] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  900.790956] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  900.790977] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  900.791002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.791028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  900.793540] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.793555] [drm:intel_power_well_enable [i915]] enabling display
>[  900.793569] [drm:hsw_set_power_well [i915]] Enabling power well
>[  900.793596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.793612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.793662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.793684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.793704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.793725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.793750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.793773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.793796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.793815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.793835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.793860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  900.793881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  900.795873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  900.795891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  900.795908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.795926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  900.797430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  900.797446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  900.797460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.798954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  900.798970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  900.800770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  900.803713] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  900.803780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  900.803796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  900.803818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  900.820519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.820543] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  900.820577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.846211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.846275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  910.846300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.846342] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  910.865173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  910.865192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.865213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.865276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.865305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.865331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.865355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.865377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.865397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.865414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.865430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.865447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.865461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.865475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.865504] [drm:intel_power_well_disable [i915]] disabling display
>[  910.865526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.865548] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  910.865564] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.865749] [drm:drm_mode_addfb2] [FB:75]
>[  910.865773] [drm:drm_mode_addfb2] [FB:78]
>[  910.888822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.888906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  910.888964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  910.889018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  910.889027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.889076] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.889093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.889110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.889129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.889143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.889159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.889174] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  910.889189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  910.889203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.889216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.889264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.889271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.889291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.889297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.889317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.889337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.889356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.889376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  910.889399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.889418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.889438] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  910.889458] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  910.889478] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  910.889501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.889526] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  910.892046] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.892062] [drm:intel_power_well_enable [i915]] enabling display
>[  910.892075] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.892103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.892119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.892134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.892148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.892161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.892176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.892193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.892207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.892222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.892272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.892295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.892320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  910.892342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.894336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.894352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.894366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.894381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.895882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.895897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.895911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.897404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.897420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.899219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.902154] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  910.902189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.902206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  910.902267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.918921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.918945] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  910.918979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.944622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.944670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.944695] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.944736] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.963604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.963623] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.963644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.963660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.963678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.963693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.963713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.963732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.963754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.963775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.963796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.963816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.963879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.963904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.963948] [drm:intel_power_well_disable [i915]] disabling display
>[  920.963985] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.964021] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.964048] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.965328] [IGT] kms_flip: exiting, ret=0
>[  920.982299] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.982317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.982335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.982355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.982370] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.982386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.982402] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  920.982417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  920.982435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.982454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.982472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.982477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.982495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.982498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.982517] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.982536] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.982554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.982572] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  920.982591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.982609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.982628] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  920.982646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  920.982665] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  920.982684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.982705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  920.982770] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.982786] [drm:intel_power_well_enable [i915]] enabling display
>[  920.982800] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.982838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.982874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.982890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.982905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.982919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.982935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.982952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.982968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.982984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.982998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.983011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.983029] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  920.983044] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.985033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.985048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.985064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.985082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.986594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.986609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.986623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.988122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.988136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.989952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.992982] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  920.993011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.993027] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  920.993049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.993094] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  920.993110] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.009768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.009793] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.009829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.009973] Console: switching to colour frame buffer device 240x75
>[  921.318288] Console: switching to colour dummy device 80x25
>[  921.318382] [IGT] kms_flip: executing
>[  921.329348] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  921.329372] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  921.330919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  921.330939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  921.332908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  921.332914] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  921.334909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  921.334930] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  921.336910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  921.336916] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  921.336920] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  921.336936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  921.336959] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  921.337995] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  921.338907] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  921.338924] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  921.338939] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  921.338953] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  921.339942] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  921.339966] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  921.341038] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  921.341041] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  921.341123] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  921.341125] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  921.341129] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  921.341131] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  921.341135] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  921.341137] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  921.341144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  921.341147] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.341149] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.341152] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.341154] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  921.341157] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  921.341160] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  921.341162] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  921.341165] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.341167] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.341170] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  921.341172] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  921.341175] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  921.341177] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  921.341179] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  921.341182] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  921.341184] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  921.341187] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  921.341189] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  921.341192] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  921.341194] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  921.341197] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  921.341199] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  921.341201] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  921.341204] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  921.341206] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  921.341209] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  921.341211] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  921.341213] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  921.341216] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  921.341218] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  921.341249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  921.341266] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  921.342909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  921.342927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  921.344909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  921.344915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  921.346917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  921.346937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  921.348912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  921.348917] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  921.348921] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  921.349126] [IGT] kms_flip: starting subtest 2x-wf_vblank
>[  921.351425] [IGT] kms_flip: exiting, ret=77
>[  921.376863] Console: switching to colour frame buffer device 240x75
>[  921.508490] Console: switching to colour dummy device 80x25
>[  921.508583] [IGT] kms_flip: executing
>[  921.525375] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  921.525400] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  921.526926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  921.526947] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  921.528921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  921.528927] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  921.530921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  921.530942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  921.532922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  921.532928] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  921.532933] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  921.532948] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  921.532971] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  921.534006] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  921.534904] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  921.534924] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  921.534947] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  921.534970] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  921.535961] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  921.535981] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  921.537058] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  921.537061] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  921.537141] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  921.537143] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  921.537147] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  921.537149] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  921.537153] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  921.537155] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  921.537162] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  921.537165] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.537168] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.537170] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.537173] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  921.537175] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  921.537178] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  921.537180] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  921.537182] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.537185] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  921.537187] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  921.537190] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  921.537192] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  921.537195] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  921.537197] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  921.537200] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  921.537202] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  921.537205] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  921.537207] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  921.537210] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  921.537212] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  921.537215] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  921.537217] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  921.537219] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  921.537222] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  921.537224] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  921.537227] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  921.537229] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  921.537231] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  921.537234] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  921.537236] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  921.537265] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  921.537283] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  921.538919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  921.538936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  921.540924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  921.540929] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  921.542923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  921.542943] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  921.544922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  921.544927] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  921.544931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  921.546162] [IGT] kms_flip: starting subtest flip-vs-dpms-off-vs-modeset-interruptible
>[  921.546560] [drm:drm_mode_addfb2] [FB:75]
>[  921.546581] [drm:drm_mode_addfb2] [FB:79]
>[  921.589131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.589186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.593607] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.593632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.593680] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  921.612555] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  921.612579] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  921.612595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.612615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.612632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.612650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.612666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.612681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.612697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.612715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.612732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.612748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.612764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.612778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.612792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.612820] [drm:intel_power_well_disable [i915]] disabling display
>[  921.612842] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.612864] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.612927] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.613008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  921.613080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.613140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.613151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.613193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.613211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.613230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.613256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.613282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.613301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.613318] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.613335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.613350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.613365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.613390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.613394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.613407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.613410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.613424] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.613436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.613450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.613462] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.613478] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.613491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.613505] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  921.613517] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.613531] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.613546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.613563] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.616100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.616117] [drm:intel_power_well_enable [i915]] enabling display
>[  921.616131] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.616160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.616177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.616193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.616208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.616223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.616238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.616255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.616271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.616287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.616301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.616315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.616333] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  921.616348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.618346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.618364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.618381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.618400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.619934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.619951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.619965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.621463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.621479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.623298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.626234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  921.626307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.626324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  921.626347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.626386] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  921.626405] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.643051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.643078] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.643115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.659804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.659823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.659842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.659861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.659922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.659947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.659975] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.659999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.660024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.660046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.660069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.660076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.660099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.660104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.660127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.660148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.660170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.660191] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.660215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.660236] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.660260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  921.660280] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.660303] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.660328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.660355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.676407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.676430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.676465] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  921.695314] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  921.695337] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  921.695357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.695379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.695399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.695419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.695438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.695457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.695476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.695497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.695517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.695537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.695556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.695575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.695602] [drm:intel_power_well_disable [i915]] disabling display
>[  921.695624] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.695644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.695665] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.695687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.695702] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.695747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.695757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.695804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.695823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.695843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.695865] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.695924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.695951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.695976] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.695999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.696022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.696044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.696066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.696073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.696093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.696100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.696121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.696143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.696164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.696185] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.696209] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.696230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.696260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  921.696279] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.696298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.696321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.696346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.696411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.696435] [drm:intel_power_well_enable [i915]] enabling display
>[  921.696449] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.696474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.696489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.696503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.696517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.696530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.696545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.696561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.696575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.696590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.696603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.696616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.696632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  921.696647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.698616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.698632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.698646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.698661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.700164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.700179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.700193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.701683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.701699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.703503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.706168] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  921.706208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.706224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  921.706246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.706294] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  921.706320] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.722961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.722991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.723027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.723132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.723188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.756342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.756368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.756414] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  921.774545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  921.774567] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  921.774583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.774603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.774619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.774637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.774653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.774668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.774684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.774702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.774718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.774734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.774750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.774764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.774778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.774805] [drm:intel_power_well_disable [i915]] disabling display
>[  921.774826] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.774847] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.774864] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.775069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.775083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.775147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.775170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.775193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.775219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.775240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.775263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.775284] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.775306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.775327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.775347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.775366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.775372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.775391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.775396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.775417] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.775436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.775456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.775475] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.775498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.775517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.775537] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  921.775556] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.775576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.775597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.775621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.775673] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.775696] [drm:intel_power_well_enable [i915]] enabling display
>[  921.775717] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.775753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.775774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.775795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.775815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.775835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.775855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.775879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.775919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.775943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.775963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.775985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.776011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  921.776032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.778027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.778044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.778058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.778072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.779579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.779594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.779608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.781108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.781124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.782934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.785868] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  921.785944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.785961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  921.785983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.786022] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  921.786038] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.802688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.802713] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.802747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.802855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.802945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.836044] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.836068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.836103] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  921.854960] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  921.854983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  921.854999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.855018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.855035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.855052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.855068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.855082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.855098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.855116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.855133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.855149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.855165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.855179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.855193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.855220] [drm:intel_power_well_disable [i915]] disabling display
>[  921.855241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.855262] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.855279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.855396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.855405] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.855452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.855472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.855492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.855514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.855533] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.855552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.855571] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.855591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.855610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.855629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.855648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.855652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.855670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.855674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.855701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.855718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.855733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.855747] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.855763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.855778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.855792] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  921.855805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.855818] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.855833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.855850] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.855930] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.855951] [drm:intel_power_well_enable [i915]] enabling display
>[  921.855971] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.856007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.856029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.856051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.856071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.856091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.856112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.856135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.856158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.856180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.856200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.856219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.856243] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  921.856264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.858258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.858274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.858288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.858303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.859829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.859845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.859858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.861355] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.861371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.863179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.866114] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  921.866189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.866208] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  921.866234] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.866274] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  921.866293] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.882932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.882958] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.882994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.883108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.883151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.916288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.916314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.916351] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  921.935205] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  921.935227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  921.935243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.935263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.935279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.935296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.935311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.935326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.935342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.935360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.935376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.935392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.935408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.935422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.935436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.935462] [drm:intel_power_well_disable [i915]] disabling display
>[  921.935483] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.935504] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.935521] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.935612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.935621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.935664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.935680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.935698] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.935718] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.935733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.935749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.935766] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  921.935784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  921.935804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.935823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.935842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.935847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.935873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.935916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.935935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.935951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.935968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.935982] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  921.936001] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.936019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.936040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  921.936061] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  921.936082] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  921.936105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.936128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  921.936176] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.936193] [drm:intel_power_well_enable [i915]] enabling display
>[  921.936209] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.936239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.936267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.936292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.936317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.936342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.936366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.936385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.936402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.936425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.936439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.936452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.936468] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  921.936483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.938463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.938479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.938493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.938508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.940023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.940039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.940053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.941548] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.941564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.943387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.946336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  921.946396] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.946413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  921.946434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.946472] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  921.946489] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  921.963138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.963163] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  921.963197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.963302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  921.963345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.996497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  921.996532] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.996566] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  922.015390] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  922.015412] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  922.015428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.015448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.015464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.015482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.015497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.015512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.015527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.015545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.015561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.015577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.015592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.015606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.015620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.015646] [drm:intel_power_well_disable [i915]] disabling display
>[  922.015668] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.015689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  922.015706] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.015813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.015822] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.015867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.015883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.015945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.015973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.015996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.016021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.016045] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  922.016069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  922.016091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.016114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.016135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.016142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.016162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.016169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.016190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.016219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.016240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.016260] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  922.016282] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.016302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.016322] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  922.016343] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  922.016364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  922.016388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.016412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  922.016477] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.016500] [drm:intel_power_well_enable [i915]] enabling display
>[  922.016522] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.016560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.016576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.016590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.016605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.016622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.016641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.016660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.016680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.016699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.016717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.016732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.016752] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  922.016770] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.018750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.018766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.018780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.018795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.020304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.020319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.020332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.021843] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.021858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.023670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.026617] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  922.026679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.026696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  922.026718] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.026757] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  922.026773] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  922.043423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.043448] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  922.043483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.043591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.043631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.076811] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  922.076835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.076871] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  922.095748] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  922.095769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  922.095786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.095805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.095822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.095839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.095855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.095870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.095886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.095949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.095976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.096125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.096147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.096166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.096186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.096214] [drm:intel_power_well_disable [i915]] disabling display
>[  922.096237] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.096263] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  922.096281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.096403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.096413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.096460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.096479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.096499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.096521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.096540] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.096560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.096579] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  922.096598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  922.096617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.096636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.096655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.096659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.096677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.096681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.096701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.096720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.096739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.096758] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  922.096777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.096796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.096815] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  922.096834] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  922.096853] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  922.096873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.096893] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  922.096990] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.097011] [drm:intel_power_well_enable [i915]] enabling display
>[  922.097031] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.097071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.097267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.097283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.097297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.097311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.097328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.097347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.097367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.097386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.097404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.097421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.097440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  922.097458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.099458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.099475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.099492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.099510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.101036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.101054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.101072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.102570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.102587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.104409] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.107346] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  922.107419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.107436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  922.107458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.107506] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  922.107532] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  922.124163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.124188] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  922.124223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.124324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.124364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.157519] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  922.157545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.157592] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  922.175252] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  922.175274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  922.175290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.175309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.175326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.175344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.175363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.175382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.175401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.175423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.175444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.175464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.175484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.175503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.175519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.175546] [drm:intel_power_well_disable [i915]] disabling display
>[  922.175568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.175593] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  922.175612] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.175776] [drm:drm_mode_addfb2] [FB:75]
>[  922.175798] [drm:drm_mode_addfb2] [FB:78]
>[  922.198771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.198853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.198947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.199043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.199058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.199128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.199146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.199163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.199182] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.199196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.199212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.199228] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.199242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.199257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.199270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.199283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.199287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.199299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.199302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.199316] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.199333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.199351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.199368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.199386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.199403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.199421] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.199439] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.199456] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.199475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.199495] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.202106] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.202121] [drm:intel_power_well_enable [i915]] enabling display
>[  922.202134] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.202163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.202180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.202194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.202208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.202222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.202237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.202253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.202267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.202282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.202295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.202307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.202324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.202339] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.204333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.204350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.204365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.204380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.205890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.205915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.205932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.207435] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.207453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.209279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.212222] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.212288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.212303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.212323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.229032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.229058] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.229093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.245782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.245802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.245821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.245840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.245856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.245873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.245890] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.245906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.245965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.245989] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.246013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.246021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.246044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.246051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.246075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.246097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.246121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.246142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.246168] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.246192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.246214] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  922.246236] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.246257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.246282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.246306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.246389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.246428] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.246478] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.263292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.263318] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.263344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.263361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.263377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.263392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.263407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.263423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.263440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.263456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.263471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.263486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.263500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.263527] [drm:intel_power_well_disable [i915]] disabling display
>[  922.263548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.263564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.263580] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.263597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.263611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.263662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.263671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.263715] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.263731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.263748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.263768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.263783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.263800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.263818] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.263838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.263857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.263876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.263895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.263937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.263967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.263974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.264001] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.264026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.264052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.264076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.264104] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.264128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.264155] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  922.264179] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.264203] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.264231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.264259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.264331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.264355] [drm:intel_power_well_enable [i915]] enabling display
>[  922.264379] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.264427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.264450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.264472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.264494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.264516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.264538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.264563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.264587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.264610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.264632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.264653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.264677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.264700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.266692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.266709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.266725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.266743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.268252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.268268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.268283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.269775] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.269792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.271598] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.274519] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.274555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.274572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.274594] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.291297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.291326] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.291360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.291470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.291509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.307980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.308003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.308038] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.326892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.326911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.326979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.327008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.327038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.327062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.327087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.327112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.327141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.327168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.327193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.327219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.327243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.327266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.327309] [drm:intel_power_well_disable [i915]] disabling display
>[  922.327343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.327375] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.327401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.327528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.327537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.327582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.327599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.327617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.327636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.327651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.327668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.327685] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.327700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.327715] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.327730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.327744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.327748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.327768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.327771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.327784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.327796] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.327809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.327821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.327836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.327849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.327862] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.327874] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.327886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.327902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.327949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.328015] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.328038] [drm:intel_power_well_enable [i915]] enabling display
>[  922.328061] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.328099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.328122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.328146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.328168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.328190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.328211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.328235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.328259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.328283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.328305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.328326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.328351] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.328375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.330384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.330400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.330415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.330429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.331937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.331953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.331967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.333562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.333578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.335407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.338353] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.338417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.338434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.338456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.355134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.355157] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.355190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.355289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.355327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.371846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.371871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.371905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.390800] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.390819] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.390839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.390856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.390874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.390889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.390903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.390960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.390988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.391017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.391044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.391197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.391221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.391245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.391283] [drm:intel_power_well_disable [i915]] disabling display
>[  922.391317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.391350] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.391375] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.391505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.391514] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.391558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.391575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.391593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.391612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.391628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.391645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.391662] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.391678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.391693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.391707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.391721] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.391725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.391739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.391742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.391757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.391770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.391784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.391798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.391814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.391828] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.391842] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.391855] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.391869] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.391885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.391903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.391994] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.392019] [drm:intel_power_well_enable [i915]] enabling display
>[  922.392044] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.392093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.392117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.392140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.392162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.392384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.392408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.392433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.392457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.392481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.392502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.392523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.392548] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.392571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.394574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.394591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.394606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.394621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.396133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.396149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.396162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.397659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.397675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.399484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.402421] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.402493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.402510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.402533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.419236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.419261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.419296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.419404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.419445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.435949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.435972] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.436007] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.454884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.454902] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.454922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.454983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.455014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.455116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.455133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.455150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.455168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.455185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.455201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.455217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.455231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.455245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.455270] [drm:intel_power_well_disable [i915]] disabling display
>[  922.455292] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.455313] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.455337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.455438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.455446] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.455487] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.455501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.455517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.455535] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.455549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.455564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.455579] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.455593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.455606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.455620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.455632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.455636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.455649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.455652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.455665] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.455678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.455690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.455702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.455717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.455730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.455747] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.455764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.455782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.455800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.455819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.455862] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.455876] [drm:intel_power_well_enable [i915]] enabling display
>[  922.455889] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.455917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.455964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.455989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.456013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.456037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.456062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.456087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.456112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.456137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.456159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.456182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.456208] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.456231] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.458231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.458249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.458266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.458284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.459791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.459808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.459826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.461324] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.461342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.463151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.466101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.466160] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.466177] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.466199] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.482901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.482969] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.483023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.483152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.483198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.499600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.499624] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.499661] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.518535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.518555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.518578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.518597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.518619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.518638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.518658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.518677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.518699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.518719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.518740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.518760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.518779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.518795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.518822] [drm:intel_power_well_disable [i915]] disabling display
>[  922.518844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.518869] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.518886] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.519175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.519190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.519264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.519291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.519319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.519349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.519373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.519400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.519426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.519451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.519476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.519500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.519524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.519530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.519552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.519559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.519583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.519606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.519629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.519652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.519678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.519701] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.519725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.519747] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.519768] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.519801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.519826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.519887] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.519909] [drm:intel_power_well_enable [i915]] enabling display
>[  922.519953] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.519993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.520016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.520040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.520062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.520085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.520108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.520134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.520159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.520183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.520205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.520227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.520253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.520277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.522495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.522511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.522525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.522540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.524050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.524066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.524080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.525574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.525589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.527397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.529772] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.529851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.529870] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.529896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.546600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.546626] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.546661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.546770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.546811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.563281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.563303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.563337] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.582188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.582206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.582226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.582243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.582264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.582284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.582304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.582323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.582345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.582365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.582385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.582405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.582424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.582443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.582470] [drm:intel_power_well_disable [i915]] disabling display
>[  922.582492] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.582516] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.582533] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.582646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.582655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.582702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.582722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.582742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.582764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.582782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.582802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.582821] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.582840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.582859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.582878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.582897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.582901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.582919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.582960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.582989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.583015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.583041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.583063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.583090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.583112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.583137] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.583159] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.583182] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.583210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.583238] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.583312] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.583334] [drm:intel_power_well_enable [i915]] enabling display
>[  922.583363] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.583401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.583424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.583444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.583465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.583484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.583505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.583529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.583552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.583575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.583595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.583615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.583637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.583659] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.585660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.585677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.585693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.585711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.587229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.587247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.587262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.588757] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.588773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.590582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.593505] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.593540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.593556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.593578] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.610283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.610309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.610345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.610457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.610499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.626964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.626988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.627032] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.645890] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.645909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.645930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.645988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.646017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.646039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.646063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.646086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.646114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.646140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.646165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.646191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.646212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.646234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.646277] [drm:intel_power_well_disable [i915]] disabling display
>[  922.646309] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.646341] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.646366] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.646517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.646525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.646569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.646586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.646604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.646623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.646638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.646655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.646672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.646695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.646709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.646722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.646735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.646739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.646751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.646754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.646767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.646780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.646793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.646805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.646820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.646833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.646845] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.646858] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.646870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.646885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.646901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.646973] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.646996] [drm:intel_power_well_enable [i915]] enabling display
>[  922.647017] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.647057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.647078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.647100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.647121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.647142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.647164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.647188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.647212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.647236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.647256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.647277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.647303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.647324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.649319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.649335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.649348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.649363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.650876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.650892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.650906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.652402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.652418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.654226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.657166] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.657236] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.657252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.657274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.673978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.674004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.674038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.674139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.674180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.690672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.690696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.690732] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.708707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.708725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.708745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.708762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.708780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.708795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.708810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.708826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.708844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.708860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.708876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.708891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.708906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.708924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.708998] [drm:intel_power_well_disable [i915]] disabling display
>[  922.709034] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.709069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.709095] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.709248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.709262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.709333] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.709358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.709384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.709412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.709435] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.709460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.709483] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  922.709507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  922.709529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.709551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.709572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.709578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.709599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.709605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.709628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.709649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.709671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.709691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.709715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.709736] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.709758] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  922.709778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  922.709800] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  922.709826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.709852] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  922.709921] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.709974] [drm:intel_power_well_enable [i915]] enabling display
>[  922.709999] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.710037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.710061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.710082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.710105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.710125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.710148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.710173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.710197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.710222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.710242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.710264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.710291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  922.710312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.712310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.712327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.712341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.712356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.713875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.713891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.713905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.715401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.715417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.717224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.719595] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  922.719626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.719645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  922.719671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.736377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.736403] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.736438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.736538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.736578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.753065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  922.753089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.753126] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  922.771994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  922.772013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.772033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.772050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.772067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.772082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.772096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.772112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.772130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.772146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.772161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.772176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.772195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.772212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.772240] [drm:intel_power_well_disable [i915]] disabling display
>[  922.772262] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.772287] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  922.772303] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.772470] [drm:drm_mode_addfb2] [FB:75]
>[  922.772494] [drm:drm_mode_addfb2] [FB:78]
>[  922.795918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  922.796066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  922.796140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.796196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.796205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.796254] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.796272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.796291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.796312] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.796329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.796347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.796365] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.796382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.796400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.796417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.796434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.796438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.796455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.796458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.796476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.796493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.796510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.796527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.796545] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.796562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.796580] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.796597] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.796615] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.796633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.796653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.799262] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.799279] [drm:intel_power_well_enable [i915]] enabling display
>[  922.799295] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.799326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.799345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.799364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.799383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.799402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.799420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.799441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.799461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.799481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.799499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.799525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.799547] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.799567] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.801565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.801582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.801596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.801611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.803132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.803150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.803167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.804661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.804678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.806493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.809441] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.809503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.809519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.809545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.826246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.826273] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.826308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.843012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.843033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.843052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.843074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.843090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.843108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.843126] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.843143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.843160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.843176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.843191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.843195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.843210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.843214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.843229] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.843244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.843259] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.843273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.843291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.843306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.843322] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  922.843337] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.843352] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.843369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.843388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.843442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.843463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.843498] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.861417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.861436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.861456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.861473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.861488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.861504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.861518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.861534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.861551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.861567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.861583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.861597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.861610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.861636] [drm:intel_power_well_disable [i915]] disabling display
>[  922.861657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.861673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.861693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.861714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.861729] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.861774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.861783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.861831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.861851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.861871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.861899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.861914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.861931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.861982] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.862006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.862030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.862050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.862072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.862078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.862100] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.862106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.862128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.862149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.862170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.862190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.862213] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.862233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.862256] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  922.862276] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.862297] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.862322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.862347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.862413] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.862435] [drm:intel_power_well_enable [i915]] enabling display
>[  922.862456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.862493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.862514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.862536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.862555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.862576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.862597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.862620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.862643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.862666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.862685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.862705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.862727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.862749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.864742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.864759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.864774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.864788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.866294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.866309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.866323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.867814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.867829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.869636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.872562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.872592] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.872608] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.872630] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.889337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.889368] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.889404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.889526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.889577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.906037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.906061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.906107] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.923991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.924010] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.924031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.924048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.924069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.924088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.924108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.924127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.924149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.924170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.924190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.924211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.924230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.924246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.924273] [drm:intel_power_well_disable [i915]] disabling display
>[  922.924296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.924328] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.924344] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.924449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.924458] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.924503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.924520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.924538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.924557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.924572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.924588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.924604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.924620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.924635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.924653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.924672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.924676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.924694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.924697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.924716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.924735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.924753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.924772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.924790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.924809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.924827] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.924846] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.924864] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.924883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.924903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.924977] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.925000] [drm:intel_power_well_enable [i915]] enabling display
>[  922.925021] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.925062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.925086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.925108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.925130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.925152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.925174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.925199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.925223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.925246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.925267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.925288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.925313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.925336] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.927330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.927348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.927365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.927383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.928899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.928915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.928929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.930457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.930473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.932311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.935258] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.935321] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.935341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.935367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.952054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.952079] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.952113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.952220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.952259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.968760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.968786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.968833] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.987691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.987709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.987730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.987747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.987765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.987780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.987799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.987818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.987840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.987861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.987881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.987901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.987920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.987936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.988013] [drm:intel_power_well_disable [i915]] disabling display
>[  922.988048] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.988083] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.988110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.988303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.988318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.988391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.988418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.988445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.988475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.988501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.988527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.988554] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.988586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.988609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.988631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.988652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.988657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.988678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.988684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.988706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.988727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.988748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.988769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.988793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.988812] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.988834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.988854] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.988873] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.988897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.988922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.988998] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.989022] [drm:intel_power_well_enable [i915]] enabling display
>[  922.989045] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.989083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.989107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.989130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.989153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.989175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.989198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.989223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.989247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.989271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.989292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.989314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.989340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.989363] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.991371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.991390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.991408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.991426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.992937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.992967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.992981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.994489] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.994506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.996338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.999291] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.999348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.999365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.999387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.016088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.016115] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.016150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.016251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.016291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.032789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.032812] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.032858] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.051727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.051746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.051766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.051783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.051800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.051816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.051830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.051847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.051868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.051888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.051909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.051929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.051948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.052011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.052055] [drm:intel_power_well_disable [i915]] disabling display
>[  923.052090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.052123] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.052149] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.052294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.052309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.052379] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.052405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.052433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.052462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.052487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.052512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.052538] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.052563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.052588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.052612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.052635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.052642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.052664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.052670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.052693] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.052717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.052739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.052760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.052785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.052808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.052838] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.052857] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.052877] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.052901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.052926] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.053013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.053036] [drm:intel_power_well_enable [i915]] enabling display
>[  923.053058] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.053097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.053121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.053145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.053168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.053190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.053213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.053238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.053262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.053286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.053308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.053329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.053355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.053379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.055383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.055401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.055424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.055443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.056952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.056981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.056995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.058501] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.058519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.060340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.063279] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.063349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.063365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.063387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.080092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.080117] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.080152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.080258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.080299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.096791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.096815] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.096861] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.115732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.115752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.115775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.115794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.115816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.115835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.115855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.115874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.115895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.115916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.115936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.115957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.116021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.116050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.116093] [drm:intel_power_well_disable [i915]] disabling display
>[  923.116134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.116166] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.116191] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.116366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.116380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.116448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.116472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.116498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.116526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.116549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.116574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.116599] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.116623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.116646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.116668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.116690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.116696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.116718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.116723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.116745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.116767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.116789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.116808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.116832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.116853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.116873] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.116894] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.116914] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.116938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.116963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.117057] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.117080] [drm:intel_power_well_enable [i915]] enabling display
>[  923.117104] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.117142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.117173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.117196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.117218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.117240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.117263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.117287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.117311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.117335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.117356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.117378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.117402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.117425] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.119436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.119452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.119466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.119480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.121023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.121042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.121059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.122562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.122579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.124391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.127317] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.127348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.127365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.127393] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.144091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.144117] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.144153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.144260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.144302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.160772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.160797] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.160834] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.179085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.179103] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.179123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.179140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.179158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.179174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.179189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.179205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.179226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.179247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.179267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.179288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.179306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.179323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.179350] [drm:intel_power_well_disable [i915]] disabling display
>[  923.179373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.179397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.179414] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.179527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.179537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.179583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.179603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.179623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.179645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.179664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.179683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.179703] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.179722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.179741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.179760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.179779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.179783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.179802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.179805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.179825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.179844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.179863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.179882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.179901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.179919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.179938] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.179958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.180010] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.180038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.180066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.180135] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.180156] [drm:intel_power_well_enable [i915]] enabling display
>[  923.180178] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.180221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.180464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.180480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.180495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.180509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.180524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.180541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.180556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.180571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.180588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.180605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.180625] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.180643] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.182626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.182643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.182657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.182671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.184180] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.184195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.184209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.185703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.185719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.187529] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.190468] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.190539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.190558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.190584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.207281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.207307] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.207342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.207444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.207484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.223998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.224023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.224068] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.242938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.242957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.243024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.243051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.243080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.243105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.243129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.243154] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.243183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.243209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.243235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.243260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.243283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.243306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.243349] [drm:intel_power_well_disable [i915]] disabling display
>[  923.243383] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.243416] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.243441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.243555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.243564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.243608] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.243626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.243644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.243663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.243679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.243696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.243712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.243728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.243743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.243757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.243771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.243775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.243788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.243792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.243806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.243820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.243841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.243853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.243868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.243880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.243893] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.243905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.243917] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.243932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.243951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.244036] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.244059] [drm:intel_power_well_enable [i915]] enabling display
>[  923.244082] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.244121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.244145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.244169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.244192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.244214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.244238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.244264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.244288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.244312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.244333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.244352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.244377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.244401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.246405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.246424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.246442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.246460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.247972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.248003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.248020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.249519] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.249537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.251402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.254349] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.254412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.254429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.254451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.271155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.271181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.271216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.271324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.271365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.287853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.287878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.287924] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.306747] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.306766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.306786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.306803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.306820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.306835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.306854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.306873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.306895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.306916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.306936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.306956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.307014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.307041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.307085] [drm:intel_power_well_disable [i915]] disabling display
>[  923.307118] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.307159] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.307182] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.307358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.307372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.307437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.307454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.307471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.307490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.307505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.307520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.307538] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.307556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.307575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.307593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.307610] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.307614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.307631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.307635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.307653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.307671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.307689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.307707] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.307725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.307743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.307761] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.307779] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.307796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.307815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.307835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.307879] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.307893] [drm:intel_power_well_enable [i915]] enabling display
>[  923.307907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.307936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.307954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.307972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.308018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.308045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.308068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.308095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.308121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.308147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.308168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.308192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.308218] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.308241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.310244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.310260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.310274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.310288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.311795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.311810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.311824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.313323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.313338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.315161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.317642] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.317717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.317736] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.317762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.334455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.334480] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.334514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.334640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.334687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.351149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.351174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.351209] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.370062] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.370081] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.370101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.370117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.370135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.370150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.370165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.370181] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.370199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.370215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.370231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.370251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.370270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.370287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.370315] [drm:intel_power_well_disable [i915]] disabling display
>[  923.370337] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.370362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.370378] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.371738] [IGT] kms_flip: exiting, ret=0
>[  923.392445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.392465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.392485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.392506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.392522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.392539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.392557] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  923.392574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  923.392590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.392605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.392620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.392624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.392639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.392642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.392657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.392671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.392686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.392700] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  923.392719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.392739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.392759] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  923.392778] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  923.392798] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  923.392819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.392841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  923.392913] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.392929] [drm:intel_power_well_enable [i915]] enabling display
>[  923.392943] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.392973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.393003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.393019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.393034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.393052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.393071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.393092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.393112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.393132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.393150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.393169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.393189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  923.393207] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.395199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.395215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.395228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.395242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.396754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.396767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.396780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.398277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.398292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.400109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.403136] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  923.403167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.403182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  923.403204] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.403246] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  923.403260] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  923.419917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.419941] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  923.419978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.420121] Console: switching to colour frame buffer device 240x75
>[  923.549107] Console: switching to colour dummy device 80x25
>[  923.549200] [IGT] kms_flip: executing
>[  923.563487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  923.563517] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  923.565423] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  923.565443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  923.567520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  923.567527] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  923.569305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  923.569326] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  923.571400] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  923.571407] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  923.571411] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  923.571429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  923.571453] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  923.572481] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  923.573367] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  923.573384] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  923.573399] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  923.573412] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  923.574396] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  923.574411] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  923.575459] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  923.575462] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  923.575542] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  923.575544] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  923.575548] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  923.575550] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  923.575554] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  923.575555] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  923.575563] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  923.575566] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.575568] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  923.575571] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  923.575573] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  923.575575] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  923.575578] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  923.575580] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  923.575583] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  923.575585] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  923.575588] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  923.575590] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  923.575593] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  923.575595] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  923.575597] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  923.575600] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  923.575602] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  923.575605] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  923.575607] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  923.575610] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  923.575612] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  923.575614] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  923.575617] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  923.575619] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  923.575622] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  923.575624] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  923.575627] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  923.575629] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  923.575632] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  923.575634] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  923.575636] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  923.575666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  923.575684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  923.577046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  923.577066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  923.579044] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  923.579049] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  923.581042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  923.581063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  923.583042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  923.583047] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  923.583051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  923.584317] [IGT] kms_flip: starting subtest vblank-vs-dpms-suspend-interruptible
>[  923.584707] [drm:drm_mode_addfb2] [FB:77]
>[  923.584728] [drm:drm_mode_addfb2] [FB:79]
>[  923.627119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  923.627172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.636788] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  923.636814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.636863] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  923.655716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  923.655740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  923.655756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.655776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.655793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.655810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.655826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.655841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.655857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.655875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.655891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.655907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.655923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.655937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.655950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.655978] [drm:intel_power_well_disable [i915]] disabling display
>[  923.656047] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.656081] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  923.656108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.656188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  923.656300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.656367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  923.656378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.656420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.656438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.656458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.656480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.656507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.656525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.656541] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  923.656557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  923.656571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.656586] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.656599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.656603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.656616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.656619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.656633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.656646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.656658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.656671] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  923.656686] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.656700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.656713] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  923.656726] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  923.656738] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  923.656754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.656770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  923.659377] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.659395] [drm:intel_power_well_enable [i915]] enabling display
>[  923.659410] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.659440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.659459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.659478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.659497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.659515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.659533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.659554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.659573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.659593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.659611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.659627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.659647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  923.659666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.661653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.661671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.661686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.661703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.663214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.663231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.663246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.664743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.664759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.666568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.668925] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  923.668969] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.668986] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  923.669045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.669253] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  923.669271] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  923.685724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.685749] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  923.685786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.719186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.719206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.719226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.719247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.719263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.719282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.719303] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  923.719324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  923.719344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.719365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.719385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.719389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.719409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.719413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.719433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.719454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.719474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.719495] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  923.719515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.719535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.719556] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  923.719577] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  923.719597] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  923.719618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.719640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  923.735780] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  923.735806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.735872] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  923.754735] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  923.754757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  923.754773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.754793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.754810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.754825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.754841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.754855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.754871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.754892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.754912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.754933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.754952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.754968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.754995] [drm:intel_power_well_disable [i915]] disabling display
>[  923.755066] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.755095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.755122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  923.755154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.755170] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.824706] PM: Syncing filesystems ... done.
>[  923.850980] PM: Preparing system for sleep (mem)
>[  923.851380] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  923.852797] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  923.854064] PM: Suspending system (mem)
>[  923.854145] Suspending console(s) (use no_console_suspend to debug)
>[  923.855461] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  923.856865] e1000e: EEE TX LPI TIMER: 00000011
>[  923.857414] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.857441] [drm:intel_power_well_enable [i915]] enabling display
>[  923.857468] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.860307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.860382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.860399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.860421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.860437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.860451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.860467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.860485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.860502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.860518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.860533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.860547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.860561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.860585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  923.865039] sd 3:0:0:0: [sda] Stopping disk
>[  923.925128] PM: suspend of devices complete after 70.260 msecs
>[  923.926549] [drm:intel_power_well_disable [i915]] disabling display
>[  923.926598] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.926611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.926631] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  923.938069] PM: late suspend of devices complete after 12.925 msecs
>[  923.939523] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  923.939891] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  923.939977] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  923.951101] PM: noirq suspend of devices complete after 13.027 msecs
>[  923.951360] ACPI: Preparing to enter system sleep state S3
>[  923.973704] PM: Saving platform NVS memory
>[  923.973846] Disabling non-boot CPUs ...
>[  923.985406] smpboot: CPU 1 is now offline
>[  923.996292] Broke affinity for irq 42
>[  923.996300] Broke affinity for irq 44
>[  923.997342] smpboot: CPU 2 is now offline
>[  924.014179] Broke affinity for irq 8
>[  924.014183] Broke affinity for irq 9
>[  924.014187] Broke affinity for irq 23
>[  924.014190] Broke affinity for irq 42
>[  924.014193] Broke affinity for irq 43
>[  924.014196] Broke affinity for irq 44
>[  924.015234] smpboot: CPU 3 is now offline
>[  924.017339] ACPI: Low-level resume complete
>[  924.017462] PM: Restoring platform NVS memory
>[  924.017953] Suspended for 15.770 seconds
>[  924.018106] Enabling non-boot CPUs ...
>[  924.018215] x86: Booting SMP configuration:
>[  924.018220] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  924.019871]  cache: parent cpu1 should not be sleeping
>[  924.021054] CPU1 is up
>[  924.021145] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  924.022321]  cache: parent cpu2 should not be sleeping
>[  924.023014] CPU2 is up
>[  924.023070] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  924.024151]  cache: parent cpu3 should not be sleeping
>[  924.025256] CPU3 is up
>[  924.031330] ACPI: Waking up from system sleep state S3
>[  924.041269] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  924.053311] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  924.053396] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  924.053400] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  924.053572] PM: noirq resume of devices complete after 12.557 msecs
>[  924.057768] hpet1: lost 6068 rtc interrupts
>[  924.058526] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  924.058636] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.058658] [drm:intel_power_well_enable [i915]] enabling display
>[  924.060453] PM: early resume of devices complete after 2.566 msecs
>[  924.060772] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  924.060816] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  924.060847] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  924.060883] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  924.063795] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  924.066026] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  924.066046] [drm:intel_opregion_setup [i915]] ASLE supported
>[  924.066065] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  924.066082] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  924.066306] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  924.066327] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  924.066352] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  924.066374] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  924.066397] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  924.066419] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  924.066438] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  924.066794] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  924.066867] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  924.066884] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  924.066908] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  924.066927] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  924.066951] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  924.066969] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  924.066997] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  924.067027] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  924.067045] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  924.067060] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  924.067073] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  924.067085] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  924.067102] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  924.067117] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  924.067132] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  924.067147] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  924.067161] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  924.067188] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  924.067207] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  924.067227] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  924.067250] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  924.067266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  924.067281] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  924.067296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.067301] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067316] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.067319] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067335] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  924.067350] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  924.067363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.067378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.067395] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.067409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.067424] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  924.067441] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  924.067459] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  924.067475] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  924.067489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  924.067504] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  924.067518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.067521] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.067538] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067555] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  924.067570] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  924.067583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.067595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.067613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.067628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.067644] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  924.067656] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  924.067670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  924.067687] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  924.067699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  924.067714] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  924.067729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.067731] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.067749] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  924.067761] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  924.067773] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  924.067786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.067800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.067817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.067832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.067844] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.067859] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.067874] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.067891] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  924.067906] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  924.067919] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  924.067972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.067988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.068016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.068047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.068064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.068081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.068097] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  924.068112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  924.068128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.068146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.068158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.068161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.068173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.068176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.068191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.068206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.068219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.068231] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  924.068245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.068257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.068270] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  924.068281] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  924.068293] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  924.068308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.068325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  924.068423] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  924.070504] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  924.070522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.070539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.070555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.070571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.070586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.070602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  924.070620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  924.070638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.070654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.070670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.070689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.070708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.070727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.070758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.070781] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  924.070805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.070825] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  924.070849] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.070958] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  924.071166] sd 3:0:0:0: [sda] Starting disk
>[  924.071318] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  924.073059] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  924.073083] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  924.075145] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  924.075150] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  924.077227] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  924.077248] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  924.079322] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  924.079327] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  924.079332] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  924.079353] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  924.080435] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  924.081324] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  924.081340] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  924.081354] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  924.081367] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  924.082354] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  924.082371] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  924.083363] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  924.083382] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  924.085449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  924.085465] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  924.087539] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  924.087545] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  924.089621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  924.089642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  924.091715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  924.091720] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  924.091724] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  924.379680] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  924.420617] ata4.00: configured for UDMA/133
>[  924.432611] ahci 0000:00:1f.2: port does not support device sleep
>[  924.587524] PM: resume of devices complete after 527.035 msecs
>[  924.588331] PM: Finishing wakeup.
>[  924.588333] Restarting tasks ... 
>[  924.592407] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  924.592413] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  924.592565] [drm:intel_power_well_disable [i915]] disabling display
>[  924.592680] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.592703] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.592744] done.
>[  924.596867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.596895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.596922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.596950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.596972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.596997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.597021] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  924.597068] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  924.597092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.597115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.597137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.597145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.597166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.597173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.597195] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.597216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.597238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.597259] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  924.597283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.597305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.597327] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  924.597347] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  924.597367] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  924.597392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.597417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  924.597480] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.597502] [drm:intel_power_well_enable [i915]] enabling display
>[  924.597522] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.597559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.597582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.597604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.597626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.597648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.597671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.597696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.597719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.597743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.597764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.597784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.597809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  924.597832] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.599861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.599887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.599910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.599934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.601474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.601500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.601523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.603073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.603099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.604948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.607258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  924.607310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.607334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  924.607368] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.607431] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  924.607455] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  924.607521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.607551] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  924.607599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.624213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.624235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.624256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.624278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.624298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.624320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.624341] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  924.624361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  924.624382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.624402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.624422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.624427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.624447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.624451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.624471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.624492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.624512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.624532] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  924.624552] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.624572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.624594] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  924.624614] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  924.624634] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  924.624655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.624680] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  924.640720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  924.640747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.640789] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  924.659638] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  924.659662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  924.659678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.659698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.659715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.659731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.659746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.659760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.659776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.659795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.659816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.659836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.659855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.659874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.659902] [drm:intel_power_well_disable [i915]] disabling display
>[  924.659925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.659945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.659966] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  924.659988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.660004] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.740168] PM: Syncing filesystems ... done.
>[  924.762089] PM: Preparing system for sleep (mem)
>[  924.762415] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  924.763843] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  924.765109] PM: Suspending system (mem)
>[  924.765191] Suspending console(s) (use no_console_suspend to debug)
>[  924.766540] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  924.767568] e1000e: EEE TX LPI TIMER: 00000011
>[  924.768686] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.768706] [drm:intel_power_well_enable [i915]] enabling display
>[  924.768720] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.774957] sd 3:0:0:0: [sda] Stopping disk
>[  924.776205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.776263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.776281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.776299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.776316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.776331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.776348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.776367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.776384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.776401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.776418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.776432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.776447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.776466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  924.881259] PM: suspend of devices complete after 115.352 msecs
>[  924.882554] [drm:intel_power_well_disable [i915]] disabling display
>[  924.882575] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.882588] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.882607] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  924.894143] PM: late suspend of devices complete after 12.876 msecs
>[  924.895621] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  924.895709] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  924.895910] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  924.907157] PM: noirq suspend of devices complete after 13.008 msecs
>[  924.907416] ACPI: Preparing to enter system sleep state S3
>[  924.929730] PM: Saving platform NVS memory
>[  924.929873] Disabling non-boot CPUs ...
>[  924.941646] smpboot: CPU 1 is now offline
>[  924.955296] Broke affinity for irq 42
>[  924.955303] Broke affinity for irq 44
>[  924.956592] smpboot: CPU 2 is now offline
>[  924.967219] Broke affinity for irq 8
>[  924.967222] Broke affinity for irq 9
>[  924.967226] Broke affinity for irq 23
>[  924.967230] Broke affinity for irq 42
>[  924.967233] Broke affinity for irq 43
>[  924.967236] Broke affinity for irq 44
>[  924.968264] smpboot: CPU 3 is now offline
>[  924.970031] ACPI: Low-level resume complete
>[  924.970156] PM: Restoring platform NVS memory
>[  924.970640] Suspended for 16.049 seconds
>[  924.970727] Enabling non-boot CPUs ...
>[  924.970835] x86: Booting SMP configuration:
>[  924.970839] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  924.972559]  cache: parent cpu1 should not be sleeping
>[  924.973724] CPU1 is up
>[  924.973814] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  924.975012]  cache: parent cpu2 should not be sleeping
>[  924.975705] CPU2 is up
>[  924.975761] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  924.976845]  cache: parent cpu3 should not be sleeping
>[  924.977960] CPU3 is up
>[  924.984435] ACPI: Waking up from system sleep state S3
>[  924.996866] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  925.008337] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  925.008342] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  925.008382] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  925.008614] PM: noirq resume of devices complete after 11.959 msecs
>[  925.009206] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  925.009267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.009300] [drm:intel_power_well_enable [i915]] enabling display
>[  925.010870] PM: early resume of devices complete after 2.228 msecs
>[  925.011092] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  925.011137] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  925.011158] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  925.012382] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  925.013698] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  925.017232] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  925.017250] [drm:intel_opregion_setup [i915]] ASLE supported
>[  925.017265] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  925.017282] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  925.017448] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  925.017468] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  925.017490] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  925.017512] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  925.017533] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  925.017554] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  925.017569] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  925.017872] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  925.017944] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  925.017964] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  925.017986] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  925.018004] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  925.018025] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  925.018041] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  925.018077] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  925.018096] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  925.018115] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  925.018131] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  925.018144] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  925.018157] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  925.018174] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  925.018192] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  925.018207] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  925.018221] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  925.018236] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  925.018256] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  925.018275] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  925.018291] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  925.018312] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  925.018331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  925.018347] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.018361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.018365] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.018381] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018394] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.018407] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.018420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.018432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.018447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.018460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.018472] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  925.018489] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  925.018506] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  925.018526] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  925.018543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  925.018560] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.018577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.018580] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.018600] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018618] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.018635] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.018652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.018669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.018686] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.018703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.018720] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  925.018738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  925.018755] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  925.018774] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  925.018791] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  925.018807] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.018824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.018827] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.018847] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.018864] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.018881] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.018899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.018915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.018933] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.018949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.018967] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.018984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.019001] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.019020] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  925.019038] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  925.019068] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  925.019120] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.019136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.019153] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.019173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.019190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.019209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.019226] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  925.019243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  925.019261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.019278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.019295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.019298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.019315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.019318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.019336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.019353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.019370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.019387] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  925.019404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.019421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.019438] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  925.019456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  925.019473] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  925.019491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.019511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  925.019576] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  925.021660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  925.021688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.021714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.021716] sd 3:0:0:0: [sda] Starting disk
>[  925.021736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.021752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.021766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.021782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  925.021801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  925.021818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.021834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.021849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.021864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.021878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.021891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.021908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.021926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  925.021945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.021961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  925.021980] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.022096] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  925.022130] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  925.024198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  925.024217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  925.026312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  925.026318] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  925.028420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  925.028441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  925.030515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  925.030521] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  925.030526] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  925.030546] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  925.031577] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  925.032474] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  925.032490] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  925.032504] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  925.032517] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  925.033504] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  925.033521] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  925.034448] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  925.034466] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  925.036545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  925.036566] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  925.038639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  925.038645] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  925.040721] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  925.040742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  925.042817] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  925.042822] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  925.042826] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  925.325665] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  925.366610] ata4.00: configured for UDMA/133
>[  925.378541] ahci 0000:00:1f.2: port does not support device sleep
>[  925.537202] PM: resume of devices complete after 526.295 msecs
>[  925.538061] PM: Finishing wakeup.
>[  925.538064] Restarting tasks ... 
>[  925.538325] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  925.538329] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  925.538406] [drm:intel_power_well_disable [i915]] disabling display
>[  925.538429] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.538441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.539547] done.
>[  925.549128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.549184] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.549214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.549238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.549264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.549286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.549307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.549330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.549353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.549377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.549401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.549424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.549445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.549466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.549498] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  925.549525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.549758] [drm:drm_mode_addfb2] [FB:77]
>[  925.549794] [drm:drm_mode_addfb2] [FB:78]
>[  925.580278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  925.580367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  925.580423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.580473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  925.580482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.580529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.580547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.580564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.580583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.580597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.580613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.580629] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  925.580644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  925.580658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.580672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.580688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.580692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.580709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.580713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.580731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.580748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.580766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.580783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.580801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.580818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.580836] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  925.580853] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  925.580870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  925.580889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.580908] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  925.583526] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.583542] [drm:intel_power_well_enable [i915]] enabling display
>[  925.583555] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.583584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.583600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.583615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.583629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.583642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.583657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.583673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.583688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.583706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.583724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.583740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.583759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  925.583776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.585764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.585782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.585796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.585811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.587319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.587337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.587354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.588848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.588866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.590672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.593031] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  925.593078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.593131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  925.593167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.609816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.609843] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  925.609881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.643297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.643318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.643339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.643360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.643376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.643394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.643411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  925.643428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  925.643444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.643459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.643473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.643478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.643492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.643495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.643510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.643529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.643548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.643567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.643587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.643606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.643626] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  925.643645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  925.643664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  925.643685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.643707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  925.643763] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  925.643789] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.643833] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  925.661870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  925.661889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.661910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.661927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.661943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.661958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.661973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.661989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.662007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.662023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.662039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.662053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.662067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.662143] [drm:intel_power_well_disable [i915]] disabling display
>[  925.662179] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.662205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.662224] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  925.662242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.662257] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.743040] PM: Syncing filesystems ... done.
>[  925.767515] PM: Preparing system for sleep (mem)
>[  925.767834] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  925.769285] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
>[  925.770204] PM: Suspending system (mem)
>[  925.770285] Suspending console(s) (use no_console_suspend to debug)
>[  925.771525] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  925.772487] e1000e: EEE TX LPI TIMER: 00000011
>[  925.772586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.772607] [drm:intel_power_well_enable [i915]] enabling display
>[  925.772628] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.775361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.775416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.775432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.775450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.775466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.775480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.775496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.775514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.775530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.775546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.775561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.775575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.775589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.775608] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  925.779950] sd 3:0:0:0: [sda] Stopping disk
>[  925.841219] PM: suspend of devices complete after 70.219 msecs
>[  925.842612] [drm:intel_power_well_disable [i915]] disabling display
>[  925.842635] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.842649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.842669] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  925.854161] PM: late suspend of devices complete after 12.926 msecs
>[  925.855651] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  925.855865] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  925.855988] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  925.867200] PM: noirq suspend of devices complete after 13.035 msecs
>[  925.867459] ACPI: Preparing to enter system sleep state S3
>[  925.889784] PM: Saving platform NVS memory
>[  925.889917] Disabling non-boot CPUs ...
>[  925.901703] smpboot: CPU 1 is now offline
>[  925.915354] Broke affinity for irq 42
>[  925.915361] Broke affinity for irq 44
>[  925.916411] smpboot: CPU 2 is now offline
>[  925.928325] Broke affinity for irq 8
>[  925.928328] Broke affinity for irq 9
>[  925.928332] Broke affinity for irq 23
>[  925.928335] Broke affinity for irq 42
>[  925.928338] Broke affinity for irq 43
>[  925.928341] Broke affinity for irq 44
>[  925.929372] smpboot: CPU 3 is now offline
>[  925.931045] ACPI: Low-level resume complete
>[  925.931177] PM: Restoring platform NVS memory
>[  925.931659] Suspended for 16.041 seconds
>[  925.931737] Enabling non-boot CPUs ...
>[  925.931846] x86: Booting SMP configuration:
>[  925.931851] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  925.933556]  cache: parent cpu1 should not be sleeping
>[  925.934719] CPU1 is up
>[  925.934808] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  925.936010]  cache: parent cpu2 should not be sleeping
>[  925.936695] CPU2 is up
>[  925.936748] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  925.937793]  cache: parent cpu3 should not be sleeping
>[  925.938930] CPU3 is up
>[  925.945386] ACPI: Waking up from system sleep state S3
>[  925.955568] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  925.967348] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  925.967355] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  925.967360] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  925.967609] PM: noirq resume of devices complete after 12.350 msecs
>[  925.968299] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  925.968359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.968390] [drm:intel_power_well_enable [i915]] enabling display
>[  925.970115] PM: early resume of devices complete after 2.473 msecs
>[  925.970355] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  925.970407] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  925.970431] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  925.970638] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  925.972398] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  925.976522] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  925.976541] [drm:intel_opregion_setup [i915]] ASLE supported
>[  925.976557] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  925.976571] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  925.976732] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  925.976752] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  925.976773] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  925.976792] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  925.976813] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  925.976833] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  925.976850] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  925.977121] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  925.977191] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  925.977210] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  925.977231] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  925.977249] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  925.977269] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  925.977284] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  925.977300] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  925.977317] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  925.977335] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  925.977351] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  925.977364] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  925.977378] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  925.977396] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  925.977413] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  925.977426] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  925.977441] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  925.977457] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  925.977473] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  925.977490] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  925.977508] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  925.977532] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  925.977548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  925.977564] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.977579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.977584] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.977599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.977602] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.977615] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.977628] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.977644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.977657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.977673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.977689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.977705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  925.977717] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  925.977729] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  925.977746] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  925.977758] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  925.977773] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.977787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.977790] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.977803] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.977808] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.977820] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.977835] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.977850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.977862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.977876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.977890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.977903] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  925.977917] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  925.977929] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  925.977943] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  925.977954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  925.977966] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  925.977977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.977980] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.977992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.977995] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  925.978006] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  925.978018] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  925.978030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.978046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.978063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.978080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.978109] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.978126] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.978144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.978163] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  925.978181] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  925.978198] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  925.978241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.978259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.978277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.978297] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.978314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.978332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.978349] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  925.978367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  925.978384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.978401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.978418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.978421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.978438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.978441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.978459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.978476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.978493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.978510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.978528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.978544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.978562] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  925.978579] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  925.978596] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  925.978615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.978636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  925.978702] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  925.980774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  925.980801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.980826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.980828] sd 3:0:0:0: [sda] Starting disk
>[  925.980848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.980863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.980882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.980901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  925.980923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  925.980944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.980965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.980985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.981006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.981025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.981043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.981065] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  925.981105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.981127] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  925.981151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.981172] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.981271] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  925.981318] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  925.983152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  925.983168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  925.985224] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  925.985228] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  925.987283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  925.987298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  925.989352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  925.989356] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  925.989360] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  925.989377] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  925.990403] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  925.991292] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  925.991307] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  925.991321] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  925.991334] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  925.992320] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  925.992334] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  925.993257] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  925.993275] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  925.995352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  925.995373] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  925.997447] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  925.997452] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  925.999530] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  925.999551] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  926.001626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  926.001631] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  926.001635] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  926.287428] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  926.328367] ata4.00: configured for UDMA/133
>[  926.340358] ahci 0000:00:1f.2: port does not support device sleep
>[  926.493341] PM: resume of devices complete after 523.190 msecs
>[  926.494135] PM: Finishing wakeup.
>[  926.494138] Restarting tasks ... 
>[  926.498532] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  926.498538] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  926.498657] [drm:intel_power_well_disable [i915]] disabling display
>[  926.498692] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.498713] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.498839] done.
>[  926.507425] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.507452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.507478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.507506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.507529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.507553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.507577] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  926.507600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  926.507621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.507642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.507662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.507669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.507689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.507694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.507715] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.507736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.507757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.507777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.507801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.507821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.507843] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.507864] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  926.507885] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  926.507908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.507934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  926.508012] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.508034] [drm:intel_power_well_enable [i915]] enabling display
>[  926.508055] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.508096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.508118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.508410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.508433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.508456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.508479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.508505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.508529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.508553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.508574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.508595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.508620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  926.508643] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.510718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.510744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.510767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.510791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.512617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.512643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.512665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.514258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.514284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.516226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.519292] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  926.519346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.519369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  926.519402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.519492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.519524] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  926.519573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.536213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.536233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.536252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.536273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.536288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.536306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.536323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  926.536339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  926.536355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.536372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.536395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.536403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.536419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.536422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.536437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.536451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.536465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.536479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.536495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.536510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.536524] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.536538] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  926.536553] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  926.536569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.536587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  926.536641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  926.536666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.536708] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  926.554974] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  926.554993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.555014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.555031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.555046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.555061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.555076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.555092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.555109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.555171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.555199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.555221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.555243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.555287] [drm:intel_power_well_disable [i915]] disabling display
>[  926.555324] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.555350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.555377] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  926.555403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.555428] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.641602] PM: Syncing filesystems ... done.
>[  926.651135] PM: Preparing system for sleep (mem)
>[  926.651453] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  926.652884] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  926.654149] PM: Suspending system (mem)
>[  926.654231] Suspending console(s) (use no_console_suspend to debug)
>[  926.655519] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  926.656435] e1000e: EEE TX LPI TIMER: 00000011
>[  926.656551] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.656572] [drm:intel_power_well_enable [i915]] enabling display
>[  926.656593] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.658814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.658870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.658890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.658912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.658931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.658950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.658969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.658990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.659011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.659031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.659051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.659070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.659088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.659111] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  926.664955] sd 3:0:0:0: [sda] Stopping disk
>[  926.725250] PM: suspend of devices complete after 70.281 msecs
>[  926.726678] [drm:intel_power_well_disable [i915]] disabling display
>[  926.726699] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.726710] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.726728] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  926.738190] PM: late suspend of devices complete after 12.926 msecs
>[  926.739740] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  926.740017] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  926.740110] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  926.751213] PM: noirq suspend of devices complete after 13.019 msecs
>[  926.751472] ACPI: Preparing to enter system sleep state S3
>[  926.773792] PM: Saving platform NVS memory
>[  926.773928] Disabling non-boot CPUs ...
>[  926.785516] smpboot: CPU 1 is now offline
>[  926.796388] Broke affinity for irq 42
>[  926.796396] Broke affinity for irq 44
>[  926.797678] smpboot: CPU 2 is now offline
>[  926.803300] Broke affinity for irq 8
>[  926.803304] Broke affinity for irq 9
>[  926.803308] Broke affinity for irq 23
>[  926.803311] Broke affinity for irq 42
>[  926.803314] Broke affinity for irq 43
>[  926.803317] Broke affinity for irq 44
>[  926.804344] smpboot: CPU 3 is now offline
>[  926.806415] ACPI: Low-level resume complete
>[  926.806541] PM: Restoring platform NVS memory
>[  926.807024] Suspended for 16.126 seconds
>[  926.807102] Enabling non-boot CPUs ...
>[  926.807243] x86: Booting SMP configuration:
>[  926.807248] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  926.808968]  cache: parent cpu1 should not be sleeping
>[  926.810153] CPU1 is up
>[  926.810244] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  926.811462]  cache: parent cpu2 should not be sleeping
>[  926.812150] CPU2 is up
>[  926.812206] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  926.813318]  cache: parent cpu3 should not be sleeping
>[  926.814387] CPU3 is up
>[  926.820403] ACPI: Waking up from system sleep state S3
>[  926.830592] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  926.842400] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  926.842404] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  926.842526] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  926.842675] PM: noirq resume of devices complete after 12.380 msecs
>[  926.842848] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  926.842911] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.842933] [drm:intel_power_well_enable [i915]] enabling display
>[  926.844613] PM: early resume of devices complete after 1.903 msecs
>[  926.844821] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  926.844865] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  926.844886] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  926.844989] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  926.847577] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  926.850165] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  926.850186] [drm:intel_opregion_setup [i915]] ASLE supported
>[  926.850204] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  926.850219] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  926.850384] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  926.850405] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  926.850428] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  926.850451] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  926.850470] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  926.850492] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  926.850511] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  926.850550] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  926.850616] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  926.850634] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  926.850655] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  926.850673] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  926.850690] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  926.850705] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  926.850723] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  926.850741] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  926.850758] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  926.850775] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  926.850787] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  926.850800] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  926.850818] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  926.850836] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  926.850849] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  926.850864] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  926.850879] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  926.850899] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  926.850917] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  926.850933] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  926.850953] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  926.850970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  926.850986] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  926.851002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.851006] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.851025] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851039] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  926.851054] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  926.851070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.851082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.851097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.851114] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.851149] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  926.851162] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.851177] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.851191] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  926.851204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  926.851219] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  926.851234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.851237] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.851255] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851269] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  926.851283] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  926.851295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.851307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.851325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.851340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.851355] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  926.851368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  926.851383] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  926.851400] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  926.851413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  926.851427] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  926.851442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.851444] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.851462] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  926.851475] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  926.851489] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  926.851504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.851517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.851534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.851549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.851565] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  926.851577] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  926.851592] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  926.851612] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  926.851629] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  926.851642] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  926.851685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.851701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.851720] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.851740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.851757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.851775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.851789] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  926.851803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  926.851820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.851835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.851848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.851852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.851867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.851870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.851886] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.851902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.851916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.851929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.851947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.851962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.851974] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  926.851986] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  926.852000] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  926.852017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.852037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  926.852111] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  926.854179] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  926.854196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.854215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.854234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.854254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.854273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.854292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  926.854314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  926.854335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.854356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.854376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.854396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.854415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.854434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.854456] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.854480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.854502] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  926.854526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.854546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.854644] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  926.854689] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  926.855309] sd 3:0:0:0: [sda] Starting disk
>[  926.856709] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  926.856726] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  926.858800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  926.858806] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  926.860883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  926.860902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  926.862976] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  926.862982] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  926.862986] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  926.863008] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  926.864037] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  926.864929] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  926.864946] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  926.864963] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  926.864981] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  926.865969] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  926.865985] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  926.866908] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  926.866927] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  926.869005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  926.869025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  926.871099] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  926.871104] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  926.873199] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  926.873218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  926.875291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  926.875296] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  926.875300] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  927.161882] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  927.202831] ata4.00: configured for UDMA/133
>[  927.214785] ahci 0000:00:1f.2: port does not support device sleep
>[  927.368342] PM: resume of devices complete after 523.693 msecs
>[  927.369216] PM: Finishing wakeup.
>[  927.369218] Restarting tasks ... 
>[  927.369460] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  927.369463] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  927.369538] [drm:intel_power_well_disable [i915]] disabling display
>[  927.369559] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.369571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.370286] done.
>[  927.373114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.373172] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.373196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.373221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.373247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.373271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.373294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.373317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.373333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.373351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.373371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.373390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.373408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.373432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.373465] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  927.373491] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.373718] [drm:drm_mode_addfb2] [FB:77]
>[  927.373755] [drm:drm_mode_addfb2] [FB:78]
>[  927.413255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  927.413385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  927.413483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  927.413580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  927.413593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  927.413662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.413687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.413714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.413741] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.413765] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.413789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.413814] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  927.413836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  927.413859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.413880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.413901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.413906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.413927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.413932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.413954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.413974] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.413995] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.414015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.414038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.414058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.414079] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  927.414100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  927.414121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  927.414145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.414212] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  927.416881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.416906] [drm:intel_power_well_enable [i915]] enabling display
>[  927.416929] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.416971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.416996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.417020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.417042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.417064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.417087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.417113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.417138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.417357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.417380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.417401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.417427] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  927.417450] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.419576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.419601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.419623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.419646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.421162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.421235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.421255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.422746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.422763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.424578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.427529] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  927.427588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.427605] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  927.427627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.444339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.444365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  927.444401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.477779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.477799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.477820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.477844] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.477864] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.477885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.477906] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  927.477926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  927.477947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.477967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.477987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.477992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.478012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.478016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.478037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.478057] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.478078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.478098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.478119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.478138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.478160] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.478227] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  927.478252] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  927.478281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.478311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  927.478381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  927.478412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.478466] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  927.495297] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  927.495316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.495337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.495353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.495369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.495384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.495398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.495414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.495431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.495447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.495463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.495476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.495495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.495523] [drm:intel_power_well_disable [i915]] disabling display
>[  927.495545] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.495565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.495586] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  927.495606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.495622] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.571375] PM: Syncing filesystems ... done.
>[  927.579992] PM: Preparing system for sleep (mem)
>[  927.580381] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  927.581839] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  927.583150] PM: Suspending system (mem)
>[  927.583244] Suspending console(s) (use no_console_suspend to debug)
>[  927.584554] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  927.585519] e1000e: EEE TX LPI TIMER: 00000011
>[  927.585599] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.585614] [drm:intel_power_well_enable [i915]] enabling display
>[  927.585628] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.587824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.587879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.587896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.587914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.587930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.587944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.587960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.587978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.587994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.588009] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.588025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.588039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.588052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.588071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  927.593828] sd 3:0:0:0: [sda] Stopping disk
>[  927.700384] PM: suspend of devices complete after 116.415 msecs
>[  927.701677] [drm:intel_power_well_disable [i915]] disabling display
>[  927.701708] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.701727] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.701752] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  927.713281] PM: late suspend of devices complete after 12.881 msecs
>[  927.714820] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  927.714975] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  927.715110] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  927.726267] PM: noirq suspend of devices complete after 12.970 msecs
>[  927.726532] ACPI: Preparing to enter system sleep state S3
>[  927.748816] PM: Saving platform NVS memory
>[  927.748952] Disabling non-boot CPUs ...
>[  927.760572] smpboot: CPU 1 is now offline
>[  927.772456] Broke affinity for irq 42
>[  927.772464] Broke affinity for irq 44
>[  927.773513] smpboot: CPU 2 is now offline
>[  927.779392] Broke affinity for irq 8
>[  927.779396] Broke affinity for irq 9
>[  927.779400] Broke affinity for irq 23
>[  927.779403] Broke affinity for irq 42
>[  927.779406] Broke affinity for irq 43
>[  927.779409] Broke affinity for irq 44
>[  927.780440] smpboot: CPU 3 is now offline
>[  927.782090] ACPI: Low-level resume complete
>[  927.782211] PM: Restoring platform NVS memory
>[  927.782691] Suspended for 16.026 seconds
>[  927.782770] Enabling non-boot CPUs ...
>[  927.782878] x86: Booting SMP configuration:
>[  927.782883] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  927.784572]  cache: parent cpu1 should not be sleeping
>[  927.785729] CPU1 is up
>[  927.785820] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  927.787009]  cache: parent cpu2 should not be sleeping
>[  927.787688] CPU2 is up
>[  927.787741] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  927.788820]  cache: parent cpu3 should not be sleeping
>[  927.789905] CPU3 is up
>[  927.796331] ACPI: Waking up from system sleep state S3
>[  927.808826] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  927.820436] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  927.820505] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  927.820509] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  927.820717] PM: noirq resume of devices complete after 12.235 msecs
>[  927.820884] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  927.820946] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.820967] [drm:intel_power_well_enable [i915]] enabling display
>[  927.822641] PM: early resume of devices complete after 1.893 msecs
>[  927.822860] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  927.822907] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  927.822928] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  927.824088] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  927.825608] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  927.828180] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  927.828198] [drm:intel_opregion_setup [i915]] ASLE supported
>[  927.828215] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  927.828233] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  927.828399] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  927.828420] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  927.828443] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  927.828464] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  927.828488] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  927.828510] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  927.828527] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  927.828557] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  927.828629] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  927.828659] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  927.828680] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  927.828697] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  927.828717] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  927.828733] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  927.828751] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  927.828770] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  927.828785] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  927.828800] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  927.828814] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  927.828830] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  927.828848] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  927.828865] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  927.828879] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  927.828894] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  927.828909] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  927.828925] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  927.828941] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  927.828959] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  927.828986] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  927.829002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  927.829018] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  927.829035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.829039] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.829058] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829071] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  927.829084] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  927.829099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.829115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.829131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.829160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.829173] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  927.829185] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.829200] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.829217] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  927.829230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  927.829245] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  927.829260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.829263] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.829277] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829289] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  927.829304] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  927.829318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.829331] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.829349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.829364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.829380] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  927.829395] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  927.829410] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  927.829427] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  927.829440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  927.829454] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  927.829469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.829472] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.829490] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  927.829503] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  927.829518] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  927.829533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.829546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.829562] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.829577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.829594] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  927.829607] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  927.829622] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  927.829638] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  927.829655] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  927.829669] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  927.829714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.829729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.829748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.829768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.829782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.829797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.829814] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  927.829831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  927.829847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.829863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.829876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.829880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.829894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.829898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.829913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.829929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.829943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.829957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  927.829971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.829985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.829999] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  927.830014] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  927.830029] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  927.830045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.830065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  927.830132] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  927.832202] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  927.832218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.832234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.832248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.832262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.832276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.832291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  927.832309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  927.832325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.832341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.832356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.832371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.832384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.832397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.832415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.832433] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  927.832451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.832468] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  927.832486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.832572] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  927.832617] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  927.833400] sd 3:0:0:0: [sda] Starting disk
>[  927.834182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  927.834198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  927.836270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  927.836276] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  927.838352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  927.838371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  927.840445] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  927.840451] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  927.840455] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  927.840477] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  927.841507] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  927.842407] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  927.842423] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  927.842438] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  927.842451] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  927.843440] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  927.843454] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  927.844377] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  927.844396] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  927.846473] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  927.846494] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  927.848570] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  927.848575] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  927.850651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  927.850670] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  927.852745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  927.852750] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  927.852754] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  928.139870] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  928.180823] ata4.00: configured for UDMA/133
>[  928.192768] ahci 0000:00:1f.2: port does not support device sleep
>[  928.345421] PM: resume of devices complete after 522.744 msecs
>[  928.346190] PM: Finishing wakeup.
>[  928.346192] Restarting tasks ... done.
>[  928.352744] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  928.352750] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  928.352874] [drm:intel_power_well_disable [i915]] disabling display
>[  928.352911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.352932] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.357717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.357745] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.357771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.357799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.357823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.357848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.357873] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  928.357896] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  928.357919] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.357941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.357962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.357969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.357990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.358007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.358029] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.358049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.358070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.358091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.358115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.358136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.358159] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.358376] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  928.358399] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  928.358424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.358451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  928.358516] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.358539] [drm:intel_power_well_enable [i915]] enabling display
>[  928.358561] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.358603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.358626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.358648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.358669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.358691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.358713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.358739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.358763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.358786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.358807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.358827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.358853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  928.358876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.360905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.360932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.360955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.360980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.362528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.362552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.362574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.364544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.364571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.366412] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.369373] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  928.369432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.369456] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  928.369489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.369581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.369614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  928.369663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.386320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.386341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.386362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.386386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.386407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.386428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.386448] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  928.386469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  928.386490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.386510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.386530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.386535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.386555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.386559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.386579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.386600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.386620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.386640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.386661] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.386681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.386702] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.386722] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  928.386742] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  928.386764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.386787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  928.386843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  928.386871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.386916] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  928.404879] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  928.404898] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.404919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.404936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.404952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.404967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.404983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.404999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.405016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.405032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.405047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.405062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.405075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.405103] [drm:intel_power_well_disable [i915]] disabling display
>[  928.405126] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.405147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.405168] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  928.405237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.405265] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.494912] PM: Syncing filesystems ... done.
>[  928.504480] PM: Preparing system for sleep (mem)
>[  928.504800] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  928.506250] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  928.507276] PM: Suspending system (mem)
>[  928.507357] Suspending console(s) (use no_console_suspend to debug)
>[  928.508784] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[  928.509799] e1000e: EEE TX LPI TIMER: 00000011
>[  928.509907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.509927] [drm:intel_power_well_enable [i915]] enabling display
>[  928.509948] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.510255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.510331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.510354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.510379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.510402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.510423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.510445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.510471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.510495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.510518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.510540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.510560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.510580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.510607] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  928.517892] sd 3:0:0:0: [sda] Stopping disk
>[  928.706273] PM: suspend of devices complete after 198.171 msecs
>[  928.707723] [drm:intel_power_well_disable [i915]] disabling display
>[  928.707754] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.707773] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.707798] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  928.719231] PM: late suspend of devices complete after 12.952 msecs
>[  928.720765] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  928.720926] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  928.721012] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  928.732276] PM: noirq suspend of devices complete after 13.040 msecs
>[  928.732535] ACPI: Preparing to enter system sleep state S3
>[  928.754852] PM: Saving platform NVS memory
>[  928.754987] Disabling non-boot CPUs ...
>[  928.766950] smpboot: CPU 1 is now offline
>[  928.779440] Broke affinity for irq 42
>[  928.779447] Broke affinity for irq 44
>[  928.780740] smpboot: CPU 2 is now offline
>[  928.789350] Broke affinity for irq 8
>[  928.789353] Broke affinity for irq 9
>[  928.789357] Broke affinity for irq 23
>[  928.789361] Broke affinity for irq 42
>[  928.789364] Broke affinity for irq 43
>[  928.789367] Broke affinity for irq 44
>[  928.790407] smpboot: CPU 3 is now offline
>[  928.792108] ACPI: Low-level resume complete
>[  928.792236] PM: Restoring platform NVS memory
>[  928.792727] Suspended for 15.992 seconds
>[  928.792806] Enabling non-boot CPUs ...
>[  928.792915] x86: Booting SMP configuration:
>[  928.792920] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  928.794634]  cache: parent cpu1 should not be sleeping
>[  928.795813] CPU1 is up
>[  928.795906] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  928.797133]  cache: parent cpu2 should not be sleeping
>[  928.797834] CPU2 is up
>[  928.797886] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  928.798962]  cache: parent cpu3 should not be sleeping
>[  928.799690] CPU3 is up
>[  928.803088] ACPI: Waking up from system sleep state S3
>[  928.815753] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  928.827474] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  928.827499] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  928.827503] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  928.827827] PM: noirq resume of devices complete after 12.363 msecs
>[  928.827968] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  928.828038] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.828059] [drm:intel_power_well_enable [i915]] enabling display
>[  928.829773] PM: early resume of devices complete after 1.917 msecs
>[  928.829965] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[  928.830007] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  928.830028] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  928.830237] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  928.832682] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  928.835252] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  928.835273] [drm:intel_opregion_setup [i915]] ASLE supported
>[  928.835292] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  928.835309] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  928.835465] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  928.835485] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  928.835509] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  928.835532] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  928.835555] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  928.835577] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  928.835598] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[  928.835628] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  928.835697] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  928.835717] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  928.835740] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  928.835759] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  928.835781] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  928.835797] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  928.835816] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  928.835835] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  928.835854] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  928.835870] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  928.835885] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  928.835901] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  928.835920] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  928.835936] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  928.835950] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  928.835966] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  928.835982] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  928.836003] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  928.836023] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  928.836042] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  928.836066] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  928.836082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  928.836097] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  928.836113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.836118] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.836138] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836154] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  928.836171] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  928.836185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.836222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.836240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.836257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.836283] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  928.836295] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.836307] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.836321] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  928.836336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  928.836349] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  928.836362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.836365] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.836382] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836397] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  928.836410] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  928.836424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.836439] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.836454] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.836467] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.836482] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  928.836496] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  928.836509] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  928.836524] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  928.836539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  928.836551] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  928.836565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.836567] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.836585] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  928.836598] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  928.836611] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  928.836626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.836639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.836655] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.836667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.836681] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  928.836694] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  928.836709] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  928.836727] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  928.836742] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  928.836757] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  928.836800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.836813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.836832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.836853] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.836869] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.836886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.836903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  928.836919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  928.836934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.836947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.836962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.836965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.836980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.836983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.837000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.837017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.837031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.837046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  928.837063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.837077] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.837091] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  928.837106] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  928.837120] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  928.837136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.837155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  928.837235] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  928.839293] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  928.839309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.839324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.839338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.839352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.839366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.839381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  928.839398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  928.839418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.839439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.839460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.839480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.839499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.839518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.839541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.839565] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  928.839588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.839610] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  928.839634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.839726] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  928.839772] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  928.840560] sd 3:0:0:0: [sda] Starting disk
>[  928.841252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  928.841275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  928.843332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  928.843337] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  928.845413] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  928.845432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  928.847507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  928.847512] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  928.847517] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  928.847538] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  928.848564] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  928.849453] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  928.849469] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  928.849483] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  928.849496] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  928.850485] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  928.850499] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  928.851423] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  928.851441] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  928.853518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  928.853539] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  928.855613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  928.855619] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  928.857695] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  928.857715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  928.859788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  928.859793] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  928.859797] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  929.149884] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  929.190840] ata4.00: configured for UDMA/133
>[  929.202789] ahci 0000:00:1f.2: port does not support device sleep
>[  929.352294] PM: resume of devices complete after 522.485 msecs
>[  929.353065] PM: Finishing wakeup.
>[  929.353067] Restarting tasks ... 
>[  929.354714] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  929.354720] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  929.354835] [drm:intel_power_well_disable [i915]] disabling display
>[  929.354868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.354888] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.355266] done.
>[  929.360491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.360544] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.360573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.360597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.360622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.360645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.360667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.360691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.360715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.360740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.360763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.360787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.360809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.360830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.360861] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  929.360885] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.362878] [IGT] kms_flip: exiting, ret=0
>[  929.363532] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  929.385878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.385895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.385913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.385930] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.385944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.385959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.385976] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.385994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.386011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.386028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.386044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.386049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.386065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.386068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.386085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.386102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.386119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.386136] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.386153] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.386169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.386186] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  929.386203] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.386225] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.386408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.386427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.386488] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.386511] [drm:intel_power_well_enable [i915]] enabling display
>[  929.386532] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.386576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.386599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.386621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.386642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.386664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.386685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.386710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.386733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.386756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.386776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.386795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.386819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.386840] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.389187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.389211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.389260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.389284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.390834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.390858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.390880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.392420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.392445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.394692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.397698] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.397762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.397785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.397820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.397886] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.397907] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.414504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.414530] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.414568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.414708] Console: switching to colour frame buffer device 240x75
>[  929.562375] Console: switching to colour dummy device 80x25
>[  929.562469] [IGT] kms_flip: executing
>[  929.576628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  929.576658] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  929.578307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  929.578327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  929.580293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  929.580299] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  929.582293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  929.582314] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  929.584295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  929.584301] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  929.584305] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  929.584321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  929.584343] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  929.585381] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  929.586288] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  929.586314] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  929.586335] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  929.586350] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  929.587338] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  929.587361] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  929.588418] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  929.588421] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  929.588500] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  929.588502] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  929.588506] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  929.588508] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  929.588512] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  929.588514] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  929.588521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  929.588524] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.588526] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  929.588529] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  929.588531] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  929.588534] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  929.588536] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  929.588539] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  929.588541] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  929.588544] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  929.588546] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  929.588548] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  929.588551] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  929.588553] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  929.588556] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  929.588558] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  929.588561] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  929.588563] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  929.588566] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  929.588568] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  929.588570] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  929.588573] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  929.588575] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  929.588578] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  929.588580] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  929.588583] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  929.588585] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  929.588587] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  929.588590] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  929.588592] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  929.588595] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  929.588626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  929.588644] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  929.590293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  929.590311] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  929.592293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  929.592298] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  929.594293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  929.594311] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  929.596293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  929.596298] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  929.596302] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  929.597544] [IGT] kms_flip: starting subtest flip-vs-modeset-interruptible
>[  929.598033] [drm:drm_mode_addfb2] [FB:75]
>[  929.598055] [drm:drm_mode_addfb2] [FB:79]
>[  929.640758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.640813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.648036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.648064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.648107] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.666941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.666964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.666980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.667002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.667022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.667043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.667063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.667082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.667102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.667123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.667144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.667164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.667185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.667203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.667220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.667293] [drm:intel_power_well_disable [i915]] disabling display
>[  929.667329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.667365] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.667384] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.667439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  929.667515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  929.667583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.667593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.667640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.667660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.667680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.667703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.667722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.667742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.667762] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.667782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.667802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.667821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.667840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.667844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.667863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.667867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.667887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.667906] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.667923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.667942] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.667961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.667980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.667999] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  929.668018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.668039] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.668060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.668082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.670604] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.670621] [drm:intel_power_well_enable [i915]] enabling display
>[  929.670635] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.670663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.670683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.670702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.670720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.670739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.670758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.670778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.670798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.670817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.670836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.670852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.670872] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.670891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.672886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.672904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.672918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.672933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.674439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.674457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.674475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.675968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.675985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.677792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.680725] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.680802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.680818] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.680841] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.680881] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.680897] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.697547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.697572] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.697607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.714258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.714268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.730991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.731037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.764280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.764306] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.764344] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.783183] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.783205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.783224] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.783246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.783309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.783333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.783350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.783365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.783382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.783401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.783417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.783433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.783449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.783463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.783478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.783504] [drm:intel_power_well_disable [i915]] disabling display
>[  929.783527] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.783552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.783570] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.783644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.783654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.783700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.783720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.783747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.783777] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.783794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.783819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.783835] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.783850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.783864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.783878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.783891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.783895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.783908] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.783911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.783925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.783938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.783951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.783964] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.783980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.783992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.784006] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  929.784018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.784032] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.784047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.784066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.784109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.784124] [drm:intel_power_well_enable [i915]] enabling display
>[  929.784138] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.784166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.784184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.784203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.784220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.784239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.784280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.784305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.784328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.784352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.784372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.784391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.784416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.784437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.786431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.786447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.786461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.786475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.787979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.787995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.788008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.789503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.789521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.791326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.795339] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.795399] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.795418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.795444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.795485] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.795504] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.812144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.812170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.812205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.812381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.812442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.845500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.845525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.845563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.864415] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.864437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.864453] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.864473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.864490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.864507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.864522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.864537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.864553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.864571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.864587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.864604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.864619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.864634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.864648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.864674] [drm:intel_power_well_disable [i915]] disabling display
>[  929.864696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.864717] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.864734] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.864813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.864823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.864865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.864881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.864901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.864924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.864943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.864962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.864982] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.865001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.865020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.865039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.865058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.865061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.865080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.865084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.865103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.865122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.865141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.865160] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.865179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.865198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.865217] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  929.865236] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.865298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.865326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.865353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.865420] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.865444] [drm:intel_power_well_enable [i915]] enabling display
>[  929.865465] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.865507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.865533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.865555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.865578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.865602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.865628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.865649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.865677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.865693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.865707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.865721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.865737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.865753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.867727] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.867744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.867761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.867780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.869371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.869387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.869401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.870897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.870915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.872721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.875648] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.875678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.875694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.875717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.875756] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.875772] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.892423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.892449] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.892484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.892609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.892657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.925775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.925798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.925832] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.944689] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.944712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.944732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.944754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.944774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.944795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.944814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.944834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.944853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.944874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.944895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.944915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.944936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.944955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.944970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.944998] [drm:intel_power_well_disable [i915]] disabling display
>[  929.945020] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.945045] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.945062] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.945162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.945171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.945216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.945234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.945253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.945316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.945341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.945365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.945388] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.945411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.945433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.945455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.945475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.945482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.945502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.945508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.945530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.945550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.945572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.945591] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.945615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.945635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.945656] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  929.945676] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.945697] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.945722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.945748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.945809] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.945831] [drm:intel_power_well_enable [i915]] enabling display
>[  929.945853] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.945889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.945909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.945931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.945950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.945971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.945991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.946014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.946037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.946060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.946080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.946100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.946123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.946145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.948136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.948153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.948167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.948182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.949688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.949703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.949717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.951212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.951228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.953041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.955974] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.956051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.956068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.956090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.956128] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.956145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.972793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.972820] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.972857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.972983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.973031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.006151] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.006175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.006210] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.025052] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.025073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.025090] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.025109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.025125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.025143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.025158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.025173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.025188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.025206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.025223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.025238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.025254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.025311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.025334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.025378] [drm:intel_power_well_disable [i915]] disabling display
>[  930.025411] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.025443] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.025470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.025576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.025590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.025658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.025682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.025708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.025737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.025760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.025785] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.025809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.025832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.025855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.025877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.025898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.025904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.025925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.025930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.025953] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.025974] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.025996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.026017] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.026042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.026063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.026085] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.026112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.026133] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.026154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.026178] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.026241] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.026263] [drm:intel_power_well_enable [i915]] enabling display
>[  930.026304] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.026340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.026362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.026384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.026405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.026427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.026448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.026473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.026497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.026521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.026541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.026563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.026586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.026609] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.028598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.028614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.028629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.028643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.030147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.030162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.030176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.031672] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.031688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.033490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.035927] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.035994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.036011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.036036] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.036079] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.036098] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.052746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.052771] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.052806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.052898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.052937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.086126] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.086150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.086186] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.105058] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.105080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.105096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.105116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.105133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.105151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.105166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.105180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.105196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.105214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.105230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.105245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.105261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.105318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.105341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.105385] [drm:intel_power_well_disable [i915]] disabling display
>[  930.105420] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.105453] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.105482] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.105601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.105616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.105685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.105709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.105736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.105764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.105787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.105820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.105841] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.105863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.105884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.105905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.105924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.105929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.105949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.105954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.105975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.105994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.106014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.106033] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.106056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.106075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.106096] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.106115] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.106135] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.106156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.106180] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.106245] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.106268] [drm:intel_power_well_enable [i915]] enabling display
>[  930.106312] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.106350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.106371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.106393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.106414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.106436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.106457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.106482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.106506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.106531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.106551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.106573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.106598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.106621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.108616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.108633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.108647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.108661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.110167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.110183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.110196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.112809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.112828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.114652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.117602] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.117662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.117681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.117707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.117747] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.117767] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.134434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.134460] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.134497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.134598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.134640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.167794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.167818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.167854] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.186698] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.186720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.186736] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.186756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.186775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.186797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.186816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.186836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.186855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.186876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.186897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.186917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.186938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.186957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.186973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.187000] [drm:intel_power_well_disable [i915]] disabling display
>[  930.187022] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.187047] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.187065] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.187144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.187154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.187200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.187220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.187239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.187262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.187319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.187349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.187377] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.187401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.187427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.187449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.187473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.187480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.187503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.187510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.187534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.187556] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.187580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.187608] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.187632] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.187652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.187674] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.187694] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.187715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.187740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.187766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.188130] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.188153] [drm:intel_power_well_enable [i915]] enabling display
>[  930.188175] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.188211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.188233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.188255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.188276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.188315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.188337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.188362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.188386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.188410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.188570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.188589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.188614] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.188635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.190623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.190639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.190656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.190674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.192179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.192196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.192214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.193711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.193728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.195531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.198477] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.198540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.198557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.198579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.198627] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.198652] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.215300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.215326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.215360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.215494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.215539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.248641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.248666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.248711] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.267566] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.267588] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.267604] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.267624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.267641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.267659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.267674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.267689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.267705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.267723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.267740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.267756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.267772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.267786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.267800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.267827] [drm:intel_power_well_disable [i915]] disabling display
>[  930.267848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.267869] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.267886] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.267964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.267973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.268015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.268031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.268049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.268068] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.268084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.268100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.268116] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.268131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.268146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.268161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.268175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.268179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.268192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.268196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.268210] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.268224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.268237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.268250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.268267] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.268323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.268346] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.268371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.268400] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.268424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.268450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.268513] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.268537] [drm:intel_power_well_enable [i915]] enabling display
>[  930.268559] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.268595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.268615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.268637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.268656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.268678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.268699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.268723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.268746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.268769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.268788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.268808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.268832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.268853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.270962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.270978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.270992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.271007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.272514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.272529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.272546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.274040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.274056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.275862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.278782] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.278819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.278835] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.278860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.278908] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.278934] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.295564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.295589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.295624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.295734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.295787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.328920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.328945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.328989] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.347835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.347859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.347879] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.347900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.347920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.347941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.347960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.347980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.347999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.348020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.348041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.348061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.348081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.348100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.348116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.348143] [drm:intel_power_well_disable [i915]] disabling display
>[  930.348166] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.348190] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.348208] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.348327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.348342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.348413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.348438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.348465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.348494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.348516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.348542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.348566] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.348590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.348612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.348636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.348657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.348664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.348685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.348690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.348714] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.348735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.348757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.348777] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.348802] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.348822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.348844] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.348865] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.348887] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.348910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.348936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.349003] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.349028] [drm:intel_power_well_enable [i915]] enabling display
>[  930.349058] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.349094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.349115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.349136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.349156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.349176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.349197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.349220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.349243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.349266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.349305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.349327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.349350] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.349374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.351366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.351382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.351396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.351411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.352924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.352939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.352953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.354449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.354465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.356268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.358913] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.358984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.359001] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.359022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.359071] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.359096] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.375730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.375756] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.375790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.375913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.375963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.409086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.409112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.409158] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.428012] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.428034] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.428051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.428070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.428086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.428103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.428119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.428133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.428149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.428166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.428183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.428199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.428215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.428229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.428242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.428269] [drm:intel_power_well_disable [i915]] disabling display
>[  930.428332] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.428365] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.428394] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.428692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.428707] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.428767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.428785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.428803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.428823] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.428838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.428855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.428872] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.428887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.428909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.428923] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.428936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.428939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.428956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.428959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.428977] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.428995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.429012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.429029] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.429047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.429064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.429082] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.429100] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.429118] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.429136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.429155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.429197] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.429211] [drm:intel_power_well_enable [i915]] enabling display
>[  930.429225] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.429252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.429270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.429287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.429331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.429359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.429381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.429406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.429431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.429456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.429477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.429498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.429524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.429546] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.431832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.431849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.431863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.431878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.433397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.433414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.433429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.434926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.434942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.436751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.439687] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.439759] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.439775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.439797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.439834] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.439851] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.456518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.456544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.456581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.456684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.456726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.489858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.489881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.489925] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.508671] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.508693] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.508710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.508729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.508746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.508764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.508778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.508793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.508809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.508826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.508842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.508862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.508883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.508902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.508921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.508948] [drm:intel_power_well_disable [i915]] disabling display
>[  930.508970] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.508995] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.509013] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.509093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.509102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.509148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.509168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.509187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.509209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.509228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.509247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.509267] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.509286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.509349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.509373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.509395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.509403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.509424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.509430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.509453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.509475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.509496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.509518] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.509543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.509571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.509591] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.509610] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.509630] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.509653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.509676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.509740] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.509761] [drm:intel_power_well_enable [i915]] enabling display
>[  930.509775] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.509800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.509815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.509829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.509843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.509860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.509878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.509898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.509916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.509936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.509953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.509971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.509990] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.510008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.511988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.512005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.512022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.512040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.513549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.513567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.513584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.515079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.515096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.516903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.519842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.519912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.519931] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.519957] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.520006] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.520032] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.536646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.536670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.536703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.536810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.536862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.570011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.570035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.570080] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.588151] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.588174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.588194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.588215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.588235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.588256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.588276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.588295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.588358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.588389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.588418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.588445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.588471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.588493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.588516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.588559] [drm:intel_power_well_disable [i915]] disabling display
>[  930.588593] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.588625] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.588653] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.588763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.588778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.588847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.588870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.588896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.588925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.588947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.588973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.588996] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.589020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.589042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.589065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.589086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.589091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.589112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.589118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.589141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.589161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.589183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.589203] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.589228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.589248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.589270] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.589291] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.589336] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.589371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.589397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.589450] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.589473] [drm:intel_power_well_enable [i915]] enabling display
>[  930.589496] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.589533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.589555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.589576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.589598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.589617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.589638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.589662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.589685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.589708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.589727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.589747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.589770] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.589791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.591785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.591803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.591821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.591839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.593361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.593378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.593393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.594888] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.594904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.596708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.599345] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.599416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.599435] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.599461] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.599503] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.599529] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.616166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.616192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.616226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.616380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.616420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.649514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.649537] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.649572] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.667057] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.667079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.667095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.667115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.667131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.667149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.667164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.667178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.667194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.667212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.667228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.667244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.667259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.667274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.667288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.667366] [drm:intel_power_well_disable [i915]] disabling display
>[  930.667402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.667425] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.667442] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.667520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.667538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.667595] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.667613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.667631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.667651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.667667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.667683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.667700] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.667715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.667731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.667745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.667759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.667763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.667777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.667781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.667796] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.667810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.667824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.667838] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.667857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.667877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.667897] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.667916] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.667937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.667957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.667979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.668030] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.668045] [drm:intel_power_well_enable [i915]] enabling display
>[  930.668059] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.668086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.668104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.668122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.668140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.668159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.668176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.668196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.668214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.668234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.668251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.668269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.668288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.668330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.670334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.670350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.670364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.670379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.671885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.671900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.671914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.673413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.673431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.675248] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.678193] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.678255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.678270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.678290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.678461] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.678477] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.695000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.695026] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.695060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.695168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.695208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.728365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.728389] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.728426] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.747268] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.747290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.747347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.747379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.747403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.747430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.747452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.747476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.747498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.747526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.747551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.747577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.747602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.747623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.747646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.747686] [drm:intel_power_well_disable [i915]] disabling display
>[  930.747719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.747750] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.747777] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.747899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.747911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.747951] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.747966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.747983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.748000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.748014] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.748030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.748045] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.748059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.748073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.748086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.748099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.748102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.748115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.748118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.748131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.748148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.748166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.748183] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.748201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.748218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.748235] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.748253] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.748271] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.748289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.748333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.748399] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.748423] [drm:intel_power_well_enable [i915]] enabling display
>[  930.748446] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.748483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.748506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.748529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.748549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.748570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.748592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.748617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.748641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.748664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.748684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.748704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.748727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.748749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.751788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.751804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.751818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.751833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.753373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.753391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.753409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.754902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.754920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.756731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.759676] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.759739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.759756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.759778] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.759816] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.759833] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.776481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.776505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.776537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.776638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.776675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.809861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.809886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.809923] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.828801] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.828824] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.828840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.828860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.828877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.828898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.828917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.828936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.828956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.828977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.828998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.829018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.829039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.829057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.829076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.829104] [drm:intel_power_well_disable [i915]] disabling display
>[  930.829126] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.829151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.829169] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.829245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.829255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.829301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.829398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.829426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.829457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.829476] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.829497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.829517] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.829534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.829554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.829574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.829592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.829597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.829616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.829620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.829639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.829659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.829679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.829705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.829723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.829740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.829754] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.829768] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.829786] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.829805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.829825] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.829867] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.829882] [drm:intel_power_well_enable [i915]] enabling display
>[  930.829896] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.829924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.829942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.829960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.829978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.829996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.830013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.830032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.830051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.830071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.830089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.830106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.830125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.830143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.832125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.832142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.832156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.832171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.833678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.833693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.833707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.835200] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.835218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.837024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.839910] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.839987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.840003] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.840024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.840062] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.840079] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.856725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.856752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.856789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.856897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.856939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.890080] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.890104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.890149] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.907840] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.907862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.907878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.907897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.907914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.907932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.907947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.907962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.907978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.907995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.908012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.908027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.908043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.908057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.908071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.908098] [drm:intel_power_well_disable [i915]] disabling display
>[  930.908119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.908146] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.908163] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.908241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.908250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.908293] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.908309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.908369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.908399] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.908423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.908449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.908480] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.908503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.908524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.908546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.908565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.908572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.908592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.908598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.908620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.908640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.908662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.908681] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.908705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.908725] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.908746] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.908766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.908789] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.908811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.908836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.908900] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.908922] [drm:intel_power_well_enable [i915]] enabling display
>[  930.908944] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.908980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.909002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.909023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.909044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.909063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.909085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.909109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.909132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.909155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.909175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.909195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.909218] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.909240] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.911231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.911247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.911261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.911276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.912780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.912795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.912810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.914303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.914332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.916134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.919054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.919092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.919111] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.919137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.919187] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.919213] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  930.935836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.935861] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.935896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.936002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.936041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.969193] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  930.969217] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.969261] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  930.988107] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  930.988129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  930.988145] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.988165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.988182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.988199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.988214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.988229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.988245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.988263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.988279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.988295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.988315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.988374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.988398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.988443] [drm:intel_power_well_disable [i915]] disabling display
>[  930.988476] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.988509] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  930.988536] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.988658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  930.988673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  930.988743] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.988766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.988793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.988822] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.988845] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.988870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.988893] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  930.988917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  930.988940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.988962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.988983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.988989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.989010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.989016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.989039] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.989060] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.989082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.989103] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  930.989127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.989148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.989170] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  930.989191] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  930.989213] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  930.989242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.989266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  930.989344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.989368] [drm:intel_power_well_enable [i915]] enabling display
>[  930.989390] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.989427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.989451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.989472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.989494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.989514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.989536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.989561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.989585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.989609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.989629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.989651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.989675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  930.989696] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.991683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.991701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.991718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.991736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.993266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.993283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.993297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.994825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.994841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.996672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.999604] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  930.999680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.999697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  930.999718] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.999766] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  930.999792] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.016426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.016451] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.016485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.016591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.016631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.049782] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.049806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.049851] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.068716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.068738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.068755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.068774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.068792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.068809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.068825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.068840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.068856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.068874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.068891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.068907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.068922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.068937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.068951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.068977] [drm:intel_power_well_disable [i915]] disabling display
>[  931.068998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.069022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.069041] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.069113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.069122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.069169] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.069189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.069209] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.069231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.069250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.069269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.069288] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.069307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.069327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.069389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.069414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.069422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.069446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.069453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.069478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.069501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.069525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.069546] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.069573] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.069595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.069618] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.069640] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.069664] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.069691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.069717] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.069787] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.069812] [drm:intel_power_well_enable [i915]] enabling display
>[  931.069843] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.069879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.069900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.069921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.069941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.069962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.069985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.070008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.070031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.070054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.070073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.070094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.070118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.070139] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.072130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.072148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.072165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.072183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.073690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.073706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.073721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.075213] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.075229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.077034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.079954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.079991] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.080007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.080029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.080082] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.080105] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.096736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.096761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.096798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.096900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.096941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.130084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.130110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.130155] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.149007] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.149029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.149045] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.149064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.149081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.149099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.149115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.149130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.149146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.149164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.149180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.149196] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.149212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.149230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.149248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.149276] [drm:intel_power_well_disable [i915]] disabling display
>[  931.149298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.149323] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.149385] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.149505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.149519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.149589] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.149613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.149640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.149675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.149696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.149719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.149741] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.149763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.149783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.149805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.149824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.149829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.149849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.149854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.149875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.149894] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.149914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.149933] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.149956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.149975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.149995] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.150014] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.150035] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.150056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.150080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.150144] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.150166] [drm:intel_power_well_enable [i915]] enabling display
>[  931.150188] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.150224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.150245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.150266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.150286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.150307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.150327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.150368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.150393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.150417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.150437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.150459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.150484] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.150506] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.152494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.152510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.152524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.152538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.154045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.154061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.154075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.155574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.155590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.157394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.160325] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.160404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.160421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.160447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.160496] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.160522] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.177144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.177170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.177207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.177316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.177497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.210504] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.210528] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.210572] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.229430] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.229451] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.229467] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.229486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.229503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.229520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.229535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.229550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.229566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.229584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.229601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.229617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.229632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.229646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.229660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.229686] [drm:intel_power_well_disable [i915]] disabling display
>[  931.229707] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.229729] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.229745] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.229823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.229832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.229875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.229890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.229908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.229927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.229943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.229959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.229975] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.229990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.230005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.230019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.230033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.230036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.230050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.230053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.230067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.230081] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.230094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.230107] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.230124] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.230142] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.230161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.230181] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.230200] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.230220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.230241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.230287] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.230302] [drm:intel_power_well_enable [i915]] enabling display
>[  931.230324] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.230393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.230417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.230441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.230465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.230486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.230509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.230535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.230560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.230586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.230606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.230627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.230654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.230676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.232675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.232691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.232706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.232720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.234223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.234238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.234252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.235747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.235762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.237569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.240501] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.240576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.240591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.240612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.240655] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.240679] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.257322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.257366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.257403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.257515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.257573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.290679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.290703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.290747] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.309614] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.309636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.309655] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.309677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.309697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.309718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.309737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.309756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.309775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.309797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.309817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.309838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.309858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.309877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.309893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.309920] [drm:intel_power_well_disable [i915]] disabling display
>[  931.309948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.309980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.309998] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.310069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.310085] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.310125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.310141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.310157] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.310175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.310189] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.310204] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.310220] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.310234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.310248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.310262] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.310275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.310278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.310291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.310294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.310308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.310321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.310333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.310385] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.310410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.310430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.310453] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.310473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.310494] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.310519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.310543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.310607] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.310631] [drm:intel_power_well_enable [i915]] enabling display
>[  931.310652] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.310688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.310710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.310732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.310751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.310772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.310792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.310816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.310839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.310862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.310881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.310901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.310925] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.310946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.312939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.312956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.312973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.312992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.314500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.314517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.314531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.316022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.316038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.317842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.320781] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.320852] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.320868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.320890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.320938] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.320964] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.337594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.337620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.337654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.337752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.337792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.370951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.370975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.371020] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.389863] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.389886] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.389906] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.389928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.389948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.389969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.389988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.390008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.390027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.390049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.390069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.390090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.390110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.390129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.390145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.390173] [drm:intel_power_well_disable [i915]] disabling display
>[  931.390195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.390220] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.390237] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.390319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.390329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.390423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.390449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.390478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.390508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.390531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.390558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.390582] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.390606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.390628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.390652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.390672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.390679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.390700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.390706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.390728] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.390749] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.390772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.390798] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.390820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.390839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.390860] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.390878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.390898] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.390920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.390944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.391006] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.391029] [drm:intel_power_well_enable [i915]] enabling display
>[  931.391050] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.391086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.391107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.391128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.391148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.391168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.391188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.391212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.391235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.391257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.391276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.391296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.391318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.391341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.393367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.393384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.393398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.393413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.394931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.394950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.394967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.396472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.396489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.398307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.401239] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.401317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.401334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.401396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.401448] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.401475] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.418061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.418087] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.418124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.418233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.418275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.451417] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.451443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.451489] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.470355] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.470387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.470403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.470422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.470439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.470457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.470472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.470486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.470502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.470520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.470536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.470552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.470568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.470582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.470596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.470622] [drm:intel_power_well_disable [i915]] disabling display
>[  931.470643] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.470664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.470681] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.470758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.470767] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.470809] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.470825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.470843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.470872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.470894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.470911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.470927] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.470942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.470957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.470972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.470986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.470989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.471003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.471006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.471021] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.471034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.471048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.471061] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.471077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.471091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.471104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.471117] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.471131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.471147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.471164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.471209] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.471224] [drm:intel_power_well_enable [i915]] enabling display
>[  931.471239] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.471269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.471289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.471308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.471327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.471347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.471397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.471425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.471451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.471477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.471505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.471524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.471549] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.471570] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.473561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.473577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.473591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.473608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.475111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.475127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.475140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.476635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.476651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.478457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.481404] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.481466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.481483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.481505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.481554] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.481579] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.498209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.498235] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.498269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.498433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.498492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.531544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.531567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.531612] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.550447] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.550469] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.550485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.550505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.550522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.550539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.550555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.550570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.550586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.550604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.550620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.550636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.550652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.550666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.550680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.550706] [drm:intel_power_well_disable [i915]] disabling display
>[  931.550727] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.550748] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.550765] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.550843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.550852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.550894] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.550910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.550928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.550947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.550963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.550979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.550995] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.551011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.551026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.551040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.551054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.551058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.551071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.551075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.551089] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.551102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.551116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.551129] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.551145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.551166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.551179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.551191] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.551203] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.551218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.551234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.551275] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.551289] [drm:intel_power_well_enable [i915]] enabling display
>[  931.551301] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.551325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.551339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.551391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.551414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.551436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.551457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.551482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.551506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.551530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.551550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.551571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.551598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.551619] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.553612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.553628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.553642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.553656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.555160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.555175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.555189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.556683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.556699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.558502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.561442] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.561511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.561527] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.561549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.561597] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.561622] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.578252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.578278] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.578315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.578485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.578525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.611609] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.611635] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.611681] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.629142] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.629163] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.629179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.629198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.629214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.629232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.629247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.629261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.629277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.629294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.629310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.629326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.629341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.629355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.629410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.629452] [drm:intel_power_well_disable [i915]] disabling display
>[  931.629486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.629517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.629544] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.629663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.629678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.629747] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.629770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.629805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.629834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.629857] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.629889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.629910] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.629933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.629954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.629975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.629993] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.629999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.630018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.630023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.630044] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.630064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.630084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.630102] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.630125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.630144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.630164] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.630183] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.630203] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.630224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.630248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.630311] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.630334] [drm:intel_power_well_enable [i915]] enabling display
>[  931.630356] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.630410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.630432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.630454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.630475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.630496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.630518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.630542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.630566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.630591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.630611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.630632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.630658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.630679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.632667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.632683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.632697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.632712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.634214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.634229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.634243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.635737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.635753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.637558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.640490] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.640567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.640583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.640605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.640652] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.640678] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.657310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.657335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.657411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.657540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.657579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.690667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.690693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.690739] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.709595] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.709617] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.709632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.709651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.709668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.709686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.709701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.709715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.709734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.709756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.709777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.709797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.709818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.709836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.709853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.709881] [drm:intel_power_well_disable [i915]] disabling display
>[  931.709903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.709928] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.709945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.710026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.710035] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.710081] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.710101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.710121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.710143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.710162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.710182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.710201] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.710220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.710239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.710258] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.710277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.710281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.710300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.710303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.710323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.710342] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.710361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.710422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.710449] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.710476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.710500] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.710524] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.710546] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.710579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.710605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.710669] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.710692] [drm:intel_power_well_enable [i915]] enabling display
>[  931.710714] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.710750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.710775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.710797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.710818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.710837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.710859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.710882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.710906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.710928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.710947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.710968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.710990] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.711013] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.713022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.713039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.713054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.713069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.714576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.714592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.714605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.716097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.716114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.717921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.720853] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.720931] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.720948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.720971] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.721020] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.721046] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.737675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.737701] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.737735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.737842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.737882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.771032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.771057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.771100] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.789964] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.789988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.790007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.790029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.790048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.790069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.790089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.790108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.790127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.790148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.790169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.790190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.790210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.790229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.790247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.790275] [drm:intel_power_well_disable [i915]] disabling display
>[  931.790298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.790322] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.790340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.790485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.790500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.790570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.790595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.790622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.790651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.790674] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.790699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.790723] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.790747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.790770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.790792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.790813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.790819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.790841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.790847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.790869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.790890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.790913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.790934] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.790958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.790981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.791002] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.791024] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.791045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.791069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.791096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.791165] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.791196] [drm:intel_power_well_enable [i915]] enabling display
>[  931.791217] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.791254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.791274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.791296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.791315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.791335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.791356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.791399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.791424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.791449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.791469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.791490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.791516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.791538] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.793527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.793545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.793562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.793580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.795084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.795101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.795115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.796610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.796627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.798429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.801348] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.801424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.801448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.801480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.801610] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.801625] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.818121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.818147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.818184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.818286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.818328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.851488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.851513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.851548] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.870406] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.870428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.870451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.870476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.870493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.870511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.870526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.870541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.870556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.870574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.870590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.870606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.870622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.870636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.870649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.870676] [drm:intel_power_well_disable [i915]] disabling display
>[  931.870697] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.870718] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.870735] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.870806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.870814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.870856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.870872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.870890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.870916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.870931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.870945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.870960] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.870975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.870988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.871002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.871014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.871018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.871030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.871033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.871046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.871059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.871071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.871083] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.871098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.871111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.871127] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.871145] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.871162] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.871181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.871200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.871242] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.871256] [drm:intel_power_well_enable [i915]] enabling display
>[  931.871270] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.871297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.871315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.871332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.871350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.871368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.871422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.871451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.871477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.871502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.871523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.871545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.871571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.871593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.873586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.873603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.873617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.873632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.875135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.875150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.875164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.876660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.876676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.878481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.881416] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.881490] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.881507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.881529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.881568] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.881584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.898234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.898259] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.898294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.898458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.898518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.931590] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  931.931615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.931650] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  931.950509] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  931.950533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  931.950552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.950574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.950594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.950615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.950634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.950654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.950672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.950694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.950715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.950735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.950755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.950774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.950790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.950818] [drm:intel_power_well_disable [i915]] disabling display
>[  931.950840] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.950865] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.950883] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.950964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.950974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  931.951020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.951040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.951059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.951081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.951100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.951119] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.951139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  931.951158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  931.951177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.951196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.951215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.951219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.951237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.951241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.951260] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.951279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.951298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.951317] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  931.951336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.951354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.951373] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  931.951435] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  931.951461] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  931.951490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.951520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  931.951589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.951615] [drm:intel_power_well_enable [i915]] enabling display
>[  931.951639] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.951686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.951708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.951729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.951750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.951772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.951793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.951817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.951840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.951863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.951883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.951903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.951928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  931.951949] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.953949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.953966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.953980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.953995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.955510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.955527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.955542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.957035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.957051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.958874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.961259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  931.961327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.961344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  931.961366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.961452] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  931.961476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  931.978075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.978099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  931.978133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.978235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  931.978273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.011426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.011450] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.011495] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.029567] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.029589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.029605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.029624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.029641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.029659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.029674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.029689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.029705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.029723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.029739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.029755] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.029770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.029784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.029798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.029825] [drm:intel_power_well_disable [i915]] disabling display
>[  932.029847] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.029872] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.029890] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.029972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.029981] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.030025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.030042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.030060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.030079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.030094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.030111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.030127] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.030143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.030159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.030173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.030187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.030191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.030205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.030209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.030223] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.030237] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.030251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.030264] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.030280] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.030302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.030314] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.030327] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.030339] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.030354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.030370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.030462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.030484] [drm:intel_power_well_enable [i915]] enabling display
>[  932.030504] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.030542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.030739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.030757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.030775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.030793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.030811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.030831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.030850] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.030869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.030887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.030902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.030922] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.030939] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.033027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.033043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.033057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.033072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.034581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.034599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.034616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.036110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.036128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.037935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.040867] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.040944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.040961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.040983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.041032] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.041057] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.057689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.057714] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.057750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.057879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.057927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.091045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.091069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.091113] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.109970] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.109993] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.110013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.110035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.110054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.110076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.110096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.110115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.110134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.110156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.110177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.110197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.110217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.110236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.110253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.110280] [drm:intel_power_well_disable [i915]] disabling display
>[  932.110302] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.110327] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.110345] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.110464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.110479] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.110531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.110550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.110570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.110592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.110612] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.110632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.110652] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.110672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.110691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.110711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.110730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.110735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.110754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.110758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.110778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.110797] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.110817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.110836] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.110855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.110874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.110894] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.110913] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.110933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.110953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.110975] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.111026] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.111040] [drm:intel_power_well_enable [i915]] enabling display
>[  932.111053] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.111086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.111111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.111126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.111141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.111154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.111169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.111186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.111201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.111216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.111229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.111243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.111259] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.111274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.113250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.113266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.113281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.113296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.114801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.114818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.114835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.116331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.116349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.118157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.121090] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.121167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.121186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.121219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.121264] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.121289] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.137910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.137937] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.137974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.138096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.138146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.168463] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  932.171259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.171295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.171351] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.189956] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.189983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.190004] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.190028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.190049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.190071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.190091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.190110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.190130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.190152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.190173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.190193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.190214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.190233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.190249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.190279] [drm:intel_power_well_disable [i915]] disabling display
>[  932.190303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.190329] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.190348] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.190502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.190519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.190593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.190620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.190648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.190672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.190688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.190705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.190723] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.190739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.190762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.190776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.190789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.190793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.190806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.190809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.190827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.190845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.190863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.190881] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.190900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.190917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.190936] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.190954] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.190972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.190991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.191011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.191061] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.191076] [drm:intel_power_well_enable [i915]] enabling display
>[  932.191090] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.191119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.191137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.191155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.191172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.191190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.191208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.191228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.191247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.191266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.191284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.191299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.191319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.191336] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.193330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.193348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.193363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.193379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.194931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.194949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.194967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.196464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.196482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.198285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.201223] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.201296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.201312] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.201335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.201379] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.201436] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.218051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.218076] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.218111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.218224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.218264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.251443] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.251469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.251508] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.270359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.270381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.270444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.270475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.270504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.270532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.270557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.270581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.270607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.270635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.270662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.270687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.270713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.270736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.270759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.270802] [drm:intel_power_well_disable [i915]] disabling display
>[  932.270836] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.270868] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.270896] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.270994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.271003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.271049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.271069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.271088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.271111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.271130] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.271150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.271169] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.271188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.271207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.271226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.271245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.271249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.271268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.271271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.271291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.271309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.271328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.271347] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.271367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.271393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.271441] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.271467] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.271490] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.271516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.271543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.271611] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.271634] [drm:intel_power_well_enable [i915]] enabling display
>[  932.271657] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.271696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.271719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.271742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.271762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.271784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.271807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.271832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.271856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.271879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.271898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.271919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.271942] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.271965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.273974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.273993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.274010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.274029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.275543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.275560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.275574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.277065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.277083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.278909] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.281604] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.281666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.281683] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.281705] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.281746] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.281765] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.298435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.298461] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.298495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.298610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.298650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.331798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.331823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.331860] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.350083] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.350106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.350122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.350141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.350158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.350176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.350191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.350205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.350221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.350239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.350255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.350270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.350286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.350300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.350314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.350341] [drm:intel_power_well_disable [i915]] disabling display
>[  932.350362] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.350386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.350449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.350565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.350579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.350648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.350674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.350702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.350732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.350757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.350783] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.350809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.350835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.350860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.350884] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.350907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.350913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.350935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.350941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.350965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.350995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.351016] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.351038] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.351060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.351081] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.351103] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.351125] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.351146] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.351170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.351195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.351261] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.351284] [drm:intel_power_well_enable [i915]] enabling display
>[  932.351306] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.351344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.351366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.351389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.351429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.351451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.351474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.351498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.351523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.351547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.351570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.351592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.351618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.351642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.353630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.353648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.353665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.353683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.355203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.355221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.355239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.356738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.356756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.358564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.361497] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.361573] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.361590] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.361612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.361661] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.361687] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.378316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.378342] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.378376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.378538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.378592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.411673] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.411698] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.411743] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.430600] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.430624] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.430644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.430665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.430685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.430707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.430726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.430745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.430764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.430786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.430806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.430827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.430847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.430866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.430882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.430910] [drm:intel_power_well_disable [i915]] disabling display
>[  932.430933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.430957] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.430975] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.431057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.431066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.431113] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.431132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.431152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.431174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.431193] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.431213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.431232] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.431251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.431270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.431289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.431308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.431312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.431331] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.431334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.431354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.431381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.431407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.431464] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.431490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.431517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.431540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.431564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.431587] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.431614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.431642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.431713] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.431738] [drm:intel_power_well_enable [i915]] enabling display
>[  932.431769] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.431805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.431827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.431849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.431868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.431889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.431910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.431933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.431957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.431980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.431999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.432019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.432044] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.432065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.434064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.434082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.434098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.434117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.435628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.435644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.435658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.437154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.437170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.438981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.441924] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.441989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.442005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.442026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.442063] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.442079] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.458736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.458761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.458795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.458921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.458969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.492083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.492106] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.492151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.511019] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.511041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.511058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.511077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.511094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.511112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.511127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.511142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.511158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.511176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.511193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.511208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.511224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.511243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.511261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.511288] [drm:intel_power_well_disable [i915]] disabling display
>[  932.511311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.511335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.511353] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.511481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.511495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.511567] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.511592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.511619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.511648] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.511671] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.511697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.511721] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.511745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.511768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.511790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.511811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.511817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.511839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.511845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.511868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.511888] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.511911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.511931] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.511956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.511977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.511999] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.512020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.512042] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.512065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.512091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.512160] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.512185] [drm:intel_power_well_enable [i915]] enabling display
>[  932.512208] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.512247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.512270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.512300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.512319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.512340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.512360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.512384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.512407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.512449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.512470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.512490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.512516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.512537] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.514530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.514547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.514564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.514582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.516087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.516103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.516117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.517613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.517628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.519447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.522379] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.522501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.522525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.522559] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.522691] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.522707] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.539200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.539226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.539261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.539385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.539479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.572557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.572581] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.572617] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.591496] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.591519] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.591535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.591554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.591571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.591589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.591604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.591619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.591635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.591653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.591669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.591685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.591701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.591715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.591729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.591756] [drm:intel_power_well_disable [i915]] disabling display
>[  932.591778] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.591802] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.591821] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.591896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.591913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.591953] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.591968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.591984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.592002] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.592015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.592031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.592046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.592060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.592073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.592087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.592099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.592103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.592115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.592119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.592132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.592145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.592157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.592170] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.592185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.592197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.592210] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.592222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.592235] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.592250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.592266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.592308] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.592322] [drm:intel_power_well_enable [i915]] enabling display
>[  932.592334] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.592358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.592376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.592394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.592411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.592478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.592500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.592526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.592551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.592576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.592596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.592617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.592643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.592665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.594657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.594674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.594688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.594703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.596207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.596222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.596236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.597732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.597748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.599551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.602490] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.602560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.602577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.602599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.602638] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.602654] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.619306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.619331] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.619369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.619533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.619591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.652662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.652686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.652722] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.671581] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.671603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.671619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.671639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.671655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.671676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.671696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.671715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.671734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.671755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.671776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.671797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.671817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.671836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.671852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.671880] [drm:intel_power_well_disable [i915]] disabling display
>[  932.671903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.671927] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.671945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.672026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.672037] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.672083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.672103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.672122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.672144] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.672163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.672183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.672202] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.672221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.672240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.672259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.672278] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.672282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.672301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.672304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.672324] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.672343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.672362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.672381] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.672400] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.672418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.672480] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.672506] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.672533] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.672562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.672591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.672662] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.672694] [drm:intel_power_well_enable [i915]] enabling display
>[  932.672716] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.672754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.672775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.672797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.672818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.672839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.672861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.672885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.672908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.672931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.672951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.672971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.672996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.673017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.675013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.675029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.675043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.675058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.676565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.676581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.676595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.678086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.678102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.679918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.682850] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.682926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.682941] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.682962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.682996] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.683013] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.699671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.699696] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.699731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.699854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.699903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.733027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.733051] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.733087] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.751935] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.751957] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.751973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.751993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.752009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.752027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.752043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.752058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.752074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.752092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.752108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.752125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.752140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.752154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.752168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.752194] [drm:intel_power_well_disable [i915]] disabling display
>[  932.752216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.752237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.752253] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.752339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.752347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.752388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.752404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.752421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.752484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.752507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.752533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.752557] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.752581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.752604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.752627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.752648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.752655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.752677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.752683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.753237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.753259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.753281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.753302] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.753326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.753347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.753369] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.753389] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.753417] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.753468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.753493] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.753550] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.753572] [drm:intel_power_well_enable [i915]] enabling display
>[  932.753592] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.753629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.753651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.753672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.753693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.753712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.753733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.753757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.753780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.753803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.753822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.753842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.753864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.753886] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.755896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.755913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.755927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.755942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.757452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.757468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.757482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.758985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.759001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.760873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.763805] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.763881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.763898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.763920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.763958] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.763974] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.780625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.780651] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.780687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.780815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.780865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.813983] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.814007] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.814043] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.832193] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.832215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.832231] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.832251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.832267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.832285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.832300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.832315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.832331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.832349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.832365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.832381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.832397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.832416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.832472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.832514] [drm:intel_power_well_disable [i915]] disabling display
>[  932.832549] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.832735] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.832763] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.832887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.832897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.832942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.832962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.832982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.833004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.833023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.833049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.833065] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.833080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.833095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.833109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.833122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.833125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.833138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.833141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.833153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.833166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.833179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.833196] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.833213] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.833230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.833249] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.833266] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.833284] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.833302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.833321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.833363] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.833378] [drm:intel_power_well_enable [i915]] enabling display
>[  932.833391] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.833419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.833462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.833490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.833511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.833534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.833556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.833581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.833606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.833632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.833652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.833674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.833701] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.833723] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.835716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.835732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.835747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.835761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.837266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.837283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.837300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.838797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.838813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.840617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.843543] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.843576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.843601] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.843625] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.843663] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.843682] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.860321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.860356] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.860393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.860618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.860669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.893677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.893701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.893736] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.912598] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.912621] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.912637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.912657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.912673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.912691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.912706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.912730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.912752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.912770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.912786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.912803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.912818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.912833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.912847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.912873] [drm:intel_power_well_disable [i915]] disabling display
>[  932.912894] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.912915] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.912932] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.913009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.913018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.913060] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.913075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.913093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.913112] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.913127] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.913143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.913159] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.913174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.913189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.913204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.913222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.913226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.913245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.913248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.913268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.913287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.913306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.913325] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.913344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.913363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.913382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.913401] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.913420] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.913478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.913508] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.913577] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.913603] [drm:intel_power_well_enable [i915]] enabling display
>[  932.913627] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.913669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.913693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.913718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.913741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.914116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.914138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.914163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.914186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.914209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.914228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.914249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.914271] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.914294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.916287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.916304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.916318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.916332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.917838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.917853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.917867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.919374] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.919390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.921194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.924115] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  932.924152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.924169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  932.924191] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.924228] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  932.924245] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  932.940898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.940923] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.940958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.941082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.941131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.974253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  932.974279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.974317] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  932.992201] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  932.992223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  932.992239] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.992259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.992276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.992293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.992309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.992323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.992339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.992357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.992374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.992389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.992405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.992420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.992433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.992505] [drm:intel_power_well_disable [i915]] disabling display
>[  932.992540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.992737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  932.992764] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.992885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  932.992899] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  932.992963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.992981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.992999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.993018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.993033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.993050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.993067] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  932.993083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  932.993099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.993113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.993127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.993131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.993145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.993149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.993163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.993177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.993191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.993205] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  932.993221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.993235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.993249] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  932.993263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  932.993276] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  932.993292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.993310] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  932.993355] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.993370] [drm:intel_power_well_enable [i915]] enabling display
>[  932.993384] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.993410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.993426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.993469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.993502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.993522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.993545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.993570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.993594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.993619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.993639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.993661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.993686] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  932.993708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.996003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.996021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.996035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.996050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.997577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.997594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.997609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.999104] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.999121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.000944] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.003879] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.003953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.003972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.003998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.004039] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.004058] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.020698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.020723] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.020758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.020882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.020930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.054054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.054078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.054114] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.072970] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.072992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.073008] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.073028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.073044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.073062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.073077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.073092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.073108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.073125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.073142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.073157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.073173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.073187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.073200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.073227] [drm:intel_power_well_disable [i915]] disabling display
>[  933.073248] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.073268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.073285] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.073363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.073372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.073414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.073430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.073490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.073518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.073542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.073567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.073591] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.073614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.073637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.073659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.073680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.073687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.073708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.073715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.073737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.073758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.073780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.073801] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.073827] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.073849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.073871] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.073892] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.073914] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.073940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.073962] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.074008] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.074023] [drm:intel_power_well_enable [i915]] enabling display
>[  933.074037] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.074063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.074078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.074093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.074107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.074126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.074145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.074167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.074188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.074209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.074228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.074248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.074275] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.074292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.076262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.076279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.076294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.076309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.077814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.077829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.077843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.079335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.079350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.081154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.084076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.084111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.084128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.084149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.084188] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.084208] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.100858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.100884] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.100922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.101034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.101088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.134214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.134238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.134274] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.153140] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.153162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.153178] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.153197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.153214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.153232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.153247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.153261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.153277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.153295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.153311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.153326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.153341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.153355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.153369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.153396] [drm:intel_power_well_disable [i915]] disabling display
>[  933.153419] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.153444] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.153504] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.153615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.153630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.153701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.153727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.153755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.153784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.153807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.153833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.153867] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.153891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.153915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.153936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.153967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.153972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.153992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.153998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.154019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.154038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.154058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.154077] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.154100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.154119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.154140] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.154158] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.154178] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.154200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.154224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.154277] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.154298] [drm:intel_power_well_enable [i915]] enabling display
>[  933.154320] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.154355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.154375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.154396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.154415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.154436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.154473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.154499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.154523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.154547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.154566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.154588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.154612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.154635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.156628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.156646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.156660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.156676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.158180] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.158196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.158210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.159705] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.159723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.161527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.164454] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.164538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.164558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.164584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.164624] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.164643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.181279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.181305] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.181339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.181491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.181551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.214636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.214660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.214695] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.233560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.233582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.233601] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.233622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.233642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.233663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.233682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.233701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.233720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.233742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.233762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.233783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.233803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.233822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.233838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.233866] [drm:intel_power_well_disable [i915]] disabling display
>[  933.233888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.233912] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.233930] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.234012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.234021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.234067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.234087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.234107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.234129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.234148] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.234168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.234187] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.234206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.234225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.234244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.234263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.234267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.234286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.234289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.234309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.234328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.234347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.234366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.234385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.234404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.234423] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.234442] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.234510] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.234538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.234567] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.234641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.234665] [drm:intel_power_well_enable [i915]] enabling display
>[  933.234687] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.234725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.234747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.234769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.234791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.234814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.234837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.234863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.234887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.234911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.234932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.234953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.234978] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.235001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.237001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.237017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.237032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.237050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.238641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.238660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.238677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.240173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.240191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.241997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.244919] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.244954] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.244971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.244993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.245031] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.245049] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.261701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.261727] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.261764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.261892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.261941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.295056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.295080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.295116] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.312231] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.312254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.312270] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.312289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.312306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.312323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.312338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.312357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.312376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.312398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.312419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.312439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.312460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.312516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.312544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.312586] [drm:intel_power_well_disable [i915]] disabling display
>[  933.312818] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.312853] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.312880] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.312999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.313009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.313053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.313070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.313089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.313109] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.313124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.313141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.313158] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.313174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.313190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.313212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.313225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.313228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.313241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.313244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.313257] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.313269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.313282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.313294] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.313311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.313329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.313346] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.313364] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.313381] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.313399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.313418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.313484] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.313511] [drm:intel_power_well_enable [i915]] enabling display
>[  933.313534] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.313572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.313595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.313619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.313640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.313662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.313684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.313709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.313734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.313759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.313780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.313802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.313825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.314107] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.316095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.316112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.316125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.316140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.317646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.317664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.317681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.319175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.319192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.320997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.323925] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.323954] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.323971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.323993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.324031] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.324048] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.340699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.340725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.340760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.340887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.340935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.374056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.374080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.374116] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.392225] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.392246] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.392263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.392282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.392298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.392316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.392331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.392345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.392361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.392379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.392395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.392410] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.392426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.392440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.392453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.392525] [drm:intel_power_well_disable [i915]] disabling display
>[  933.392559] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.392772] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.392800] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.392908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.392930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.392987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.393003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.393019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.393037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.393052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.393067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.393083] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.393097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.393111] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.393125] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.393138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.393141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.393154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.393157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.393170] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.393183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.393196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.393212] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.393230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.393248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.393265] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.393283] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.393300] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.393318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.393338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.393380] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.393395] [drm:intel_power_well_enable [i915]] enabling display
>[  933.393409] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.393436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.393454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.393498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.393524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.393545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.393569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.393595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.393619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.393643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.393664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.393685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.393711] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.393733] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.395728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.395745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.395760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.395779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.397283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.397299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.397312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.398808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.398824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.400627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.403561] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.403637] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.403656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.403682] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.403723] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.403743] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.420380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.420406] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.420443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.420698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.420747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.453737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.453761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.453797] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.472659] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.472681] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.472698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.472717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.472734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.472752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.472768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.472783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.472799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.472817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.472833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.472849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.472865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.472879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.472893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.472919] [drm:intel_power_well_disable [i915]] disabling display
>[  933.472940] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.472961] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.472979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.473061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.473070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.473116] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.473136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.473156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.473178] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.473197] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.473217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.473236] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.473255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.473275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.473294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.473312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.473316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.473335] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.473338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.473358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.473377] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.473396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.473415] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.473434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.473452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.473471] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.473538] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.473562] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.473589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.473615] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.473680] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.473703] [drm:intel_power_well_enable [i915]] enabling display
>[  933.473726] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.473763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.474062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.474084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.474105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.474126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.474148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.474173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.474196] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.474220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.474239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.474259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.474282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.474304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.476297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.476313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.476329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.476347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.477856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.477874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.477891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.479409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.479426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.481232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.484152] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.484191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.484210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.484236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.484277] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.484297] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.500936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.500962] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.500996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.501128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.501174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.534292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.534317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.534352] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.552234] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.552257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.552276] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.552298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.552317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.552339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.552358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.552378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.552397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.552418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.552439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.552459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.552523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.552549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.552574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.552616] [drm:intel_power_well_disable [i915]] disabling display
>[  933.552841] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.552875] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.552903] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.553000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.553009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.553053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.553070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.553088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.553108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.553124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.553147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.553162] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.553176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.553190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.553204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.553220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.553224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.553241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.553245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.553262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.553280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.553297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.553315] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.553332] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.553350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.553367] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.553384] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.553402] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.553420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.553439] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.553512] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.553533] [drm:intel_power_well_enable [i915]] enabling display
>[  933.553553] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.553591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.553613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.553635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.553655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.553676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.553697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.553720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.553744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.553767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.553788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.553807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.553832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.553853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.555843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.555859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.555874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.555889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.557417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.557434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.557452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.558984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.559001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.560836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.563775] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.563845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.563861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.563884] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.563923] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.563942] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.580599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.580626] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.580663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.580791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.580840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.613946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.613971] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.614009] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.632079] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.632104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.632124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.632148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.632168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.632190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.632210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.632229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.632249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.632271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.632292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.632313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.632334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.632353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.632372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.632402] [drm:intel_power_well_disable [i915]] disabling display
>[  933.632425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.632451] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.632469] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.632818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.632833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.632912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.632936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.632961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.632988] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.633009] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.633033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.633055] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.633078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.633099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.633120] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.633139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.633145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.633164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.633169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.633191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.633210] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.633230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.633249] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.633272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.633291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.633311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.633331] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.633351] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.633374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.633399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.633466] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.633512] [drm:intel_power_well_enable [i915]] enabling display
>[  933.633536] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.633575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.633599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.633620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.633643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.633663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.633686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.633711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.633735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.633759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.633779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.633800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.633824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.634084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.636082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.636100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.636115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.636130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.638734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.638753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.638768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.640264] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.640281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.642087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.645007] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.645044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.645061] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.645083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.645126] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.645143] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.661792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.661817] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.661852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.661970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.662024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.695146] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.695171] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.695208] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.713241] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.713263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.713279] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.713299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.713316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.713333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.713349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.713364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.713380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.713398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.713414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.713430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.713446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.713460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.713474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.713547] [drm:intel_power_well_disable [i915]] disabling display
>[  933.713581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.713804] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.713830] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.713940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.713949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.713990] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.714006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.714023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.714041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.714055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.714070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.714086] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.714100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.714115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.714128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.714141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.714145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.714158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.714161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.714174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.714187] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.714204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.714222] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.714239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.714257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.714274] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.714292] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.714309] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.714327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.714346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.714389] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.714403] [drm:intel_power_well_enable [i915]] enabling display
>[  933.714417] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.714445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.714463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.714480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.714525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.714549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.714572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.714598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.714623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.714647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.714667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.714689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.714716] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.714738] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.716728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.716744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.716759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.716773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.718276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.718291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.718304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.719800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.719816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.721621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.724564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.724630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.724647] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.724670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.724710] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.724730] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.741375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.741401] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.741435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.741676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.741721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.774731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.774755] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.774792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.793657] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.793679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.793695] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.793715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.793731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.793749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.793764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.793779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.793795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.793813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.793830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.793845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.793861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.793875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.793889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.793916] [drm:intel_power_well_disable [i915]] disabling display
>[  933.793937] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.793958] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.793975] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.794056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.794065] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.794108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.794124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.794141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.794164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.794183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.794203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.794222] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.794241] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.794261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.794280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.794299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.794303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.794322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.794325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.794345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.794364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.794383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.794402] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.794421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.794439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.794458] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.794485] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.794539] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.794565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.794592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.794655] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.794679] [drm:intel_power_well_enable [i915]] enabling display
>[  933.794702] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.794739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.795040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.795061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.795083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.795104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.795126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.795151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.795174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.795197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.795217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.795237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.795260] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.795283] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.797276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.797293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.797307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.797322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.798829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.798844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.798857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.800350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.800366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.802171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.805091] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.805128] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.805144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.805166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.805205] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.805222] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.821874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.821899] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.821935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.822063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.822111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.855230] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.855254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.855290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.874135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.874157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.874174] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.874193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.874210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.874228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.874244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.874259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.874275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.874293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.874310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.874326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.874342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.874356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.874370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.874396] [drm:intel_power_well_disable [i915]] disabling display
>[  933.874417] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.874438] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.874455] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.874743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.874758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.874828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.874852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.874879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.874908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.874930] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.874955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.874979] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.875003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.875026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.875049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.875069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.875075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.875097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.875102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.875125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.875154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.875174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.875193] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.875216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.875235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.875255] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.875274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.875294] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.875316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.875340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.875402] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.875425] [drm:intel_power_well_enable [i915]] enabling display
>[  933.875446] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.875482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.875525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.875548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.875571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.875591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.875615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.875641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.875665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.875689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.875711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.875731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.875756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.875777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.878058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.878074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.878088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.878102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.879631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.879648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.879663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.881157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.881173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.882995] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.885951] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.886004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.886021] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.886043] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.886081] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.886101] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.902745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.902769] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.902802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.902924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.902976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.936106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  933.936131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.936167] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  933.955025] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  933.955047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  933.955063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.955082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.955099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.955117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.955132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.955147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.955163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.955181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.955197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.955223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.955244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.955263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.955280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.955308] [drm:intel_power_well_disable [i915]] disabling display
>[  933.955331] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.955355] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.955373] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.955457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.955467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.955559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.955585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.955614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.955644] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.955668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.955696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.955721] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  933.955746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  933.955769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.955794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.955816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.955823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.955844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.956087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.956110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.956131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.956153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.956172] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  933.956196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.956215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.956237] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  933.956257] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  933.956277] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  933.956299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.956323] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  933.956386] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.956409] [drm:intel_power_well_enable [i915]] enabling display
>[  933.956430] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.956466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.956487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.956526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.956547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.956569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.956590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.956615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.956639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.956664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.956684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.956706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.956730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  933.956753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.958932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.958948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.958963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.958978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.960551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.960566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.960580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.962083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.962101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.963914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.966864] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  933.966924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.966940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  933.966962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.967012] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  933.967038] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  933.983676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.983702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  933.983736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.983839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.983878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.017057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.017081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.017127] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.036002] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.036023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.036040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.036059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.036076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.036094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.036109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.036123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.036139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.036157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.036173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.036189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.036204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.036219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.036232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.036259] [drm:intel_power_well_disable [i915]] disabling display
>[  934.036280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.036301] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.036318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.036397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.036406] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.036448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.036464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.036482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.036501] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.036556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.036583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.036609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.036633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.036658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.036680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.036710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.036716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.036737] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.036745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.036767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.036787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.036808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.036828] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.036852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.036871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.036892] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.036912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.036933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.036958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.036984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.037326] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.037349] [drm:intel_power_well_enable [i915]] enabling display
>[  934.037371] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.037408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.037430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.037452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.037472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.037493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.037532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.037557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.037582] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.037606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.037770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.037791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.037817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.037838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.039827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.039843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.039857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.039872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.041374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.041392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.041409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.042906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.042923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.044727] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.047660] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.047737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.047756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.047782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.047822] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.047841] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.064479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.064505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.064591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.064725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.064764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.097835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.097860] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.097896] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.116744] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.116766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.116782] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.116802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.116819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.116837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.116852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.116871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.116890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.116912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.116933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.116953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.116974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.116993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.117010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.117038] [drm:intel_power_well_disable [i915]] disabling display
>[  934.117061] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.117085] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.117103] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.117189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.117198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.117244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.117264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.117284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.117306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.117325] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.117344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.117364] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.117383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.117402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.117429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.117446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.117449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.117465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.117468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.117482] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.117496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.117550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.117571] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.117597] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.117617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.117639] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.117660] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.117681] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.117707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.117733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.117798] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.117822] [drm:intel_power_well_enable [i915]] enabling display
>[  934.117842] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.117880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.117901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.117923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.117942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.117963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.117983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.118006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.118029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.118052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.118071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.118091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.118113] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.118135] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.120136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.120154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.120171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.120190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.121706] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.121723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.121738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.123231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.123247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.125054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.127987] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.128064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.128083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.128109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.128150] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.128170] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.144806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.144832] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.144869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.144976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.145018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.178163] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.178187] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.178223] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.196080] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.196103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.196123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.196145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.196164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.196186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.196205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.196224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.196243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.196265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.196286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.196306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.196326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.196345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.196361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.196389] [drm:intel_power_well_disable [i915]] disabling display
>[  934.196411] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.196436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.196454] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.196586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.196602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.196655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.196674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.196693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.196713] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.196729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.196747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.196764] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.196780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.196796] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.196811] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.196829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.196834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.196853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.196857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.196877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.196896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.196914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.196933] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.196953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.196973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.196992] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.197012] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.197031] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.197051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.197072] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.197124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.197138] [drm:intel_power_well_enable [i915]] enabling display
>[  934.197151] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.197179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.197195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.197209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.197223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.197237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.197251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.197267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.197282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.197297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.197310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.197323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.197340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.197354] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.199328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.199344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.199358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.199373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.200886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.200901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.200914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.202405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.202421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.204226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.207158] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.207235] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.207251] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.207281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.207318] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.207334] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.223980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.224007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.224044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.224157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.224199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.257336] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.257360] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.257397] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.276247] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.276269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.276285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.276305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.276322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.276340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.276355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.276370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.276386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.276404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.276420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.276436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.276452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.276466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.276480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.276506] [drm:intel_power_well_disable [i915]] disabling display
>[  934.276576] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.276609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.276636] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.276729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.276739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.276782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.276799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.276818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.276837] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.276852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.276869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.276894] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.276908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.276922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.276936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.276949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.276953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.276966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.276969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.276982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.276995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.277008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.277020] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.277035] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.277048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.277060] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.277073] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.277085] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.277100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.277117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.277159] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.277174] [drm:intel_power_well_enable [i915]] enabling display
>[  934.277186] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.277211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.277225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.277238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.277251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.277267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.277289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.277309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.277324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.277338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.277351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.277364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.277380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.277394] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.279367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.279384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.279398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.279412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.280918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.280933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.280946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.282460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.282476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.285348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.288281] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.288358] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.288378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.288403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.288445] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.288464] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.305101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.305126] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.305160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.305270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.305310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.338456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.338481] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.338517] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.357398] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.357420] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.357436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.357456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.357472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.357490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.357505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.357520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.357579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.357609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.357721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.357738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.357754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.357768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.357782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.357808] [drm:intel_power_well_disable [i915]] disabling display
>[  934.357830] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.357852] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.357869] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.357949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.357958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.358001] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.358018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.358036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.358056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.358072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.358088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.358106] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.358121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.358138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.358152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.358167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.358171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.358185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.358189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.358204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.358218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.358233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.358246] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.358266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.358285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.358305] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.358324] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.358345] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.358365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.358387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.358433] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.358450] [drm:intel_power_well_enable [i915]] enabling display
>[  934.358465] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.358495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.358515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.358558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.358584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.358636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.358660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.358686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.358719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.358742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.358761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.358781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.358805] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.358826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.360823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.360839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.360853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.360868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.362371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.362386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.362400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.363896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.363912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.365717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.368651] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.368727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.368744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.368767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.368807] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.368823] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.385469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.385494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.385567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.385731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.385770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.418828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.418852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.418889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.437745] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.437767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.437784] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.437803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.437823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.437845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.437864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.437883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.437903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.437924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.437945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.437966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.437986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.438005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.438021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.438049] [drm:intel_power_well_disable [i915]] disabling display
>[  934.438071] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.438095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.438113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.438190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.438199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.438246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.438266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.438285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.438308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.438326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.438346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.438365] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.438384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.438420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.438441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.438456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.438459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.438473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.438476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.438490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.438503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.438516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.438568] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.438593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.438613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.438635] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.438656] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.438677] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.438702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.438728] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.438794] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.438817] [drm:intel_power_well_enable [i915]] enabling display
>[  934.438839] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.438875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.438898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.438918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.438939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.438958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.438980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.439004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.439027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.439050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.439069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.439089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.439113] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.439134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.441144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.441161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.441176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.441191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.442699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.442715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.442729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.444222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.444238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.446043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.448991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.449053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.449070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.449092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.449131] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.449148] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.465797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.465822] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.465856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.465966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.466007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.499127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.499150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.499185] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.518034] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.518056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.518073] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.518092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.518108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.518126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.518141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.518156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.518171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.518189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.518205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.518221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.518236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.518251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.518265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.518292] [drm:intel_power_well_disable [i915]] disabling display
>[  934.518313] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.518334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.518351] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.518431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.518440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.518483] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.518498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.518516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.518575] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.518601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.518628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.518652] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.518677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.518700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.518724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.518745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.518753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.518775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.518781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.518805] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.518827] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.518851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.518872] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.518898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.518920] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.518943] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.518965] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.518987] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.519014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.519048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.519112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.519135] [drm:intel_power_well_enable [i915]] enabling display
>[  934.519156] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.519192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.519213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.519234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.519254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.519274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.519295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.519318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.519341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.519364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.519383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.519403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.519426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.519448] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.521439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.521455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.521469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.521484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.522989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.523004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.523018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.524513] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.524529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.526359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.530371] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.530430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.530447] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.530469] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.530508] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.530527] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.547186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.547211] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.547245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.547355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.547395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.580531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.580574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.580624] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.599425] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.599447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.599464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.599483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.599500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.599518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.599538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.599598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.599623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.599653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.599680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.599706] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.599731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.599752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.599774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.599817] [drm:intel_power_well_disable [i915]] disabling display
>[  934.599850] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.599882] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.599909] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.600036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.600051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.600119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.600142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.600168] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.600197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.600220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.600245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.600268] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.600292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.600315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.600338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.600359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.600364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.600386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.600391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.600414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.600435] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.600457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.600478] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.600503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.600523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.600568] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.600594] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.600615] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.600642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.600676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.600740] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.600763] [drm:intel_power_well_enable [i915]] enabling display
>[  934.600786] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.600822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.600843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.600864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.600884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.600904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.600925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.600948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.600971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.600994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.601013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.601034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.601056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.601078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.603094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.603110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.603123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.603138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.604656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.604671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.604688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.606181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.606198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.608002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.610934] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.610961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.610981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.611007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.611048] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.611067] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.627707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.627732] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.627767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.627880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.627919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.661057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.661082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.661119] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.679978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.680000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.680016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.680036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.680052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.680073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.680093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.680112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.680132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.680153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.680174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.680195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.680215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.680234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.680250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.680278] [drm:intel_power_well_disable [i915]] disabling display
>[  934.680300] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.680324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.680342] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.680417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.680426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.680473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.680492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.680512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.680534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.680592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.680622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.680649] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.680674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.680699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.680722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.680745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.680752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.680775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.680782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.680807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.680829] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.680852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.680873] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.680900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.680922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.680945] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.680967] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.680990] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.681017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.681045] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.681116] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.681140] [drm:intel_power_well_enable [i915]] enabling display
>[  934.681163] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.681202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.681224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.681248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.681276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.681296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.681316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.681339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.681362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.681385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.681405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.681425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.681448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.681470] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.683460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.683476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.683490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.683504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.685008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.685023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.685036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.686528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.686552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.688353] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.691307] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.691363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.691383] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.691409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.691456] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.691471] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.708096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.708119] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.708151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.708257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.708295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.741450] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.741471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.741505] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.760338] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.760360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.760376] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.760396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.760413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.760431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.760446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.760461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.760476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.760494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.760510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.760526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.760541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.760599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.760623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.760666] [drm:intel_power_well_disable [i915]] disabling display
>[  934.760701] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.760734] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.760762] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.760888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.760903] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.760972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.761005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.761031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.761058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.761081] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.761105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.761129] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.761152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.761175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.761197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.761218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.761224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.761245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.761251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.761273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.761294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.761315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.761337] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.761360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.761381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.761401] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.761422] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.761443] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.761466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.761492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.761572] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.761596] [drm:intel_power_well_enable [i915]] enabling display
>[  934.761617] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.761655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.761679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.761702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.761725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.761747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.761771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.761797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.761822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.761846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.761868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.761890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.761915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.761938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.763926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.763943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.763961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.763979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.765495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.765511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.765526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.767051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.767067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.768900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.771846] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.771910] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.771927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.771948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.771990] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.772010] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.788656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.788681] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.788715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.788825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.788865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.822010] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.822035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.822070] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.840929] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.840951] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.840967] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.840986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.841003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.841021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.841036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.841051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.841067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.841085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.841101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.841117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.841133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.841147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.841161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.841187] [drm:intel_power_well_disable [i915]] disabling display
>[  934.841208] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.841229] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.841246] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.841327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.841337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.841380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.841396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.841413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.841433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.841448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.841465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.841481] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.841497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.841512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.841526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.841539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.841615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.841638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.841645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.841670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.841694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.841718] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.841742] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.841769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.841800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.841823] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.841844] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.841866] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.841891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.841916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.841981] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.842004] [drm:intel_power_well_enable [i915]] enabling display
>[  934.842025] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.842062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.842084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.842106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.842127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.842149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.842172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.842196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.842220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.842244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.842265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.842286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.842311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.842334] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.844328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.844344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.844358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.844372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.845879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.845894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.845907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.847398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.847414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.849218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.852137] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.852177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.852196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.852222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.852263] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.852282] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.868921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.868947] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.868981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.869090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.869131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.902278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.902304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.902341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  934.921204] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  934.921225] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  934.921241] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.921261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.921277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.921294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.921309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.921324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.921339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.921357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.921377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.921397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.921418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.921437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.921454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.921481] [drm:intel_power_well_disable [i915]] disabling display
>[  934.921504] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.921528] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.921546] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.921695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.921709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  934.921779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.921807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.921834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.921864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.921888] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.921915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.921941] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  934.921967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  934.921992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.922016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.922039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.922045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.922068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.922074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.922097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.922120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.922143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.922166] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  934.922193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.922216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.922240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  934.922263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  934.922286] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  934.922313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.922340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  934.922410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.922436] [drm:intel_power_well_enable [i915]] enabling display
>[  934.922467] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.922504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.922527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.922550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.922590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.922613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.922635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.922660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.922685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.922709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.922731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.922754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.922780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  934.922803] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.924792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.924808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.924822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.924836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.926339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.926354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.926367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.927863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.927880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.929708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.932858] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  934.932930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.932952] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  934.932974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.933027] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  934.933051] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  934.949678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.949705] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  934.949741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.949863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  934.949903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.983027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  934.983062] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.983117] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.001057] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.001080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.001096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.001116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.001131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.001148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.001166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.001184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.001201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.001222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.001241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.001259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.001278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.001295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.001310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.001339] [drm:intel_power_well_disable [i915]] disabling display
>[  935.001360] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.001384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.001401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.001497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.001506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.001552] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.001605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.001630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.001656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.001677] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.001701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.001723] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.001744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.001765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.001785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.001804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.001810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.001829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.001835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.001855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.001875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.001894] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.001913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.001936] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.001956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.001977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.001997] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.002016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.002040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.002065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.002123] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.002147] [drm:intel_power_well_enable [i915]] enabling display
>[  935.002169] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.002207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.002230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.002252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.002274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.002293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.002315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.002338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.002361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.002384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.002404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.002424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.002448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.002468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.004569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.004620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.004644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.004668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.006239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.006256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.006271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.007766] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.007785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.009613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.012447] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.012523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.012539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.012566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.012659] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.012683] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.029270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.029297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.029333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.029466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.029518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.062656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.062684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.062728] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.080130] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.080164] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.080190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.080221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.080248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.080276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.080300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.080324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.080349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.080377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.080403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.080429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.080453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.080476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.080499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.080553] [drm:intel_power_well_disable [i915]] disabling display
>[  935.080636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.080669] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.080696] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.080826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.080841] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.080907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.080931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.080954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.080981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.081002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.081023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.081047] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.081067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.081089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.081109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.081129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.081135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.081155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.081160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.081181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.081200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.081220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.081239] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.081262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.081281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.081301] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.081320] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.081340] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.081361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.081386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.081444] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.081466] [drm:intel_power_well_enable [i915]] enabling display
>[  935.081488] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.081524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.081545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.081566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.081604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.081625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.081648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.081674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.081698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.081722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.081742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.081764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.081790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.081811] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.083814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.083832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.083846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.083862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.085370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.085387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.085401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.086903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.086920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.088736] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.091636] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.091694] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.091709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.091730] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.091781] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.091804] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.108440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.108476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.108526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.108736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.108794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.141803] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.141829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.141869] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.160374] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.160397] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.160414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.160434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.160451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.160469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.160484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.160499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.160516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.160533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.160550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.160565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.160627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.160655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.160680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.160725] [drm:intel_power_well_disable [i915]] disabling display
>[  935.160759] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.160793] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.160821] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.160948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.160964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.161036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.161062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.161089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.161119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.161143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.161169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.161195] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.161220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.161245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.161275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.161295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.161301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.161322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.161327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.161348] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.161369] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.161390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.161410] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.161433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.161452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.161473] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.161494] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.161513] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.161537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.161562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.161641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.161665] [drm:intel_power_well_enable [i915]] enabling display
>[  935.161687] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.161725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.161748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.161770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.161793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.161815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.161837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.161862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.161885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.161908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.161929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.161950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.161975] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.161998] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.163998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.164014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.164031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.164050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.165564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.165600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.165614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.169243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.169261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.171092] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.173704] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.173757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.173781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.173815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.173878] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.173901] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.190498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.190534] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.190614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.190765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.190823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.223850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.223884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.223939] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.241077] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.241100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.241115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.241135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.241150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.241166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.241180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.241193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.241208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.241224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.241239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.241254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.241268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.241281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.241293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.241320] [drm:intel_power_well_disable [i915]] disabling display
>[  935.241340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.241361] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.241377] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.241465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.241475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.241532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.241555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.241579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.241654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.241677] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.241701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.241726] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.241749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.241772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.241794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.241814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.241821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.241842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.241847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.241868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.241890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.241909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.241927] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.241945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.241963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.241981] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.241998] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.242016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.242035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.242055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.242094] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.242108] [drm:intel_power_well_enable [i915]] enabling display
>[  935.242122] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.242150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.242169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.242187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.242205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.242223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.242241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.242260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.242279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.242299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.242317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.242332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.242351] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.242368] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.244333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.244350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.244364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.244379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.245895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.245911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.245927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.247445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.247471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.249318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.251457] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.251519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.251535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.251556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.251752] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.251776] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.268277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.268304] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.268339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.268485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.268543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.301669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.301699] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.301743] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.320620] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.320644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.320661] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.320682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.320698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.320717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.320733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.320748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.320764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.320782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.320798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.320814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.320830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.320844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.320858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.320887] [drm:intel_power_well_disable [i915]] disabling display
>[  935.320909] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.320931] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.320948] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.321045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.321056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.321102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.321119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.321137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.321156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.321172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.321188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.321205] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.321221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.321236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.321250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.321264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.321269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.321282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.321286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.321300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.321318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.321337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.321356] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.321375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.321394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.321413] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.321433] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.321452] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.321472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.321499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.321537] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.321550] [drm:intel_power_well_enable [i915]] enabling display
>[  935.321563] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.321636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.321661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.321686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.321709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.321732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.321755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.321781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.321806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.321831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.321853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.321875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.321901] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.321925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.323931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.323949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.323967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.323985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.325492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.325509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.325523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.327023] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.327041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.328842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.331478] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.331549] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.331566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.331654] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.331715] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.331731] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.348298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.348333] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.348383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.348551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.348650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.381679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.381715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.381768] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.400110] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.400143] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.400169] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.400198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.400223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.400250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.400273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.400295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.400318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.400345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.400370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.400393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.400417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.400439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.400459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.400501] [drm:intel_power_well_disable [i915]] disabling display
>[  935.400535] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.400567] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.400639] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.400771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.400785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.400852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.400877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.400902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.400930] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.400953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.400978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.401003] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.401026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.401050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.401071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.401092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.401098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.401119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.401124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.401146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.401167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.401189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.401210] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.401234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.401255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.401276] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.401298] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.401319] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.401343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.401368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.401429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.401453] [drm:intel_power_well_enable [i915]] enabling display
>[  935.401475] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.401513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.401536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.401558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.401580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.401628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.401651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.401677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.401701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.401726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.401747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.401802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.401827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.401851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.403873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.403898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.403921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.403946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.405463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.405480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.405495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.407013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.407039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.408872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.411457] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.411529] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.411547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.411572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.411808] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.411832] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.428293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.428320] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.428356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.428469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.428510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.461630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.461658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.461707] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.480558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.480583] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.480643] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.480673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.480699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.480728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.480750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.480765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.480782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.480801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.480818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.480834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.480855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.480875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.480895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.480923] [drm:intel_power_well_disable [i915]] disabling display
>[  935.480946] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.480971] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.480989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.481072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.481082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.481129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.481149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.481175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.481203] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.481220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.481238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.481256] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.481275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.481295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.481314] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.481333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.481338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.481357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.481361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.481381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.481400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.481421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.481439] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.481459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.481479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.481499] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.481518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.481537] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.481564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.481582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.481656] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.481678] [drm:intel_power_well_enable [i915]] enabling display
>[  935.481698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.481736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.481757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.481779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.481799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.481819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.481840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.481864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.481888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.481911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.481932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.481952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.481978] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.482001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.483994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.484011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.484025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.484040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.485546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.485562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.485575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.487113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.487129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.488954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.491900] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.491963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.491980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.492002] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.492052] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.492078] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.508707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.508734] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.508770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.508881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.508923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.542063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.542087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.542131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.560973] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.560994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.561011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.561030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.561046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.561067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.561087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.561106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.561125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.561147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.561167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.561188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.561208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.561227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.561244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.561271] [drm:intel_power_well_disable [i915]] disabling display
>[  935.561294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.561318] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.561336] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.561416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.561426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.561472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.561491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.561511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.561533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.561552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.561572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.561591] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.561651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.561677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.561700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.561723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.561730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.561752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.561758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.561780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.561802] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.561824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.561845] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.561869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.561890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.561912] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.561933] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.561954] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.561980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.562005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.562281] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.562295] [drm:intel_power_well_enable [i915]] enabling display
>[  935.562308] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.562334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.562349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.562364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.562378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.562391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.562406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.562422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.562437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.562452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.562465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.562479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.562495] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.562510] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.564499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.564515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.564529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.564544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.566047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.566062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.566076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.567571] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.567588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.569429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.571924] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.571983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.572000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.572023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.572071] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.572097] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.588718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.588744] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.588780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.588889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.588930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.622082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.622108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.622153] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.639385] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.639406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.639422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.639442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.639458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.639476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.639491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.639506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.639524] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.639546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.639567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.639587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.639651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.639675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.639701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.639743] [drm:intel_power_well_disable [i915]] disabling display
>[  935.639776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.639809] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.639836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.639959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.639974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.640048] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.640070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.640094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.640121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.640151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.640174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.640197] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.640217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.640239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.640259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.640279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.640285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.640305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.640310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.640332] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.640351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.640372] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.640390] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.640413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.640432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.640453] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.640472] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.640492] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.640513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.640538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.640603] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.640645] [drm:intel_power_well_enable [i915]] enabling display
>[  935.640667] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.640703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.640725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.640748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.640768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.640790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.640811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.640836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.640860] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.640884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.640904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.640925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.640951] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.640973] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.642960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.642976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.642990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.643004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.644508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.644523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.644537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.646032] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.646048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.647850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.650782] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.650859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.650875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.650896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.650944] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.650970] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.667601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.667644] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.667678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.667778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.667819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.700958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.700982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.701026] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.718101] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.718123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.718139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.718158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.718175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.718192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.718208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.718223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.718239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.718257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.718273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.718289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.718305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.718319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.718333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.718359] [drm:intel_power_well_disable [i915]] disabling display
>[  935.718380] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.718401] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.718418] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.718490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.718499] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.718546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.718565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.718585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.718607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.718669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.718697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.718725] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.718749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.718780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.718801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.718823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.718829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.718850] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.718856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.718878] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.718898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.718919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.718939] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.718963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.718983] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.719005] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.719025] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.719047] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.719072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.719097] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.719161] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.719184] [drm:intel_power_well_enable [i915]] enabling display
>[  935.719205] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.719241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.719262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.719283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.719303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.719323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.719344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.719367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.719391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.719414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.719433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.719454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.719476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.719498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.721489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.721505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.721519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.721533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.723037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.723051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.723065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.724556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.724572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.726385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.729306] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.729343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.729359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.729381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.729429] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.729455] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.746084] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.746108] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.746141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.746248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.746286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.779444] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.779469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.779513] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.798389] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.798410] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.798426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.798446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.798462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.798483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.798503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.798522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.798541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.798563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.798583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.798604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.798697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.798721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.798745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.798786] [drm:intel_power_well_disable [i915]] disabling display
>[  935.798820] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.798852] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.798879] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.799001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.799016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.799085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.799109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.799135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.799164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.799186] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.799212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.799235] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.799260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.799283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.799305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.799326] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.799332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.799353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.799359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.799382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.799403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.799425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.799445] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.799477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.799496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.799516] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.799534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.799555] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.799578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.799603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.799688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.799712] [drm:intel_power_well_enable [i915]] enabling display
>[  935.799735] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.799772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.799792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.799814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.799835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.799857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.799877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.799901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.799925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.799948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.799967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.799987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.800011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.800032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.802023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.802039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.802053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.802067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.803574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.803590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.803604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.805146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.805164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.806987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.809921] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.809997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.810014] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.810037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.810085] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.810110] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.826741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.826766] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.826800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.826907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.826947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.860094] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.860118] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.860163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.879014] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.879038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.879058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.879080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.879100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.879121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.879140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.879160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.879179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.879201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.879221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.879242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.879262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.879281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.879298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.879325] [drm:intel_power_well_disable [i915]] disabling display
>[  935.879348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.879372] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.879391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.879473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.879482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.879528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.879548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.879568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.879590] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.879609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.879672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.879699] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.879726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.879749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.879774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.879795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.879803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.879825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.879831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.879856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.879877] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.879901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.879922] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.879949] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.879970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.879995] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.880016] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.880040] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.880067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.880095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.880166] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.880191] [drm:intel_power_well_enable [i915]] enabling display
>[  935.880215] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.880254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.880276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.880306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.880326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.880346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.880366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.880390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.880413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.880437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.880456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.880476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.880501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.880522] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.882529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.882546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.882561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.882576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.884091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.884107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.884122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.886695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.886715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.888521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.891456] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.891529] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.891545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.891566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.891614] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.891683] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.908276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.908302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.908337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.908461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.908502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.941656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  935.941682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.941729] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  935.960580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  935.960603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  935.960622] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.960687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.960712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.960742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.960764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.960787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.960810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.960837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.960863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.960888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.960913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.960934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.960956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.960999] [drm:intel_power_well_disable [i915]] disabling display
>[  935.961038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.961066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.961091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.961191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.961204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  935.961264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.961279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.961296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.961314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.961328] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.961343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.961358] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  935.961372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  935.961386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.961399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.961412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.961415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.961428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.961431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.961444] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.961457] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.961469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.961481] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  935.961496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.961508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.961521] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  935.961534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  935.961546] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  935.961566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.961590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  935.961672] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.961696] [drm:intel_power_well_enable [i915]] enabling display
>[  935.961718] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.961756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.961780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.961801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.961824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.961844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.961867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.961892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.961916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.961940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.961960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.961982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.962007] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  935.962029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.964015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.964031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.964045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.964060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.965565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.965581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.965595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.967091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.967107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.968910] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.971843] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  935.971920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.971937] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  935.971959] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.972008] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  935.972034] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  935.988660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.988684] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  935.988717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.988824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  935.988862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.022020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.022044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.022088] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.040939] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.040961] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.040977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.040996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.041013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.041034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.041053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.041072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.041091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.041113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.041134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.041154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.041175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.041193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.041209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.041236] [drm:intel_power_well_disable [i915]] disabling display
>[  936.041259] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.041283] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.041301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.041381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.041390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.041436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.041456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.041475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.041498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.041516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.041536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.041555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.041574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.041593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.041612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.041681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.041688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.041712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.041719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.041743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.041764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.041786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.041807] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.041831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.041851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.041874] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.041894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.041916] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.041941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.041967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.042031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.042053] [drm:intel_power_well_enable [i915]] enabling display
>[  936.042075] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.042112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.042133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.042154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.042174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.042195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.042218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.042242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.042266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.042289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.042309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.042330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.042356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.042378] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.044372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.044388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.044402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.044417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.045924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.045942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.045959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.047453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.047470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.049277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.052197] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.052234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.052251] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.052272] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.052320] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.052345] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.068980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.069005] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.069039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.069147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.069187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.102338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.102362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.102406] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.121270] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.121292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.121308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.121328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.121344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.121362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.121377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.121391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.121407] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.121425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.121442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.121457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.121473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.121487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.121500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.121527] [drm:intel_power_well_disable [i915]] disabling display
>[  936.121548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.121572] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.121590] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.121726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.121741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.121810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.121834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.121861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.121890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.121913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.121938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.121962] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.121986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.122008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.122032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.122053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.122059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.122080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.122086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.122109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.122130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.122153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.122173] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.122199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.122220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.122242] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.122263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.122285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.122308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.122334] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.122403] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.122427] [drm:intel_power_well_enable [i915]] enabling display
>[  936.122452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.122497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.122517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.122539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.122558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.122579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.122599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.122623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.122668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.122693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.122713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.122735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.122761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.122783] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.124773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.124789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.124803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.124818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.126321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.126337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.126351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.127847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.127865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.129670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.132602] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.132702] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.132727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.132760] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.132900] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.132924] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.149415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.149439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.149475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.149585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.149626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.182777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.182801] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.182845] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.201690] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.201712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.201729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.201748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.201765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.201783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.201798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.201813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.201829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.201847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.201863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.201879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.201895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.201909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.201922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.201949] [drm:intel_power_well_disable [i915]] disabling display
>[  936.201970] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.201990] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.202007] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.202077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.202086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.202128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.202144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.202162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.202188] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.202203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.202218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.202233] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.202247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.202261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.202277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.202295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.202298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.202315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.202319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.202337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.202354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.202371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.202388] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.202406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.202423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.202440] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.202458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.202475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.202493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.202512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.202554] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.202569] [drm:intel_power_well_enable [i915]] enabling display
>[  936.202582] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.202609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.202627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.202681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.202706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.202729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.202751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.202777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.202802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.202828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.202848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.202870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.202896] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.202918] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.204913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.204929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.204944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.204959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.206462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.206477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.206490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.207984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.208000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.209805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.212738] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.212815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.212831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.212854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.212902] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.212927] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.229559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.229585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.229622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.229782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.229834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.262915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.262939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.262983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.281846] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.281868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.281884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.281904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.281921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.281938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.281954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.281969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.281985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.282002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.282022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.282043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.282064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.282083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.282100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.282127] [drm:intel_power_well_disable [i915]] disabling display
>[  936.282149] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.282173] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.282191] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.282272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.282281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.282327] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.282347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.282367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.282389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.282408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.282428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.282447] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.282466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.282485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.282504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.282523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.282527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.282545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.282549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.282568] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.282587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.282606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.282625] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.282684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.282709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.282734] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.282757] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.282786] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.282810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.282833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.282898] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.283102] [drm:intel_power_well_enable [i915]] enabling display
>[  936.283115] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.283142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.283158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.283173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.283187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.283201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.283215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.283232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.283246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.283261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.283274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.283288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.283304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.283319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.285299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.285317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.285334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.285352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.286858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.286874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.286888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.288380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.288398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.290204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.292571] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.292606] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.292623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.292689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.292850] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.292867] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.309374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.309399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.309436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.309561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.309611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.342706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.342731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.342767] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.361327] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.361350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.361370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.361392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.361411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.361433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.361452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.361472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.361491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.361512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.361533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.361553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.361574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.361592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.361609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.361636] [drm:intel_power_well_disable [i915]] disabling display
>[  936.361705] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.361741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.361860] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.361938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.361947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.361991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.362010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.362029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.362049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.362068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.362089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.362108] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.362130] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.362157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.362182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.362201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.362206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.362224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.362228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.362248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.362267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.362286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.362305] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.362325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.362344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.362364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.362383] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.362403] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.362423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.362445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.362499] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.362514] [drm:intel_power_well_enable [i915]] enabling display
>[  936.362527] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.362554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.362571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.362586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.362600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.362614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.362632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.362672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.362697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.362720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.362740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.362760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.362785] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.362806] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.364797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.364815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.364832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.364850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.366354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.366370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.366384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.367878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.367894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.369698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.372630] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.372715] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.372730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.372751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.372786] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.372801] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.389450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.389476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.389510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.389748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.389805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.422806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  936.422831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.422866] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  936.441344] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  936.441366] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  936.441383] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.441402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.441419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.441436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.441451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.441467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.441482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.441500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.441516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.441532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.441548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.441562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.441575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.441601] [drm:intel_power_well_disable [i915]] disabling display
>[  936.441623] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.441643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.441705] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.441976] [drm:drm_mode_addfb2] [FB:75]
>[  936.442017] [drm:drm_mode_addfb2] [FB:78]
>[  936.467747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  936.467827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.467895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  936.467956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.467965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.468013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.468030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.468048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.468066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.468082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.468101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.468118] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.468136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.468154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.468171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.468188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.468192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.468209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.468212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.468230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.468247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.468264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.468282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.468299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.468316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.468333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.468351] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.468368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.468386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.468406] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.470929] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.470946] [drm:intel_power_well_enable [i915]] enabling display
>[  936.470961] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.470991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.471008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.471024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.471040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.471054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.471070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.471087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.471102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.471118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.471132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.471146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.471163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.471179] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.473191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.473209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.473223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.473239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.474766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.474784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.474802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.476302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.476320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.478159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.481096] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.481170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.481189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.481215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.497912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.497939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.497977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.514605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.514617] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.531361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.531416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.547967] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.547990] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.548025] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.566850] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.566868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.566888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.566906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.566923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.566939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.566954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.566970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.566987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.567003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.567019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.567035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.567049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.567063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.567090] [drm:intel_power_well_disable [i915]] disabling display
>[  936.567111] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.567132] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.567147] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.567224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.567233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.567275] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.567292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.567310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.567332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.567351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.567371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.567390] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.567409] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.567428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.567447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.567466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.567470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.567489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.567493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.567512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.567531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.567550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.567569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.567588] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.567607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.567625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.567644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.567707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.567734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.567764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.567833] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.567858] [drm:intel_power_well_enable [i915]] enabling display
>[  936.567883] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.567925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.567948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.567973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.567995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.568020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.568043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.568096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.568122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.568153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.568173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.568193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.568218] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.568239] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.570240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.570257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.570271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.570286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.571803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.571821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.571839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.573332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.573349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.575171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.578104] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.578181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.578197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.578220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.594921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.594948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.594985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.595113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.595162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.611615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.611639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.611823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.629428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.629447] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.629467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.629484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.629502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.629517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.629532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.629549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.629566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.629583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.629599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.629615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.629629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.629642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.629711] [drm:intel_power_well_disable [i915]] disabling display
>[  936.629748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.629782] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.629808] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.629920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.629934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.630005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.630031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.630059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.630088] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.630113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.630138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.630164] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.630189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.630214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.630237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.630261] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.630267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.630290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.630296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.630320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.630343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.630373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.630394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.630417] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.630438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.630458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.630479] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.630500] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.630523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.630549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.630603] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.630625] [drm:intel_power_well_enable [i915]] enabling display
>[  936.630647] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.630707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.630730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.630754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.630777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.630799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.630822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.630848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.630873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.630897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.630919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.630941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.630967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.630990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.632990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.633007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.633022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.633036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.634541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.634556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.634570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.636066] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.636081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.637885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.640813] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.640842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.640858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.640880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.657586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.657611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.657648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.657808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.657861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.674277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.674301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.674335] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.692423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.692444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.692466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.692486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.692507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.692527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.692546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.692565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.692587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.692608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.692628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.692649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.692709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.692734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.692777] [drm:intel_power_well_disable [i915]] disabling display
>[  936.692880] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.692903] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.692919] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.692993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.693001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.693044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.693063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.693083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.693105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.693123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.693143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.693162] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.693181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.693200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.693219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.693237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.693242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.693260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.693263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.693283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.693302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.693321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.693339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.693359] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.693377] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.693397] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.693416] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.693434] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.693453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.693474] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.693519] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.693535] [drm:intel_power_well_enable [i915]] enabling display
>[  936.693550] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.693579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.693599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.693618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.693637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.693656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.693705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.693734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.693760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.693784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.693806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.693833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.693858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.693879] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.695868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.695884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.695898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.695916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.697419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.697435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.697449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.698943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.698959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.700765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.703379] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.703419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.703436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.703458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.720152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.720177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.720212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.720335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.720384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.736853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.736876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.736920] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.754879] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.754898] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.754918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.754935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.754952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.754967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.754981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.754997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.755014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.755030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.755046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.755061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.755075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.755089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.755115] [drm:intel_power_well_disable [i915]] disabling display
>[  936.755137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.755157] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.755173] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.755250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.755258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.755301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.755320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.755340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.755362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.755381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.755401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.755420] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.755439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.755458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.755477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.755496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.755500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.755519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.755522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.755542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.755561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.755580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.755598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.755617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.755636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.755655] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.755717] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.755744] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.755772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.755802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.755871] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.755896] [drm:intel_power_well_enable [i915]] enabling display
>[  936.755920] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.755962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.755986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.756010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.756034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.756059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.756084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.756112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.756138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.756164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.756187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.756217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.756242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.756265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.758273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.758291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.758309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.758327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.759842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.759859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.759873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.761375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.761394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.763200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.766081] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.766158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.766175] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.766197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.782899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.782925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.782960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.783083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.783131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.799584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.799608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.799652] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.817601] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.817619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.817639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.817656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.817842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.817859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.817875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.817891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.817909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.817926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.817942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.817958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.817972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.817990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.818017] [drm:intel_power_well_disable [i915]] disabling display
>[  936.818039] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.818063] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.818080] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.818160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.818169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.818215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.818235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.818255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.818277] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.818296] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.818316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.818335] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.818354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.818374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.818393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.818411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.818415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.818434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.818438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.818457] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.818477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.818496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.818522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.818548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.818564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.818580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.818594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.818607] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.818623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.818640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.818711] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.818734] [drm:intel_power_well_enable [i915]] enabling display
>[  936.818756] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.818794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.818818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.818839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.818861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.818882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.818905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.818930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.818955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.818979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.818999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.819021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.819047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.819068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.821356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.821372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.821386] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.821401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.822905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.822921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.822935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.824425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.824443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.826256] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.829177] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.829213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.829229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.829250] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.845958] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.845985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.846022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.846133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.846186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.862648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.862672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.862817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.880673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.880710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.880730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.880747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.880765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.880781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.880795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.880811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.880829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.880845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.880860] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.880876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.880894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.880912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.880940] [drm:intel_power_well_disable [i915]] disabling display
>[  936.880962] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.880986] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.881003] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.881081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.881090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.881136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.881156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.881176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.881198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.881217] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.881236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.881256] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.881275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.881294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.881313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.881332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.881336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.881355] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.881358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.881378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.881397] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.881416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.881435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.881454] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.881473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.881492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.881511] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.881530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.881550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.881570] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.881616] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.881631] [drm:intel_power_well_enable [i915]] enabling display
>[  936.881646] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.881676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.881724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.881754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.881778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.881803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.881827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.881860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.881885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.881910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.881930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.881952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.881978] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.882000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.883993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.884010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.884024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.884039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.885542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.885560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.885577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.887074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.887091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.888897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.891839] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.891908] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.891927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.891953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.908648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.908674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.908754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.908898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.908945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.925342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.925365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.925399] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  936.943447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  936.943466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.943486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.943503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.943520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.943535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.943554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.943573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.943595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.943615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.943636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.943656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.943675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.943735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.943778] [drm:intel_power_well_disable [i915]] disabling display
>[  936.943813] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.944022] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.944047] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.944157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.944165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  936.944205] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.944221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.944238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.944256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.944270] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.944286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.944301] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  936.944316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  936.944330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.944343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.944356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.944360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.944373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.944376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.944389] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.944402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.944415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.944427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.944442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.944455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.944467] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  936.944480] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  936.944492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  936.944507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.944523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  936.944565] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.944579] [drm:intel_power_well_enable [i915]] enabling display
>[  936.944593] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.944620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.944638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.944656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.944674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.944717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.944744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.944769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.944795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.944821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.944841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.944863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.944890] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  936.944912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.946903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.946920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.946934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.946949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.948453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.948468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.948482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.949979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.949995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.951800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.954712] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  936.954756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.954774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  936.954798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.971500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.971525] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  936.971561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.971719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  936.971877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.988192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  936.988216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.988250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.006441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.006460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.006480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.006497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.006515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.006530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.006544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.006560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.006578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.006598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.006618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.006639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.006658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.006675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.006746] [drm:intel_power_well_disable [i915]] disabling display
>[  937.006780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.007003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.007028] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.007139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.007148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.007193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.007210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.007228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.007248] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.007264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.007281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.007300] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.007319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.007338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.007357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.007376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.007380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.007399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.007402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.007422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.007441] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.007460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.007479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.007506] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.007523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.007538] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.007552] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.007565] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.007580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.007597] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.007638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.007652] [drm:intel_power_well_enable [i915]] enabling display
>[  937.007664] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.007721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.007743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.007766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.007786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.007807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.007829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.007853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.007878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.007902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.007923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.007944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.007970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.007991] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.010235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.010252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.010266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.010282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.011804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.011821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.011836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.013341] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.013359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.015181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.018134] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.018192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.018212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.018238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.034934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.034960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.034994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.035102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.035156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.051626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.051650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.051688] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.070590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.070609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.070629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.070647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.070665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.070680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.070741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.070824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.070843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.070861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.070877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.070894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.070908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.070923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.070948] [drm:intel_power_well_disable [i915]] disabling display
>[  937.070970] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.070991] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.071007] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.071076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.071086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.071128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.071144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.071163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.071182] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.071199] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.071215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.071232] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.071247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.071263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.071277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.071296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.071300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.071319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.071323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.071343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.071363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.071380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.071399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.071419] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.071438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.071458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.071477] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.071497] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.071518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.071538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.071585] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.071601] [drm:intel_power_well_enable [i915]] enabling display
>[  937.071616] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.071647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.071667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.071688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.071732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.071757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.071781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.071813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.071836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.071859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.071879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.071899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.071923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.071945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.073933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.073950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.073964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.073980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.075482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.075497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.075511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.077005] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.077020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.078825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.081766] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.081835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.081852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.081874] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.098578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.098603] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.098638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.098858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.098905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.115270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.115293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.115327] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.134169] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.134188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.134209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.134229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.134251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.134270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.134290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.134309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.134330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.134351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.134371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.134392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.134410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.134429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.134456] [drm:intel_power_well_disable [i915]] disabling display
>[  937.134479] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.134503] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.134519] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.134598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.134607] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.134653] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.134673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.134693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.134759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.134784] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.134813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.134838] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.134864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.134888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.134912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.134933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.134941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.134963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.134969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.134993] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.135015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.135038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.135059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.135085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.135106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.135131] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.135158] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.135180] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.135205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.135228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.135291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.135314] [drm:intel_power_well_enable [i915]] enabling display
>[  937.135337] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.135376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.135400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.135422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.135443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.135465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.135488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.135512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.135536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.135560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.135579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.135600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.135622] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.135645] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.137654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.137670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.137684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.137730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.139241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.139257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.139270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.140835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.140851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.142721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.145654] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.145757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.145785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.145889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.162473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.162498] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.162533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.162655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.162744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.179164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.179187] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.179226] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.196447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.196466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.196485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.196502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.196519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.196533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.196547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.196563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.196581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.196597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.196613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.196628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.196642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.196656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.196683] [drm:intel_power_well_disable [i915]] disabling display
>[  937.196748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.196782] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.196808] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.197101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.197113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.197157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.197174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.197193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.197215] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.197234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.197253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.197273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.197292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.197311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.197330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.197349] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.197353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.197371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.197375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.197395] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.197414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.197440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.197456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.197472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.197487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.197501] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.197514] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.197527] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.197542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.197559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.197600] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.197613] [drm:intel_power_well_enable [i915]] enabling display
>[  937.197625] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.197650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.197665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.197678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.197718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.197742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.197763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.197788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.197812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.197836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.197856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.197877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.197904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.197925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.200163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.200179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.200193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.200208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.201754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.201772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.201790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.203294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.203311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.205139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.208085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.208149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.208167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.208189] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.224891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.224918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.224955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.225082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.225130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.241584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.241608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.241642] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.260504] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.260523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.260543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.260560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.260577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.260592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.260607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.260623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.260641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.260658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.260674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.260690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.260749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.260771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.260815] [drm:intel_power_well_disable [i915]] disabling display
>[  937.260851] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.260884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.260910] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.260992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.261001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.261040] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.261056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.261072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.261092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.261109] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.261128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.261146] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.261164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.261182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.261200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.261218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.261222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.261239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.261243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.261261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.261279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.261296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.261314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.261332] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.261349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.261367] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.261385] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.261403] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.261422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.261441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.261484] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.261499] [drm:intel_power_well_enable [i915]] enabling display
>[  937.261513] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.261541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.261559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.261578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.261595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.261614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.261632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.261651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.261670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.261689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.261728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.261752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.261776] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.261798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.263788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.263805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.263819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.263834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.265337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.265352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.265366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.266860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.266876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.268703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.271087] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.271166] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.271192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.271215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.287915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.287942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.287979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.288083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.288124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.304604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.304628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.304665] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.323548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.323567] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.323587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.323604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.323621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.323640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.323660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.323679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.323701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.323765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.323794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.323820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.323845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.323869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.323911] [drm:intel_power_well_disable [i915]] disabling display
>[  937.323947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.323980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.324001] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.324081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.324090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.324136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.324156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.324176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.324198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.324217] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.324238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.324257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.324277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.324295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.324315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.324334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.324339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.324358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.324362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.324382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.324401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.324421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.324448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.324466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.324482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.324498] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.324512] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.324526] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.324542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.324559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.324602] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.324615] [drm:intel_power_well_enable [i915]] enabling display
>[  937.324632] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.324669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.324684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.324698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.324738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.324757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.324779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.324802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.324825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.324847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.324867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.324887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.324910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.324931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.326925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.326941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.326955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.326972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.328479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.328495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.328508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.330009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.330025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.331834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.334767] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.334843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.334859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.334880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.351586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.351612] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.351648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.351837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.351887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.368277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.368300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.368344] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.387019] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.387038] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.387059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.387076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.387093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.387108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.387123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.387142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.387163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.387184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.387205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.387232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.387251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.387267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.387295] [drm:intel_power_well_disable [i915]] disabling display
>[  937.387317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.387341] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.387358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.387440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.387449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.387496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.387515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.387535] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.387557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.387576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.387596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.387615] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.387641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.387658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.387673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.387686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.387689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.387740] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.387747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.387772] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.387792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.387815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.387837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.387862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.387884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.387906] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.387929] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.387950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.387975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.388001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.388067] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.388315] [drm:intel_power_well_enable [i915]] enabling display
>[  937.388337] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.388376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.388400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.388423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.388445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.388467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.388489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.388514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.388538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.388561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.388583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.388604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.388629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.388652] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.390660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.390676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.390689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.390736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.392243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.392258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.392272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.393843] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.393860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.395735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.398668] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.398778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.398804] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.398842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.415488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.415514] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.415549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.415673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.415765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.432180] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.432203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.432248] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.451110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.451128] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.451148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.451165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.451182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.451197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.451212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.451228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.451245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.451261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.451277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.451292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.451307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.451321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.451347] [drm:intel_power_well_disable [i915]] disabling display
>[  937.451368] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.451389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.451404] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.451475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.451484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.451526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.451542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.451560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.451579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.451594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.451611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.451627] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.451642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.451657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.451671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.451685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.451689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.451703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.451741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.451767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.451793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.451818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.451842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.451868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.451893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.451916] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.451941] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.451964] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.451992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.452027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.452091] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.452366] [drm:intel_power_well_enable [i915]] enabling display
>[  937.452388] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.452426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.452450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.452473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.452495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.452517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.452537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.452561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.452585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.452609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.452631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.452650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.452674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.452697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.454841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.454858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.454872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.454887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.456393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.456409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.456423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.457917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.457933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.459743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.462674] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.462782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.462811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.462846] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.479496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.479522] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.479557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.479671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.479770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.496187] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.496211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.496255] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.514130] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.514149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.514169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.514186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.514204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.514219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.514233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.514249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.514267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.514284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.514299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.514315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.514329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.514343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.514369] [drm:intel_power_well_disable [i915]] disabling display
>[  937.514390] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.514411] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.514427] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.514505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.514522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.514561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.514575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.514592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.514609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.514623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.514638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.514653] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.514670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.514687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.514705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.514757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.514766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.514788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.514794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.514817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.514838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.514860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.514880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.514904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.514924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.514947] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.514967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.514989] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.515012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.515037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.515383] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.515405] [drm:intel_power_well_enable [i915]] enabling display
>[  937.515426] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.515465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.515488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.515509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.515531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.515550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.515572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.515596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.515619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.515642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.515662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.515682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.515704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.515750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.517869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.517886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.517900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.517914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.519418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.519433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.519447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.520942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.520958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.522764] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.525703] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.525772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.525788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.525809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.542516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.542542] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.542580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.542744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.542885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.559207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.559231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.559275] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.578137] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.578156] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.578176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.578193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.578210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.578225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.578239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.578255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.578273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.578289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.578305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.578320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.578335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.578348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.578375] [drm:intel_power_well_disable [i915]] disabling display
>[  937.578396] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.578423] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.578439] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.578518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.578527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.578570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.578586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.578603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.578622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.578637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.578653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.578669] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.578684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.578699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.578718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.578772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.578781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.578803] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.578810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.578834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.578863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.578885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.578904] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.578928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.578948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.578970] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.578990] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.579011] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.579036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.579062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.579393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.579414] [drm:intel_power_well_enable [i915]] enabling display
>[  937.579436] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.579474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.579495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.579518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.579538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.579559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.579579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.579603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.579626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.579649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.579669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.579689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.579712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.579755] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.581915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.581930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.581944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.581959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.583479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.583496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.583510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.585010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.585026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.586835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.589776] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.589844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.589861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.589883] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.606595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.606621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.606656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.606839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.606882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.623307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.623332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.623367] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.642232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.642250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.642271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.642287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.642305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.642320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.642335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.642351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.642368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.642385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.642400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.642416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.642430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.642444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.642470] [drm:intel_power_well_disable [i915]] disabling display
>[  937.642491] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.642512] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.642528] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.642599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.642608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.642651] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.642667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.642685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.642703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.642719] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.642777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.642802] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.642825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.642847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.642869] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.642890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.642897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.642917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.642924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.642945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.642966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.642988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.643008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.643033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.643053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.643075] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.643096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.643117] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.643142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.643176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.643240] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.643262] [drm:intel_power_well_enable [i915]] enabling display
>[  937.643286] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.643325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.643348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.643371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.643393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.643415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.643438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.643463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.643479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.643494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.643507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.643520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.643536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.643551] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.645529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.645547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.645564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.645582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.647095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.647111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.647125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.648619] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.648635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.650446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.653376] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.653402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.653417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.653438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.670132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.670156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.670190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.670303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.670354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.686868] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.686893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.686928] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.705797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.705816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.705836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.705853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.705871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.705886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.705901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.705917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.705934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.705950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.705966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.705981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.705995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.706009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.706036] [drm:intel_power_well_disable [i915]] disabling display
>[  937.706057] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.706082] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.706098] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.706180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.706189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.706236] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.706256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.706276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.706298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.706317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.706336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.706362] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.706377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.706392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.706405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.706418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.706422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.706434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.706438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.706451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.706464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.706477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.706489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.706504] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.706516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.706529] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.706542] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.706554] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.706569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.706588] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.706630] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.706644] [drm:intel_power_well_enable [i915]] enabling display
>[  937.706658] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.706686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.706704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.706722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.706781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.706808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.706833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.706860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.706885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.706910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.706932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.706955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.706981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.707005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.709011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.709028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.709042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.709057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.710565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.710581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.710595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.712091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.712107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.713913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.716852] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.716923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.716942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.716968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.733664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.733690] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.733725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.733902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.733942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.750340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.750362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.750407] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.769247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.769266] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.769286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.769303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.769320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.769336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.769350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.769366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.769384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.769400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.769416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.769432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.769451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.769469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.769496] [drm:intel_power_well_disable [i915]] disabling display
>[  937.769518] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.769543] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.769560] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.769640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.769650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.769696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.769716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.769767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.769801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.769825] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.769854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.769879] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.769905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.769928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.769952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.769974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.769981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.770003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.770010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.770034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.770056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.770080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.770102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.770128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.770149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.770173] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.770194] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.770217] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.770243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.770269] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.770339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.770363] [drm:intel_power_well_enable [i915]] enabling display
>[  937.770386] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.770426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.770450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.770472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.770496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.770516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.770547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.770571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.770594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.770617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.770635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.770655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.770678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.770700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.772709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.772727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.772776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.772804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.774389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.774404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.774418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.775914] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.775931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.777751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.780682] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.780709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.780726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.780797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.797453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.797479] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.797514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.797622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.797662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.814133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.814157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.814202] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.833060] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.833081] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.833102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.833122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.833144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.833163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.833182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.833201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.833223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.833244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.833264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.833284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.833303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.833319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.833347] [drm:intel_power_well_disable [i915]] disabling display
>[  937.833369] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.833393] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.833410] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.833507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.833517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.833563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.833582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.833602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.833624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.833643] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.833662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.833682] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.833701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.833720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.833782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.833807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.833815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.833840] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.833847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.833872] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.833895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.833919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.833946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.833971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.833991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.834013] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.834033] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.834054] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.834079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.834105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.834170] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.834191] [drm:intel_power_well_enable [i915]] enabling display
>[  937.834213] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.834251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.834274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.834294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.834315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.834334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.834356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.834380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.834404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.834427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.834446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.834466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.834491] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.834511] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.836505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.836522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.836536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.836551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.838058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.838074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.838088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.839580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.839595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.841400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.844324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.844359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.844379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.844405] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.861101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.861127] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.861161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.861261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.861300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.877782] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.877808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.877854] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.896715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.896734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.896798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.896823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.896852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.896874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.896898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.896920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.896948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.896974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.897001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.897027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.897048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.897070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.897110] [drm:intel_power_well_disable [i915]] disabling display
>[  937.897143] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.897173] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.897198] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.897323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.897333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.897373] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.897389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.897405] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.897426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.897443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.897461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.897478] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.897496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.897513] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.897531] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.897548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.897551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.897568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.897572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.897590] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.897607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.897625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.897642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.897659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.897676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.897693] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.897711] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.897728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.897773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.897802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.897865] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.897888] [drm:intel_power_well_enable [i915]] enabling display
>[  937.897910] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.897949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.897970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.898044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.898064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.898086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.898107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.898130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.898154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.898177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.898196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.898217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.898240] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.898262] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.900272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.900289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.900303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.900318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.901839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.901857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.901871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.903378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.903397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.905206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.908136] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.908164] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.908183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.908209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.924908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.924933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.924968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.925075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.925115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.941588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  937.941613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.941657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  937.960462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  937.960481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.960501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.960518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.960536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.960550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.960565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.960581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.960598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.960614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.960634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.960655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.960673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.960690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.960718] [drm:intel_power_well_disable [i915]] disabling display
>[  937.960781] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.960818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.960845] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.960966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.960980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.961051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.961078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.961104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.961134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.961157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.961183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.961207] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  937.961231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  937.961253] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.961276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.961297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.961303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.961325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.961330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.961353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.961375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.961397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.961418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  937.961443] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.961463] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.961486] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  937.961506] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  937.961529] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  937.961552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.961578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  937.961646] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.961670] [drm:intel_power_well_enable [i915]] enabling display
>[  937.961693] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.961740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.961780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.961803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.961823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.961846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.961866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.961891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.961916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.961940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.961960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.961982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.962005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  937.962029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.964023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.964041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.964058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.964077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.965584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.965601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.965616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.967112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.967128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.968932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.971870] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  937.971948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.971963] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  937.971984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.988674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.988700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  937.988736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.988911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.988951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.005363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.005388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.005431] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.024315] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.024334] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.024355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.024372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.024389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.024405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.024419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.024435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.024453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.024474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.024494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.024515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.024534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.024553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.024580] [drm:intel_power_well_disable [i915]] disabling display
>[  938.024602] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.024627] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.024643] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.024726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.024769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.024839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.024866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.024893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.024923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.024946] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.024972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.024996] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.025020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.025043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.025072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.025092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.025097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.025117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.025122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.025143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.025162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.025183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.025201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.025225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.025244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.025265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.025284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.025304] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.025326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.025349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.025413] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.025434] [drm:intel_power_well_enable [i915]] enabling display
>[  938.025456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.025493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.025514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.025536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.025555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.025576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.025596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.025619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.025643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.025666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.025685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.025705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.025728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.025769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.027778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.027795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.027810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.027825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.029339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.029356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.029371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.030873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.030890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.032697] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.035172] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.035199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.035216] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.035245] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.051940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.051964] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.051997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.052090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.052128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.068623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.068648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.068685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.087541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.087560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.087582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.087601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.087623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.087642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.087662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.087681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.087702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.087723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.087743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.087809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.087834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.087857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.087900] [drm:intel_power_well_disable [i915]] disabling display
>[  938.087936] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.087970] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.087996] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.088070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.088079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.088123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.088140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.088158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.088178] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.088195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.088212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.088229] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.088245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.088261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.088276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.088290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.088294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.088308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.088312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.088327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.088342] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.088356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.088370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.088386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.088401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.088422] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.088436] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.088448] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.088464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.088480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.088523] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.088536] [drm:intel_power_well_enable [i915]] enabling display
>[  938.088549] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.088574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.088588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.088602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.088615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.088629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.088642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.088658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.088672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.088686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.088699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.088712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.088730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.088750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.090865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.090882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.090897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.090911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.092416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.092431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.092445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.093942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.093958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.095780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.098715] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.098828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.098855] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.098891] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.115533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.115559] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.115594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.115705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.115744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.132242] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.132266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.132311] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.151170] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.151189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.151209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.151226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.151247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.151267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.151286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.151305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.151327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.151347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.151368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.151388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.151407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.151422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.151450] [drm:intel_power_well_disable [i915]] disabling display
>[  938.151472] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.151497] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.151514] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.151596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.151605] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.151651] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.151671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.151691] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.151721] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.151738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.151796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.151823] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.151848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.151872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.151895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.151917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.151924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.151945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.151951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.151973] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.151995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.152017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.152039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.152064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.152086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.152108] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.152130] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.152152] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.152177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.152203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.152269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.152291] [drm:intel_power_well_enable [i915]] enabling display
>[  938.152313] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.152352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.152374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.152397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.152417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.152438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.152461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.152485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.152509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.152532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.152553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.152573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.152597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.152620] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.154623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.154639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.154653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.154668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.156176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.156191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.156205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.157703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.157719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.159525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.162444] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.162482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.162499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.162521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.179225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.179251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.179286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.179393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.179433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.195906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.195930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.195975] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.214835] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.214854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.214875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.214894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.214916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.214935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.214955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.214974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.214996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.215016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.215036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.215057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.215076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.215092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.215119] [drm:intel_power_well_disable [i915]] disabling display
>[  938.215141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.215172] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.215188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.215265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.215274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.215317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.215334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.215351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.215370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.215387] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.215406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.215425] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.215443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.215462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.215480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.215498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.215502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.215520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.215523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.215542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.215561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.215579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.215597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.215616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.215634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.215652] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.215670] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.215689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.215708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.215728] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.215825] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.215850] [drm:intel_power_well_enable [i915]] enabling display
>[  938.215874] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.215916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.215943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.215968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.215993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.216017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.216043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.216071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.216098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.216124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.216148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.216171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.216205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.216229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.218223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.218239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.218253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.218268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.219822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.219837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.219851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.221345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.221363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.223171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.226109] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.226180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.226197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.226219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.242922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.242948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.242986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.243098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.243139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.259603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.259627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.259671] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.278542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.278561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.278581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.278598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.278616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.278631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.278645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.278661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.278679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.278695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.278711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.278727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.278741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.278755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.278832] [drm:intel_power_well_disable [i915]] disabling display
>[  938.278867] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.278899] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.278925] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.279034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.279049] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.279121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.279147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.279175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.279205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.279229] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.279256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.279282] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.279307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.279332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.279356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.279379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.279386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.279409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.279415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.279439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.279462] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.279485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.279515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.279538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.279559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.279579] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.279600] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.279621] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.279644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.279669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.279732] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.279754] [drm:intel_power_well_enable [i915]] enabling display
>[  938.279799] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.279838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.279862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.279885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.279907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.279930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.279953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.279979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.280004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.280028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.280050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.280072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.280097] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.280121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.282109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.282125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.282139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.282154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.283659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.283674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.283687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.285183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.285201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.287007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.289940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.290016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.290033] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.290055] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.306759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.306804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.306842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.306951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.306992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.323438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.323464] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.323510] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.342382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.342401] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.342422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.342442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.342463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.342483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.342502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.342521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.342542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.342563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.342583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.342604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.342622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.342639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.342667] [drm:intel_power_well_disable [i915]] disabling display
>[  938.342689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.342713] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.342730] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.342879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.342893] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.342957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.342981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.343008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.343035] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.343057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.343081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.343105] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.343129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.343152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.343174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.343195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.343201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.343221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.343227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.343248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.343270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.343291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.343312] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.343336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.343358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.343380] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.343401] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.343423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.343447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.343472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.343537] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.343559] [drm:intel_power_well_enable [i915]] enabling display
>[  938.343581] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.343620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.343644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.343666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.343687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.343709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.343732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.343756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.343801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.343826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.343849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.343871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.343898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.343922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.345912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.345928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.345942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.345957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.347461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.347479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.347496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.348992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.349008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.350813] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.353751] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.353823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.353840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.353862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.370573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.370599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.370634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.370802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.370864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.387287] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.387311] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.387347] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.405437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.405456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.405476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.405493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.405510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.405525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.405540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.405556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.405573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.405589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.405605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.405620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.405634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.405648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.405674] [drm:intel_power_well_disable [i915]] disabling display
>[  938.405695] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.405716] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.405732] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.405870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.405880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.405925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.405942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.405960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.405981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.405996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.406014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.406031] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.406047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.406063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.406078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.406092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.406097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.406111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.406115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.406138] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.406155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.406174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.406192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.406210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.406228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.406246] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.406263] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.406282] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.406301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.406320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.406356] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.406370] [drm:intel_power_well_enable [i915]] enabling display
>[  938.406384] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.406412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.406430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.406449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.406466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.406485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.406502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.406522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.406542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.406561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.406578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.406596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.406615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.406633] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.408615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.408632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.408647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.408662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.410167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.410182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.410196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.411713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.411729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.413534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.416465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.416543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.416560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.416582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.433285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.433311] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.433345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.433454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.433494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.449966] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.449990] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.450034] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.468901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.468920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.468940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.468957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.468974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.468990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.469004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.469020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.469038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.469054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.469069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.469085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.469099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.469112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.469139] [drm:intel_power_well_disable [i915]] disabling display
>[  938.469160] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.469181] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.469196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.469266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.469275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.469317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.469333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.469351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.469370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.469386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.469402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.469418] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.469434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.469451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.469474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.469501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.469505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.469517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.469520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.469533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.469546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.469559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.469571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.469586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.469599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.469611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.469624] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.469636] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.469651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.469667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.469708] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.469721] [drm:intel_power_well_enable [i915]] enabling display
>[  938.469734] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.469758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.469808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.469829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.469849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.469869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.469889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.469913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.469935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.469957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.469977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.469996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.470020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.470041] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.472032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.472048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.472062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.472077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.473578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.473596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.473620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.475119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.475135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.476940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.479886] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.479949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.479966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.479988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.496699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.496725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.496760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.496947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.496989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.513382] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.513405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.513450] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.532316] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.532335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.532355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.532372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.532390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.532405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.532420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.532436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.532454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.532470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.532485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.532501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.532515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.532529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.532555] [drm:intel_power_well_disable [i915]] disabling display
>[  938.532576] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.532597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.532612] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.532690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.532699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.532741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.532757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.532818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.532849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.532870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.532896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.532918] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.532942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.532963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.532985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.533005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.533012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.533032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.533038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.533060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.533080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.533102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.533121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.533145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.533165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.533187] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.533207] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.533228] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.533517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.533543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.533605] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.533627] [drm:intel_power_well_enable [i915]] enabling display
>[  938.533649] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.533686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.533708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.533730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.533750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.533771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.533811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.533837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.533862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.533887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.533907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.533928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.534077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.534098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.536088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.536104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.536118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.536133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.537636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.537652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.537666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.539163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.539178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.540981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.543912] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.543939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.543955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.543977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.560682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.560708] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.560743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.560930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.560975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.577376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.577399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.577444] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.596305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.596324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.596345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.596361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.596382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.596402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.596421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.596440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.596461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.596482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.596503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.596523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.596542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.596558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.596586] [drm:intel_power_well_disable [i915]] disabling display
>[  938.596608] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.596632] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.596649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.596730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.596740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.596829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.596855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.596884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.596914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.596938] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.596965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.596990] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.597015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.597040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.597064] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.597086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.597094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.597123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.597129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.597151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.597171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.597193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.597212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.597235] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.597255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.597277] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.597296] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.597317] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.597340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.597365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.597428] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.597449] [drm:intel_power_well_enable [i915]] enabling display
>[  938.597472] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.597509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.597530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.597551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.597571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.597591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.597611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.597635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.597658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.597681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.597700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.597720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.597743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.597765] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.599774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.599802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.599817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.599831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.601349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.601364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.601378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.602876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.602892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.604724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.607655] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.607734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.607751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.607773] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.624475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.624500] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.624537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.624664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.624713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.641167] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.641190] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.641235] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.660111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.660130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.660151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.660170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.660192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.660211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.660230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.660249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.660271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.660291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.660312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.660332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.660351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.660368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.660395] [drm:intel_power_well_disable [i915]] disabling display
>[  938.660418] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.660442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.660458] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.660532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.660549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.660589] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.660606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.660622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.660640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.660654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.660669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.660685] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.660699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.660714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.660727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.660740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.660744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.660757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.660760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.660773] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.660822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.660845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.660867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.660889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.660911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.660931] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.660953] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.660972] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.660997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.661023] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.661086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.661382] [drm:intel_power_well_enable [i915]] enabling display
>[  938.661403] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.661441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.661463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.661485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.661505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.661526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.661547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.661571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.661594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.661617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.661636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.661656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.661679] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.661701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.663692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.663708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.663722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.663737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.665242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.665257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.665270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.666814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.666830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.668632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.671551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.671590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.671606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.671628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.688333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.688359] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.688393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.688504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.688556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.705027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.705052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.705097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.723964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.723983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.724004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.724021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.724039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.724054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.724069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.724085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.724103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.724119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.724135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.724150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.724164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.724178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.724205] [drm:intel_power_well_disable [i915]] disabling display
>[  938.724225] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.724246] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.724262] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.724339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.724348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.724390] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.724407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.724425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.724444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.724459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.724476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.724492] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.724507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.724523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.724537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.724551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.724555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.724568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.724572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.724586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.724601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.724614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.724628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.724644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.724658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.724672] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.724690] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.724709] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.724730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.724750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.724840] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.724863] [drm:intel_power_well_enable [i915]] enabling display
>[  938.724886] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.724924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.724946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.724970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.724991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.725013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.725035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.725060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.725084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.725109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.725129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.725150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.725177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.725199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.727508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.727524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.727538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.727553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.729061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.729077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.729091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.730583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.730599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.732405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.735336] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.735413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.735430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.735452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.752156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.752182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.752217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.752338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.752387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.768849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.768873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.768918] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.787099] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.787118] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.787139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.787156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.787173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.787188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.787203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.787219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.787236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.787252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.787268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.787283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.787298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.787311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.787338] [drm:intel_power_well_disable [i915]] disabling display
>[  938.787360] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.787381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.787396] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.787474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.787483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.787525] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.787541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.787559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.787581] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.787600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.787620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.787639] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.787658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.787677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.787696] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.787715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.787719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.787738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.787741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.787761] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.787780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.787846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.787875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.787903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.787930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.787955] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.787980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.788005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.788033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.788061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.788120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.788145] [drm:intel_power_well_enable [i915]] enabling display
>[  938.788170] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.788216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.788239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.788262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.788284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.788306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.788328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.788353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.788376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.788400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.788421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.788440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.788464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.788488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.790495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.790512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.790527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.790541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.792049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.792065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.792079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.793572] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.793589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.795394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.798327] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.798410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.798426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.798446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.815146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.815172] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.815207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.815332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.815380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.831839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.831864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.831909] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.850740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.850759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.850779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.850840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.850863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.850879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.850893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.850911] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.850928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.850945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.850961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.850977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.850991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.851005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.851032] [drm:intel_power_well_disable [i915]] disabling display
>[  938.851053] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.851075] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.851091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.851170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.851180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.851223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.851239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.851257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.851276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.851292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.851309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.851325] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.851342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.851357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.851373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.851386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.851391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.851405] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.851408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.851423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.851437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.851451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.851466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.851482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.851497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.851511] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.851526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.851539] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.851555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.851583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.851625] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.851638] [drm:intel_power_well_enable [i915]] enabling display
>[  938.851651] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.851676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.851690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.851704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.851717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.851730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.851745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.851762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.851781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.851821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.851842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.851862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.851885] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.851906] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.853894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.853910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.853924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.853938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.855441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.855457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.855471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.856965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.856983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.858795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.861740] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.861837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.861863] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.861942] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.878554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.878580] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.878615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.878728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.878780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.895246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.895270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.895315] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.914180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.914199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.914220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.914237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.914254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.914273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.914293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.914312] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.914334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.914354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.914375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.914395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.914414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.914430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.914458] [drm:intel_power_well_disable [i915]] disabling display
>[  938.914480] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.914505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.914522] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.914602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.914611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.914657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.914677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.914697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.914719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.914738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.914757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.914776] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.914795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.914862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.914886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.914909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.914915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.914935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.914941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.914961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.914982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.915002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.915021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.915044] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.915063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.915083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.915102] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.915121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.915144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.915168] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.915392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.915405] [drm:intel_power_well_enable [i915]] enabling display
>[  938.915418] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.915446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.915464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.915482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.915500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.915519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.915536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.915557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.915575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.915594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.915612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.915627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.915647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.915664] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.917635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.917653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.917671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.917689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.919197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.919213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.919227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.920739] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.920757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.922565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.925495] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.925521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.925537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.925559] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  938.942264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.942290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.942325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.942447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.942495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.958956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  938.958979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  938.959025] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  938.977863] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  938.977881] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  938.977902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.977919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.977936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.977952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.977966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.977983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  938.978000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.978020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.978041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.978061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.978080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.978097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.978124] [drm:intel_power_well_disable [i915]] disabling display
>[  938.978147] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  938.978171] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  938.978187] [drm:intel_power_well_disable [i915]] disabling always-on
>[  938.978269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  938.978278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  938.978331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  938.978348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  938.978365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  938.978383] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  938.978397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  938.978412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  938.978428] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  938.978444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  938.978462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  938.978480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  938.978497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  938.978500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.978517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  938.978521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  938.978539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  938.978556] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  938.978574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  938.978591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  938.978609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  938.978625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  938.978643] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  938.978660] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  938.978677] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  938.978696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  938.978715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  938.978757] [drm:intel_power_well_enable [i915]] enabling always-on
>[  938.978771] [drm:intel_power_well_enable [i915]] enabling display
>[  938.978784] [drm:hsw_set_power_well [i915]] Enabling power well
>[  938.978851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  938.978874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  938.978896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  938.978917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  938.978937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  938.978959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  938.978982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  938.979004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  938.979027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  938.979047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  938.979067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  938.979091] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  938.979113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  938.981397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  938.981413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  938.981428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.981443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  938.982953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  938.982969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  938.982983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  938.984479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  938.984495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  938.986313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  938.989250] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  938.989321] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  938.989338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  938.989359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.006064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.006091] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.006128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.006253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.006302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.022759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.022782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.022864] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.041812] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.041846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.041867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.041887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.041908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.041928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.041947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.041966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.041988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.042008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.042029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.042049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.042068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.042084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.042112] [drm:intel_power_well_disable [i915]] disabling display
>[  939.042134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.042159] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.042175] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.042257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.042267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.042326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.042347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.042365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.042385] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.042400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.042417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.042434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.042450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.042466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.042481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.042495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.042498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.042512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.042516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.042530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.042545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.042558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.042572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.042589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.042603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.042617] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.042638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.042650] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.042665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.042681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.042722] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.042735] [drm:intel_power_well_enable [i915]] enabling display
>[  939.042748] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.042772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.042787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.042801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.042840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.042865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.042886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.042911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.042936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.042961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.042981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.043002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.043028] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.043050] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.045044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.045061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.045075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.045090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.046594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.046610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.046624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.048119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.048135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.049941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.052887] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.052950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.052967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.052992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.069692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.069718] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.069756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.069978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.070019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.086373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.086396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.086441] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.105290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.105309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.105329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.105346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.105364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.105379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.105394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.105410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.105428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.105443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.105459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.105474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.105488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.105502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.105529] [drm:intel_power_well_disable [i915]] disabling display
>[  939.105551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.105575] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.105592] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.105668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.105678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.105724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.105743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.105763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.105785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.105804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.105863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.105892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.105918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.105942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.105967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.105989] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.105996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.106018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.106025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.106049] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.106077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.106099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.106119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.106142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.106162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.106185] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.106205] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.106226] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.106251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.106276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.106599] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.106621] [drm:intel_power_well_enable [i915]] enabling display
>[  939.106643] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.106681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.106702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.106724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.106744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.106765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.106785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.106809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.106849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.106873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.106893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.106914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.106940] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.106962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.109100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.109117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.109131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.109148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.110653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.110668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.110682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.112178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.112196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.114002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.116936] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.117012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.117029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.117051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.133754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.133781] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.133855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.134043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.134083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.150434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.150459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.150503] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.167545] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.167563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.167583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.167603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.167624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.167644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.167663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.167682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.167704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.167725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.167745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.167766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.167785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.167803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.167873] [drm:intel_power_well_disable [i915]] disabling display
>[  939.167907] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.168162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.168187] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.168299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.168308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.168349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.168364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.168381] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.168401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.168419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.168437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.168454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.168472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.168489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.168507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.168524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.168527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.168544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.168548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.168565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.168583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.168600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.168617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.168635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.168652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.168669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.168686] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.168704] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.168722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.168741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.168783] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.168797] [drm:intel_power_well_enable [i915]] enabling display
>[  939.168838] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.168881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.168906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.168927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.168950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.168970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.168994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.169020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.169044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.169068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.169088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.169110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.169136] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.169157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.171398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.171415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.171429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.171444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.172957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.172972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.172986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.174479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.174495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.176316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.179254] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.179325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.179341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.179366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.196068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.196094] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.196131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.196241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.196283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.212748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.212774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.212819] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.231807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.231844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.231864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.231880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.231898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.231913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.231927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.231943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.231961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.231977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.231993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.232013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.232032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.232049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.232076] [drm:intel_power_well_disable [i915]] disabling display
>[  939.232099] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.232123] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.232140] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.232222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.232231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.232277] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.232296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.232316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.232338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.232357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.232376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.232396] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.232415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.232434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.232455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.232489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.232495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.232512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.232516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.232530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.232544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.232557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.232570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.232585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.232598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.232611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.232624] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.232637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.232652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.232668] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.232710] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.232723] [drm:intel_power_well_enable [i915]] enabling display
>[  939.232736] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.232760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.232775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.232789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.232802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.232842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.232868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.232893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.232918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.232942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.232962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.232984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.233010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.233031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.235031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.235047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.235062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.235079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.236583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.236599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.236617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.238118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.238134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.239939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.242895] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.242949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.242968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.242994] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.259688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.259713] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.259746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.259970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.260010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.276381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.276404] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.276449] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.295310] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.295329] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.295349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.295366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.295384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.295400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.295414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.295431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.295449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.295469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.295490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.295510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.295529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.295546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.295574] [drm:intel_power_well_disable [i915]] disabling display
>[  939.295596] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.295621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.295637] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.295711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.295721] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.295767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.295786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.295806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.295868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.295901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.295928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.295951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.295975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.295996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.296019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.296038] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.296045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.296065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.296071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.296093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.296113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.296135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.296155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.296180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.296200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.296222] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.296241] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.296263] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.296288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.296311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.296618] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.296641] [drm:intel_power_well_enable [i915]] enabling display
>[  939.296663] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.296701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.296722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.296744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.296764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.296785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.296805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.296848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.296872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.296898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.296918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.296939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.296965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.297155] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.299145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.299162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.299176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.299191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.300694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.300709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.300722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.302219] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.302235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.304038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.306966] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.306995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.307012] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.307033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.323730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.323755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.323788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.324008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.324048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.340420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.340444] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.340488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.358396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.358415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.358436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.358453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.358470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.358485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.358500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.358516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.358533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.358549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.358565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.358581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.358595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.358609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.358635] [drm:intel_power_well_disable [i915]] disabling display
>[  939.358656] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.358677] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.358692] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.358768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.358778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.358820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.358887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.358917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.358949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.358974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.359001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.359027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.359053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.359079] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.359103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.359127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.359134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.359164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.359170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.359192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.359215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.359237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.359259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.359283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.359304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.359326] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.359348] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.359369] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.359394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.359418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.359472] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.359495] [drm:intel_power_well_enable [i915]] enabling display
>[  939.359517] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.359554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.359577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.359599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.359619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.359641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.359663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.359688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.359711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.359734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.359756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.359775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.359800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.359822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.361845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.361862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.361879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.361898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.363418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.363437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.363454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.364964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.364981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.366789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.369722] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.369798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.369815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.369877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.386533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.386557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.386590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.386698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.386737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.403222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.403247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.403293] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.422158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.422177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.422197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.422214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.422232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.422246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.422261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.422277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.422295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.422311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.422328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.422343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.422357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.422371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.422397] [drm:intel_power_well_disable [i915]] disabling display
>[  939.422418] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.422439] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.422455] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.422534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.422543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.422586] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.422602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.422620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.422639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.422654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.422671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.422687] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.422702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.422725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.422748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.422763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.422767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.422780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.422784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.422798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.422811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.422824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.422878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.422902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.422924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.422946] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.422968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.422989] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.423014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.423040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.423110] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.423327] [drm:intel_power_well_enable [i915]] enabling display
>[  939.423341] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.423370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.423388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.423403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.423419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.423434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.423453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.423478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.423494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.423509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.423522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.423535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.423552] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.423566] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.425538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.425554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.425568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.425583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.427088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.427103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.427117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.428610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.428626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.430433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.433363] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.433389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.433406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.433428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.450133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.450158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.450195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.450307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.450349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.466813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.466854] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.466898] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.485737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.485756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.485777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.485793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.485811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.485826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.485878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.485903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.485933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.486020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.486037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.486054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.486068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.486088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.486115] [drm:intel_power_well_disable [i915]] disabling display
>[  939.486137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.486163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.486180] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.486254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.486263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.486310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.486330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.486350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.486372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.486392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.486412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.486431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.486451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.486470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.486489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.486508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.486513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.486531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.486535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.486555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.486575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.486594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.486613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.486632] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.486651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.486671] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.486690] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.486710] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.486730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.486752] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.486798] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.486813] [drm:intel_power_well_enable [i915]] enabling display
>[  939.486836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.486896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.486919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.486941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.486962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.486982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.487003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.487027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.487050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.487073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.487092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.487112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.487136] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.487157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.489370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.489387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.489401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.489416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.490927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.490942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.490955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.492448] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.492464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.494267] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.497208] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.497277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.497294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.497316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.514019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.514045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.514080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.514179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.514220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.530699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.530724] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.530767] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.549608] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.549627] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.549647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.549663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.549681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.549695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.549710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.549726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.549743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.549759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.549774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.549790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.549804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.549818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.549887] [drm:intel_power_well_disable [i915]] disabling display
>[  939.549921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.549955] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.549981] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.550101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.550115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.550185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.550208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.550235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.550271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.550292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.550316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.550337] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.550359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.550379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.550400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.550419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.550425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.550444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.550449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.550470] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.550489] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.550510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.550529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.550553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.550572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.550592] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.550611] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.550631] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.550653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.550677] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.550740] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.550762] [drm:intel_power_well_enable [i915]] enabling display
>[  939.550784] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.550821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.550863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.550887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.550907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.550929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.550950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.550975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.551000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.551025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.551045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.551066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.551092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.551114] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.553104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.553127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.553145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.553163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.554670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.554687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.554701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.556197] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.556214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.558018] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.560951] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.561026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.561043] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.561064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.577767] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.577794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.577829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.578008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.578048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.594448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.594472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.594516] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.613006] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.613024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.613045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.613062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.613080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.613095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.613110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.613126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.613144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.613161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.613176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.613192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.613206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.613220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.613246] [drm:intel_power_well_disable [i915]] disabling display
>[  939.613268] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.613289] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.613304] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.613384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.613393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.613435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.613451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.613470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.613492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.613511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.613531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.613550] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.613569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.613588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.613607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.613626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.613630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.613648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.613652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.613678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.613694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.613709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.613722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.613738] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.613751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.613765] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.613778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.613790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.613805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.613822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.613902] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.613925] [drm:intel_power_well_enable [i915]] enabling display
>[  939.613948] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.613986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.614008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.614030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.614051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.614073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.614095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.614120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.614144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.614169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.614189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.614210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.614235] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.614256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.616251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.616267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.616281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.616296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.617803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.617818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.617831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.619371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.619389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.621226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.624164] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.624235] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.624252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.624274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.640977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.641003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.641038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.641147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.641186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.657686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.657710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.657754] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.676622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.676640] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.676661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.676677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.676694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.676709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.676724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.676740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.676757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.676773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.676789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.676804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.676818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.676837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.676913] [drm:intel_power_well_disable [i915]] disabling display
>[  939.676948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.676981] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.677014] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.677121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.677135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.677202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.677226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.677253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.677282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.677306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.677331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.677356] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.677381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.677405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.677428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.677451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.677457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.677479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.677484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.677507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.677530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.677553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.677576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.677601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.677623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.677646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.677666] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.677688] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.677713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.677739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.677808] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.677832] [drm:intel_power_well_enable [i915]] enabling display
>[  939.677873] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.677916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.677941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.677966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.677989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.678021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.678044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.678070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.678095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.678119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.678141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.678163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.678189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.678213] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.680202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.680220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.680237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.680255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.681789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.681805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.681819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.683357] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.683373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.685205] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.688137] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.688221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.688236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.688259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.704966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.704992] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.705027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.705127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.705166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.721637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.721662] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.721706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.740546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.740565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.740585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.740604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.740626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.740645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.740665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.740684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.740705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.740726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.740746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.740766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.740786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.740802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.740829] [drm:intel_power_well_disable [i915]] disabling display
>[  939.740896] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.740935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.740962] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.741083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.741097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.741167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.741194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.741222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.741252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.741276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.741303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.741329] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.741362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.741385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.741407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.741429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.741434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.741456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.741461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.741483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.741505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.741526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.741547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.741571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.741592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.741611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.741633] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.741654] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.741677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.741702] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.741767] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.741788] [drm:intel_power_well_enable [i915]] enabling display
>[  939.741810] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.741849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.741889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.741914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.741936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.741959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.741982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.742008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.742032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.742057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.742078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.742100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.742126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.742150] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.744139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.744154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.744168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.744182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.745685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.745703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.745720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.747218] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.747236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.749041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.751973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.751999] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.752016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.752038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.768741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.768768] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.768805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.768982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.769022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.785421] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.785446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.785491] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.803690] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.803709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.803729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.803746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.803764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.803779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.803794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.803810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.803828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.803844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.803905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.803931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.803952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.803974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.804019] [drm:intel_power_well_disable [i915]] disabling display
>[  939.804053] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.804087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.804113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.804239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.804254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.804323] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.804347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.804373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.804402] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.804425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.804450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.804474] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.804498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.804520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.804543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.804564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.804570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.804591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.804596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.804619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.804640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.804662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.804683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.804707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.804728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.804751] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.804771] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.804792] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.804818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.804851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.804925] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.804948] [drm:intel_power_well_enable [i915]] enabling display
>[  939.804970] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.805008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.805029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.805051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.805072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.805093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.805115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.805139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.805163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.805186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.805205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.805226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.805250] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.805271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.807266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.807283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.807301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.807319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.808828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.808844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.808889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.810389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.810404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.812222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.814515] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.814575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.814591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.814613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.831325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.831351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.831385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.831501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.831554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.848038] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.848063] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.848099] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.866960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.866979] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.866999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.867016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.867034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.867049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.867064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.867080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.867097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.867114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.867129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.867145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.867159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.867173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.867200] [drm:intel_power_well_disable [i915]] disabling display
>[  939.867221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.867246] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.867262] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.867344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.867353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.867399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.867419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.867439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.867461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.867480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.867500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.867519] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.867538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.867557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.867576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.867595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.867599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.867617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.867621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.867640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.867660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.867679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.867697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.867716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.867735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.867754] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.867773] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.867792] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.867812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.867833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.867916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.867941] [drm:intel_power_well_enable [i915]] enabling display
>[  939.867966] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.868009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.868036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.868060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.868085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.868108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.868133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.868162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.868190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.868217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.868239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.868262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.868296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.868318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.870332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.870349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.870366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.870384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.871921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.871937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.871952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.873454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.873472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.875285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.878223] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.878295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.878312] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.878334] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.895036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.895061] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.895094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.895188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.895226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.911718] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.911741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.911777] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.930642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.930660] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.930681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.930697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.930715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.930730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.930745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.930761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.930778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.930795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.930810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.930826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.930844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.930905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.930946] [drm:intel_power_well_disable [i915]] disabling display
>[  939.930981] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.931014] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.931039] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.931158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.931172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.931242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.931268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.931296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.931325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.931350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.931376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.931403] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.931428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.931452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.931476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.931500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.931506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.931528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.931535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.931558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.931581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.931605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.931627] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.931651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.931681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.931703] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.931724] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.931743] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.931767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.931791] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.931845] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.931884] [drm:intel_power_well_enable [i915]] enabling display
>[  939.931907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.931946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.931970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.931993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.932016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.932038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.932062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.932087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.932112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.932136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.932158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.932180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.932206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.932230] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.934222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.934238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.934252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.934266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.935775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.935790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.935805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.937304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  939.937320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  939.939126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  939.942072] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  939.942135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  939.942152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  939.942174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  939.958879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.958903] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.958942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.959049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.959087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.975559] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  939.975583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  939.975619] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  939.994480] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  939.994499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  939.994519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.994536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.994553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.994569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.994583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.994602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  939.994624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.994644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.994665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.994685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.994704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.994720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.994748] [drm:intel_power_well_disable [i915]] disabling display
>[  939.994770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  939.994794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  939.994811] [drm:intel_power_well_disable [i915]] disabling always-on
>[  939.994942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  939.994956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  939.995027] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  939.995058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  939.995084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  939.995111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  939.995131] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  939.995155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  939.995177] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  939.995199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  939.995220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  939.995241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  939.995260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  939.995266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.995286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  939.995291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  939.995312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  939.995331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  939.995351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.995370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  939.995393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  939.995411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  939.995432] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  939.995451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  939.995471] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  939.995495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  939.995518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  939.995583] [drm:intel_power_well_enable [i915]] enabling always-on
>[  939.995605] [drm:intel_power_well_enable [i915]] enabling display
>[  939.995626] [drm:hsw_set_power_well [i915]] Enabling power well
>[  939.995663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  939.995683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  939.995705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  939.995724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  939.995745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  939.995765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  939.995788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  939.995811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  939.995834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  939.995853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  939.995892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  939.995915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  939.995938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  939.997927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  939.997943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  939.997957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  939.997972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  939.999473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  939.999488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  939.999501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.000997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.001014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.002821] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.005740] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.005778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.005795] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.005817] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.022522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.022548] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.022582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.022689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.022729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.039203] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.039227] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.039261] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.058122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.058141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.058161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.058178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.058196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.058211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.058225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.058241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.058259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.058279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.058300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.058320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.058339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.058358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.058386] [drm:intel_power_well_disable [i915]] disabling display
>[  940.058408] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.058433] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.058449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.058531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.058540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.058586] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.058606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.058626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.058648] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.058667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.058686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.058706] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.058724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.058744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.058763] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.058781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.058785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.058804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.058807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.058827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.058845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.058864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.058924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.058952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.058979] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.059002] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.059027] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.059049] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.059076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.059104] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.059175] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.059198] [drm:intel_power_well_enable [i915]] enabling display
>[  940.059221] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.059262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.059284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.059308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.059329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.059352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.059381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.059404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.059427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.059450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.059469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.059490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.059514] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.059535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.061526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.061542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.061556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.061571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.063075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.063090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.063104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.064594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.064610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.066414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.069347] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.069424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.069444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.069470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.086164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.086190] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.086225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.086322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.086361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.102846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.102870] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.103072] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.121641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.121660] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.121681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.121697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.121715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.121734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.121753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.121773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.121794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.121815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.121835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.121856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.121912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.121936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.121980] [drm:intel_power_well_disable [i915]] disabling display
>[  940.122016] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.122050] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.122077] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.122164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.122173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.122218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.122236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.122254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.122274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.122290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.122307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.122325] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.122341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.122357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.122371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.122386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.122390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.122404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.122408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.122423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.122437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.122451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.122465] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.122481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.122495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.122510] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.122523] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.122536] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.122553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.122571] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.122618] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.122632] [drm:intel_power_well_enable [i915]] enabling display
>[  940.122647] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.122681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.122696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.122710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.122724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.122737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.122751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.122767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.122781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.122796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.122808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.122821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.122837] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.122851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.124857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.124885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.124900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.124915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.126509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.126524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.126538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.128034] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.128050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.129877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.132823] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.132922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.132948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.133033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.149637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.149664] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.149701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.149817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.149859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.166317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.166341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.166376] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.184645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.184664] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.184684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.184701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.184719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.184738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.184757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.184776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.184798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.184819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.184840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.184860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.184920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.184944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.184987] [drm:intel_power_well_disable [i915]] disabling display
>[  940.185103] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.185128] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.185145] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.185224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.185234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.185279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.185296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.185314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.185334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.185350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.185367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.185384] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.185401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.185416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.185431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.185446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.185450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.185464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.185468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.185483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.185497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.185512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.185525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.185542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.185557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.185571] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.185590] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.185610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.185631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.185652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.185699] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.185715] [drm:intel_power_well_enable [i915]] enabling display
>[  940.185730] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.185761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.185781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.185801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.185820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.185840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.185859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.185905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.185940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.185964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.185984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.186005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.186030] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.186052] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.188041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.188059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.188076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.188095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.189601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.189617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.189631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.191128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.191144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.192950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.195891] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.195959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.195976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.195997] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.212702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.212729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.212766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.212996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.213057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.229381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.229406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.229441] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.247634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.247652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.247674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.247694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.247715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.247734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.247754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.247773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.247795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.247815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.247836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.247856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.247875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.247938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.247979] [drm:intel_power_well_disable [i915]] disabling display
>[  940.248014] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.248208] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.248234] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.248359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.248373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.248431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.248447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.248463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.248481] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.248495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.248511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.248526] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.248540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.248555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.248568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.248581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.248585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.248597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.248600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.248613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.248626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.248638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.248650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.248667] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.248685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.248702] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.248720] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.248737] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.248755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.248774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.248816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.248830] [drm:intel_power_well_enable [i915]] enabling display
>[  940.248844] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.248871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.248920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.248944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.248970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.248993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.249016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.249043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.249067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.249092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.249114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.249137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.249163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.249186] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.251425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.251442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.251456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.251471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.252997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.253015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.253031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.254526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.254543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.256347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.258693] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.258748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.258764] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.258786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.275489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.275515] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.275550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.275659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.275699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.292170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.292194] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.292230] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.309568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.309587] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.309607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.309624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.309641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.309656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.309670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.309686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.309703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.309720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.309736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.309752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.309766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.309779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.309806] [drm:intel_power_well_disable [i915]] disabling display
>[  940.309827] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.309848] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.309863] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.310005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.310021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.310091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.310117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.310144] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.310174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.310206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.310233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.310259] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.310285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.310310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.310334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.310357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.310363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.310385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.310391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.310414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.310437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.310461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.310484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.310508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.310531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.310555] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.310579] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.310608] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.310631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.310657] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.310721] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.310744] [drm:intel_power_well_enable [i915]] enabling display
>[  940.310766] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.310804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.310827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.310850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.310873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.310911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.310935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.310959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.310985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.311009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.311031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.311053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.311080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.311103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.313094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.313110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.313124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.313139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.314644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.314662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.314679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.316176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.316193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.318000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.320934] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.321009] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.321026] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.321048] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.337750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.337776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.337811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.338045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.338086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.354431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.354455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.354491] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.372644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.372663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.372683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.372700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.372717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.372733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.372747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.372763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.372781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.372797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.372813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.372829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.372847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.372865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.372940] [drm:intel_power_well_disable [i915]] disabling display
>[  940.372975] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.373009] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.373034] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.373155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.373170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.373239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.373265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.373292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.373323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.373347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.373373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.373399] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.373423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.373448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.373472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.373494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.373500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.373523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.373529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.373552] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.373575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.373598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.373621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.373646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.373670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.373693] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.373715] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.373736] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.373761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.373788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.373855] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.373879] [drm:intel_power_well_enable [i915]] enabling display
>[  940.373931] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.373971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.373995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.374018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.374041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.374064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.374087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.374113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.374138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.374163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.374184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.374206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.374231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.374256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.376246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.376262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.376278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.376296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.377828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.377845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.377862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.379388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.379405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.381237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.383513] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.383589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.383606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.383628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.400330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.400357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.400394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.400504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.400546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.417012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.417036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.417071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.435930] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.435948] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.435969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.435985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.436003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.436018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.436037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.436056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.436078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.436098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.436119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.436139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.436158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.436175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.436202] [drm:intel_power_well_disable [i915]] disabling display
>[  940.436225] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.436249] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.436265] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.436348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.436358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.436410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.436427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.436444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.436462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.436477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.436493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.436510] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.436527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.436545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.436562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.436579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.436583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.436600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.436603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.436621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.436639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.436656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.436674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.436691] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.436708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.436725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.436743] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.436760] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.436778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.436797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.436840] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.436854] [drm:intel_power_well_enable [i915]] enabling display
>[  940.436868] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.436927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.436951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.436976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.436999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.437023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.437046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.437073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.437098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.437123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.437146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.437168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.437194] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.437218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.439213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.439229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.439244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.439259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.440770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.440785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.440799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.442296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.442312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.444116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.447049] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.447126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.447142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.447164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.463868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.463893] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.463983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.464111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.464150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.480549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.480573] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.480609] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.499468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.499489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.499511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.499530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.499552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.499571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.499590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.499609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.499631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.499652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.499672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.499692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.499711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.499728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.499755] [drm:intel_power_well_disable [i915]] disabling display
>[  940.499778] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.499802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.499818] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.499932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.499947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.500201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.500229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.500257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.500287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.500312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.500338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.500365] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.500390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.500415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.500440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.500463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.500469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.500492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.500498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.500522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.500546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.500570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.500593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.500619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.500642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.500664] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.500693] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.500714] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.500738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.500763] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.500825] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.500847] [drm:intel_power_well_enable [i915]] enabling display
>[  940.500869] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.500928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.500954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.500979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.501002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.501025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.501049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.501076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.501101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.501125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.501147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.501170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.501196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.501219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.503441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.503457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.503471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.503486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.505005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.505023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.505037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.506534] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.506551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.508361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.511295] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.511369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.511386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.511408] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.528112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.528139] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.528176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.528279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.528321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.544792] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.544819] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.544864] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.563662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.563681] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.563701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.563717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.563735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.563751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.563765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.563780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.563798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.563814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.563830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.563849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.563868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.563887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.563960] [drm:intel_power_well_disable [i915]] disabling display
>[  940.563994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.564028] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.564053] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.564177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.564190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.564253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.564275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.564299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.564326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.564346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.564370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.564391] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.564413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.564434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.564454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.564473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.564479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.564498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.564503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.564525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.564544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.564565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.564584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.564607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.564626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.564647] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.564666] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.564686] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.564708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.564732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.564795] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.564817] [drm:intel_power_well_enable [i915]] enabling display
>[  940.564838] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.564875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.564895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.564936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.564957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.564979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.565000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.565025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.565050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.565075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.565095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.565117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.565143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.565164] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.567154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.567171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.567184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.567199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.568697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.568713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.568726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.570222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.570239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.572043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.574471] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.574547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.574564] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.574586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.591288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.591314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.591348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.591454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.591494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.607968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.607993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.608037] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.625682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.625703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.625725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.625744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.625765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.625785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.625804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.625823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.625845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.625865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.625886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.625973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.625999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.626022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.626064] [drm:intel_power_well_disable [i915]] disabling display
>[  940.626098] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.626130] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.626155] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.626278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.626293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.626360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.626383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.626416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.626443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.626463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.626486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.626507] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.626529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.626549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.626570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.626588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.626594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.626613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.626618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.626639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.626658] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.626678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.626697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.626720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.626738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.626759] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.626777] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.626797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.626821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.626845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.626923] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.626947] [drm:intel_power_well_enable [i915]] enabling display
>[  940.626969] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.627007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.627029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.627052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.627072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.627095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.627116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.627141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.627166] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.627190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.627210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.627231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.627255] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.627278] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.629266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.629283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.629297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.629311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.630845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.630860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.630874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.632370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.632386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.634191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.637120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.637149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.637166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.637188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.653891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.653934] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.653969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.654074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.654116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.670573] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.670597] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.670641] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.689502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.689521] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.689541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.689557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.689575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.689594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.689613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.689632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.689654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.689675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.689695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.689715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.689734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.689753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.689780] [drm:intel_power_well_disable [i915]] disabling display
>[  940.689803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.689827] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.689843] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.689955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.689970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.690260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.690285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.690311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.690340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.690363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.690388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.690412] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.690437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.690460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.690483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.690504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.690510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.690531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.690537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.690560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.690581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.690603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.690623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.690648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.690668] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.690690] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.690719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.690739] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.690762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.690786] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.690849] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.690871] [drm:intel_power_well_enable [i915]] enabling display
>[  940.690892] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.690951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.690973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.690996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.691017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.691038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.691059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.691084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.691108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.691134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.691154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.691176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.691201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.691223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.693475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.693492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.693506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.693521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.695031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.695046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.695062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.696556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.696573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.698378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.701324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.701387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.701403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.701425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.718130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.718156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.718190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.718291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.718330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.734809] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.734834] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.734879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.753714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.753733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.753753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.753772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.753794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.753813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.753833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.753852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.753873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.753894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.754099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.754118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.754135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.754150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.754177] [drm:intel_power_well_disable [i915]] disabling display
>[  940.754198] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.754228] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.754242] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.754314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.754322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.754361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.754376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.754393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.754410] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.754424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.754439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.754454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.754468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.754482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.754495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.754508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.754512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.754524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.754527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.754540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.754553] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.754565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.754578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.754593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.754609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.754627] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.754645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.754662] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.754680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.754699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.754741] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.754755] [drm:intel_power_well_enable [i915]] enabling display
>[  940.754769] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.754796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.754814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.754832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.754849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.754867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.754884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.754903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.754951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.754977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.754998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.755018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.755042] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.755064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.757054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.757071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.757085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.757099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.758602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.758618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.758631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.760128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.760145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.761950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.764883] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.764989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.765016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.765119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.781701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.781727] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.781762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.781868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.781908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.798382] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.798408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.798453] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.817311] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.817331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.817351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.817368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.817385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.817400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.817414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.817430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.817448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.817464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.817480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.817496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.817510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.817524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.817550] [drm:intel_power_well_disable [i915]] disabling display
>[  940.817571] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.817592] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.817608] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.817686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.817695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.817737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.817753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.817770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.817790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.817805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.817821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.817838] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.817853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.817868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.817882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.817896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.817929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.817955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.817962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.817985] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.818010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.818032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.818056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.818080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.818104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.818126] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.818149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.818171] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.818198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.818225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.818295] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.818577] [drm:intel_power_well_enable [i915]] enabling display
>[  940.818599] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.818637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.818659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.818681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.818701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.818721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.818742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.818765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.818788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.818811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.818830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.818850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.818873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.818896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.821079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.821096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.821110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.821125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.822628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.822644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.822657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.824152] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.824168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.825974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.828367] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.828427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.828444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.828467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.845196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.845221] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.845256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.845371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.845423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.861863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.861887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.861967] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.880841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.880860] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.880880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.880897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.880915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.881006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.881029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.881055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.881083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.881109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.881135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.881160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.881181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.881203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.881243] [drm:intel_power_well_disable [i915]] disabling display
>[  940.881276] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.881307] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.881333] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.881455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.881469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.881512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.881529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.881546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.881566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.881581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.881598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.881614] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.881630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.881645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.881660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.881674] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.881678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.881691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.881695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.881709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.881723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.881736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.881749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.881766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.881780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.881794] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.881812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.881831] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.881855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.881878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.881948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.881973] [drm:intel_power_well_enable [i915]] enabling display
>[  940.881996] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.882034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.882056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.882078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.882099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.882121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.882142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.882167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.882191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.882216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.882236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.882258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.882284] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.882306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.884298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.884314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.884329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.884344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.885859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.885873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.885887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.887382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.887399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.889203] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.892130] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.892160] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.892176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.892198] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.908904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.908946] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.908981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.909083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.909122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.925585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.925611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.925657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  940.944521] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  940.944540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  940.944560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.944577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.944594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.944609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.944623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.944639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.944656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.944672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.944688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.944703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.944722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.944739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.944767] [drm:intel_power_well_disable [i915]] disabling display
>[  940.944789] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  940.944814] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.944830] [drm:intel_power_well_disable [i915]] disabling always-on
>[  940.944944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.944960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  940.945203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  940.945226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  940.945252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  940.945278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  940.945299] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  940.945323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  940.945345] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  940.945367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  940.945388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  940.945409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  940.945428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  940.945434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.945454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  940.945459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  940.945480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  940.945499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  940.945520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  940.945539] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  940.945561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  940.945581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  940.945602] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  940.945621] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  940.945641] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  940.945665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.945687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  940.945750] [drm:intel_power_well_enable [i915]] enabling always-on
>[  940.945772] [drm:intel_power_well_enable [i915]] enabling display
>[  940.945793] [drm:hsw_set_power_well [i915]] Enabling power well
>[  940.945830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  940.945851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  940.945873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  940.945892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  940.945913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  940.945955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  940.945981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  940.946005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  940.946030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.946050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  940.946072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  940.946098] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  940.946119] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  940.949449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  940.949468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  940.949484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.949500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  940.952179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  940.952196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  940.952211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  940.954756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  940.954774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  940.957646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  940.960580] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  940.960656] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  940.960673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  940.960695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  940.977398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  940.977424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  940.977458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  940.977564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  940.977603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  940.994079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  940.994105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  940.994150] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.013002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.013021] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.013042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.013062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.013084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.013103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.013123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.013142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.013163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.013184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.013204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.013225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.013243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.013259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.013287] [drm:intel_power_well_disable [i915]] disabling display
>[  941.013309] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.013333] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.013350] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.013431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.013441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.013487] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.013506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.013526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.013548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.013570] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.013599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.013626] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.013641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.013655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.013668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.013681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.013684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.013697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.013700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.013713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.013726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.013738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.013755] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.013773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.013790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.013807] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.013824] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.013841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.013860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.013879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.013958] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.013979] [drm:intel_power_well_enable [i915]] enabling display
>[  941.013999] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.014038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.014060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.014081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.014102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.014123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.014144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.014168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.014191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.014213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.014233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.014252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.014276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.014297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.017397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.017418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.017437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.017456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.021178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.021197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.021213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.023778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.023803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.026678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.029612] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.029688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.029705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.029727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.046430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.046456] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.046491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.046598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.046639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.063111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.063135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.063179] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.082045] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.082064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.082084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.082101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.082119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.082134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.082148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.082164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.082182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.082198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.082214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.082229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.082243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.082256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.082283] [drm:intel_power_well_disable [i915]] disabling display
>[  941.082304] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.082325] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.082340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.082419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.082427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.082478] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.082501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.082520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.082542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.082561] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.082581] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.082600] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.082619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.082638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.082657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.082676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.082680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.082698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.082702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.082721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.082740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.082759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.082778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.082797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.082816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.082835] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.082854] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.082873] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.082893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.082914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.083016] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.083041] [drm:intel_power_well_enable [i915]] enabling display
>[  941.083066] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.083109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.083134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.083160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.083184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.083215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.083237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.083262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.083285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.083309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.083330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.083351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.083377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.083400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.085400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.085417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.085431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.085446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.090291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.090312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.090331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.092908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.092927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.095829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.098749] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.098787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.098803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.098828] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.115526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.115550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.115584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.115687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.115724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.132212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.132236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.132279] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.151136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.151155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.151175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.151192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.151209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.151225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.151240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.151256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.151273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.151290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.151306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.151321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.151335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.151349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.151376] [drm:intel_power_well_disable [i915]] disabling display
>[  941.151397] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.151418] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.151434] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.151512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.151521] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.151564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.151580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.151598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.151617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.151632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.151649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.151665] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.151680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.151702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.151715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.151728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.151731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.151744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.151747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.151761] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.151774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.151786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.151798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.151813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.151826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.151839] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.151851] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.151863] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.151881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.151900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.151982] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.152005] [drm:intel_power_well_enable [i915]] enabling display
>[  941.152028] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.152066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.152089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.152112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.152132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.152155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.152176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.152202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.152226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.152252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.152272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.152294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.152320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.152342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.155433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.155452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.155468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.155484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.159205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.159226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.159245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.161821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.161841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.164717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.167650] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.167727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.167743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.167765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.184467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.184493] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.184528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.184636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.184676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.201149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.201173] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.201216] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.220083] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.220102] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.220123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.220139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.220157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.220172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.220187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.220203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.220221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.220237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.220257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.220278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.220297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.220314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.220341] [drm:intel_power_well_disable [i915]] disabling display
>[  941.220364] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.220388] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.220405] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.220492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.220502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.220548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.220568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.220588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.220610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.220628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.220648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.220667] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.220686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.220706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.220725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.220744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.220748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.220766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.220770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.220789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.220808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.220827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.220846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.220865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.220884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.220903] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.220922] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.220980] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.221009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.221038] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.221109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.221134] [drm:intel_power_well_enable [i915]] enabling display
>[  941.221156] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.221201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.221517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.221538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.221561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.221581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.221603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.221628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.221651] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.221675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.221694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.221714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.221737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.221759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.224835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.224853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.224869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.224888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.228589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.228609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.228625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.231196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.231215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.234088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.237024] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.237104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.237124] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.237150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.253830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.253855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.253889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.254109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.254149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.270520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.270545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.270590] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.289456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.289475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.289495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.289512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.289529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.289544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.289559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.289575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.289592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.289609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.289624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.289640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.289659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.289676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.289704] [drm:intel_power_well_disable [i915]] disabling display
>[  941.289726] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.289751] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.289767] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.289849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.289859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.289905] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.289924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.289984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.290017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.290041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.290069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.290094] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.290120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.290144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.290168] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.290190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.290197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.290220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.290226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.290250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.290272] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.290296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.290317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.290343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.290365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.290388] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.290410] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.290432] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.290729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.290755] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.290815] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.290837] [drm:intel_power_well_enable [i915]] enabling display
>[  941.290858] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.290896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.290917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.290939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.290979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.291000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.291023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.291048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.291072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.291096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.291238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.291257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.291281] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.291302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.293294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.293312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.293329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.293348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.295969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.295986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.296000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.300723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.300742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.300758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.303327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.303345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.306238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.309180] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.309247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.309262] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.309284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.325998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.326024] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.326059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.326177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.326228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.342711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.342735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.342771] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.361673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.361692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.361712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.361729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.361747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.361762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.361777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.361793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.361811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.361827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.361843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.361858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.361873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.361887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.361913] [drm:intel_power_well_disable [i915]] disabling display
>[  941.361935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.362002] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.362029] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.362140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.362155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.362226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.362250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.362275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.362304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.362327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.362352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.362376] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.362400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.362430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.362452] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.362471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.362477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.362497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.362502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.362523] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.362543] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.362563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.362582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.362605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.362623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.362644] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.362666] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.362685] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.362707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.362732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.362796] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.362818] [drm:intel_power_well_enable [i915]] enabling display
>[  941.362840] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.362876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.362897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.362918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.362938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.362976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.362998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.363023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.363048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.363072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.363093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.363114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.363140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.363162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.366255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.366273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.366289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.366306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.368881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.368899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.368915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.371482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.371502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.374459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.377392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.377468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.377487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.377513] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.394211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.394236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.394271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.394379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.394419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.410890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.410916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.411000] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.429837] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.429856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.429875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.429893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.429910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.429925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.429940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.429994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.430026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.430054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.430081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.430278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.430295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.430310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.430336] [drm:intel_power_well_disable [i915]] disabling display
>[  941.430357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.430379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.430394] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.430472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.430481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.430524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.430540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.430558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.430577] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.430592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.430608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.430625] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.430640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.430655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.430669] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.430683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.430687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.430700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.430704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.430718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.430732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.430750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.430769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.430789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.430808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.430827] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.430846] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.430865] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.430885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.430906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.430983] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.431009] [drm:intel_power_well_enable [i915]] enabling display
>[  941.431031] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.431071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.431094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.431118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.431139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.431161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.431183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.431209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.431234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.431259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.431279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.431301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.431327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.431349] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.434702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.434721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.434736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.434753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.438469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.438488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.438504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.441167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.441193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.444065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.446994] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.447022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.447038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.447060] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.463764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.463790] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.463825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.463934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.464051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.480447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.480472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.480516] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.499376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.499395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.499415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.499432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.499449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.499464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.499479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.499495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.499512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.499528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.499544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.499560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.499574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.499592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.499620] [drm:intel_power_well_disable [i915]] disabling display
>[  941.499643] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.499667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.499684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.499767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.499776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.499822] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.499842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.499862] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.499884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.499903] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.499923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.499942] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.500002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.500028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.500051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.500074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.500080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.500102] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.500108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.500130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.500152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.500174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.500195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.500220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.500241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.500262] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.500284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.500306] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.500331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.500357] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.500614] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.500636] [drm:intel_power_well_enable [i915]] enabling display
>[  941.500655] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.500682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.500697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.500712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.500726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.500739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.500754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.500770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.500785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.500799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.500812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.500825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.500841] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.500856] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.503912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.503936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.503950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.503998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.506568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.506585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.506602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.509173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.509191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.512083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.515027] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.515093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.515110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.515140] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.531834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.531863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.531911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.532137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.532177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.548516] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.548540] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.548584] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.567444] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.567463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.567484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.567501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.567518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.567534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.567549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.567565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.567582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.567599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.567614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.567630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.567644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.567658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.567684] [drm:intel_power_well_disable [i915]] disabling display
>[  941.567706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.567726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.567742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.567814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.567823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.567865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.567881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.567898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.567924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.567938] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.567953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.568008] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.568034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.568058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.568081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.568103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.568109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.568130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.568137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.568159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.568180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.568202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.568224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.568248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.568270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.568292] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.568313] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.568335] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.568360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.568387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.568701] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.568724] [drm:intel_power_well_enable [i915]] enabling display
>[  941.568747] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.568786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.568809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.568832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.568855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.568877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.568899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.568924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.568948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.568990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.569012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.569034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.569060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.569083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.572330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.572349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.572365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.572381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.576090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.576115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.576129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.578690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.578709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.581579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.583577] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.583628] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.583645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.583666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.600370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.600393] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.600427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.600529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.600582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.617091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.617115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.617150] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.636015] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.636034] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.636054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.636071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.636089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.636104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.636118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.636134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.636151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.636167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.636183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.636198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.636212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.636226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.636252] [drm:intel_power_well_disable [i915]] disabling display
>[  941.636273] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.636294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.636310] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.636388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.636397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.636458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.636475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.636493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.636519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.636533] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.636549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.636567] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.636584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.636602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.636619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.636637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.636640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.636657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.636660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.636678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.636696] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.636713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.636730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.636747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.636765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.636782] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.636799] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.636817] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.636835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.636853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.636888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.636902] [drm:intel_power_well_enable [i915]] enabling display
>[  941.636916] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.636943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.636961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.637019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.637042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.637063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.637085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.637109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.637132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.637155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.637174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.637193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.637217] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.637238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.640336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.640355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.640371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.640388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.644093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.644111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.644127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.646707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.646725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.649604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.652540] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.652614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.652630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.652652] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.669361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.669387] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.669422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.669546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.669593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.686077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.686101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.686137] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.704794] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.704813] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.704833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.704850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.704868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.704883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.704898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.704914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.704931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.704947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.704963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.705022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.705049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.705074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.705118] [drm:intel_power_well_disable [i915]] disabling display
>[  941.705284] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.705316] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.705342] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.705464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.705474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.705518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.705534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.705553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.705573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.705588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.705605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.705622] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.705638] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.705653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.705668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.705682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.705685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.705699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.705703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.705717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.705731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.705745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.705758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.705774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.705788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.705802] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.705815] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.705828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.705844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.705862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.705907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.705922] [drm:intel_power_well_enable [i915]] enabling display
>[  941.705938] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.705968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.706027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.706052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.706077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.706100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.706125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.706151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.706176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.706201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.706223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.706245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.706272] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.706295] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.709621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.709638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.709653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.709669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.713350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.713367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.713382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.715945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.715963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.718856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.721789] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.721866] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.721885] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.721911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.738607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.738633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.738671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.738782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.738824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.755308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.755333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.755370] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.774238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.774257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.774277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.774294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.774312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.774328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.774347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.774366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.774388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.774409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.774429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.774449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.774468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.774485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.774512] [drm:intel_power_well_disable [i915]] disabling display
>[  941.774534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.774559] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.774575] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.774648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.774658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.774704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.774724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.774744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.774766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.774785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.774804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.774824] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.774843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.774862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.774881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.774900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.774904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.774922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.774926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.774945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.774964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.775030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.775060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.775088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.775115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.775141] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.775167] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.775191] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.775219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.775248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.775320] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.775344] [drm:intel_power_well_enable [i915]] enabling display
>[  941.775368] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.775411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.775436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.775461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.775484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.775508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.775539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.775563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.775587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.775610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.775632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.775653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.775676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.775699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.778793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.778814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.778833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.778853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.781435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.781455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.781473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.784067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.784086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.787007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.789949] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.790058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.790087] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.790121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.806768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.806794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.806829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.806933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.806973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.823459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.823485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.823524] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.842403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.842422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.842442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.842459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.842476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.842491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.842505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.842521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.842538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.842555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.842571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.842586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.842600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.842614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.842640] [drm:intel_power_well_disable [i915]] disabling display
>[  941.842662] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.842683] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.842698] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.842777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.842787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.842831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.842851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.842871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.842893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.842912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.842932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.842951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.842970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.843031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.843056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.843078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.843086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.843108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.843121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.843141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.843161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.843181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.843201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.843223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.843243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.843263] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.843282] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.843302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.843325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.843350] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.843586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.843601] [drm:intel_power_well_enable [i915]] enabling display
>[  941.843613] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.843640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.843655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.843670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.843684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.843698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.843712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.843729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.843744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.843758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.843771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.843784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.843801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.843816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.846870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.846888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.846903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.846919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.850599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.850618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.850637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.853216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.853235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.856108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.859040] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.859116] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.859132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.859155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.875859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.875885] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.875921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.876091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.876135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.892560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.892584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.892621] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.910746] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.910764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.910786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.910806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.910827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.910847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.910866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.910885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.910907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.910927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.910948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.910968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.911030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.911055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.911098] [drm:intel_power_well_disable [i915]] disabling display
>[  941.911194] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.911218] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.911235] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.911314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.911323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.911367] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.911384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.911403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.911423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.911439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.911455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.911472] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.911488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.911504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.911519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.911533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.911537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.911551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.911563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.911576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.911589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.911602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.911615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.911630] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.911643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.911656] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.911670] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.911682] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.911698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.911714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.911756] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.911769] [drm:intel_power_well_enable [i915]] enabling display
>[  941.911782] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.911807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.911825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.911843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.911860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.911878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.911895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.911915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.911934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.911953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.911970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.912010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.912035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.912058] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.914048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.914064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.914079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.914093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.917757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.917773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.917787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.920356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.920374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.923259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.926208] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.926269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.926286] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.926308] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  941.943011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.943038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.943075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.943187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.943229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.959712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  941.959736] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  941.959773] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  941.978649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  941.978668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  941.978688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.978704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.978722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.978737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.978751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.978767] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  941.978785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.978802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.978818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.978834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.978848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.978862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.978888] [drm:intel_power_well_disable [i915]] disabling display
>[  941.978909] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  941.978930] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  941.978946] [drm:intel_power_well_disable [i915]] disabling always-on
>[  941.979090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  941.979106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  941.979180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  941.979202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  941.979228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  941.979254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  941.979275] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  941.979298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  941.979319] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  941.979341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  941.979362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  941.979382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  941.979401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  941.979406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.979426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  941.979431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  941.979452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  941.979471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  941.979491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  941.979510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  941.979532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  941.979551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  941.979572] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  941.979590] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  941.979610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  941.979632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  941.979655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  941.979719] [drm:intel_power_well_enable [i915]] enabling always-on
>[  941.979741] [drm:intel_power_well_enable [i915]] enabling display
>[  941.979763] [drm:hsw_set_power_well [i915]] Enabling power well
>[  941.979799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  941.979820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  941.979841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  941.979861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  941.979881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  941.979901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  941.979925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  941.979948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  941.979971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  941.980010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  941.980030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  941.980055] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  941.980077] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  941.983171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  941.983189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  941.983203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.983218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  941.986921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  941.986941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  941.986960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  941.989581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  941.989601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  941.992500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  941.995428] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  941.995459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  941.995476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  941.995498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.012231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.012257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.012292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.012398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.012438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.028900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.028924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.028961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.047839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.047858] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.047878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.047895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.047913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.047927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.047942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.047958] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.047976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.048041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.048070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.048097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.048121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.048146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.048187] [drm:intel_power_well_disable [i915]] disabling display
>[  942.048221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.048254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.048279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.048401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.048416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.048485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.048510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.048538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.048567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.048591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.048617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.048649] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.048671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.048694] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.048715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.048736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.048742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.048762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.048767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.048789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.048810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.048831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.048849] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.048872] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.048893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.048912] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.048933] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.048953] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.048975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.049021] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.049086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.049109] [drm:intel_power_well_enable [i915]] enabling display
>[  942.049131] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.049169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.049194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.049216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.049238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.049260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.049282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.049306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.049330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.049353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.049374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.049395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.049420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.049443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.052563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.052581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.052595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.052610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.056304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.056321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.056337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.058926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.058945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.061818] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.064748] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.064775] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.064792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.064814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.081521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.081546] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.081581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.081703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.081748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.098220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.098245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.098282] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.117156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.117175] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.117194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.117211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.117228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.117243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.117258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.117283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.117306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.117322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.117337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.117353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.117366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.117380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.117406] [drm:intel_power_well_disable [i915]] disabling display
>[  942.117428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.117448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.117464] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.117541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.117550] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.117592] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.117608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.117626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.117645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.117661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.117677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.117693] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.117708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.117727] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.117746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.117765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.117769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.117788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.117791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.117811] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.117830] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.117849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.117868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.117887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.117906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.117925] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.117944] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.117963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.117983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.118049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.118120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.118145] [drm:intel_power_well_enable [i915]] enabling display
>[  942.118169] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.118219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.118242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.118265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.118286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.118307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.118328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.118353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.118377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.118400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.118420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.118440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.118463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.118485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.121574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.121593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.121609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.121625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.125346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.125363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.125378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.127942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.127960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.130837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.133771] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.133847] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.133864] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.133898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.150595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.150620] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.150653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.150760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.150798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.167270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.167294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.167343] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.186202] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.186221] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.186241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.186257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.186275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.186290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.186304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.186320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.186338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.186354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.186370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.186386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.186400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.186414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.186440] [drm:intel_power_well_disable [i915]] disabling display
>[  942.186461] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.186482] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.186497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.186578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.186587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.186629] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.186645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.186662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.186687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.186701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.186716] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.186731] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.186744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.186758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.186771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.186784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.186787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.186799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.186803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.186815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.186828] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.186841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.186853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.186867] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.186880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.186893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.186905] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.186917] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.186932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.186948] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.186990] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.187041] [drm:intel_power_well_enable [i915]] enabling display
>[  942.187062] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.187100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.187122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.187144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.187164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.187187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.187208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.187232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.187257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.187282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.187302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.187323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.187349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.187371] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.190459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.190477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.190493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.190509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.193140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.193158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.193174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.195738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.195755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.198630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.201552] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.201589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.201608] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.201634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.218331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.218357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.218392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.218493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.218534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.235029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.235056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.235095] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.253955] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.253974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.253994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.254049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.254080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.254103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.254243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.254260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.254279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.254295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.254311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.254327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.254341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.254355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.254381] [drm:intel_power_well_disable [i915]] disabling display
>[  942.254402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.254424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.254439] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.254509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.254518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.254560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.254577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.254595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.254614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.254629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.254645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.254664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.254683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.254703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.254722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.254741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.254745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.254763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.254767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.254787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.254806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.254825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.254844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.254863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.254882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.254901] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.254920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.254939] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.254959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.254980] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.255068] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.255093] [drm:intel_power_well_enable [i915]] enabling display
>[  942.255117] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.255167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.255190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.255213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.255234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.255256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.255278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.255303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.255327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.255609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.255630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.255651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.255675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.255698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.258789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.258808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.258824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.258840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.262522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.262540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.262557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.265146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.265164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.268041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.270973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.271089] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.271110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.271133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.287793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.287818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.287853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.287962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.288002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.304474] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.304499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.304543] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.323396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.323415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.323435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.323452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.323470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.323486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.323501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.323517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.323534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.323550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.323566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.323582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.323596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.323610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.323636] [drm:intel_power_well_disable [i915]] disabling display
>[  942.323657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.323681] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.323698] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.323778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.323788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.323834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.323854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.323873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.323895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.323914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.323934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.323953] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.323972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.323991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.324053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.324077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.324084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.324106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.324113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.324136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.324158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.324180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.324201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.324226] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.324248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.324270] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.324291] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.324312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.324337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.324363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.324432] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.324454] [drm:intel_power_well_enable [i915]] enabling display
>[  942.324470] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.324504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.324519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.324533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.324546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.324559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.324573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.324589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.324603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.324618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.324631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.324643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.324659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.324674] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.327753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.327772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.327788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.327804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.331521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.331539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.331555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.334148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.334168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.337067] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.340035] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.340076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.340093] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.340115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.356858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.356884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.356918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.357068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.357127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.373543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.373570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.373605] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.392476] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.392495] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.392515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.392532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.392550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.392565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.392580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.392596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.392617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.392637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.392658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.392678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.392697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.392714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.392741] [drm:intel_power_well_disable [i915]] disabling display
>[  942.392764] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.392788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.392804] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.392887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.392897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.392943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.392963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.392983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.393005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.393068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.393093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.393116] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.393138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.393159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.393179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.393199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.393205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.393225] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.393230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.393250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.393270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.393290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.393309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.393331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.393351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.393371] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.393390] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.393409] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.393433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.393458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.393521] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.393544] [drm:intel_power_well_enable [i915]] enabling display
>[  942.393566] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.393605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.393628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.393651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.393673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.393694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.393717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.393740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.393756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.393770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.393783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.393796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.393812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.393826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.396904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.396922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.396938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.396954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.399554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.399573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.399589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.402187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.402207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.405097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.408041] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.408108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.408125] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.408148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.424840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.424864] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.424898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.425133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.425179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.441531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.441555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.441599] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.460477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.460496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.460516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.460532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.460550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.460565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.460579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.460595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.460613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.460629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.460644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.460660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.460674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.460688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.460714] [drm:intel_power_well_disable [i915]] disabling display
>[  942.460735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.460756] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.460771] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.460842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.460851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.460893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.460909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.460927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.460946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.460961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.460977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.460993] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.461009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.461060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.461083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.461105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.461112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.461133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.461139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.461161] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.461182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.461204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.461224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.461249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.461270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.461291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.461312] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.461333] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.461358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.461383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.461615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.461629] [drm:intel_power_well_enable [i915]] enabling display
>[  942.461643] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.461669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.461685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.461699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.461713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.461727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.461742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.461758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.461773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.461787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.461800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.461814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.461830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.461845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.464902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.464920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.464936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.464952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.468670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.468689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.468704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.471272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.471292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.474183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.477117] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.477194] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.477211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.477233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.493934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.493960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.493998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.494204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.494244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.510616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.510641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.510685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.529546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.529565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.529585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.529601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.529619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.529633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.529648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.529663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.529681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.529697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.529712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.529728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.529742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.529761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.529788] [drm:intel_power_well_disable [i915]] disabling display
>[  942.529811] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.529835] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.529852] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.529932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.529942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.529988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.530008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.530069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.530099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.530122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.530148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.530173] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.530196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.530219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.530242] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.530263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.530270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.530291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.530297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.530319] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.530340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.530364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.530560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.530578] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.530594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.530610] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.530625] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.530639] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.530657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.530676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.530721] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.530735] [drm:intel_power_well_enable [i915]] enabling display
>[  942.530749] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.530776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.530792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.530808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.530823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.530837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.530860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.530875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.530890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.530904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.530917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.530930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.530947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.530969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.534048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.534066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.534082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.534101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.537772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.537791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.537807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.540369] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.540388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.543263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.546198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.546273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.546291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.546313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.563013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.563056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.563091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.563199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.563239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.579714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.579738] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.579775] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.598645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.598663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.598685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.598705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.598726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.598746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.598765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.598784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.598806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.598827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.598847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.598867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.598886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.598902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.598930] [drm:intel_power_well_disable [i915]] disabling display
>[  942.598952] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.598976] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.598993] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.599221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.599238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.599281] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.599298] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.599316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.599334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.599348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.599364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.599380] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.599395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.599410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.599427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.599445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.599449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.599467] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.599470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.599489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.599507] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.599525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.599542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.599561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.599578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.599596] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.599614] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.599632] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.599651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.599670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.599712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.599726] [drm:intel_power_well_enable [i915]] enabling display
>[  942.599741] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.599769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.599787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.599805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.599823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.599848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.599873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.599890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.599909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.599927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.599945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.599962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.599982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.600000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.603101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.603119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.603135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.603152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.605731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.605749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.605764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.608355] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.608374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.611160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.614108] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.614170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.614187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.614212] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.630912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.630939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.630976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.631209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.631249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.647612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.647638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.647677] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.666550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.666571] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.666592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.666612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.666634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.666653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.666672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.666698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.666724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.666741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.666757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.666773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.666787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.666801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.666828] [drm:intel_power_well_disable [i915]] disabling display
>[  942.666850] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.666874] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.666891] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.666964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.666973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.667019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.667079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.667106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.667135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.667158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.667183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.667208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.667232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.667255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.667277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.667298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.667305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.667326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.667333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.667355] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.667378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.667562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.667578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.667595] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.667610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.667625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.667644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.667663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.667685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.667705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.667757] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.667771] [drm:intel_power_well_enable [i915]] enabling display
>[  942.667784] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.667811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.667826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.667841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.667855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.667868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.667883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.667899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.667914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.667928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.667941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.667954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.667970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.667984] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.671072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.671091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.671107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.671123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.674806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.674825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.674841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.677405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.677424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.680296] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.683239] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.683312] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.683329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.683351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.700058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.700082] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.700116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.700216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.700254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.716752] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.716777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.716817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.735700] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.735719] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.735738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.735755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.735773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.735788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.735802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.735818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.735836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.735852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.735868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.735884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.735898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.735911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.735938] [drm:intel_power_well_disable [i915]] disabling display
>[  942.735959] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.735980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.735996] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.736267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.736276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.736319] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.736338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.736356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.736377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.736395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.736413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.736431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.736449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.736467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.736485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.736503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.736507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.736524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.736528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.736546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.736564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.736582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.736599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.736617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.736634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.736652] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.736670] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.736687] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.736706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.736725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.736768] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.736782] [drm:intel_power_well_enable [i915]] enabling display
>[  942.736796] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.736824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.736842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.736861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.736879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.736897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.736915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.736935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.736954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.736973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.736991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.737006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.737025] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.737065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.740150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.740169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.740183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.740199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.743881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.743900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.743919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.746495] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.746512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.749399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.752356] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.752408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.752425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.752447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.769150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.769176] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.769211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.769318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.769357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.785828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.785850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.785894] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.804759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.804778] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.804799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.804816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.804834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.804849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.804864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.804880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.804898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.804918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.804939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.804959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.804978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.804995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.805023] [drm:intel_power_well_disable [i915]] disabling display
>[  942.805092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.805127] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.805224] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.805304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.805314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.805358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.805378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.805398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.805420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.805439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.805460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.805479] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.805499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.805518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.805538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.805558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.805562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.805581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.805585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.805605] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.805624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.805644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.805663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.805682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.805708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.805726] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.805741] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.805758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.805777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.805797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.805839] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.805854] [drm:intel_power_well_enable [i915]] enabling display
>[  942.805868] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.805896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.805914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.805932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.805950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.805968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.805985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.806005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.806024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.806067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.806089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.806110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.806134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.806157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.809228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.809247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.809263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.809279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.812973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.812989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.813004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.814498] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  942.814514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.818502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.821457] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.821511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.821528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.821549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.838252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.838278] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.838312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.838421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.838461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.854934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.854958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.855002] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.873831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.873849] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.873869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.873886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.873903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.873919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.873933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.873950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.873967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.873984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.873999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.874015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.874029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.874087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.874128] [drm:intel_power_well_disable [i915]] disabling display
>[  942.874162] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.874193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.874218] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.874334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.874348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.874410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.874431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.874455] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.874482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.874502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.874525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.874547] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.874569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.874589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.874610] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.874629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.874635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.874654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.874659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.874681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.874700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.874720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.874739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.874762] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.874781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.874802] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.874821] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.874841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.874862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.874886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.874949] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.874970] [drm:intel_power_well_enable [i915]] enabling display
>[  942.874992] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.875028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.875068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.875091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.875111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.875133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.875154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.875179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.875204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.875229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.875248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.875270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.875295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.875317] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.878382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.878398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.878421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.878437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.882130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.882150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.882169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.884740] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.884760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.887639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.890568] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.890597] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.890614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.890636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.907330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.907354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.907388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.907486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.907524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.924011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.924034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.924234] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  942.942794] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  942.942813] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  942.942834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.942850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.942868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.942883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.942898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.942915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.942933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.942949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.942965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.942981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.942995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.943009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.943035] [drm:intel_power_well_disable [i915]] disabling display
>[  942.943102] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  942.943136] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.943163] [drm:intel_power_well_disable [i915]] disabling always-on
>[  942.943282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.943296] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  942.943366] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  942.943390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  942.943418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  942.943447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  942.943470] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  942.943495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  942.943518] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  942.943542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  942.943565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  942.943587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  942.943608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  942.943614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.943635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  942.943641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  942.943664] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  942.943685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  942.943707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  942.943728] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  942.943753] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  942.943773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  942.943795] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  942.943823] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  942.943844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  942.943865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.943889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  942.943953] [drm:intel_power_well_enable [i915]] enabling always-on
>[  942.943975] [drm:intel_power_well_enable [i915]] enabling display
>[  942.943996] [drm:hsw_set_power_well [i915]] Enabling power well
>[  942.944033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  942.944074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  942.944097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  942.944118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  942.944140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  942.944161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  942.944186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  942.944210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  942.944234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.944254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  942.944275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  942.944301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  942.944323] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  942.947413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  942.947432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  942.947448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.947464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  942.951182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  942.951202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  942.951221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  942.953780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  942.953799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  942.956677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  942.959599] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  942.959635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  942.959651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  942.959673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  942.976366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  942.976389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  942.976422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  942.976526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  942.976565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  942.993073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  942.993097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  942.993136] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  943.010797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  943.010816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.010836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.010853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.010870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.010885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.010900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.010916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.010934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.010950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.010966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.010981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.010996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.011010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.011036] [drm:intel_power_well_disable [i915]] disabling display
>[  943.011106] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.011141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.011168] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.011417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.011430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.011494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.011517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.011543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.011570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.011592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.011616] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.011639] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  943.011662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  943.011685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.011706] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.011727] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.011733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.011753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.011759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.011780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.011801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.011822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.011842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.011864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.011885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.011906] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  943.011925] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  943.011946] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  943.011967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.011992] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  943.012072] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.012096] [drm:intel_power_well_enable [i915]] enabling display
>[  943.012121] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.012159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.012183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.012207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.012229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.012253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.012276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.012301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.012326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.012349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.012578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.012592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.012609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  943.012624] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.015705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.015724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.015740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.015756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.018353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.018378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.018396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.022042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.022075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.024945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.027865] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  943.027902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.027919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  943.027941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.044644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.044670] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.044704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.044810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.044849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.061327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  943.061352] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.061395] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  943.080264] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  943.080283] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.080303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.080320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.080338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.080354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.080369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.080385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.080403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.080419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.080435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.080450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.080465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.080478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.080505] [drm:intel_power_well_disable [i915]] disabling display
>[  943.080528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.080552] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.080569] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.080657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.080666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.080708] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.080724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.080742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.080763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.080781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.080800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.080819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  943.080838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  943.080857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.080875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.080893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.080897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.080915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.080918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.080937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.080956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.080974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.080992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.081011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.081029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.081047] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  943.081108] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  943.081134] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  943.081161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.081190] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  943.081256] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.081280] [drm:intel_power_well_enable [i915]] enabling display
>[  943.081304] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.081344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.081367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.081390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.081413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.081436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.081461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.081488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.081513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.081538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.081560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.081582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.081609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  943.081633] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.084733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.084752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.084768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.084784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.088480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.088499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.088515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.091099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.091119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.093992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.096928] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  943.097000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.097015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  943.097036] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.113732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.113757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.113792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.113891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.113931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.130454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  943.130478] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.130514] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  943.149367] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  943.149386] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.149406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.149423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.149441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.149456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.149470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.149486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.149503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.149520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.149535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.149551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.149565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.149579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.149605] [drm:intel_power_well_disable [i915]] disabling display
>[  943.149626] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.149647] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.149663] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.149738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.149748] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.149790] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.149806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.149823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.149843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.149858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.149874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.149891] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  943.149906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  943.149921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.149939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.149958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.149962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.149981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.149985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.150004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.150023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.150043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.150108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.150139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.150166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.150200] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  943.150223] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  943.150246] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  943.150272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.150298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  943.150364] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.150387] [drm:intel_power_well_enable [i915]] enabling display
>[  943.150409] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.150447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.150471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.150493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.150515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.150537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.150560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.150584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.150607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.150631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.150652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.150671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.150696] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  943.150719] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.153830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.153849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.153865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.153881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.157585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.157604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.157621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.160217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.160236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.163148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.166098] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  943.166157] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.166174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  943.166196] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.182903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.182930] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.182967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.183181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.183228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.199600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  943.199624] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.199663] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  943.218546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  943.218564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.218584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.218601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.218619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.218634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.218648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.218664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.218682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.218698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.218714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.218730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.218744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.218758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.218784] [drm:intel_power_well_disable [i915]] disabling display
>[  943.218805] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.218826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  943.218842] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.219024] [drm:drm_mode_addfb2] [FB:75]
>[  943.219101] [drm:drm_mode_addfb2] [FB:78]
>[  943.245320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  943.245411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  943.245470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.245527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.245536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.245582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.245600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.245618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.245637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.245652] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.245668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.245683] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.245698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.245712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.245725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.245738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.245742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.245754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.245758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.245775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.245792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.245810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.245827] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.245845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.245863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.245880] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.245898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.245915] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.245934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.245953] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.248512] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.248529] [drm:intel_power_well_enable [i915]] enabling display
>[  943.248543] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.248574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.248591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.248607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.248622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.248637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.248653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.248670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.248686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.248701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.248715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.248729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.248747] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.248765] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.251846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.251865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.251882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.251898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.254476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.254493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.254508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.257099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.257117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.259994] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.262939] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.263005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.263022] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.263045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.279749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.279776] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.279814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.296427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.296438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.313179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.313222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.329791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.329816] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.329861] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.348725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.348744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.348764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.348781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.348798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.348813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.348828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.348844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.348861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.348877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.348893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.348908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.348926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.348944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.348972] [drm:intel_power_well_disable [i915]] disabling display
>[  943.348994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.349018] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.349035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.349372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.349387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.349459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.349483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.349511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.349540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.349569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.349593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.349615] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.349637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.349658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.349679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.349698] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.349703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.349723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.349728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.349749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.349768] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.349788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.349806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.349829] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.349848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.349869] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.349888] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.349908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.349932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.349956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.350020] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.350042] [drm:intel_power_well_enable [i915]] enabling display
>[  943.350062] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.350121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.350143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.350166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.350188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.350210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.350231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.350256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.350281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.350306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.350326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.350347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.350373] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.350395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.353729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.353748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.353764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.353780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.357467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.357485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.357501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.360101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.360119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.363016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.365500] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.365571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.365588] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.365610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.382311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.382337] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.382373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.382480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.382520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.399007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.399031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.399069] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.417779] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.417798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.417818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.417835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.417853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.417868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.417883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.417901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.417923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.417944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.417964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.417984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.418003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.418020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.418048] [drm:intel_power_well_disable [i915]] disabling display
>[  943.418109] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.418147] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.418174] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.418297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.418312] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.418381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.418406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.418433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.418462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.418485] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.418510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.418534] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.418558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.418580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.418603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.418624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.418630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.418651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.418657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.418680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.418700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.418723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.418743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.418768] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.418788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.418811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.418831] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.418853] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.418876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.418903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.418975] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.418996] [drm:intel_power_well_enable [i915]] enabling display
>[  943.419018] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.419066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.419106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.419128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.419150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.419171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.419194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.419218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.419242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.419267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.419287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.419308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.419334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.419355] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.422441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.422461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.422480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.422500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.426202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.426221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.426237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.428801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.428820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.431696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.434620] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.434654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.434671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.434693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.451386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.451411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.451444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.451549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.451586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.468068] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.468113] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.468157] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.487009] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.487028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.487049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.487069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.487131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.487157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.487182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.487207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.487236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.487262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.487287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.487312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.487332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.487354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.487395] [drm:intel_power_well_disable [i915]] disabling display
>[  943.487427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.487460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.487486] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.487608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.487622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.487684] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.487701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.487719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.487739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.487754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.487771] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.487788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.487803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.487819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.487833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.487847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.487851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.487865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.487869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.487883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.487897] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.487911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.487924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.487941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.487954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.487968] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.487982] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.487995] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.488012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.488029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.488105] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.488129] [drm:intel_power_well_enable [i915]] enabling display
>[  943.488153] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.488194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.488216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.488247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.488266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.488287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.488307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.488330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.488353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.488376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.488395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.488416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.488438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.488460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.491547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.491566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.491582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.491598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.495342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.495361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.495377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.497944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.497963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.500840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.503764] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.503797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.503814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.503835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.520541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.520568] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.520606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.520708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.520750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.537242] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.537267] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.537304] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.555460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.555479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.555499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.555516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.555534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.555553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.555573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.555592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.555614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.555635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.555655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.555675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.555694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.555710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.555738] [drm:intel_power_well_disable [i915]] disabling display
>[  943.555760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.555785] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.555801] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.555875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.555885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.555931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.555951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.555971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.555993] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.556012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.556032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.556051] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.556070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.556131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.556156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.556178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.556185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.556207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.556213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.556235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.556257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.556279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.556300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.556325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.556346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.556368] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.556389] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.556411] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.556436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.556462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.556709] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.556724] [drm:intel_power_well_enable [i915]] enabling display
>[  943.556738] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.556767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.556784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.556808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.556825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.556844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.556861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.556881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.556900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.556920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.556938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.556956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.556975] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.556993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.560070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.560099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.560115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.560132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.563817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.563836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.563852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.566415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.566433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.569309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.572246] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.572319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.572336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.572358] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.589059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.589126] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.589184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.589305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.589344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.605757] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.605783] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.605822] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.623969] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.623988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.624008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.624025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.624043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.624058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.624073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.624130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.624160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.624187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.624214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.624240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.624263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.624284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.624312] [drm:intel_power_well_disable [i915]] disabling display
>[  943.624335] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.624360] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.624377] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.624460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.624470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.624516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.624537] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.624558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.624581] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.624600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.624621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.624640] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.624660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.624679] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.624696] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.624715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.624720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.624738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.624743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.624762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.624782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.624800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.624819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.624839] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.624858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.624878] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.624898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.624917] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.624937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.624959] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.625005] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.625022] [drm:intel_power_well_enable [i915]] enabling display
>[  943.625037] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.625067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.625111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.625137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.625160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.625183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.625214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.625238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.625262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.625284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.625303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.625323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.625348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.625369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.628452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.628471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.628486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.628503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.631118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.631137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.631152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.633720] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.633738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.636619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.639547] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.639576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.639592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.639614] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.656320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.656346] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.656382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.656489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.656529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.673020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.673044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.673081] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.691789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.691808] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.691828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.691845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.691862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.691877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.691896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.691916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.691937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.691958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.691978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.691999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.692018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.692034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.692061] [drm:intel_power_well_disable [i915]] disabling display
>[  943.692125] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.692160] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.692184] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.692308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.692323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.692394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.692415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.692435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.692455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.692471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.692489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.692506] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.692523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.692539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.692554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.692569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.692574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.692587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.692591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.692606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.692620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.692635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.692648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.692665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.692679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.692704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.692717] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.692734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.692753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.692784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.692829] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.692842] [drm:intel_power_well_enable [i915]] enabling display
>[  943.692855] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.692881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.692896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.692910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.692923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.692936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.692951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.692966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.692980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.692995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.693012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.693030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.693048] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.693067] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.696166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.696185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.696202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.696218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.699887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.699904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.699919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.702482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.702501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.705368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.708311] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.708378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.708395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.708417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.725120] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.725147] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.725183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.725296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.725338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.741819] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.741846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.741884] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.760022] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.760041] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.760061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.760079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.760139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.760164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.760190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.760214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.760243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.760269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.760295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.760321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.760343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.760366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.760406] [drm:intel_power_well_disable [i915]] disabling display
>[  943.760439] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.760470] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.760495] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.760603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.760618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.760687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.760710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.760736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.760765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.760788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.760813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.760837] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.760861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.760883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.760906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.760926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.760932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.760954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.760959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.760983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.761003] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.761032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.761051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.761073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.761116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.761139] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.761160] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.761180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.761204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.761230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.761294] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.761316] [drm:intel_power_well_enable [i915]] enabling display
>[  943.761338] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.761375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.761396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.761417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.761437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.761458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.761478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.761501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.761524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.761548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.761567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.761587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.761610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.761632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.764717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.764734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.764749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.764765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.768492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.768511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.768527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.771130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.771149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.774025] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.776969] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.777035] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.777055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.777081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.793785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.793811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.793846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.793956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.793996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.810475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.810499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.810537] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.828866] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.828885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.828905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.828923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.828940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.828956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.828970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.828986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.829004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.829020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.829036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.829055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.829074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.829092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.829203] [drm:intel_power_well_disable [i915]] disabling display
>[  943.829237] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.829271] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.829297] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.829420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.829435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.829506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.829530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.829555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.829582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.829605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.829629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.829653] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.829676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.829699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.829720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.829742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.829748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.829768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.829773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.829795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.829817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.829838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.829858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.829880] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.829901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.829922] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.829943] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.829962] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.829985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.830010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.830071] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.830093] [drm:intel_power_well_enable [i915]] enabling display
>[  943.830138] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.830177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.830201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.830225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.830247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.830271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.830294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.830320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.830345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.830369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.830391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.830413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.830439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.830463] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.833535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.833552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.833568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.833584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.837280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.837300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.837315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.839878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.839898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.842773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.845712] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.845780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.845795] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.845815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.862523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.862549] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.862584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.862690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.862730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.879205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.879231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.879276] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.898126] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.898147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.898168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.898188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.898209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.898229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.898248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.898267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.898289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.898309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.898330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.898350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.898369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.898385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.898412] [drm:intel_power_well_disable [i915]] disabling display
>[  943.898435] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.898459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.898476] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.898557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.898566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.898612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.898632] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.898652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.898674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.898692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.898712] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.898731] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.898750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.898770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.898788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.898813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.898817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.898832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.898836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.898850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.898864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.898877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.898890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.898906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.898919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.898932] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.898945] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.898957] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.898973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.898989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.899030] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.899043] [drm:intel_power_well_enable [i915]] enabling display
>[  943.899056] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.899083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.899129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.899152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.899176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.899199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.899222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.899247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.899272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.899296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.899318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.899340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.899366] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.899390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.902467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.902485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.902501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.902517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.906208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.906228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.906247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.908810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.908829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.911703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.914626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.914661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.914677] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.914699] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  943.931402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.931429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.931464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.931572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.931612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.948085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  943.948126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  943.948169] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  943.967025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  943.967044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  943.967064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.967081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.967099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.967155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.967179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.967207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  943.967237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.967385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.967412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.967438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.967461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.967483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.967522] [drm:intel_power_well_disable [i915]] disabling display
>[  943.967556] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  943.967588] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  943.967613] [drm:intel_power_well_disable [i915]] disabling always-on
>[  943.967708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  943.967717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  943.967760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  943.967777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  943.967795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  943.967814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  943.967830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  943.967846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  943.967862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  943.967878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  943.967893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  943.967907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  943.967922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  943.967925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.967939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  943.967943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  943.967961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  943.967981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  943.968000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  943.968019] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  943.968038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  943.968057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  943.968076] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  943.968095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  943.968148] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  943.968177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  943.968208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  943.968276] [drm:intel_power_well_enable [i915]] enabling always-on
>[  943.968301] [drm:intel_power_well_enable [i915]] enabling display
>[  943.968326] [drm:hsw_set_power_well [i915]] Enabling power well
>[  943.968571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  943.968596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  943.968619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  943.968641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  943.968664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  943.968687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  943.968712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  943.968736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  943.968760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  943.968782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  943.968803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  943.968828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  943.968851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  943.971939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  943.971958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  943.971974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.971990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  943.975703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  943.975722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  943.975738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  943.978320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  943.978340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  943.981219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  943.984159] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  943.984238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  943.984262] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  943.984297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.000979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.001005] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.001038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.001284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.001340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.017679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.017706] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.017746] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.036538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.036557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.036579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.036599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.036621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.036640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.036660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.036679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.036701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.036721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.036742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.036762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.036781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.036798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.036827] [drm:intel_power_well_disable [i915]] disabling display
>[  944.036849] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.036875] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.036891] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.036984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.036993] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.037042] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.037062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.037082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.037104] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.037158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.037186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.037212] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.037235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.037259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.037281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.037302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.037310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.037330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.037337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.037359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.037380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.037402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.037423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.037447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.037469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.037490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.037512] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.037533] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.037558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.037586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.037653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.037668] [drm:intel_power_well_enable [i915]] enabling display
>[  944.037681] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.037707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.037722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.037736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.037749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.037761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.037775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.037791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.037806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.037820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.037833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.037845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.037861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.037876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.040929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.040947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.040963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.040979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.044703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.044723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.044742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.047310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.047329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.050204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.053142] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.053215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.053234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.053261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.069955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.069981] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.070017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.070175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.070235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.086636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.086660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.086695] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.105588] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.105607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.105627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.105643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.105661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.105676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.105695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.105714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.105736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.105756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.105777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.105797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.105816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.105832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.105860] [drm:intel_power_well_disable [i915]] disabling display
>[  944.105883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.105907] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.105923] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.106004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.106013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.106065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.106082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.106099] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.106155] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.106178] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.106205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.106231] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.106255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.106279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.106302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.106324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.106331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.106352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.106359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.106381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.106403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.106425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.106447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.106472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.106493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.106516] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.106538] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.106560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.106585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.106611] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.106675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.106698] [drm:intel_power_well_enable [i915]] enabling display
>[  944.106720] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.106758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.106780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.106802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.106824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.106845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.106866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.106890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.106914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.106937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.106959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.106979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.107005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.107028] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.110121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.110154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.110171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.110187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.113866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.113885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.113901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.116460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.116479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.119370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.122308] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.122379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.122403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.122423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.139136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.139161] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.139195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.139297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.139335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.155814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.155836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.155882] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.174757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.174776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.174796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.174813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.174831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.174846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.174860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.174876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.174894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.174910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.174926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.174941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.174955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.174969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.174996] [drm:intel_power_well_disable [i915]] disabling display
>[  944.175017] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.175038] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.175053] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.175163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.175178] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.175247] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.175274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.175302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.175332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.175356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.175377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.175394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.175410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.175426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.175441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.175455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.175459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.175477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.175481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.175501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.175521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.175546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.175560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.175576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.175590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.175604] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.175617] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.175630] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.175645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.175662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.175705] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.175720] [drm:intel_power_well_enable [i915]] enabling display
>[  944.175734] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.175762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.175780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.175798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.175816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.175834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.175852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.175872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.175892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.175911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.175928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.175946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.175965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.175983] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.179057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.179076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.179092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.179108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.181731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.181751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.181769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.184356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.184375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.187254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.190200] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.190264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.190280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.190303] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.207006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.207033] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.207069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.207237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.207277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.223707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.223733] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.223780] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.242658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.242679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.242701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.242721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.242742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.242762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.242781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.242800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.242822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.242843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.242863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.242884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.242903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.242919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.242947] [drm:intel_power_well_disable [i915]] disabling display
>[  944.242969] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.242994] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.243010] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.243090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.243099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.243200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.243229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.243259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.243290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.243528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.243555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.243582] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.243608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.243633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.243657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.243681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.243687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.243710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.243716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.243740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.243763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.243787] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.243811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.243837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.243860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.243883] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.243905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.243935] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.243959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.243984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.244048] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.244071] [drm:intel_power_well_enable [i915]] enabling display
>[  944.244093] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.244152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.244177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.244202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.244225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.244248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.244271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.244297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.244322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.244347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.244368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.244391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.244416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.244440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.247745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.247764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.247780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.247796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.251476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.251496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.251515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.254083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.254102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.257008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.259934] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.259966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.259986] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.260011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.276708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.276735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.276770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.276876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.276916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.293390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.293414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.293449] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.312292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.312311] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.312331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.312348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.312366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.312381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.312396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.312412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.312430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.312446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.312466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.312486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.312505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.312523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.312550] [drm:intel_power_well_disable [i915]] disabling display
>[  944.312572] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.312596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.312613] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.312693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.312702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.312748] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.312768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.312787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.312809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.312828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.312848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.312867] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.312886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.312906] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.312925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.312943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.312947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.312966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.312969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.312989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.313008] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.313027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.313046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.313065] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.313084] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.313103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.313122] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.313189] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.313221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.313250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.313321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.313345] [drm:intel_power_well_enable [i915]] enabling display
>[  944.313370] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.313412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.313438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.313463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.313495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.313517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.313541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.313566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.313590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.313614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.313635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.313657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.313681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.313704] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.315707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.315725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.315740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.315755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.318350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.318369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.318388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.320958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.320977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.323862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.326803] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.326871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.326887] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.326909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.343641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.343667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.343702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.343813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.343854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.360310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.360334] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.360379] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.379249] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.379268] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.379288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.379305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.379322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.379337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.379351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.379367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.379388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.379409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.379429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.379450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.379469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.379485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.379512] [drm:intel_power_well_disable [i915]] disabling display
>[  944.379534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.379559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.379575] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.379657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.379666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.379712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.379732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.379752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.379774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.379793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.379813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.379832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.379851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.379871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.379889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.379908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.379912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.379931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.379934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.379954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.379981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.379998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.380013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.380029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.380043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.380058] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.380071] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.380084] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.380099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.380116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.380212] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.380233] [drm:intel_power_well_enable [i915]] enabling display
>[  944.380256] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.380294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.380318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.380342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.380364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.380387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.380410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.380436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.380762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.380787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.380810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.380832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.380857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.380881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.383966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.383984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.383998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.384013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.387707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.387724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.387740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.390320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.390340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.393237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.397263] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.397315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.397331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.397352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.414053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.414078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.414112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.414310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.414356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.430772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.430796] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.430842] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.449714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.449732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.449752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.449769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.449787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.449802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.449816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.449832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.449850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.449866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.449882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.449897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.449911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.449930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.449957] [drm:intel_power_well_disable [i915]] disabling display
>[  944.449979] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.450004] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.450020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.450098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.450107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.450207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.450235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.450265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.450295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.450321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.450354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.450555] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.450578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.450601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.450623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.450645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.450651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.450672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.450677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.450699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.450721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.450740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.450761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.450785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.450806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.450828] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.450850] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.450871] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.450893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.450918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.450982] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.451004] [drm:intel_power_well_enable [i915]] enabling display
>[  944.451027] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.451065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.451088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.451110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.451131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.451170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.451193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.451219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.451244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.451268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.451290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.451312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.451338] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.451361] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.454650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.454669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.454685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.454701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.458493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.458519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.458533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.461097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.461116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.464019] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.466955] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.467029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.467047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.467069] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.483770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.483796] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.483831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.483937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.483977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.500471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.500495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.500540] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.519415] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.519433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.519453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.519470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.519487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.519502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.519516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.519532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.519549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.519569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.519590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.519610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.519629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.519646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.519673] [drm:intel_power_well_disable [i915]] disabling display
>[  944.519695] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.519719] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.519736] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.519815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.519824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.519870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.519889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.519916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.519935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.519950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.519966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.519983] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.519998] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.520012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.520025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.520038] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.520042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.520054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.520057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.520070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.520083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.520096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.520108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.520123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.520178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.520198] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.520218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.520238] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.520261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.520285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.520349] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.520371] [drm:intel_power_well_enable [i915]] enabling display
>[  944.520391] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.520428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.520444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.520457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.520471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.520484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.520499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.520514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.520528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.520543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.520560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.520577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.520596] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.520614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.523701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.523720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.523736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.523752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.527443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.527460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.527475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.530045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.530063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.532937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.535873] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.535946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.535963] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.535984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.552688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.552714] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.552749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.552856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.552896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.569369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.569393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.569428] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.588255] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.588274] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.588294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.588311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.588329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.588344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.588359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.588375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.588392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.588409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.588425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.588441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.588455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.588468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.588494] [drm:intel_power_well_disable [i915]] disabling display
>[  944.588516] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.588536] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.588552] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.588631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.588639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.588681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.588697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.588715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.588734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.588749] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.588766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.588782] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.588797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.588816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.588835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.588854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.588858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.588877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.588880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.588900] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.588919] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.588938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.588957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.588976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.588994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.589013] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.589033] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.589052] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.589072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.589092] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.589173] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.589196] [drm:intel_power_well_enable [i915]] enabling display
>[  944.589218] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.589261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.589286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.589310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.589332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.589354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.589377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.589403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.589428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.589453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.589475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.589496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.589522] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.589553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.592842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.592862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.592878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.592894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.596578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.596595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.596611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.599216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.599235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.602105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.605041] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.605115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.605132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.605200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.621855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.621882] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.621919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.622020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.622062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.638537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.638561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.638597] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.657434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.657453] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.657473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.657490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.657507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.657523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.657537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.657553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.657571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.657588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.657604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.657620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.657634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.657648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.657674] [drm:intel_power_well_disable [i915]] disabling display
>[  944.657696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.657721] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.657737] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.657810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.657819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.657865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.657885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.657904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.657926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.657952] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.657970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.657986] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.658001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.658015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.658028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.658041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.658044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.658057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.658060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.658073] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.658086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.658098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.658110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.658125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.658138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.658191] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.658211] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.658231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.658253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.658277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.658339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.658361] [drm:intel_power_well_enable [i915]] enabling display
>[  944.658383] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.658422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.658445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.658466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.658488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.658509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.658532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.658557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.658580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.658603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.658624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.658641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.658657] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.658672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.662829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.662847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.662862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.662877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.666553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.666571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.666586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.669177] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.669193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.672081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.675026] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.675091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.675107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.675129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.691834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.691860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.691895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.692001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.692042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.708513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.708537] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.708572] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.726908] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.726928] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.726950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.726970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.726991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.727011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.727030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.727050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.727071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.727092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.727112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.727132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.727194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.727219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.727262] [drm:intel_power_well_disable [i915]] disabling display
>[  944.727361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.727385] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.727401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.727476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.727485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.727529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.727546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.727564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.727584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.727600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.727617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.727634] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.727650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.727665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.727680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.727694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.727698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.727713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.727716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.727731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.727745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.727764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.727783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.727803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.727822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.727842] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.727861] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.727880] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.727901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.727923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.727984] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.727998] [drm:intel_power_well_enable [i915]] enabling display
>[  944.728013] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.728042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.728059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.728078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.728098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.728118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.728137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.728185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.728212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.728238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.728267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.728287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.728311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.728332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.731421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.731441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.731456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.731472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.734046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.734065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.734085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.736674] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.736693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.739677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.742627] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.742687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.742704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.742726] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.759427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.759454] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.759489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.759595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.759635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.776090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.776112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.776146] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.795029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.795048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.795069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.795086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.795104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.795120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.795134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.795151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.795216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.795241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.795268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.795287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.795301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.795315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.795342] [drm:intel_power_well_disable [i915]] disabling display
>[  944.795363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.795384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.795401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.795484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.795493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.795541] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.795561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.795581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.795604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.795630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.795649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.795666] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.795681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.795695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.795709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.795722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.795726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.795742] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.795747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.795765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.795782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.795801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.795818] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.795836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.795853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.795872] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.795889] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.795908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.795926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.795946] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.795988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.796003] [drm:intel_power_well_enable [i915]] enabling display
>[  944.796017] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.796046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.796064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.796082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.796100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.796117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.796135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.796178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.796203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.796227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.796247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.796267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.796291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.796314] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.799404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.799424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.799443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.799463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.803151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.803189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.803209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.805798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.805816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.808697] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.811628] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.811654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.811671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.811693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.828405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.828432] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.828469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.828588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.828641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.845073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.845097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.845133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.864051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.864069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.864089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.864106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.864123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.864138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.864152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.864210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.864240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.864267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.864294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.864321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.864344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.864359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.864386] [drm:intel_power_well_disable [i915]] disabling display
>[  944.864408] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.864430] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.864445] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.864517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.864526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.864569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.864585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.864603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.864622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.864638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.864655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.864671] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.864687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.864702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.864717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.864735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.864740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.864759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.864763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.864783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.864803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.864822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.864842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.864861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.864880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.864900] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.864920] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.864939] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.864959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.864980] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.865035] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.865048] [drm:intel_power_well_enable [i915]] enabling display
>[  944.865061] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.865088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.865105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.865119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.865133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.865147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.865186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.865210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.865233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.865256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.865277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.865297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.865320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.865342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.868430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.868448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.868464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.868481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.872204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.872221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.872236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.874793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.874812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.877684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.880609] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.880641] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.880658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.880679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.897379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.897403] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.897437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.897541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.897580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.914039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.914062] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.914096] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  944.932913] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  944.932933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  944.932953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.932973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.932994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.933014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.933033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.933052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.933074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.933095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.933115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.933136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.933155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.933218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.933260] [drm:intel_power_well_disable [i915]] disabling display
>[  944.933297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  944.933331] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.933358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  944.933478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.933500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  944.933564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  944.933588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  944.933613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  944.933640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  944.933663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  944.933687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  944.933711] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  944.933734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  944.933756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  944.933778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  944.933800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  944.933805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.933826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  944.933831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  944.933852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  944.933874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  944.933895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  944.933916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  944.933940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  944.933962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  944.933984] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  944.934006] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  944.934027] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  944.934051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.934076] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  944.934140] [drm:intel_power_well_enable [i915]] enabling always-on
>[  944.934185] [drm:intel_power_well_enable [i915]] enabling display
>[  944.934208] [drm:hsw_set_power_well [i915]] Enabling power well
>[  944.934248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  944.934272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  944.934296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  944.934319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  944.934342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  944.934365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  944.934391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  944.934416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  944.934441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.934463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  944.934485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  944.934511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  944.934533] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  944.937634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  944.937655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  944.937674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.937694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  944.941401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  944.941419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  944.941436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  944.943986] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  944.944005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  944.946874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  944.949789] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  944.949830] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  944.949846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  944.949866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  944.966575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  944.966601] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  944.966636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  944.966743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  944.966783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  944.983255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  944.983279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  944.983314] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.002076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.002095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.002115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.002132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.002149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.002210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.002236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.002264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.002293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.002320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.002346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.002371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.002394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.002418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.002460] [drm:intel_power_well_disable [i915]] disabling display
>[  945.002494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.002526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.002551] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.002663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.002671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.002714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.002731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.002748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.002768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.002783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.002800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.002816] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.002832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.002847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.002862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.002876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.002880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.002893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.002897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.002911] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.002925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.002939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.002952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.002969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.002994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.003007] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.003020] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.003033] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.003047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.003064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.003105] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.003119] [drm:intel_power_well_enable [i915]] enabling display
>[  945.003133] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.003161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.003207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.003232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.003257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.003280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.003304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.003329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.003354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.003379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.003401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.003423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.003449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.003473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.006538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.006556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.006571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.006586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.008107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.008122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.008136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.011774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.011790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.011806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.014357] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.014375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.017220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.020146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.020231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.020248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.020271] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.036976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.037002] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.037037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.037143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.037233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.053680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.053704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.053740] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.072618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.072639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.072661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.072680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.072702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.072721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.072740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.072759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.072781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.072802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.072822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.072842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.072861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.072878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.072905] [drm:intel_power_well_disable [i915]] disabling display
>[  945.072928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.072952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.072968] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.073040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.073048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.073095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.073114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.073134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.073156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.073223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.073255] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.073283] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.073309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.073335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.073360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.073384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.073392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.073416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.073423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.073446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.073470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.073495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.073518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.073545] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.073569] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.073600] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.073622] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.073644] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.073667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.073692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.073756] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.073779] [drm:intel_power_well_enable [i915]] enabling display
>[  945.073801] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.073838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.073861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.073883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.073905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.073926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.073949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.073973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.073997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.074020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.074042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.074063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.074087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.074111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.077211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.077228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.077247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.077267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.080921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.080938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.080954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.083516] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.083533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.086396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.089330] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.089405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.089421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.089443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.106138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.106163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.106261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.106380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.106419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.122826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.122851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.122894] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.140773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.140792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.140812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.140829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.140847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.140861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.140876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.140892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.140909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.140925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.140941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.140956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.140970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.140983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.141010] [drm:intel_power_well_disable [i915]] disabling display
>[  945.141031] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.141052] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.141067] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.141144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.141153] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.141248] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.141274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.141304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.141334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.141359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.141387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.141413] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.141440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.141465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.141489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.141512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.141519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.141541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.141547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.141571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.141594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.141618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.141639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.141665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.141688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.141711] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.141734] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.141757] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.141783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.141810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.141885] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.141907] [drm:intel_power_well_enable [i915]] enabling display
>[  945.141929] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.141966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.141989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.142012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.142034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.142056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.142078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.142103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.142126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.142150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.142172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.142209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.142235] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.142259] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.145331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.145349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.145364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.145380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.147954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.147969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.147982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.150546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.150563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.153434] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.156384] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.156444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.156461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.156482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.173200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.173226] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.173262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.173367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.173409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.189886] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.189909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.189946] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.208810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.208829] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.208849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.208866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.208884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.208899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.208913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.208929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.208947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.208967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.208988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.209009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.209028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.209044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.209071] [drm:intel_power_well_disable [i915]] disabling display
>[  945.209094] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.209118] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.209134] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.209433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.209446] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.209512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.209537] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.209562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.209589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.209612] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.209636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.209660] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.209683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.209706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.209728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.209749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.209755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.209776] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.209781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.209803] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.209824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.209845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.209866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.209888] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.209909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.209930] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.209951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.209970] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.209993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.210018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.210080] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.210103] [drm:intel_power_well_enable [i915]] enabling display
>[  945.210125] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.210162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.210208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.210231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.210254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.210277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.210301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.210327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.210352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.210376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.210398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.210420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.210445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.210469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.213817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.213836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.213852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.213868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.216444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.216461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.216475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.219038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.219055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.221933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.224857] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.224891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.224907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.224929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.241634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.241661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.241696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.241811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.241851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.258315] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.258339] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.258383] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.277237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.277256] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.277276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.277293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.277311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.277326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.277340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.277356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.277374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.277394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.277415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.277435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.277454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.277471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.277498] [drm:intel_power_well_disable [i915]] disabling display
>[  945.277521] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.277545] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.277562] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.277633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.277642] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.277688] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.277708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.277728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.277750] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.277768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.277796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.277813] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.277829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.277843] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.277857] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.277870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.277873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.277886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.277889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.277902] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.277915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.277928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.277940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.277955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.277968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.277981] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.277993] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.278006] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.278021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.278037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.278078] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.278091] [drm:intel_power_well_enable [i915]] enabling display
>[  945.278103] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.278128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.278142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.278156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.278169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.278230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.278255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.278281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.278305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.278330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.278352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.278374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.278400] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.278423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.280419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.280436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.280450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.280465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.284162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.284182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.284234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.285740] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  945.285757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.289786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.292713] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.292744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.292761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.292783] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.309485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.309509] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.309542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.309641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.309679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.326177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.326215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.326248] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.344790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.344810] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.344833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.344852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.344874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.344893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.344913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.344931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.344953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.344973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.344994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.345014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.345033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.345050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.345077] [drm:intel_power_well_disable [i915]] disabling display
>[  945.345099] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.345124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.345140] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.345272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.345288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.345358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.345383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.345410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.345440] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.345463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.345489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.345513] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.345538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.345560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.345584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.345605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.345611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.345632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.345638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.345661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.345682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.345704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.345725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.345750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.345771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.345793] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.345814] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.345836] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.345860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.345886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.345943] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.345967] [drm:intel_power_well_enable [i915]] enabling display
>[  945.345991] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.346030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.346053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.346076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.346098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.346120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.346148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.346171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.346217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.346241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.346262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.346284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.346309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.346331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.349426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.349445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.349461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.349477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.352051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.352068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.352083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.354642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.354659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.357536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.360491] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.360544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.360561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.360582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.377288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.377314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.377349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.377458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.377498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.393989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.394014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.394053] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.412902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.412921] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.412940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.412957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.412975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.412990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.413004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.413020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.413037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.413054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.413069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.413085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.413099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.413112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.413139] [drm:intel_power_well_disable [i915]] disabling display
>[  945.413160] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.413180] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.413230] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.413527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.413542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.413611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.413635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.413662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.413697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.413717] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.413741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.413763] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.413785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.413805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.413826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.413845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.413851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.413871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.413876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.413897] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.413916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.413936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.413955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.413978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.413997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.414018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.414037] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.414057] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.414081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.414105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.414168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.414190] [drm:intel_power_well_enable [i915]] enabling display
>[  945.414246] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.414284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.414306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.414329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.414349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.414372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.414393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.414418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.414442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.414467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.414488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.414509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.414532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.414799] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.417883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.417902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.417918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.417934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.420532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.420551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.420567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.423135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.423154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.426033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.428970] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.429050] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.429066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.429086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.445785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.445812] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.445850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.445959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.446001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.462466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.462490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.462534] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.481384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.481403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.481423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.481439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.481457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.481472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.481487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.481506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.481528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.481548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.481568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.481589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.481608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.481624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.481652] [drm:intel_power_well_disable [i915]] disabling display
>[  945.481674] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.481699] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.481715] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.481798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.481807] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.481853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.481873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.481893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.481915] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.481934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.481954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.481973] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.481992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.482019] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.482036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.482051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.482055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.482069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.482072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.482087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.482100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.482114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.482126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.482142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.482155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.482168] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.482181] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.482234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.482258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.482284] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.482349] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.482372] [drm:intel_power_well_enable [i915]] enabling display
>[  945.482395] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.482432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.482453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.482475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.482495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.482517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.482538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.482562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.482586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.482609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.482629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.482649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.482674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.482695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.485748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.485766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.485782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.485798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.489504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.489523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.489539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.492105] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.492123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.495003] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.497929] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.497961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.497980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.498006] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.514711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.514738] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.514776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.514874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.514916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.531402] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.531426] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.531463] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.550316] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.550335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.550355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.550372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.550390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.550405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.550420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.550436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.550454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.550474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.550494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.550515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.550534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.550550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.550578] [drm:intel_power_well_disable [i915]] disabling display
>[  945.550600] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.550625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.550641] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.550728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.550736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.550779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.550797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.550814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.550833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.550848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.550865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.550883] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.550902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.550921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.550939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.550957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.550961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.550979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.550983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.551002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.551021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.551039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.551057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.551076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.551094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.551112] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.551131] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.551150] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.551169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.551189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.551291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.551316] [drm:intel_power_well_enable [i915]] enabling display
>[  945.551340] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.551383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.551410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.551435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.551460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.551484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.551509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.551536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.551562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.551587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.551610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.551634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.551661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.551685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.554767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.554785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.554799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.554814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.558495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.558513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.558528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.561088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.561108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.563994] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.566944] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.567003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.567020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.567042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.583743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.583769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.583804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.583926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.583975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.600438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.600461] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.600505] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.619365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.619384] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.619404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.619420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.619438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.619452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.619467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.619483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.619501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.619517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.619533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.619548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.619567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.619586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.619613] [drm:intel_power_well_disable [i915]] disabling display
>[  945.619636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.619660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.619676] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.619756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.619765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.619811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.619831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.619851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.619873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.619892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.619911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.619931] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.619950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.619969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.619988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.620006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.620010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.620029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.620032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.620052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.620071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.620089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.620108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.620127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.620146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.620165] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.620184] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.620256] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.620281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.620308] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.620372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.620395] [drm:intel_power_well_enable [i915]] enabling display
>[  945.620417] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.620455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.620477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.620500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.620522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.620544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.620568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.620593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.620617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.620641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.620663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.620684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.620709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.620732] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.624918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.624937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.624953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.624970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.627589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.627606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.627624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.631282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.631300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.631315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.633871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.633892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.636789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.639712] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.639746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.639762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.639784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.656488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.656515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.656553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.656677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.656727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.673184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.673247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.673384] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.691970] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.691989] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.692009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.692025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.692042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.692057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.692071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.692087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.692105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.692122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.692137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.692153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.692167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.692181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.692251] [drm:intel_power_well_disable [i915]] disabling display
>[  945.692285] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.692318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.692343] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.692466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.692480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.692549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.692574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.692607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.692633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.692653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.692676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.692698] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.692720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.692740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.692762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.692781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.692787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.692806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.692811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.692832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.692851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.692871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.692890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.692913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.692931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.692952] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.692971] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.692991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.693012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.693037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.693100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.693121] [drm:intel_power_well_enable [i915]] enabling display
>[  945.693143] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.693179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.693199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.693242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.693262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.693284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.693305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.693330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.693355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.693380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.693399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.693421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.693447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.693468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.696551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.696569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.696585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.696604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.699194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.699229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.699245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.701903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.701922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.704808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.707734] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.707767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.707786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.707812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.724517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.724543] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.724578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.724679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.724719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.741207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.741249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.741286] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.759160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.759179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.759199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.759259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.759289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.759312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.759337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.759360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.759388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.759414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.759440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.759465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.759486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.759509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.759549] [drm:intel_power_well_disable [i915]] disabling display
>[  945.759582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.759613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.759638] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.759745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.759759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.759828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.759854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.759881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.759907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.759923] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.759939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.759956] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.759971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.759987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.760001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.760015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.760019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.760032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.760036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.760050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.760064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.760083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.760102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.760127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.760141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.760154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.760167] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.760180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.760195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.760239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.760305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.760328] [drm:intel_power_well_enable [i915]] enabling display
>[  945.760351] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.760389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.760410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.760432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.760453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.760474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.760494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.760517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.760540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.760563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.760583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.760603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.760625] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.760648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.763739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.763758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.763776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.763796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.767528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.767547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.767564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.770159] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.770178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.773070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.776007] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.776081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.776097] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.776119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.792822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.792848] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.792883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.793003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.793054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.809517] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.809541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.809578] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.826978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.826997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.827017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.827036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.827058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.827077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.827096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.827116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.827137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.827158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.827178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.827199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.827259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.827285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.827331] [drm:intel_power_well_disable [i915]] disabling display
>[  945.827364] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.827397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.827423] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.827544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.827558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.827632] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.827653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.827678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.827705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.827726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.827749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.827771] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.827793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.827813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.827835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.827854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.827860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.827880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.827885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.827906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.827925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.827945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.827964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.827987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.828006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.828026] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.828045] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.828065] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.828087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.828110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.828172] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.828193] [drm:intel_power_well_enable [i915]] enabling display
>[  945.828215] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.828279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.828301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.828324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.828344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.828366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.828387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.828412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.828437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.828461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.828481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.828502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.828528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.828549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.831631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.831648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.831663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.831678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.835375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.835394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.835410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.837977] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.837996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.840873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.843797] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.843830] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.843846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.843867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.860573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.860599] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.860634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.860740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.860780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.877255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.877279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.877322] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.896174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.896193] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.896213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.896272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.896302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.896326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.896351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.896375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.896404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.896430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.896455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.896481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.896502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.896524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.896564] [drm:intel_power_well_disable [i915]] disabling display
>[  945.896597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.896628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.896653] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.896775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.896787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.896831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.896847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.896866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.896885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.896901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.896918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.896935] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.896951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.896974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.896987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.897000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.897004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.897016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.897019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.897033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.897046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.897058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.897075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.897093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.897110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.897127] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.897145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.897162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.897181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.897199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.897280] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.897303] [drm:intel_power_well_enable [i915]] enabling display
>[  945.897326] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.897366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.897389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.897412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.897433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.897456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.897478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.897503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.897527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.897551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.897571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.897593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.897619] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.897640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.899633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.899649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.899664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.899678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.903376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.903396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.903415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.905981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.906000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.908874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.911797] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.911832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.911852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.911878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.928575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.928602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.928640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.928749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.928792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.945255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  945.945281] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  945.945326] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  945.964176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  945.964195] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  945.964215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.964273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.964303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.964327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.964351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.964374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.964403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.964428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.964454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.964479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.964500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.964522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.964563] [drm:intel_power_well_disable [i915]] disabling display
>[  945.964596] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  945.964627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.964652] [drm:intel_power_well_disable [i915]] disabling always-on
>[  945.964758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.964771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  945.964834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  945.964851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  945.964870] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  945.964892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  945.964911] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  945.964931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  945.964950] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  945.964969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  945.964988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  945.965007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  945.965026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  945.965029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.965048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  945.965052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  945.965071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  945.965090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  945.965109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  945.965128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  945.965147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  945.965165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  945.965185] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  945.965203] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  945.965222] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  945.965271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  945.965304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  945.965373] [drm:intel_power_well_enable [i915]] enabling always-on
>[  945.965398] [drm:intel_power_well_enable [i915]] enabling display
>[  945.965423] [drm:hsw_set_power_well [i915]] Enabling power well
>[  945.965465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  945.965494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  945.965517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  945.965537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  945.965559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  945.965582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  945.965607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  945.965630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  945.965654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.965673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  945.965695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  945.965720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  945.965742] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  945.968857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  945.968877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  945.968895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.968915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  945.973696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  945.973715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  945.973731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  945.976319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  945.976339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  945.979220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  945.982169] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  945.982281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  945.982309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  945.982343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  945.998981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  945.999006] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  945.999040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  945.999143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  945.999181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.015667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.015693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.015739] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.034605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.034624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.034644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.034661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.034679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.034695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.034710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.034726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.034744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.034760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.034776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.034791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.034805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.034824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.034851] [drm:intel_power_well_disable [i915]] disabling display
>[  946.034874] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.034898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.034915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.034993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.035001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.035054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.035071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.035088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.035106] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.035120] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.035136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.035151] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.035166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.035180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.035193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.035205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.035209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.035222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.035256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.035279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.035300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.035322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.035342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.035365] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.035386] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.035408] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.035428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.035450] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.035475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.035500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.035565] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.035886] [drm:intel_power_well_enable [i915]] enabling display
>[  946.035908] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.035946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.035968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.035990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.036010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.036031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.036052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.036075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.036098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.036121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.036140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.036161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.036183] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.036206] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.039439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.039459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.039478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.039498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.042070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.042087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.042101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.044666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.044683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.047558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.050508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.050568] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.050585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.050607] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.067310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.067336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.067371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.067477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.067516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.084000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.084026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.084072] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.101777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.101798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.101822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.101843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.101865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.101885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.101904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.101923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.101945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.101966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.101987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.102007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.102026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.102043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.102073] [drm:intel_power_well_disable [i915]] disabling display
>[  946.102096] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.102122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.102140] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.102276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.102293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.102368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.102393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.102420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.102450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.102478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.102502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.102524] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.102546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.102566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.102587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.102606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.102613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.102632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.102637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.102658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.102677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.102697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.102716] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.102739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.102758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.102778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.102798] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.102818] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.102841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.102865] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.102935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.102957] [drm:intel_power_well_enable [i915]] enabling display
>[  946.102978] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.103016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.103037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.103058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.103078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.103098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.103118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.103141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.103165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.103188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.103207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.103227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.103270] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.103291] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.106284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.106301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.106316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.106331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.110000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.110019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.110035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.112612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.112631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.115503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.118444] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.118514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.118533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.118559] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.135257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.135283] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.135319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.135439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.135480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.151937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.151962] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.152007] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.170851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.170870] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.170890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.170907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.170925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.170940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.170955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.170971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.170988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.171004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.171019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.171035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.171049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.171063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.171090] [drm:intel_power_well_disable [i915]] disabling display
>[  946.171112] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.171137] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.171153] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.171268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.171284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.171355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.171380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.171406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.171435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.171458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.171483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.171507] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.171531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.171553] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.171575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.171596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.171602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.171623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.171629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.171652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.171672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.171694] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.171714] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.171739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.171759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.171781] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.171802] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.171823] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.171846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.171873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.171944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.171974] [drm:intel_power_well_enable [i915]] enabling display
>[  946.171996] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.172034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.172055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.172076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.172096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.172116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.172136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.172160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.172183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.172207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.172227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.172264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.172290] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.172312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.175400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.175419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.175438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.175458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.179155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.179172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.179187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.181752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.181770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.184683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.187629] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.187693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.187710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.187733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.204434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.204460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.204496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.204599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.204639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.221116] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.221140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.221186] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.240005] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.240024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.240044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.240061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.240079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.240094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.240109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.240125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.240143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.240159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.240175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.240191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.240205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.240218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.240287] [drm:intel_power_well_disable [i915]] disabling display
>[  946.240321] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.240354] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.240379] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.240507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.240520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.240584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.240605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.240629] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.240655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.240676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.240698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.240720] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.240741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.240762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.240782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.240801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.240806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.240826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.240832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.240852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.240871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.240891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.240910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.240932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.240951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.240971] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.240991] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.241010] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.241033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.241058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.241121] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.241141] [drm:intel_power_well_enable [i915]] enabling display
>[  946.241163] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.241200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.241221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.241260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.241281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.241302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.241323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.241348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.241371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.241396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.241416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.241437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.241462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.241484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.245644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.245663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.245679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.245695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.248290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.248309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.248325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.250899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.250919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.253798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.256728] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.256754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.256770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.256791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.273499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.273526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.273561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.273668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.273709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.290178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.290203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.290247] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.309116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.309136] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.309156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.309173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.309191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.309207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.309222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.309238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.309298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.309326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.309353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.309380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.309402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.309424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.309466] [drm:intel_power_well_disable [i915]] disabling display
>[  946.309499] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.309530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.309555] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.309676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.309691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.309752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.309769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.309787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.309807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.309822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.309846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.309861] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.309876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.309889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.309902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.309915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.309918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.309931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.309934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.309947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.309959] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.309972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.309984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.309999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.310012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.310024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.310037] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.310049] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.310064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.310080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.310121] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.310134] [drm:intel_power_well_enable [i915]] enabling display
>[  946.310146] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.310170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.310185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.310202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.310220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.310237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.310278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.310306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.310330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.310355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.310375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.310396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.310422] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.310443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.313517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.313534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.313550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.313566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.315073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.315088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.315102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.318790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.318811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.318829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.320341] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  946.320359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.324313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.327259] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.327321] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.327338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.327359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.344064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.344091] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.344126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.344228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.344325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.360762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.360787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.360825] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.379722] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.379740] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.379760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.379777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.379794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.379809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.379828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.379847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.379868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.379889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.379910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.379930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.379949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.379965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.379992] [drm:intel_power_well_disable [i915]] disabling display
>[  946.380015] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.380040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.380056] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.380130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.380139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.380185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.380204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.380224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.380246] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.380307] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.380334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.380361] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.380385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.380409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.380431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.380455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.380461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.380485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.380499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.380521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.380541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.380562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.380581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.380605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.380625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.380646] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.380666] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.380686] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.380711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.380738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.380803] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.380824] [drm:intel_power_well_enable [i915]] enabling display
>[  946.380846] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.380885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.380906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.380928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.380948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.380968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.380988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.381011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.381034] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.381056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.381076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.381096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.381118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.381140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.384243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.384274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.384293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.384313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.386915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.386935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.386954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.389524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.389543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.392419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.395350] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.395376] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.395393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.395414] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.412131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.412157] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.412192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.412426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.412466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.428822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.428846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.428882] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.446758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.446776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.446796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.446813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.446831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.446846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.446861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.446877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.446895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.446912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.446927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.446943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.446957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.446971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.446997] [drm:intel_power_well_disable [i915]] disabling display
>[  946.447018] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.447039] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.447055] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.447132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.447141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.447183] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.447202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.447222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.447244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.447301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.447329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.447356] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.447380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.447406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.447428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.447451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.447457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.447480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.447487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.447511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.447532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.447556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.447577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.447602] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.447624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.447647] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.447668] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.447691] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.447719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.447754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.448088] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.448111] [drm:intel_power_well_enable [i915]] enabling display
>[  946.448132] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.448170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.448193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.448213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.448234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.448272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.448295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.448321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.448345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.448369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.448477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.448496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.448520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.448541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.451627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.451646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.451661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.451676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.455375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.455394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.455410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.457983] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.458000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.460874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.463800] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.463831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.463848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.463870] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.480576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.480602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.480637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.480744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.480784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.497293] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.497317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.497353] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.516222] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.516243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.516308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.516333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.516362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.516386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.516410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.516435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.516464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.516489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.516514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.516539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.516560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.516582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.516623] [drm:intel_power_well_disable [i915]] disabling display
>[  946.516657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.516689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.516714] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.516835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.516847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.516890] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.516910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.516929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.516952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.516971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.516990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.517009] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.517029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.517048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.517067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.517085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.517089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.517108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.517112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.517131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.517150] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.517169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.517188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.517207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.517226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.517245] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.517300] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.517327] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.517350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.517377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.517441] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.517464] [drm:intel_power_well_enable [i915]] enabling display
>[  946.517486] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.517524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.517546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.517568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.517590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.517613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.517637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.517662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.517687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.517711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.517732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.517753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.517778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.517801] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.520898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.520917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.520933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.520949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.524632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.524649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.524666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.527230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.527250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.530228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.533151] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.533185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.533201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.533223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.549928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.549955] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.549990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.550097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.550137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.566610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.566634] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.566678] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.585541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.585560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.585581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.585598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.585615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.585630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.585645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.585661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.585679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.585695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.585711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.585727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.585741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.585755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.585781] [drm:intel_power_well_disable [i915]] disabling display
>[  946.585802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.585823] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.585839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.585917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.585926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.585969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.585985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.586003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.586024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.586043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.586063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.586083] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.586101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.586121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.586140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.586158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.586162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.586180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.586184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.586204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.586223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.586242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.586261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.586320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.586347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.586372] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.586396] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.586420] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.586448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.586476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.586546] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.586571] [drm:intel_power_well_enable [i915]] enabling display
>[  946.586595] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.586642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.586965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.586989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.587009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.587030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.587051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.587075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.587098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.587121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.587141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.587161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.587183] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.587205] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.590312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.590331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.590347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.590364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.594039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.594059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.594078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.596648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.596667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.599544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.602490] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.602555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.602574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.602600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.619295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.619321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.619357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.619457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.619498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.635977] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.636000] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.636044] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.654908] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.654927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.654947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.654964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.654982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.654997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.655011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.655027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.655045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.655061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.655076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.655092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.655105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.655119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.655146] [drm:intel_power_well_disable [i915]] disabling display
>[  946.655167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.655188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.655204] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.655327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.655490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.655561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.655585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.655612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.655640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.655663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.655688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.655712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.655736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.655758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.655781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.655802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.655808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.655829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.655835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.655858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.655879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.655901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.655921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.655946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.655973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.655993] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.656012] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.656032] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.656053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.656077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.656139] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.656160] [drm:intel_power_well_enable [i915]] enabling display
>[  946.656182] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.656218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.656240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.656260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.656298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.656319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.656341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.656366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.656390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.656415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.656435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.656456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.656482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.656504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.659841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.659860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.659879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.659898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.662557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.662574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.662589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.668484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.668504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.668523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.671090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.671109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.673978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.676913] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.676988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.677005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.677027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.693729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.693756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.693794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.693904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.693946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.710410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.710434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.710478] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.729343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.729363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.729382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.729399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.729417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.729432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.729446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.729462] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.729483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.729504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.729525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.729545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.729564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.729581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.729608] [drm:intel_power_well_disable [i915]] disabling display
>[  946.729631] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.729655] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.729671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.729757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.729765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.729808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.729824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.729842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.729862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.729880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.729899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.729917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.729935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.729953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.729971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.729988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.729992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.730009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.730013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.730031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.730049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.730066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.730084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.730102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.730119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.730137] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.730155] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.730173] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.730192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.730211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.730255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.730310] [drm:intel_power_well_enable [i915]] enabling display
>[  946.730335] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.730375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.730401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.730423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.730447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.730468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.730491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.730518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.730543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.730568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.730589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.730611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.730637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.730659] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.733746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.733763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.733778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.733793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.737526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.737546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.737565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.740131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.740150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.743033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.745969] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.746043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.746060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.746088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.762783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.762809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.762844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.762951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.762991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.779487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.779511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.779547] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.798422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.798441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.798461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.798480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.798502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.798522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.798541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.798560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.798582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.798602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.798623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.798643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.798662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.798678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.798706] [drm:intel_power_well_disable [i915]] disabling display
>[  946.798728] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.798753] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.798770] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.798851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.798860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.798907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.798927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.798946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.798968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.798987] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.799007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.799026] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.799045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.799064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.799083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.799101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.799106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.799124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.799128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.799148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.799167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.799187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.799205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.799225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.799251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.799268] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.799320] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.799345] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.799370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.799397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.799461] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.799483] [drm:intel_power_well_enable [i915]] enabling display
>[  946.799505] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.799543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.799843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.799865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.799888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.799908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.799931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.799954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.799978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.800001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.800020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.800040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.800063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.800085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.803159] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.803176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.803191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.803206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.806894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.806911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.806925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.809496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.809512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.812399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.815345] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.815411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.815428] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.815449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.832153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.832179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.832214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.832407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.832447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.848853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.848877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.848914] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.867772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.867790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.867810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.867827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.867845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.867860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.867875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.867893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.867915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.867936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.867956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.867977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.867996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.868012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.868039] [drm:intel_power_well_disable [i915]] disabling display
>[  946.868062] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.868086] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.868103] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.868176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.868186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.868232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.868251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.868271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.868341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.868370] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.868399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.868428] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.868454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.868480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.868505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.868530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.868536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.868559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.868566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.868591] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.868615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.868639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.868663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.868690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.868719] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.868742] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.868764] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.868786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.868811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.868836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.868890] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.868912] [drm:intel_power_well_enable [i915]] enabling display
>[  946.868934] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.868972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.868996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.869018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.869040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.869062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.869084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.869108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.869132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.869155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.869177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.869197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.869220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.869243] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.872346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.872364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.872380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.872399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.874975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.874992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.875010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.877582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.877600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.880477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.883439] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.883494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.883512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.883534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.900239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.900263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.900349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.900499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.900539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.916933] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.916958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.916997] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  946.935880] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  946.935899] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  946.935919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.935936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.935953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.935968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.935983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.935999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.936016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.936032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.936048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.936063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.936077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.936091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.936117] [drm:intel_power_well_disable [i915]] disabling display
>[  946.936139] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  946.936159] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.936175] [drm:intel_power_well_disable [i915]] disabling always-on
>[  946.936251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.936260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  946.936360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  946.936387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  946.936416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  946.936446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  946.936470] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  946.936498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  946.936525] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  946.936550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  946.936575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  946.936599] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  946.936621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  946.936628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.936650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  946.936656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  946.936680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  946.936703] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  946.936727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.936749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  946.936775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  946.936798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  946.936821] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  946.936844] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  946.936868] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  946.936894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.936922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  946.937002] [drm:intel_power_well_enable [i915]] enabling always-on
>[  946.937026] [drm:intel_power_well_enable [i915]] enabling display
>[  946.937050] [drm:hsw_set_power_well [i915]] Enabling power well
>[  946.937091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  946.937117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  946.937149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  946.937171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  946.937193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  946.937216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  946.937241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  946.937265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  946.937308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.937329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  946.937352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  946.937378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  946.937402] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  946.941591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  946.941610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  946.941627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.941647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  946.944247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  946.944273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  946.944331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  946.946923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  946.946943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  946.949817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  946.952754] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  946.952826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  946.952842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  946.952864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  946.969558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  946.969583] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  946.969617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  946.969723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  946.969761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  946.986264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  946.986337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  946.986477] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.005039] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.005058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.005078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.005094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.005112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.005127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.005142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.005158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.005179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.005199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.005220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.005241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.005260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.005276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.005354] [drm:intel_power_well_disable [i915]] disabling display
>[  947.005389] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.005423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.005449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.005575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.005590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.005663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.005687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.005712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.005739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.005762] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.005786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.005810] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.005833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.005855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.005877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.005898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.005903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.005924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.005930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.005951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.005973] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.005994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.006014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.006038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.006060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.006081] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.006102] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.006121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.006144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.006169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.006232] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.006254] [drm:intel_power_well_enable [i915]] enabling display
>[  947.006276] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.006338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.006362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.006383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.006406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.006429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.006452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.006478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.006503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.006527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.006549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.006571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.006597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.006620] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.010807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.010826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.010841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.010858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.015729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.015748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.015766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.018358] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.018378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.021249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.024173] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.024208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.024224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.024246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.040952] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.040978] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.041013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.041123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.041163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.057651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.057675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.057713] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.076581] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.076600] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.076620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.076636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.076654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.076669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.076683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.076702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.076723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.076744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.076764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.076785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.076803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.076819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.076847] [drm:intel_power_well_disable [i915]] disabling display
>[  947.076869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.076894] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.076910] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.076983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.076992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.077043] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.077060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.077077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.077095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.077110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.077125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.077141] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.077156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.077171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.077185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.077199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.077202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.077215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.077219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.077236] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.077254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.077272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.077324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.077348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.077370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.077391] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.077412] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.077433] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.077456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.077481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.077547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.077569] [drm:intel_power_well_enable [i915]] enabling display
>[  947.077591] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.077628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.077644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.077659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.077674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.077688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.077703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.077720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.077735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.077749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.077763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.077776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.077793] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.077807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.080893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.080910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.080925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.080940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.084606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.084625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.084641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.087201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.087221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.090102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.093025] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.093060] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.093077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.093098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.109803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.109830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.109867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.109976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.110018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.126505] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.126529] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.126565] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.145433] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.145452] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.145472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.145489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.145506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.145521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.145540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.145559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.145581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.145602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.145622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.145642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.145661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.145678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.145705] [drm:intel_power_well_disable [i915]] disabling display
>[  947.145727] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.145752] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.145768] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.145848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.145858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.145904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.145923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.145943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.145965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.145984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.146003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.146022] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.146041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.146061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.146080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.146098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.146102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.146121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.146124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.146144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.146163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.146182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.146201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.146220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.146239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.146258] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.146277] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.146339] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.146366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.146395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.146465] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.146489] [drm:intel_power_well_enable [i915]] enabling display
>[  947.146513] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.146555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.146579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.146604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.146628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.146658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.146682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.146708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.146732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.146756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.146777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.146798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.146822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.146846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.149941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.149960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.149976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.149992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.152571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.152588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.152604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.155150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.155169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.158046] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.160971] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.161004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.161020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.161042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.177743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.177769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.177805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.177911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.177951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.194446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.194471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.194507] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.213381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.213400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.213420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.213437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.213454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.213469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.213484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.213499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.213517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.213534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.213549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.213565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.213579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.213593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.213619] [drm:intel_power_well_disable [i915]] disabling display
>[  947.213641] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.213662] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.213684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.213763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.213772] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.213814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.213830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.213848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.213867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.213882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.213898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.213915] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.213930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.213945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.213959] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.213973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.213976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.213990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.213994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.214013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.214032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.214051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.214070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.214096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.214112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.214129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.214147] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.214164] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.214183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.214201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.214244] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.214258] [drm:intel_power_well_enable [i915]] enabling display
>[  947.214272] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.214333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.214358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.214381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.214403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.214425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.214446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.214471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.214495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.214520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.214541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.214562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.214588] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.214610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.217704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.217723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.217739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.217755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.221454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.221473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.221489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.224055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.224074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.226948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.229872] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.229906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.229922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.229944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.246648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.246675] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.246710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.246817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.246857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.263350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.263376] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.263414] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.282021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.282041] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.282062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.282082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.282103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.282122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.282142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.282161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.282182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.282203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.282223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.282244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.282263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.282279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.282351] [drm:intel_power_well_disable [i915]] disabling display
>[  947.282386] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.282418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.282434] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.282506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.282515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.282559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.282576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.282595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.282621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.282636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.282651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.282667] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.282682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.282700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.282721] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.282738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.282742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.282756] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.282759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.282772] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.282785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.282798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.282811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.282826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.282839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.282852] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.282864] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.282877] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.282892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.282908] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.282950] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.282964] [drm:intel_power_well_enable [i915]] enabling display
>[  947.282977] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.283002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.283016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.283030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.283043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.283060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.283079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.283099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.283119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.283138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.283156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.283174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.283192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.283210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.286281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.286300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.286356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.286383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.288964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.288981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.288996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.291562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.291580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.294458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.297401] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.297466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.297483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.297505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.314208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.314235] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.314273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.314474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.314514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.330890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.330914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.330957] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.349784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.349802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.349822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.349839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.349856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.349871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.349886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.349901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.349919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.349935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.349950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.349965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.349979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.349993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.350019] [drm:intel_power_well_disable [i915]] disabling display
>[  947.350041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.350061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.350077] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.350161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.350170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.350210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.350226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.350243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.350262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.350277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.350293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.350348] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.350370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.350394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.350415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.350435] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.350442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.350462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.350468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.350489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.350509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.350530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.350550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.350574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.350594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.350614] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.350635] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.350655] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.350680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.350704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.350947] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.350961] [drm:intel_power_well_enable [i915]] enabling display
>[  947.350974] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.351002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.351018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.351034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.351048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.351062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.351080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.351101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.351122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.351142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.351169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.351185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.351202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.351217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.354273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.354292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.354339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.354365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.358104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.358123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.358138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.360712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.360730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.363605] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.366552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.366615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.366633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.366658] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.383357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.383384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.383422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.383531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.383573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.400037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.400061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.400105] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.418947] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.418966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.418986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.419003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.419020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.419035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.419050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.419066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.419083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.419100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.419115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.419131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.419145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.419158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.419185] [drm:intel_power_well_disable [i915]] disabling display
>[  947.419205] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.419226] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.419242] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.419363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.419480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.419524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.419542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.419560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.419580] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.419596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.419613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.419630] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.419646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.419662] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.419683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.419697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.419700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.419713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.419717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.419730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.419743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.419757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.419769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.419785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.419798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.419811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.419824] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.419837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.419852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.419869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.419910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.419923] [drm:intel_power_well_enable [i915]] enabling display
>[  947.419936] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.419961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.419975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.419989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.420003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.420020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.420038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.420057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.420077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.420096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.420114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.420131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.420150] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.420168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.423205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.423223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.423239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.423255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.425822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.425846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.425861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.428458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.428478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.431405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.434351] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.434415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.434432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.434454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.451156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.451182] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.451219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.451425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.451466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.467838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.467864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.467910] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.486787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.486806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.486826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.486843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.486860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.486876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.486890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.486906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.486924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.486941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.486957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.486973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.486991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.487009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.487037] [drm:intel_power_well_disable [i915]] disabling display
>[  947.487059] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.487084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.487100] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.487179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.487187] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.487229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.487245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.487263] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.487281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.487295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.487311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.487362] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.487384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.487405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.487426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.487447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.487453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.487473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.487479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.487500] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.487520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.487541] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.487560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.487584] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.487604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.487624] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.487644] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.487664] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.487687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.487710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.487961] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.487975] [drm:intel_power_well_enable [i915]] enabling display
>[  947.487994] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.488029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.488048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.488067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.488086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.488105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.488123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.488143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.488163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.488190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.488205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.488220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.488238] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.488253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.490225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.490240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.490255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.490269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.493949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.493965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.493980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.496543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.496563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.499444] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.502379] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.502453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.502472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.502498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.519190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.519214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.519248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.519405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.519456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.535888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.535912] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.535956] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.554802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.554819] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.554838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.554853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.554868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.554886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.554904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.554921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.554941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.554960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.554978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.554997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.555014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.555029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.555054] [drm:intel_power_well_disable [i915]] disabling display
>[  947.555075] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.555098] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.555113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.555188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.555197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.555238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.555256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.555275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.555295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.555312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.555369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.555392] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.555414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.555436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.555456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.555475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.555482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.555501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.555507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.555527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.555546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.555566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.555585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.555607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.555626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.555646] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.555665] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.555685] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.555707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.555732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.555797] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.555819] [drm:intel_power_well_enable [i915]] enabling display
>[  947.555841] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.555879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.555902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.555925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.555947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.555968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.555991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.556011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.556027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.556041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.556055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.556067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.556084] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.556099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.560250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.560269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.560286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.560302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.563976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.563994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.564010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.566592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.566612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.569507] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.572457] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.572518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.572535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.572557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.589259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.589285] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.589320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.589517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.589564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.605961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.605985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.606024] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.624899] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.624918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.624938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.624954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.624972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.624987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.625001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.625016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.625034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.625050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.625066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.625081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.625095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.625109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.625136] [drm:intel_power_well_disable [i915]] disabling display
>[  947.625157] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.625181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.625197] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.625277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.625287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.625374] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.625399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.625426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.625454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.625479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.625505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.625530] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.625553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.625576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.625598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.625621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.625798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.625815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.625818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.625835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.625849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.625864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.625882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.625903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.625921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.625942] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.625960] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.625981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.626001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.626022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.626068] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.626084] [drm:intel_power_well_enable [i915]] enabling display
>[  947.626099] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.626130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.626156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.626174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.626189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.626207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.626224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.626244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.626263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.626282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.626299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.626318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.626362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.626384] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.630568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.630587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.630603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.630619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.635455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.635473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.635489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.640201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.640222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.643099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.646035] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.646109] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.646126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.646148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.662850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.662877] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.662913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.663044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.663083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.679551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.679575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.679612] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.697852] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.697871] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.697891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.697908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.697926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.697941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.697956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.697972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.697990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.698006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.698022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.698038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.698052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.698066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.698093] [drm:intel_power_well_disable [i915]] disabling display
>[  947.698115] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.698140] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.698156] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.698238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.698247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.698293] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.698313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.698364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.698394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.698417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.698443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.698467] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.698491] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.698514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.698537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.698558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.698565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.698588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.698595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.698618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.698639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.698661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.698682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.698706] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.698727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.698749] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.698770] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.698792] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.698823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.698848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.699091] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.699105] [drm:intel_power_well_enable [i915]] enabling display
>[  947.699119] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.699148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.699164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.699183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.699200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.699219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.699237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.699257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.699277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.699295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.699313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.699353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.699379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.699401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.702568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.702587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.702603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.702620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.705196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.705214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.705229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.707801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.707819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.710690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.713629] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.713700] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.713717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.713739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.730442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.730469] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.730504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.730605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.730644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.747143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.747167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.747204] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.766064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.766083] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.766103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.766120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.766137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.766152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.766167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.766182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.766200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.766216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.766232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.766247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.766261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.766275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.766301] [drm:intel_power_well_disable [i915]] disabling display
>[  947.766322] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.766379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.766404] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.766599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.766608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.766653] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.766671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.766689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.766710] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.766726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.766743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.766760] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.766775] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.766791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.766806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.766820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.766824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.766838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.766841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.766856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.766871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.766885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.766898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.766916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.766930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.766944] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.766958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.766972] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.766992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.767014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.767060] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.767077] [drm:intel_power_well_enable [i915]] enabling display
>[  947.767092] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.767122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.767142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.767162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.767181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.767201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.767221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.767242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.767263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.767285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.767311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.767331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.767379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.767401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.770492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.770512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.770531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.770551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.774235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.774253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.774268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.776833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.776852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.779773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.782718] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.782782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.782798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.782819] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.799525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.799552] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.799590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.799700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.799742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.816205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.816229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.816274] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.835097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.835118] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.835139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.835159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.835180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.835200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.835219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.835238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.835260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.835280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.835300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.835320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.835410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.835435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.835476] [drm:intel_power_well_disable [i915]] disabling display
>[  947.835509] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.835542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.835567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.835688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.835702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.835772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.835802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.835826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.835852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.835873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.835896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.835918] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.835940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.835961] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.835982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.836001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.836007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.836026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.836031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.836052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.836071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.836092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.836111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.836133] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.836152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.836173] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.836192] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.836212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.836234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.836258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.836319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.836362] [drm:intel_power_well_enable [i915]] enabling display
>[  947.836384] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.836421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.836443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.836465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.836486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.836507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.836529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.836554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.836579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.836604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.836624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.836645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.836670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.836692] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.839772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.839789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.839804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.839819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.843501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.843518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.843533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.846098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.846116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.848993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.851918] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.851950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.851966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.851988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.868694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.868720] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.868755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.868861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.868901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.885375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.885399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.885443] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.904287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.904307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.904327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.904386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.904415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.904439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.904464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.904487] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.904515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.904540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.904566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.904591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.904612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.904634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.904674] [drm:intel_power_well_disable [i915]] disabling display
>[  947.904707] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.904738] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.904763] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.904882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.904892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.904935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.904952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.904971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.904993] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.905012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.905032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.905051] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.905070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.905089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.905108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.905127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.905131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.905150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.905153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.905173] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.905199] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.905216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.905232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.905248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.905262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.905277] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.905290] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.905303] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.905319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.905335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.905417] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.905440] [drm:intel_power_well_enable [i915]] enabling display
>[  947.905463] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.905502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.905525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.905546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.905568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.905588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.905611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.905636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.905659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.905682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.905701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.905723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.905748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.905769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.908857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.908876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.908892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.908908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.912623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.912643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.912662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.915233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.915253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.918132] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.921067] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.921141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.921158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.921180] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.937909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.937937] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.937974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.938081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.938124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.954570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  947.954594] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.954629] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  947.973489] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  947.973508] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.973528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.973545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.973562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.973577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.973592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.973608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.973625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.973642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.973658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.973673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.973687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.973701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.973728] [drm:intel_power_well_disable [i915]] disabling display
>[  947.973749] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.973770] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  947.973785] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.973855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.973864] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.973906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.973922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.973940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.973959] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.973974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.973990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.974006] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  947.974021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  947.974036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.974050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.974064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.974067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.974081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.974085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.974099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.974113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.974126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.974140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.974158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.974177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.974196] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  947.974215] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  947.974235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  947.974255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.974275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  947.974313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.974328] [drm:intel_power_well_enable [i915]] enabling display
>[  947.974386] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.974429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.974454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.974478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.974500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.974522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.974545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.974571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.974596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.974621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.974643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.974665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.974697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  947.974718] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.977813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.977832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.977847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.977864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.981608] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.981628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.981644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.983140] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  947.983157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.987130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.990066] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  947.990141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.990160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  947.990187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.006881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.006908] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.006945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.007055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.007097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.023563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.023588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.023622] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.042478] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.042497] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.042517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.042534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.042552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.042567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.042581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.042597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.042614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.042631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.042646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.042662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.042680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.042698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.042725] [drm:intel_power_well_disable [i915]] disabling display
>[  948.042748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.042772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.042788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.042868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.042877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.042922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.042942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.042962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.042984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.043002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.043022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.043049] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.043067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.043083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.043100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.043117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.043120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.043137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.043141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.043158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.043176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.043193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.043210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.043228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.043245] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.043262] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.043280] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.043297] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.043315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.043334] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.043424] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.043445] [drm:intel_power_well_enable [i915]] enabling display
>[  948.043465] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.043504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.043526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.043549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.043792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.043810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.043828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.043848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.043871] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.043898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.043914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.043928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.043946] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.043961] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.047019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.047035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.047049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.047066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.050770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.050789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.050806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.053432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.053451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.056330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.059295] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.059389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.059417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.059503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.076101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.076127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.076162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.076268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.076308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.092801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.092825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.092871] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.111745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.111765] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.111787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.111807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.111828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.111848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.111867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.111886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.111908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.111928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.111949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.111969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.111988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.112004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.112031] [drm:intel_power_well_disable [i915]] disabling display
>[  948.112053] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.112078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.112095] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.112176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.112185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.112232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.112251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.112271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.112293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.112311] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.112331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.112350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.112410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.112436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.112458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.112481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.112488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.112517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.112522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.112543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.112562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.112582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.112602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.112624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.112643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.112663] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.112683] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.112702] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.112726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.112749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.113003] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.113018] [drm:intel_power_well_enable [i915]] enabling display
>[  948.113032] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.113060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.113078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.113097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.113114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.113133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.113150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.113170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.113190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.113209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.113227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.113242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.113261] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.113279] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.116334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.116361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.116378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.116394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.120042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.120059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.120075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.122640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.122658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.125533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.128476] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.128543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.128559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.128581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.145286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.145312] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.145347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.145552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.145591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.161966] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.161991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.162026] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.180100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.180119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.180139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.180156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.180174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.180189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.180208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.180227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.180249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.180269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.180290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.180310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.180329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.180345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.180422] [drm:intel_power_well_disable [i915]] disabling display
>[  948.180547] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.180571] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.180588] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.180660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.180669] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.180716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.180736] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.180757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.180779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.180798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.180818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.180837] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.180865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.180883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.180899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.180913] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.180917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.180930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.180934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.180948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.180962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.180981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.181002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.181026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.181041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.181054] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.181068] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.181080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.181097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.181113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.181156] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.181169] [drm:intel_power_well_enable [i915]] enabling display
>[  948.181182] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.181209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.181228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.181245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.181263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.181282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.181299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.181319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.181338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.181382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.181404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.181425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.181449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.181471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.184545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.184563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.184581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.184601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.187172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.187190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.187206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.189772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.189790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.192668] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.195611] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.195676] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.195693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.195715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.212419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.212446] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.212484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.212592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.212634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.229100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.229125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.229160] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.248006] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.248025] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.248044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.248061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.248078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.248093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.248107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.248123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.248140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.248156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.248172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.248187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.248201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.248215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.248241] [drm:intel_power_well_disable [i915]] disabling display
>[  948.248263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.248288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.248305] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.248443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.248457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.248523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.248546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.248571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.248598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.248619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.248643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.248665] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.248688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.248709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.248731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.248751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.248758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.248778] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.248783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.248804] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.248824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.248845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.248864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.248887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.248907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.248928] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.248947] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.248968] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.248990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.249014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.249078] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.249100] [drm:intel_power_well_enable [i915]] enabling display
>[  948.249122] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.249160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.249182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.249203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.249224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.249244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.249266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.249291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.249314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.249337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.249357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.249395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.249419] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.249450] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.252542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.252561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.252577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.252593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.255171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.255188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.255204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.257769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.257786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.260673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.263604] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.263630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.263646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.263668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.280390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.280417] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.280454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.280563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.280605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.297054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.297078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.297113] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.315125] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.315144] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.315164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.315181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.315198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.315213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.315227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.315243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.315260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.315276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.315292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.315307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.315321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.315335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.315401] [drm:intel_power_well_disable [i915]] disabling display
>[  948.315434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.315467] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.315493] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.315761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.315779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.315819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.315835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.315852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.315870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.315884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.315899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.315917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.315935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.315953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.315970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.315988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.315991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.316009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.316012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.316030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.316047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.316064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.316081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.316099] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.316116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.316133] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.316150] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.316167] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.316186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.316204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.316246] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.316260] [drm:intel_power_well_enable [i915]] enabling display
>[  948.316274] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.316302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.316319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.316337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.316355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.316398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.316425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.316451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.316476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.316501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.316522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.316544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.316571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.316592] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.319665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.319684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.319702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.319720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.322297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.322315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.322331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.324898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.324917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.327870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.330807] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.330879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.330896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.330917] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.347622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.347649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.347684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.347791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.347830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.364321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.364345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.364432] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.381841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.381860] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.381880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.381896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.381914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.381930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.381944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.381960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.381978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.381995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.382011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.382027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.382041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.382055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.382081] [drm:intel_power_well_disable [i915]] disabling display
>[  948.382102] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.382123] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.382139] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.382216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.382224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.382263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.382277] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.382293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.382311] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.382325] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.382339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.382354] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.382400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.382422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.382442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.382462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.382468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.382487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.382493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.382513] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.382532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.382551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.382570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.382592] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.382611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.382630] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.382649] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.382668] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.382691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.382714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.382777] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.382797] [drm:intel_power_well_enable [i915]] enabling display
>[  948.382811] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.382836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.382851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.382865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.382883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.382901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.382919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.382938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.382957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.382976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.382994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.383011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.383030] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.383047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.386106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.386123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.386138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.386152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.389868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.389887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.389903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.392493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.392510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.395462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.398406] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.398471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.398489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.398518] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.415211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.415237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.415273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.415414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.415475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.431908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.431932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.431977] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.450847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.450866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.450886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.450903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.450920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.450935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.450949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.450964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.450981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.450998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.451013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.451028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.451042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.451056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.451082] [drm:intel_power_well_disable [i915]] disabling display
>[  948.451103] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.451124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.451139] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.451217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.451226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.451268] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.451284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.451303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.451326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.451345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.451364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.451424] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.451448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.451472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.451495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.451523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.451530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.451549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.451555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.451575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.451595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.451615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.451634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.451656] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.451675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.451695] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.451715] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.451734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.451757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.451781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.452032] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.452046] [drm:intel_power_well_enable [i915]] enabling display
>[  948.452059] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.452085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.452101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.452116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.452130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.452143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.452158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.452174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.452189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.452203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.452216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.452229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.452245] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.452260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.455329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.455348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.455364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.455413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.458092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.458111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.458127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.460696] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.460714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.463593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.466526] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.466602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.466622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.466648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.483345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.483371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.483505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.483616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.483656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.500025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.500049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.500084] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.518136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.518155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.518176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.518193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.518210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.518226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.518241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.518257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.518275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.518291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.518306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.518322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.518336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.518349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.518420] [drm:intel_power_well_disable [i915]] disabling display
>[  948.518456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.518489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.518506] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.518584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.518593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.518636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.518652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.518671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.518691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.518706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.518723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.518740] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.518756] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.518771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.518786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.518800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.518804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.518818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.518821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.518837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.518850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.518865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.518878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.518895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.518909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.518924] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.518944] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.518958] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.518972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.518989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.519031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.519044] [drm:intel_power_well_enable [i915]] enabling display
>[  948.519057] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.519082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.519096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.519114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.519135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.519153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.519167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.519182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.519196] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.519210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.519223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.519240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.519259] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.519277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.522331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.522349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.522365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.522411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.526095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.526113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.526127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.528690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.528708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.531584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.534532] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.534595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.534613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.534635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.551336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.551362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.551497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.551604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.551642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.568017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.568041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.568077] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.586144] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.586163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.586183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.586200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.586217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.586237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.586256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.586275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.586297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.586318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.586338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.586359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.586378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.586439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.586483] [drm:intel_power_well_disable [i915]] disabling display
>[  948.586618] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.586642] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.586658] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.586728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.586737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.586782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.586801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.586822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.586845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.586864] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.586885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.586905] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.586925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.586944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.586963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.586982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.586987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.587006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.587010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.587030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.587049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.587069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.587088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.587108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.587127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.587147] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.587166] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.587186] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.587206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.587227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.587272] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.587288] [drm:intel_power_well_enable [i915]] enabling display
>[  948.587303] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.587333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.587360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.587378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.587418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.587442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.587464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.587488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.587510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.587533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.587553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.587573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.587597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.587618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.589849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.589865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.589879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.589893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.593576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.593593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.593608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.595105] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  948.595121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.599109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.602046] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.602120] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.602136] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.602159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.618862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.618889] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.618927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.619029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.619071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.635541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.635567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.635603] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.654455] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.654475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.654497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.654517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.654539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.654558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.654577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.654596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.654617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.654638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.654658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.654678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.654697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.654713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.654741] [drm:intel_power_well_disable [i915]] disabling display
>[  948.654763] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.654787] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.654804] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.654903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.654912] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.654954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.654971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.654988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.655006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.655021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.655036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.655052] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.655067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.655081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.655095] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.655112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.655116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.655134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.655137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.655156] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.655174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.655192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.655209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.655227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.655245] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.655263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.655281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.655298] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.655317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.655336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.655379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.655435] [drm:intel_power_well_enable [i915]] enabling display
>[  948.655456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.655496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.655519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.655542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.655563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.655584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.655606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.655630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.655654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.655678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.655698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.655718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.655743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.655765] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.658844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.658862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.658876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.658893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.662590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.662610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.662629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.665194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.665213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.668099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.671036] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.671109] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.671126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.671148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.687851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.687877] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.687912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.688018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.688058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.704553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.704578] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.704625] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.723503] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.723522] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.723542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.723559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.723577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.723592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.723606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.723622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.723640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.723656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.723672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.723688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.723702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.723716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.723742] [drm:intel_power_well_disable [i915]] disabling display
>[  948.723763] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.723784] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.723803] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.723891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.723900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.723942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.723958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.723976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.723996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.724011] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.724028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.724044] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.724059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.724074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.724088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.724102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.724106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.724119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.724123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.724137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.724151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.724164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.724178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.724194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.724208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.724222] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.724236] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.724249] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.724268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.724289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.724335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.724350] [drm:intel_power_well_enable [i915]] enabling display
>[  948.724372] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.724432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.724455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.724476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.724497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.724516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.724537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.724561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.724583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.724606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.724626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.724645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.724669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.724690] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.727776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.727795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.727811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.727827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.731523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.731540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.731554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.734115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.734133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.737005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.739941] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.740016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.740036] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.740062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.756756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.756783] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.756821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.756933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.756975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.773438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.773462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.773497] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.792350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.792369] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.792389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.792448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.792475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.792498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.792523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.792546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.792575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.792600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.792626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.792651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.792672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.792694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.792734] [drm:intel_power_well_disable [i915]] disabling display
>[  948.792767] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.792800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.792825] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.792949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.792963] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.793027] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.793051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.793077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.793104] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.793121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.793137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.793152] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.793166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.793180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.793194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.793206] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.793210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.793222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.793225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.793238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.793251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.793263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.793276] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.793293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.793310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.793328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.793345] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.793363] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.793381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.793426] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.793493] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.793516] [drm:intel_power_well_enable [i915]] enabling display
>[  948.793539] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.793577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.793598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.793621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.793642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.793663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.793683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.793707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.793731] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.793755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.793774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.793794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.793817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.793839] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.796937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.796962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.796978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.796995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.800707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.800726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.800743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.803342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.803362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.806251] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.809176] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.809209] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.809225] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.809253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.825951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.825979] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.826016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.826119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.826161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.842653] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.842677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.842723] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.861599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.861618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.861638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.861655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.861672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.861687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.861701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.861717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.861735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.861755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.861776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.861796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.861815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.861832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.861859] [drm:intel_power_well_disable [i915]] disabling display
>[  948.861882] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.861906] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.861923] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.862002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.862011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.862057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.862077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.862097] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.862119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.862137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.862157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.862176] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.862195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.862215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.862234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.862252] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.862256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.862275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.862279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.862299] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.862318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.862337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.862356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.862375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.862394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.862460] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.862484] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.862508] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.862534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.862560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.862626] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.862649] [drm:intel_power_well_enable [i915]] enabling display
>[  948.862671] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.862709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.862975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.862996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.863018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.863038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.863060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.863085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.863108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.863132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.863151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.863172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.863194] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.863216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.866308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.866327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.866343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.866359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.870045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.870062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.870077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.872654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  948.872671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.875544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.878491] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.878554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.878571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.878593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.895296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.895323] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.895360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.895582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.895622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.911976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.912002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.912039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.930891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.930910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.930930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.930949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.930971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.930990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.931010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.931029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.931050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.931071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.931091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.931111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.931130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.931146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.931173] [drm:intel_power_well_disable [i915]] disabling display
>[  948.931196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.931220] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.931236] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.931317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.931327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.931373] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.931392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.931451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  948.931484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  948.931508] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  948.931537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  948.931563] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  948.931588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  948.931612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  948.931636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  948.931658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  948.931665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.931688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  948.931694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  948.931718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  948.931740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  948.931763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  948.931784] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  948.931811] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  948.931833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  948.931856] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  948.931878] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  948.931901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  948.932199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.932225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  948.932287] [drm:intel_power_well_enable [i915]] enabling always-on
>[  948.932309] [drm:intel_power_well_enable [i915]] enabling display
>[  948.932331] [drm:hsw_set_power_well [i915]] Enabling power well
>[  948.932368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.932391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.932430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.932453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.932474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.932497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.932522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.932547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.932736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.932758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.932778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.932802] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  948.932823] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  948.934813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  948.934829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  948.934843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.934861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  948.938540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  948.938558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  948.938577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  948.940075] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  948.940091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  948.944068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  948.947006] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  948.947077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  948.947094] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  948.947116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  948.963818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.963844] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.963881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.964003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.964045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  948.980520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  948.980544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  948.980588] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  948.999467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  948.999487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  948.999509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  948.999529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  948.999551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  948.999570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  948.999589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  948.999609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  948.999630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  948.999651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  948.999671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  948.999691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  948.999710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  948.999726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  948.999753] [drm:intel_power_well_disable [i915]] disabling display
>[  948.999776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  948.999800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  948.999817] [drm:intel_power_well_disable [i915]] disabling always-on
>[  948.999898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  948.999908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  948.999954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  948.999974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  948.999994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.000016] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.000035] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.000054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.000073] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.000093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.000112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.000131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.000149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.000153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.000172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.000175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.000195] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.000214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.000233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.000251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.000270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.000289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.000308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.000326] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.000345] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.000365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.000385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.000487] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.000510] [drm:intel_power_well_enable [i915]] enabling display
>[  949.000532] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.000583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.000608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.000631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.000654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.000675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.000697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.000722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.000743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.000762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.000780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.000795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.000814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.000832] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.003899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.003918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.003934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.003951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.006567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.006585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.006599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.009162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.009181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.012060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.014996] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.015070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.015086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.015109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.031811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.031837] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.031872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.031973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.032013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.048493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.048517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.048552] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.067403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.067441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.067463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.067483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.067504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.067523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.067543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.067562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.067584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.067604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.067624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.067645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.067664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.067679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.067707] [drm:intel_power_well_disable [i915]] disabling display
>[  949.067729] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.067754] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.067771] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.067843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.067860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.067901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.067918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.067935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.067953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.067968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.067986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.068004] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.068021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.068039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.068056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.068073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.068077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.068094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.068097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.068115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.068132] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.068150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.068167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.068184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.068201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.068219] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.068236] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.068253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.068272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.068290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.068333] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.068347] [drm:intel_power_well_enable [i915]] enabling display
>[  949.068369] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.068406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.068451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.068473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.068494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.068514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.068536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.068560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.068583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.068606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.068626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.068645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.068669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.068691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.071776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.071795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.071810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.071826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.075540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.075558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.075574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.078140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.078157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.081031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.083968] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.084041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.084058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.084080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.100782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.100809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.100844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.100951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.100991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.117480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.117504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.117549] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.135442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.135461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.135481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.135498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.135516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.135532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.135547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.135563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.135581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.135597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.135613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.135629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.135643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.135657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.135683] [drm:intel_power_well_disable [i915]] disabling display
>[  949.135704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.135725] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.135741] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.135818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.135827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.135869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.135885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.135903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.135922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.135938] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.135954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.135973] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.135992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.136012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.136031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.136050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.136054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.136072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.136076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.136095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.136114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.136133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.136152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.136171] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.136190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.136209] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.136228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.136246] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.136266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.136287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.136337] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.136350] [drm:intel_power_well_enable [i915]] enabling display
>[  949.136363] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.136391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.136409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.136457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.136480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.136502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.136523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.136547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.136570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.136592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.136612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.136632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.136656] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.136677] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.139763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.139782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.139798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.139814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.143517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.143535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.143550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.146120] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.146139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.149030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.151980] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.152040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.152057] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.152079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.168780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.168808] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.168845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.168956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.168997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.185483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.185507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.185553] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.204459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.204478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.204500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.204520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.204541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.204560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.204580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.204599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.204620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.204641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.204661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.204682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.204700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.204716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.204743] [drm:intel_power_well_disable [i915]] disabling display
>[  949.204766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.204790] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.204807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.204889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.204898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.204944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.204964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.204983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.205005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.205024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.205044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.205063] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.205082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.205102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.205121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.205139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.205143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.205162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.205165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.205185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.205204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.205223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.205242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.205261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.205280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.205299] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.205318] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.205337] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.205357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.205377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.205444] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.205468] [drm:intel_power_well_enable [i915]] enabling display
>[  949.205490] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.205533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.205557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.205581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.205604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.205626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.205650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.205676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.205702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.205733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.205753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.205773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.205797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.205818] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.208903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.208922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.208938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.208953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.211581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.211601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.211617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.214186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.214205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.217083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.219635] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.219688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.219705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.219727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.236454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.236480] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.236515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.236623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.236663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.253129] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.253153] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.253199] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.272067] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.272087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.272107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.272123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.272144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.272164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.272184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.272203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.272225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.272245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.272266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.272286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.272305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.272321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.272348] [drm:intel_power_well_disable [i915]] disabling display
>[  949.272370] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.272395] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.272411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.272668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.272677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.272723] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.272741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.272761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.272781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.272796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.272814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.272832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.272849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.272864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.272879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.272893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.272897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.272911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.272915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.272930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.272944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.272959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.272973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.272990] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.273004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.273019] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.273032] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.273047] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.273063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.273084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.273130] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.273147] [drm:intel_power_well_enable [i915]] enabling display
>[  949.273172] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.273215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.273231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.273245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.273259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.273272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.273286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.273301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.273316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.273331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.273344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.273356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.273373] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.273388] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.276486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.276505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.276521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.276537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.280206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.280224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.280239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.281736] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[  949.281752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.285740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.288676] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.288751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.288771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.288796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.305493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.305519] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.305555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.305665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.305708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.322193] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.322219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.322266] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.341155] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.341174] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.341194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.341210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.341228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.341243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.341257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.341273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.341300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.341322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.341338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.341354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.341368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.341382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.341408] [drm:intel_power_well_disable [i915]] disabling display
>[  949.341479] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.341513] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.341540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.341662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.341677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.341749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.341772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.341798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.341825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.341848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.341871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.341895] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.341918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.341940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.341963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.341984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.341990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.342011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.342016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.342038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.342059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.342080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.342101] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.342125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.342147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.342168] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.342188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.342209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.342232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.342257] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.342323] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.342345] [drm:intel_power_well_enable [i915]] enabling display
>[  949.342367] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.342404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.342426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.342475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.342499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.342521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.342546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.342571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.342596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.342620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.342642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.342664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.342690] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.342713] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.345805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.345824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.345843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.345863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.348462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.348481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.348496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.351079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.351099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.353979] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.356915] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.356989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.357005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.357026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.373729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.373756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.373791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.373898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.373939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.390411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.390452] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.390487] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.409329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.409348] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.409368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.409385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.409403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.409418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.409478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.409507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.409537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.409564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.409590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.409616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.409640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.409663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.409705] [drm:intel_power_well_disable [i915]] disabling display
>[  949.409739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.409771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.409797] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.409920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.409930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.409973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.409990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.410008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.410027] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.410043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.410059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.410076] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.410091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.410106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.410121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.410134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.410138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.410163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.410166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.410184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.410201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.410219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.410236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.410253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.410271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.410288] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.410305] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.410323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.410341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.410360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.410403] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.410416] [drm:intel_power_well_enable [i915]] enabling display
>[  949.410462] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.410502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.410527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.410552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.410575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.410598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.410622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.410649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.410674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.410699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.410721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.410741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.410768] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.410791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.413903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.413923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.413942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.413962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.416594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.416613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.416628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.419194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.419212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.422086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.425010] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.425043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.425060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.425081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.441785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.441811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.441846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.441955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.441994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.458468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.458492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.458527] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.477032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.477051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.477072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.477089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.477106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.477121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.477135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.477151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.477169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.477185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.477201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.477216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.477230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.477244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.477270] [drm:intel_power_well_disable [i915]] disabling display
>[  949.477292] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.477313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.477328] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.477399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.477409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.477496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.477523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.477552] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.477582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.477607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.477635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.477661] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.477687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.477713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.477738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.477981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.477988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.478011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.478018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.478042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.478066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.478090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.478111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.478136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.478160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.478183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.478206] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.478229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.478256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.478283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.478353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.478378] [drm:intel_power_well_enable [i915]] enabling display
>[  949.478409] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.478466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.478490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.478513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.478536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.478559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.478583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.478609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.478633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.478658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.478680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.478702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.478727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.478950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.482054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.482072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.482088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.482104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.485804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.485823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.485839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.488405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.488423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.491321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.494257] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.494330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.494347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.494369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.511072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.511098] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.511133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.511234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.511273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.527755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.527780] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.527817] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.547766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.547785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.547805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.547822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.547839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.547858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.547878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.547897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.547918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.547939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.547959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.547980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.547998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.548015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.548042] [drm:intel_power_well_disable [i915]] disabling display
>[  949.548064] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.548089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.548105] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.548187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.548196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.548241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.548261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.548281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.548303] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.548322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.548342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.548361] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.548380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.548400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.548419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.548438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.548481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.548512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.548519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.548546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.548572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.548598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.548622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.548650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.548675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.548700] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.548724] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.548748] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.548775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.548804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.548875] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.548899] [drm:intel_power_well_enable [i915]] enabling display
>[  949.548924] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.548970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.548992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.549015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.549036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.549058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.549081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.549106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.549130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.549153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.549174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.549196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.549220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.549243] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.552310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.552326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.552340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.552355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.556032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.556049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.556064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.558645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.558665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.561551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.564496] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.564560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.564577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.564599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.581333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.581359] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.581394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.581574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.581614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.598001] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.598025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.598071] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.616939] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.616958] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.616978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.616994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.617013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.617027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.617046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.617066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.617087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.617108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.617128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.617149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.617168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.617184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.617211] [drm:intel_power_well_disable [i915]] disabling display
>[  949.617233] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.617258] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.617274] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.617357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.617366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.617416] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.617432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.617491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.617520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.617542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.617567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.617590] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.617613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.617634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.617656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.617676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.617683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.617703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.617709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.617732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.617752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.617774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.617793] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.617817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.617837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.617858] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.617878] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.617900] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.617922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.617946] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.618010] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.618032] [drm:intel_power_well_enable [i915]] enabling display
>[  949.618053] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.618090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.618111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.618132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.618154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.618173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.618195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.618219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.618242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.618265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.618284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.618305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.618330] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.618351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.621420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.621445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.621495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.621525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.624198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.624215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.624230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.626804] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.626822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.629692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.632627] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.632699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.632714] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.632734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.649443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.649487] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.649522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.649630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.649670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.666125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.666149] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.666184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.685042] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.685061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.685081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.685098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.685116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.685131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.685146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.685162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.685180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.685196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.685212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.685228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.685242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.685256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.685283] [drm:intel_power_well_disable [i915]] disabling display
>[  949.685304] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.685325] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.685347] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.685417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.685426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.685523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.685548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.685576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.685605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.685628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.685654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.685678] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.685701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.685728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.685756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.685777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.685782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.685802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.685807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.685828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.685847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.685867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.685885] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.685908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.685927] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.685947] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.685966] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.685986] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.686007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.686030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.686092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.686114] [drm:intel_power_well_enable [i915]] enabling display
>[  949.686136] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.686173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.686194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.686214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.686236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.686255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.686277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.686301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.686324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.686347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.686366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.686386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.686408] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.686430] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.689538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.689558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.689574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.689590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.693284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.693304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.693323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.695913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.695931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.698830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.701780] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.701840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.701858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.701880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.718582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.718608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.718643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.718743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.718798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.735263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.735287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.735322] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.754142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.754161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.754181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.754198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.754215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.754230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.754244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.754260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.754277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.754293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.754325] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.754342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.754356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.754370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.754397] [drm:intel_power_well_disable [i915]] disabling display
>[  949.754418] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.754439] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.754494] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.754614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.754629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.754697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.754721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.754748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.754777] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.754799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.754824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.754848] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.754871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.754893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.754916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.754937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.754943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.754964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.754970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.754993] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.755014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.755036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.755056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.755081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.755101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.755124] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.755144] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.755166] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.755189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.755215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.755286] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.755308] [drm:intel_power_well_enable [i915]] enabling display
>[  949.755330] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.755366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.755387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.755408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.755427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.755448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.755481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.755505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.755528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.755551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.755570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.755590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.755613] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.755635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.758717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.758737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.758756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.758776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.761344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.761369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.761385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.763972] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.763991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.766899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.769823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.769858] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.769875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.769896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.786601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.786628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.786663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.786769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.786808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.803300] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.803324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.803371] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.821256] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.821275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.821295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.821312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.821330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.821345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.821359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.821375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.821393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.821409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.821425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.821441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.821532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.821549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.821577] [drm:intel_power_well_disable [i915]] disabling display
>[  949.821599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.821621] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.821637] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.821720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.821729] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.821773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.821790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.821808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.821830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.821849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.821870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.821890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.821909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.821929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.821948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.821968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.821972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.821991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.821995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.822015] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.822034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.822054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.822073] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.822092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.822111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.822131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.822150] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.822169] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.822189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.822211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.822257] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.822274] [drm:intel_power_well_enable [i915]] enabling display
>[  949.822289] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.822320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.822340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.822360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.822380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.822400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.822419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.822441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.822486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.822513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.822536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.822559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.822586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.822616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.825712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.825732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.825751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.825771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.829454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.829492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.829509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.832147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.832167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.835048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.837984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.838057] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.838073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.838095] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.854797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.854823] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.854859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.854966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.855006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.871480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.871506] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.871543] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.890384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.890403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.890423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.890440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.890494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.890521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.890624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.890641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.890661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.890678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.890694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.890710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.890724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.890738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.890764] [drm:intel_power_well_disable [i915]] disabling display
>[  949.890786] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.890807] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.890823] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.890903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.890911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.890954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.890971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.890989] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.891008] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.891024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.891041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.891058] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.891074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.891090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.891104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.891119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.891123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.891145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.891148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.891162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.891174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.891188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.891200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.891216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.891229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.891242] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.891255] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.891268] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.891282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.891299] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.891340] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.891353] [drm:intel_power_well_enable [i915]] enabling display
>[  949.891367] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.891394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.891413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.891431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.891449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.891490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.891513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.891537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.891559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.891582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.891601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.891621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.891645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.891667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.895841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.895860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.895876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.895892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.898495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.898513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.898529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.901113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.901133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.904008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.906944] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.907018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.907034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.907056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.923750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.923774] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.923807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.923906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.923943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.940455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  949.940499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  949.940544] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  949.958321] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  949.958340] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  949.958360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.958376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.958394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.958409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.958424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.958439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.958457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.958520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.958543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.958565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.958585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.958604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.958632] [drm:intel_power_well_disable [i915]] disabling display
>[  949.958655] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  949.958680] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.958697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  949.958780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.958789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  949.958852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  949.958870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  949.958889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  949.958909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  949.958925] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  949.958942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  949.958961] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  949.958977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  949.958993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  949.959009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  949.959023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  949.959027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.959046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  949.959050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  949.959070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  949.959090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  949.959109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  949.959128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  949.959148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  949.959167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  949.959187] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  949.959206] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  949.959226] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  949.959247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  949.959268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  949.959315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  949.959332] [drm:intel_power_well_enable [i915]] enabling display
>[  949.959347] [drm:hsw_set_power_well [i915]] Enabling power well
>[  949.959377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  949.959397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  949.959416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  949.959436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  949.959456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  949.959499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  949.959534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  949.959558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  949.959581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.959601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  949.959622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  949.959646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  949.959668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  949.962739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  949.962757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  949.962773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.962789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  949.965357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  949.965373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  949.965391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  949.967965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  949.967983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  949.970879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  949.973801] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  949.973843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  949.973858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  949.973878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  949.990566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  949.990590] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  949.990623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  949.990726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  949.990764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.007279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  950.007303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.007349] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  950.026200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  950.026218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.026238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.026255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.026273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.026288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.026302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.026318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.026336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.026352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.026368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.026384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.026398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.026412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.026438] [drm:intel_power_well_disable [i915]] disabling display
>[  950.026459] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.026516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  950.026540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.027841] [IGT] kms_flip: exiting, ret=0
>[  950.052884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.052904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.052924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.052945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.052962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.052980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.052998] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.053018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.053038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.053058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.053077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.053082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.053101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.053104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.053124] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.053144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.053164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.053183] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.053204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.053223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.053243] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  950.053262] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.053282] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.053303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.053325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.053381] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.053399] [drm:intel_power_well_enable [i915]] enabling display
>[  950.053415] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.053448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.053468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.053504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.053524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.053543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.053570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.053590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.053607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.053624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.053638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.053651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.053668] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.053684] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.056758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.056774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.056789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.056804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.060437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.060453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.060477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.062979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.062995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.066974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.069994] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.070032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.070046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.070070] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.070122] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.070145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.086776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.086798] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.086834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.086964] Console: switching to colour frame buffer device 240x75
>[  950.228817] Console: switching to colour dummy device 80x25
>[  950.228911] [IGT] kms_flip: executing
>[  950.239004] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  950.239033] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  950.240545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  950.240566] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  950.242535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  950.242541] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  950.244537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  950.244557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  950.246537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  950.246543] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  950.246547] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  950.246564] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  950.246587] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  950.247621] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  950.249602] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  950.249621] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  950.249636] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  950.249650] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  950.250650] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  950.250673] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  950.251729] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  950.251732] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  950.251812] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  950.251814] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  950.251818] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  950.251820] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  950.251824] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  950.251826] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  950.251834] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  950.251836] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.251839] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  950.251841] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  950.251844] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  950.251846] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  950.251849] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  950.251851] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  950.251854] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  950.251856] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  950.251859] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  950.251861] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  950.251863] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  950.251866] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  950.251868] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  950.251871] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  950.251873] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  950.251876] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  950.251878] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  950.251880] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  950.251883] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  950.251885] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  950.251888] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  950.251890] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  950.251893] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  950.251895] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  950.251897] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  950.251900] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  950.251902] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  950.251905] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  950.251907] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  950.251939] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  950.251956] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  950.253525] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  950.253543] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  950.255537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  950.255543] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  950.257537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  950.257558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  950.259535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  950.259541] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  950.259545] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  950.259771] [IGT] kms_flip: starting subtest dpms-vs-vblank-race
>[  950.260183] [drm:drm_mode_addfb2] [FB:77]
>[  950.260205] [drm:drm_mode_addfb2] [FB:79]
>[  950.302547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  950.302600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.303641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.303675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.303732] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.322586] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.322609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.322625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.322645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.322662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.322680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.322695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.322709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.322725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.322743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.322759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.322775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.322790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.322804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.322819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.322846] [drm:intel_power_well_disable [i915]] disabling display
>[  950.322868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.322889] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.322907] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.322953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  950.323017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  950.323062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  950.323072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  950.323118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.323132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.323149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.323167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.323181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.323196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.323211] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.323226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.323240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.323253] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.323266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.323269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.323282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.323285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.323298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.323310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.323323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.323335] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.323350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.323363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.323375] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  950.323388] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.323400] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.323415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.323432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.325979] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.325996] [drm:intel_power_well_enable [i915]] enabling display
>[  950.326012] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.326042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.326061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.326080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.326099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.326118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.326136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.326156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.326176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.326196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.326214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.326230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.326250] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.326268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.329333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.329352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.329368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.329385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.331963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.331980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.331995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.334563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.334583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.337456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.340397] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.340465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.340484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.340543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.340697] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.340714] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.357210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.357237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.357274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.374092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.374111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.374130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.374150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.374166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.374183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.374199] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.374215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.374231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.374246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.374260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.374264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.374278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.374281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.374296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.374309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.374323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.374337] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.374353] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.374367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.374382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.374395] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.374414] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.374434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.374455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.390575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.390599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.390641] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.409531] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.409553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.409569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.409588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.409606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.409622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.409637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.409652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.409668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.409685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.409702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.409718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.409732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.409747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.409773] [drm:intel_power_well_disable [i915]] disabling display
>[  950.409794] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.409812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.409833] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.409855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.409870] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.409990] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.410006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.410023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.410041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.410055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.410070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.410087] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.410105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.410122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.410140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.410157] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.410161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.410178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.410181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.410199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.410216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.410233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.410250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.410268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.410285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.410303] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.410320] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.410338] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.410356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.410375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.410419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.410433] [drm:intel_power_well_enable [i915]] enabling display
>[  950.410447] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.410474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.410522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.410547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.410572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.410594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.410619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.410645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.410670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.410695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.410718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.410740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.410766] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.410790] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.413872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.413889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.413904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.413918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.416529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.416546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.416561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.420207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.420224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.423102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.426026] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.426060] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.426076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.426098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.426136] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.426155] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.426198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.426222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.426257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.476265] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.476287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.476309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.476332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.476352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.476373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.476394] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.476414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.476434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.476455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.476475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.476479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.476534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.476542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.476572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.476599] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.476625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.476650] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.476677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.476702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.476729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.476754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.476779] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.476807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.477029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.492875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.492901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.492940] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.511806] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.511828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.511845] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.511865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.511882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.511897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.511913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.511927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.511943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.511960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.511976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.511992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.512006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.512020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.512046] [drm:intel_power_well_disable [i915]] disabling display
>[  950.512067] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.512083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.512099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.512117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.512131] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.512356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.512372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.512398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.512415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.512430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.512445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.512462] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.512479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.512537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.512558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.512578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.512584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.512604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.512610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.512630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.512650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.512670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.512689] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.512711] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.512731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.512752] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.512771] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.512791] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.512814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.512838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.512902] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.512921] [drm:intel_power_well_enable [i915]] enabling display
>[  950.512935] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.512959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.512974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.512988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.513001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.513015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.513029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.513044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.513059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.513073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.513086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.513099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.513116] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.513130] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.516268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.516287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.516303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.516320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.520019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.520038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.520054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.522646] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.522666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.525616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.528563] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.528626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.528643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.528666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.528705] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.528722] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.528762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.528783] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.528821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.578813] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.578833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.578853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.578877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.578897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.578918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.578938] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.578959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.578979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.578999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.579019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.579024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.579044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.579047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.579068] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.579088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.579108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.579128] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.579148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.579168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.579189] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.579210] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.579230] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.579251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.579273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.595440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.595466] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.595504] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.614404] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.614426] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.614442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.614462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.614479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.614495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.614552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.614661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.614678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.614696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.614713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.614733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.614753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.614773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.614799] [drm:intel_power_well_disable [i915]] disabling display
>[  950.614823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.614843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.614865] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.614894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.614909] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.615187] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.615204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.615221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.615239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.615253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.615268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.615284] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.615298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.615312] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.615325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.615338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.615341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.615354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.615357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.615370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.615383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.615396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.615408] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.615423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.615440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.615458] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.615475] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.615494] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.615544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.615569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.615634] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.615655] [drm:intel_power_well_enable [i915]] enabling display
>[  950.615675] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.615869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.615885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.615900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.615914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.615928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.615942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.615958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.615973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.615991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.616009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.616027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.616046] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.616064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.619135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.619154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.619170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.619186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.622878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.622897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.622913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.625470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.625488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.628414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.631348] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.631425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.631442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.631464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.631540] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.631567] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.631631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.631658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.631691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.681603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.681623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.681641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.681661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.681676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.681693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.681710] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.681726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.681742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.681756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.681771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.681775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.681789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.681792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.681807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.681821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.681834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.681848] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.681864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.681879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.681894] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.681907] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.681921] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.681937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.681955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.698206] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.698228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.698273] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.717155] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.717179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.717199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.717220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.717240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.717259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.717279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.717298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.717317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.717338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.717359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.717379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.717398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.717414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.717442] [drm:intel_power_well_disable [i915]] disabling display
>[  950.717464] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.717485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.717505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.717570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.717594] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.717877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.717895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.717914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.717934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.717950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.717967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.717984] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.718000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.718016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.718031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.718050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.718055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.718074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.718078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.718098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.718118] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.718137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.718157] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.718176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.718195] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.718215] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.718235] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.718254] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.718274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.718295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.718344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.718359] [drm:intel_power_well_enable [i915]] enabling display
>[  950.718372] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.718398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.718414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.718432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.718450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.718468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.718486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.718510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.718556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.718581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.718601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.718622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.718646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.718667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.721735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.721753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.721769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.721785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.724347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.724363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.724377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.726937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.726954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.729829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.732777] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.732838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.732855] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.732877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.732925] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.732951] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.733013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.733044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.733079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.783002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.783022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.783041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.783060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.783076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.783093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.783110] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.783126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.783141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.783156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.783170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.783174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.783188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.783192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.783206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.783220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.783234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.783248] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.783264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.783279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.783294] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.783308] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.783321] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.783338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.783355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.799620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.799643] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.799688] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.818560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.818582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.818598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.818618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.818635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.818651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.818666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.818682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.818698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.818715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.818730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.818746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.818760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.818775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.818801] [drm:intel_power_well_disable [i915]] disabling display
>[  950.818822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.818838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.818855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.818872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.818887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.819182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.819199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.819217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.819237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.819253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.819270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.819286] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.819302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.819317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.819332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.819346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.819350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.819364] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.819367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.819387] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.819406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.819425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.819444] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.819463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.819482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.819503] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.819566] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.819591] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.819617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.819644] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.819716] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.819737] [drm:intel_power_well_enable [i915]] enabling display
>[  950.819756] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.819794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.819818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.819840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.819863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.819885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.819907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.819932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.819956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.819980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.820001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.820022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.820048] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.820072] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.823108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.823126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.823142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.823159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.825754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.825772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.825789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.828356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.828375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.831256] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.834181] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.834214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.834230] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.834252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.834290] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.834306] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.834347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.834368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.834400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.884419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.884441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.884462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.884486] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.884506] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.884564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.884591] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.884619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.884645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.884670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.884695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.884702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.884725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.884731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.884755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.884779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.884804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.884825] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.884851] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.884874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.884898] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.884920] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.884943] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.884969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.884997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.901030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.901056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.901094] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  950.919959] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  950.919981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  950.919997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  950.920017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.920034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.920049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.920068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.920088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.920107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.920128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.920149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.920169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.920188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.920204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.920232] [drm:intel_power_well_disable [i915]] disabling display
>[  950.920254] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  950.920274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.920294] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.920317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.920332] [drm:intel_power_well_disable [i915]] disabling always-on
>[  950.920668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.920693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.920723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.920752] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.920775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.920801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.920825] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.920849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.920872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.920895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.920916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.920922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.920943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.920949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.920972] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.920992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.921014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.921035] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.921059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.921080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.921103] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.921124] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.921145] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.921169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.921194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.921269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  950.921292] [drm:intel_power_well_enable [i915]] enabling display
>[  950.921314] [drm:hsw_set_power_well [i915]] Enabling power well
>[  950.921349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  950.921370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  950.921391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  950.921410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  950.921430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  950.921450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  950.921473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  950.921496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  950.921520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.921680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  950.921700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  950.921724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  950.921745] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  950.923736] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  950.923752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  950.923766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.923781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  950.925282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  950.925297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  950.925311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  950.926805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  950.926821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  950.928625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  950.931567] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  950.931634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  950.931651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  950.931673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  950.931712] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  950.931728] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  950.931769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  950.931790] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  950.931822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  950.981833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  950.981855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  950.981876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  950.981900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  950.981920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  950.981941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  950.981961] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  950.981982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  950.982002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  950.982022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  950.982042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  950.982047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.982066] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  950.982070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  950.982091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  950.982112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  950.982132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  950.982152] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  950.982172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  950.982192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  950.982213] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  950.982233] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  950.982254] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  950.982275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  950.982297] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  950.998416] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  950.998441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  950.998476] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.017329] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.017350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.017367] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.017386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.017402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.017418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.017433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.017447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.017463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.017480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.017496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.017512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.017570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.017592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.017636] [drm:intel_power_well_disable [i915]] disabling display
>[  951.017672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.017699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.017725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.017755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.017778] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.018068] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.018085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.018103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.018123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.018138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.018155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.018174] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.018193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.018213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.018231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.018250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.018254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.018273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.018277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.018296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.018315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.018335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.018353] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.018372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.018391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.018411] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.018430] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.018449] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.018468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.018489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.018570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.018594] [drm:intel_power_well_enable [i915]] enabling display
>[  951.018617] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.018666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.018688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.018710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.018731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.018751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.018772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.018796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.018819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.018842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.018862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.018881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.018906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.018929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.020913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.020931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.020948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.020966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.022472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.022489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.022503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.024028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.024046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.025875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.028809] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.028882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.028897] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.028917] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.028952] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.028967] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.029007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.029026] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.029056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.079040] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.079060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.079080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.079103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.079124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.079145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.079165] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.079185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.079206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.079226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.079246] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.079250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.079270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.079274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.079294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.079314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.079335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.079355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.079375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.079395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.079416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.079436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.079457] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.079478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.079500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.095667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.095691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.095728] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.114594] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.114616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.114632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.114652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.114669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.114685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.114701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.114716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.114732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.114749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.114766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.114782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.114796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.114810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.114836] [drm:intel_power_well_disable [i915]] disabling display
>[  951.114858] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.114873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.114890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.114907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.114921] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.115185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.115202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.115220] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.115238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.115253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.115269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.115285] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.115300] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.115314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.115332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.115350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.115354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.115372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.115376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.115395] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.115413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.115432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.115450] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.115469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.115487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.115506] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.115529] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.115583] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.115603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.115624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.115669] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.115685] [drm:intel_power_well_enable [i915]] enabling display
>[  951.115699] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.115727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.115744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.115759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.115775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.115794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.115814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.115835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.115857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.115878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.115898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.115918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.115940] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.115967] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.117960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.117976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.117990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.118005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.119510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.119532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.119577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.121079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.121096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.122919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.125871] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.125929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.125946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.125967] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.126017] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.126043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.126106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.126134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.126168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.176129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.176150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.176170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.176191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.176208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.176226] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.176244] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.176261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.176277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.176293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.176308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.176312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.176327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.176331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.176346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.176362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.176377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.176391] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.176409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.176429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.176450] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.176470] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.176491] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.176512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.176534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.192711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.192735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.192771] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.211628] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.211650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.211666] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.211686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.211702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.211718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.211733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.211748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.211764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.211782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.211798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.211814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.211828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.211842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.211868] [drm:intel_power_well_disable [i915]] disabling display
>[  951.211890] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.211905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.211922] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.211940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.211954] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.212186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.212203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.212221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.212240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.212255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.212272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.212288] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.212304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.212319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.212342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.212354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.212358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.212375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.212378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.212396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.212414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.212431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.212448] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.212466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.212483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.212501] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.212518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.212536] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.212593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.212619] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.212682] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.212704] [drm:intel_power_well_enable [i915]] enabling display
>[  951.212723] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.212762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.212786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.212807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.212829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.212846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.212863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.212883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.212903] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.212922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.212940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.212958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.212976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.212994] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.214968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.214985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.215000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.215014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.216520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.216535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.216582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.218088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.218105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.219970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.222911] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.222980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.222999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.223025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.223066] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.223085] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.223131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.223155] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.223190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.273126] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.273147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.273168] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.273191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.273211] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.273232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.273253] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.273273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.273294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.273314] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.273334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.273338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.273358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.273362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.273382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.273402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.273423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.273442] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.273463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.273483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.273504] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.273524] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.273574] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.273603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.273630] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.289761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.289785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.289821] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.308685] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.308707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.308724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.308743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.308760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.308776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.308791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.308806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.308822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.308839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.308856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.308872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.308886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.308904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.308932] [drm:intel_power_well_disable [i915]] disabling display
>[  951.308954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.308974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.308995] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.309017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.309032] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.309337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.309355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.309374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.309394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.309410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.309427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.309444] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.309460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.309475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.309490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.309504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.309508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.309526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.309570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.309596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.309619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.309641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.309663] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.309695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.309715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.309736] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.309756] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.309775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.309798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.309822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.310066] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.310080] [drm:intel_power_well_enable [i915]] enabling display
>[  951.310093] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.310119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.310134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.310149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.310163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.310177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.310191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.310207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.310222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.310237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.310250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.310263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.310279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.310294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.312262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.312278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.312292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.312306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.313809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.313825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.313842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.315335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.315351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.317155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.320075] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.320112] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.320128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.320150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.320188] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.320207] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.320253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.320277] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.320313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.370281] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.370303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.370325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.370348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.370368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.370389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.370409] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.370430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.370450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.370470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.370490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.370494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.370514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.370518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.370539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.370590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.370616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.370639] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.370664] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.370687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.370711] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.370733] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.370755] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.370780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.370806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.386896] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.386920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.386955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.405309] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.405330] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.405347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.405366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.405383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.405399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.405414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.405428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.405444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.405461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.405477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.405492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.405507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.405521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.405588] [drm:intel_power_well_disable [i915]] disabling display
>[  951.405624] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.405778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.405797] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.405817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.405832] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.406103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.406119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.406136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.406154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.406168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.406183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.406198] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.406212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.406227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.406240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.406253] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.406257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.406269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.406273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.406286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.406299] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.406312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.406324] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.406339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.406351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.406365] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.406377] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.406389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.406404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.406420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.406460] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.406474] [drm:intel_power_well_enable [i915]] enabling display
>[  951.406486] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.406510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.406528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.406549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.406591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.406607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.406621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.406637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.406653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.406668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.406682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.406694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.406712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.406727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.408695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.408712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.408729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.408747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.410251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.410269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.410286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.411781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.411798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.413601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.416516] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.416589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.416620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.416721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.416761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.416780] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.416827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.416851] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.416886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.466719] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.466739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.466759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.466780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.466797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.466815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.466833] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.466850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.466866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.466882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.466897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.466901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.466916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.466920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.466935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.466950] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.466965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.466980] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.466997] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.467016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.467037] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.467058] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.467078] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.467099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.467122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.483357] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.483382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.483417] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.501318] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.501339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.501356] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.501376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.501393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.501408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.501424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.501439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.501455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.501472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.501488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.501504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.501519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.501533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.501601] [drm:intel_power_well_disable [i915]] disabling display
>[  951.501635] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.501662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.501689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.501885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.501909] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.502177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.502193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.502210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.502227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.502241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.502257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.502272] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.502287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.502301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.502315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.502327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.502331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.502343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.502346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.502359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.502372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.502385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.502397] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.502414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.502432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.502450] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.502468] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.502485] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.502503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.502522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.502595] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.502619] [drm:intel_power_well_enable [i915]] enabling display
>[  951.502642] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.502680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.502703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.502726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.502748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.502770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.502792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.502817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.502842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.502867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.502887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.503128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.503152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.503174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.505183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.505200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.505214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.505229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.506752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.506769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.506784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.508278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.508295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.510103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.513036] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.513113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.513130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.513152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.513190] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.513207] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.513250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.513270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.513308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.563283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.563305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.563327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.563350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.563370] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.563391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.563411] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.563432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.563452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.563472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.563492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.563497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.563517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.563520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.563541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.563561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.563610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.563640] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.563666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.563692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.563720] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.563743] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.563767] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.563795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.563824] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.579895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.579919] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.579954] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.598296] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.598318] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.598334] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.598353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.598370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.598386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.598405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.598424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.598443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.598464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.598484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.598505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.598524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.598540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.598609] [drm:intel_power_well_disable [i915]] disabling display
>[  951.598644] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.598674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.598703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.598888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.598913] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.599164] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.599182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.599200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.599220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.599235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.599252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.599276] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.599290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.599304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.599317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.599330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.599334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.599346] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.599349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.599362] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.599375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.599388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.599399] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.599414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.599427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.599440] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.599457] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.599474] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.599493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.599512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.599553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.599594] [drm:intel_power_well_enable [i915]] enabling display
>[  951.599618] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.599656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.599679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.599702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.599723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.599745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.599767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.599793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.599818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.599843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.599863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.599884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.599910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.599932] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.602192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.602208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.602222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.602237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.603743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.603760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.603778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.605272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.605289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.607096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.610016] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.610052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.610068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.610090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.610128] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.610144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.610187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.610210] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.610245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.660219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.660240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.660260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.660281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.660297] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.660315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.660334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.660350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.660367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.660382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.660397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.660401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.660416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.660420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.660436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.660451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.660465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.660480] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.660498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.660513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.660529] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.660543] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.660558] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.660604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.660635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.676836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.676861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.676897] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.695756] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.695778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.695794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.695814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.695831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.695847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.695862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.695876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.695892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.695912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.695937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.695961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.695976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.695990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.696017] [drm:intel_power_well_disable [i915]] disabling display
>[  951.696038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.696054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.696071] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.696088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.696102] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.696336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.696353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.696371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.696390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.696408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.696428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.696447] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.696467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.696486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.696505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.696523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.696527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.696546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.696550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.696611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.696636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.696666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.696686] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.696709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.696729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.696751] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.696771] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.696791] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.696814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.696838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.696903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.696926] [drm:intel_power_well_enable [i915]] enabling display
>[  951.696947] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.696983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.696998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.697012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.697025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.697039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.697053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.697068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.697083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.697098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.697111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.697124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.697140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.697154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.699134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.699150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.699164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.699181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.700693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.700708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.700722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.702215] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.702230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.704035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.706977] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.707044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.707061] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.707083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.707122] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.707139] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.707183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.707207] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.707242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.757208] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.757230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.757251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.757275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.757295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.757316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.757336] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.757356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.757377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.757397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.757417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.757421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.757441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.757445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.757466] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.757486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.757506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.757526] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.757546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.757566] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.757620] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.757646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.757669] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.757694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.757721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.773827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.773851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.773887] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.792750] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.792772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.792789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.792808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.792825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.792841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.792856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.792871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.792887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.792904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.792920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.792936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.792950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.792964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.792990] [drm:intel_power_well_disable [i915]] disabling display
>[  951.793012] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.793027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.793044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.793062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.793076] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.793354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.793372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.793390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.793409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.793425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.793441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.793458] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.793474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.793489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.793503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.793518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.793522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.793536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.793539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.793553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.793574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.793669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.793690] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.793710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.793730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.793752] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.793772] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.793793] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.793815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.793838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.793888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.793914] [drm:intel_power_well_enable [i915]] enabling display
>[  951.793938] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.793982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.794015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.794038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.794060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.794082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.794106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.794131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.794155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.794179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.794201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.794216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.794233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.794248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.796220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.796237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.796251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.796266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.797772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.797787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.797800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.799293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.799308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.801115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.804038] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.804072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.804088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.804110] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.804148] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.804164] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.804214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.804233] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.804263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.854240] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.854262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.854284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.854307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.854328] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.854349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.854369] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.854389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.854410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.854430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.854450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.854454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.854474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.854478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.854498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.854519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.854539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.854559] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.854579] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.854631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.854658] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.854681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.854704] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.854730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.854756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.870857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.870881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.870916] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.889777] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.889799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.889816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.889836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.889852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.889868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.889883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.889898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.889914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.889932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.889948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.889964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.889979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.889993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.890020] [drm:intel_power_well_disable [i915]] disabling display
>[  951.890041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.890057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.890073] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.890091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.890106] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.890409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.890425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.890442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.890460] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.890474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.890489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.890505] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.890519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.890533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.890547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.890560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.890564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.890618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.890626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.890646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.890667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.890686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.890705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.890728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.890747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.890768] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.890788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.890807] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.890830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.890854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.891087] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.891101] [drm:intel_power_well_enable [i915]] enabling display
>[  951.891113] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.891139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.891155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.891172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.891190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.891208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.891226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.891245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.891265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.891285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.891302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.891321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.891340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.891358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.893326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.893344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.893361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.893379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.894886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.894902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.894916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.896412] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.896430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.898236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.901157] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.901194] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.901213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.901239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.901279] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.901298] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.901344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.901368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.901403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.951341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.951363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.951384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.951408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.951428] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.951449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.951470] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.951490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.951510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.951530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.951550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.951554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.951574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.951605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.951634] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.951659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.951683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.951706] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.951730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.951752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.951776] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.951798] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.951820] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.951846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.951873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.967978] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  951.968002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  951.968037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  951.986343] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  951.986365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  951.986381] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  951.986401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.986420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.986440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.986459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.986478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.986497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.986518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.986539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.986559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.986578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.986638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.986682] [drm:intel_power_well_disable [i915]] disabling display
>[  951.986786] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  951.986806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.986826] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.986848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.986864] [drm:intel_power_well_disable [i915]] disabling always-on
>[  951.987152] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  951.987170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  951.987188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  951.987207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  951.987223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  951.987239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  951.987256] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  951.987271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  951.987287] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  951.987304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  951.987323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  951.987327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.987345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  951.987348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  951.987367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  951.987386] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  951.987404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  951.987422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  951.987441] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  951.987459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  951.987478] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  951.987496] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  951.987515] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  951.987534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  951.987554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  951.987643] [drm:intel_power_well_enable [i915]] enabling always-on
>[  951.987667] [drm:intel_power_well_enable [i915]] enabling display
>[  951.987688] [drm:hsw_set_power_well [i915]] Enabling power well
>[  951.987728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  951.987759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  951.987781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  951.987801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  951.987822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  951.987843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  951.987869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  951.988046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  951.988062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  951.988076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  951.988090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  951.988106] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  951.988122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  951.990119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  951.990136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  951.990150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.990164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  951.991671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  951.991686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  951.991700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  951.993199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  951.993215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  951.995040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  951.997983] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  951.998051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  951.998070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  951.998096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  951.998137] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  951.998157] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  951.998203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  951.998227] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  951.998262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.048216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.048237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.048257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.048278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.048295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.048313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.048331] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.048348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.048365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.048381] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.048396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.048400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.048415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.048419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.048434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.048449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.048464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.048479] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.048497] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.048512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.048528] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.048543] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.048557] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.048575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.048625] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.064832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.064857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.064892] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.083756] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.083778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.083794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.083814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.083830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.083846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.083862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.083877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.083893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.083910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.083930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.083950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.083969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.083986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.084014] [drm:intel_power_well_disable [i915]] disabling display
>[  952.084036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.084056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.084077] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.084099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.084114] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.084407] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.084426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.084444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.084463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.084479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.084496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.084513] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.084528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.084547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.084566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.084589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.084628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.084646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.084650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.084666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.084683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.084698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.084713] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.084730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.084747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.084763] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.084778] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.084793] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.084812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.084830] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.084876] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.084893] [drm:intel_power_well_enable [i915]] enabling display
>[  952.084907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.084934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.084959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.084982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.085006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.085030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.085061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.085086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.085110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.085133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.085154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.085175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.085200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.085223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.087213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.087229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.087243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.087258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.088762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.088778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.088796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.090292] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.090309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.092115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.095035] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.095073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.095089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.095111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.095149] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.095166] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.095209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.095230] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.095262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.145228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.145248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.145269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.145292] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.145312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.145333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.145353] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.145374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.145394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.145414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.145434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.145438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.145458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.145462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.145482] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.145503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.145523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.145543] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.145563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.145583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.145637] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.145663] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.145686] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.145712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.145738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.161856] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.161880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.161916] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.180775] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.180797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.180816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.180838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.180858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.180877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.180897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.180916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.180935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.180955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.180976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.180997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.181016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.181032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.181059] [drm:intel_power_well_disable [i915]] disabling display
>[  952.181082] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.181102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.181123] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.181144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.181160] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.181453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.181471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.181488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.181506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.181520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.181535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.181551] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.181565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.181579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.181633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.181655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.181662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.181681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.181687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.181707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.181727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.181747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.181766] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.181788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.181807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.181829] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.181848] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.181867] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.181890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.181913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.182148] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.182163] [drm:intel_power_well_enable [i915]] enabling display
>[  952.182176] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.182203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.182218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.182233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.182247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.182261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.182275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.182291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.182306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.182320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.182333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.182346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.182362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.182378] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.184345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.184361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.184375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.184389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.185893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.185908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.185921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.187413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.187428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.189233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.192153] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.192190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.192206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.192228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.192266] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.192283] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.192326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.192347] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.192379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.242361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.242381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.242401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.242423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.242444] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.242465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.242486] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.242506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.242527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.242547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.242567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.242571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.242591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.242622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.242651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.242675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.242700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.242722] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.242747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.242769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.242794] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.242816] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.242838] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.242863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.242891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.258974] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.258998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.259033] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.277360] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.277384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.277404] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.277425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.277445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.277465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.277484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.277503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.277523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.277543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.277564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.277584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.277642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.277667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.277711] [drm:intel_power_well_disable [i915]] disabling display
>[  952.277840] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.277859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.277878] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.277898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.277914] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.278191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.278211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.278231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.278253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.278272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.278292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.278311] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.278330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.278349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.278368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.278387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.278391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.278410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.278414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.278433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.278452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.278471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.278489] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.278509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.278527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.278547] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.278566] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.278585] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.278642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.278671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.278743] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.278766] [drm:intel_power_well_enable [i915]] enabling display
>[  952.278930] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.278958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.278974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.278989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.279003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.279016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.279031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.279047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.279062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.279077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.279090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.279103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.279119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.279134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.281134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.281149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.281163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.281178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.282686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.282701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.282715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.284215] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.284234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.286038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.288980] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.289048] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.289065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.289087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.289126] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.289143] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.289188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.289211] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.289247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.339212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.339232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.339252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.339273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.339290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.339308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.339328] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.339348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.339369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.339389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.339409] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.339413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.339433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.339437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.339458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.339478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.339498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.339518] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.339538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.339558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.339580] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.339600] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.339651] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.339680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.339707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.355850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.355876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.355913] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.374776] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.374798] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.374817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.374839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.374859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.374878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.374898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.374917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.374936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.374957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.374977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.374998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.375017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.375033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.375060] [drm:intel_power_well_disable [i915]] disabling display
>[  952.375083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.375103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.375123] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.375146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.375161] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.375465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.375483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.375501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.375521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.375536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.375553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.375570] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.375586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.375608] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.375659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.375675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.375679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.375698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.375704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.375724] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.375745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.375765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.375786] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.375807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.375827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.375849] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.375870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.375890] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.375913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.375935] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.375984] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.376017] [drm:intel_power_well_enable [i915]] enabling display
>[  952.376039] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.376079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.376104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.376128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.376152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.376174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.376197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.376222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.376246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.376270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.376292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.376314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.376335] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.376350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.378318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.378334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.378348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.378363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.379868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.379883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.379897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.381390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.381406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.383213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.386135] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.386170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.386197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.386219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.386253] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.386268] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.386308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.386327] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.386357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.436342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.436363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.436383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.436404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.436420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.436439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.436457] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.436474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.436491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.436507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.436522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.436526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.436541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.436545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.436560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.436576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.436591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.436608] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.436658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.436682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.436706] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.436727] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.436749] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.436774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.436800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.452954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.452978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.453014] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.471871] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.471893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.471909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.471929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.471948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.471968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.471988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.472007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.472026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.472047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.472068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.472088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.472107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.472123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.472151] [drm:intel_power_well_disable [i915]] disabling display
>[  952.472173] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.472193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.472214] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.472236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.472251] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.472517] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.472533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.472551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.472569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.472583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.472599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.472652] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.472675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.472697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.472717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.472737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.472743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.472763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.472769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.472789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.472808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.472828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.472847] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.472870] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.472889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.472910] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.472930] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.472949] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.472971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.472995] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.473219] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.473233] [drm:intel_power_well_enable [i915]] enabling display
>[  952.473246] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.473272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.473288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.473302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.473316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.473334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.473352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.473371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.473390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.473410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.473427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.473445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.473463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.473481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.475450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.475466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.475481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.475495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.476998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.477013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.477027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.478520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.478536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.480341] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.483262] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.483297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.483314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.483336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.483373] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.483390] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.483433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.483454] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.483486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.533465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.533485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.533505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.533529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.533549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.533570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.533590] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.533610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.533662] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.533687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.533710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.533717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.533739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.533746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.533768] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.533790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.533815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.533986] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.534004] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.534021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.534037] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.534053] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.534067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.534085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.534103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.550081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.550105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.550142] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.568988] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.569010] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.569026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.569045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.569062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.569078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.569093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.569108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.569123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.569140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.569156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.569172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.569187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.569201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.569227] [drm:intel_power_well_disable [i915]] disabling display
>[  952.569249] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.569269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.569290] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.569312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.569327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.569694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.569827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.569845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.569864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.569879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.569895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.569913] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.569931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.569950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.569968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.569986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.569990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.570007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.570011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.570029] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.570047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.570065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.570082] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.570100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.570117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.570136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.570154] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.570171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.570190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.570209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.570252] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.570267] [drm:intel_power_well_enable [i915]] enabling display
>[  952.570281] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.570308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.570326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.570344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.570362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.570380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.570397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.570417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.570436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.570455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.570473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.570491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.570510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.570527] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.572497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.572513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.572528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.572543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.574046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.574061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.574074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.575570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.575586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.577393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.580312] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.580350] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.580365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.580387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.580425] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.580442] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.580485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.580505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.580537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.630506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.630527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.630547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.630568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.630588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.630609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.630659] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.630684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.630708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.630730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.630752] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.630758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.630782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.630919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.630936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.630952] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.630968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.630982] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.630999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.631016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.631031] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.631046] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.631065] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.631086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.631107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.647134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.647160] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.647197] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.666054] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.666076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.666092] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.666111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.666128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.666147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.666167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.666186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.666205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.666225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.666246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.666266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.666285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.666301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.666329] [drm:intel_power_well_disable [i915]] disabling display
>[  952.666351] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.666371] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.666391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.666413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.666428] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.666764] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.666793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.666821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.666851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.666883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.666908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.666929] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.666945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.666959] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.666972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.666985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.666989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.667001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.667005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.667018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.667031] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.667044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.667057] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.667073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.667085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.667099] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.667112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.667125] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.667140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.667157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.667200] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.667214] [drm:intel_power_well_enable [i915]] enabling display
>[  952.667227] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.667253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.667272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.667290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.667308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.667326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.667343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.667363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.667382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.667401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.667418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.667436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.667455] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.667472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.669443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.669460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.669475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.669490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.670992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.671010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.671027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.672519] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.672536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.674339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.677256] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.677297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.677316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.677342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.677382] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.677400] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.677445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.677469] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.677504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.727540] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.727573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.727606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.727640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.727720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.727765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.727806] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.727847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.727887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.727924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.727963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.727974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.728012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.728021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.728060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.728098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.728137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.728174] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.728203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.728226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.728251] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.728274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.728297] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.728325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.728355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.744101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.744125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.744160] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.763008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.763030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.763046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.763066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.763082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.763098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.763113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.763128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.763144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.763161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.763177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.763193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.763208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.763221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.763248] [drm:intel_power_well_disable [i915]] disabling display
>[  952.763269] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.763284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.763301] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.763318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.763333] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.763690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.763718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.763745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.763774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.763797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.763822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.763846] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.763872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.763897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.763920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.763944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.763950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.763973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.763979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.764003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.764026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.764049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.764073] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.764105] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.764118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.764132] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.764145] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.764162] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.764181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.764201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.764245] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.764260] [drm:intel_power_well_enable [i915]] enabling display
>[  952.764274] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.764301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.764320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.764338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.764356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.764373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.764391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.764411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.764430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.764449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.764467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.764482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.764502] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.764520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.766490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.766506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.766523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.766541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.768047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.768063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.768077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.769583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.769599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.771406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.774340] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.774416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.774433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.774455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.774493] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.774510] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.774553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.774574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.774606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.824562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.824584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.824606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.824629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.824682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.824710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.824735] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.824761] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.824785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.824807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.824830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.824837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.824860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.824866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.824891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.824914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.824935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.824949] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.824967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.824981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.825002] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.825021] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.825042] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.825062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.825083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.841198] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.841223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.841258] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.860114] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.860138] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.860158] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.860179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.860199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.860218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.860238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.860257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.860276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.860297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.860317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.860338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.860357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.860375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.860403] [drm:intel_power_well_disable [i915]] disabling display
>[  952.860426] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.860446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.860466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.860488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.860504] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.860881] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.860900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.860920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.860940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.860956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.860974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.860991] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.861006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.861023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.861037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.861053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.861057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.861071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.861075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.861089] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.861104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.861118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.861132] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.861149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.861163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.861178] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.861192] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.861206] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.861223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.861242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.861292] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.861306] [drm:intel_power_well_enable [i915]] enabling display
>[  952.861319] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.861343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.861358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.861373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.861386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.861400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.861414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.861430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.861445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.861460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.861473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.861486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.861502] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.861517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.863486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.863502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.863516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.863534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.865038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.865053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.865067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.866585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.866601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.868405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.871338] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.871415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.871434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.871465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.871502] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.871517] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.871558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.871577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.871607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.921735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.921780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.921824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.921872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.921914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.921956] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.921998] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.922040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.922082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.922124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.922165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.922173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.922214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.922222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.922265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.922306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.922348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.922389] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.922431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.922472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.922515] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.922558] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.922599] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.922643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.922749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.938221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  952.938247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  952.938284] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  952.957134] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  952.957157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  952.957173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  952.957194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.957214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.957234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.957253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.957273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.957292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.957312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.957333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.957354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.957373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.957388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.957416] [drm:intel_power_well_disable [i915]] disabling display
>[  952.957438] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  952.957457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.957477] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.957499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.957514] [drm:intel_power_well_disable [i915]] disabling always-on
>[  952.957834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  952.957853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  952.957873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  952.957893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  952.957911] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  952.957932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  952.957952] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  952.957972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  952.957992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  952.958011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  952.958031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  952.958035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.958052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  952.958056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  952.958076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  952.958096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  952.958116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  952.958135] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  952.958155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  952.958174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  952.958195] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  952.958214] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  952.958234] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  952.958254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  952.958275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  952.958320] [drm:intel_power_well_enable [i915]] enabling always-on
>[  952.958337] [drm:intel_power_well_enable [i915]] enabling display
>[  952.958352] [drm:hsw_set_power_well [i915]] Enabling power well
>[  952.958381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  952.958401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  952.958421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  952.958447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  952.958464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  952.958480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  952.958497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  952.958512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  952.958528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  952.958541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  952.958554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  952.958571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  952.958586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  952.960556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  952.960574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  952.960592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.960610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  952.962115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  952.962132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  952.962146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  952.963667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  952.963683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  952.965484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  952.968417] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  952.968493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  952.968510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  952.968533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  952.968578] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  952.968594] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  952.968633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  952.968690] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  952.968738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.018663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.018683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.018703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.018726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.018747] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.018768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.018788] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.018808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.018829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.018849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.018869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.018873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.018893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.018897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.018917] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.018937] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.018958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.018978] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.018998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.019018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.019039] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.019059] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.019079] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.019100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.019122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.035298] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.035322] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.035358] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.054220] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.054242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.054258] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.054278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.054297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.054317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.054336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.054356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.054375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.054395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.054416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.054436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.054455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.054471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.054499] [drm:intel_power_well_disable [i915]] disabling display
>[  953.054521] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.054540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.054560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.054582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.054598] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.054974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.055000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.055026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.055053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.055076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.055100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.055124] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.055148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.055171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.055193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.055215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.055222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.055243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.055248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.055270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.055291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.055313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.055334] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.055358] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.055379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.055401] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.055422] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.055442] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.055465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.055490] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.055552] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.055576] [drm:intel_power_well_enable [i915]] enabling display
>[  953.055598] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.055634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.055676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.055699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.055722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.055744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.055768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.055794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.055818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.055843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.055865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.055887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.055913] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.055936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.057927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.057943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.057956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.057971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.059475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.059493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.059511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.061008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.061025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.062828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.065767] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.065837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.065854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.065876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.065922] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.065937] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.065977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.065996] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.066026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.116006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.116027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.116047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.116068] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.116085] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.116103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.116121] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.116138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.116155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.116171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.116187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.116191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.116206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.116209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.116230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.116250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.116271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.116291] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.116312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.116332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.116353] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.116373] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.116394] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.116415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.116437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.132619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.132644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.132828] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.151419] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.151442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.151462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.151484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.151504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.151523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.151543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.151562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.151581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.151602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.151622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.151643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.151707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.151737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.151782] [drm:intel_power_well_disable [i915]] disabling display
>[  953.151816] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.151844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.151871] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.151901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.151926] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.152222] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.152238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.152255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.152273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.152286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.152302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.152317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.152332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.152346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.152359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.152372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.152375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.152388] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.152391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.152405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.152417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.152430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.152442] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.152457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.152470] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.152483] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.152496] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.152508] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.152523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.152541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.152583] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.152598] [drm:intel_power_well_enable [i915]] enabling display
>[  953.152612] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.152639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.152689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.152711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.152735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.152758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.152783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.152808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.152834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.152858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.152881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.152903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.152930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.152954] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.154947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.154964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.154978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.154992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.156496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.156511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.156524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.158020] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.158035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.159840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.162775] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.162849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.162868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.162894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.162936] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.162955] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.162999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.163020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.163052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.213015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.213036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.213056] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.213077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.213094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.213112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.213130] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.213147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.213163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.213179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.213194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.213198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.213213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.213217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.213232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.213248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.213262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.213277] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.213295] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.213314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.213335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.213356] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.213376] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.213397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.213419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.229643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.229684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.229722] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.248581] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.248602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.248618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.248638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.248654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.248715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.248742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.248768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.248794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.248823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.248850] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.248877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.248900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.248923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.248965] [drm:intel_power_well_disable [i915]] disabling display
>[  953.248999] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.249024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.249050] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.249079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.249104] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.249460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.249476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.249493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.249511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.249525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.249540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.249555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.249569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.249583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.249597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.249609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.249613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.249626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.249629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.249642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.249661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.249711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.249732] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.249757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.249779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.249802] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.249825] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.249845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.249869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.249895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.249961] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.249985] [drm:intel_power_well_enable [i915]] enabling display
>[  953.250007] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.250043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.250065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.250088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.250108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.250129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.250150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.250175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.250198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.250222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.250244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.250264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.250289] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.250312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.252298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.252314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.252328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.252343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.253846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.253861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.253875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.255368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.255384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.257192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.260112] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.260149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.260166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.260187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.260226] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.260242] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.260285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.260306] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.260341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.310314] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.310334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.310355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.310379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.310399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.310420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.310440] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.310460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.310481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.310501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.310521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.310525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.310545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.310549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.310569] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.310590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.310610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.310630] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.310650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.310705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.310732] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.310760] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.310785] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.310813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.310842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.326933] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.326957] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.326999] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.345861] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.345882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.345901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.345923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.345943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.345962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.345982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.346001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.346020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.346040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.346061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.346081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.346100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.346119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.346146] [drm:intel_power_well_disable [i915]] disabling display
>[  953.346169] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.346189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.346209] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.346232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.346247] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.346528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.346547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.346565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.346585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.346600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.346617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.346634] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.346651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.346720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.346740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.346761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.346767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.346787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.346793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.346813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.346833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.346852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.346871] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.346894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.346913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.346934] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.346953] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.346973] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.346995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.347018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.347085] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.347109] [drm:intel_power_well_enable [i915]] enabling display
>[  953.347130] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.347168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.347191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.347214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.347235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.347258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.347280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.347304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.347320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.347334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.347348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.347365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.347385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.347403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.349374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.349391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.349405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.349419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.350926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.350941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.350955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.352448] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.352464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.354272] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.357193] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.357229] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.357245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.357267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.357305] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.357321] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.357364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.357385] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.357417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.407397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.407418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.407437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.407458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.407475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.407493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.407511] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.407529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.407545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.407561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.407577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.407581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.407596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.407599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.407619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.407640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.407660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.407710] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.407736] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.407760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.407784] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.407806] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.407828] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.407853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.407879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.424012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.424036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.424072] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.442933] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.442958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.442977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.442999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.443019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.443038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.443058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.443077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.443096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.443117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.443137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.443157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.443177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.443193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.443220] [drm:intel_power_well_disable [i915]] disabling display
>[  953.443243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.443262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.443283] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.443305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.443320] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.443572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.443592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.443612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.443634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.443653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.443673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.443734] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.443760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.443784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.443806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.443828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.443835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.443856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.443862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.443884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.443906] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.443928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.443949] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.443980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.443999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.444020] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.444040] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.444059] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.444082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.444108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.444173] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.444197] [drm:intel_power_well_enable [i915]] enabling display
>[  953.444218] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.444256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.444279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.444301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.444322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.444344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.444366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.444388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.444404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.444419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.444433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.444445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.444462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.444477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.446448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.446464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.446478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.446492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.447998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.448013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.448027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.449520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.449536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.451344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.454264] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.454301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.454317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.454339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.454377] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.454393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.454437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.454457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.454489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.504451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.504472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.504492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.504516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.504536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.504557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.504578] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.504598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.504618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.504639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.504658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.504692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.504721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.504728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.504753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.504777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.504800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.504822] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.504847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.504869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.504895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.504918] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.504941] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.504966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.504994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.521084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.521109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.521145] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.540006] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.540029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.540049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.540071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.540090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.540110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.540130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.540149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.540168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.540189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.540209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.540229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.540248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.540264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.540292] [drm:intel_power_well_disable [i915]] disabling display
>[  953.540314] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.540335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.540355] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.540377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.540392] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.540747] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.540773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.540801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.540831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.540855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.540883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.540910] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.540935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.540960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.540984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.541008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.541014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.541037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.541042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.541062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.541082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.541102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.541121] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.541141] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.541159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.541179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.541196] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.541215] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.541235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.541257] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.541305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.541321] [drm:intel_power_well_enable [i915]] enabling display
>[  953.541343] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.541371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.541387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.541402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.541417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.541431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.541446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.541462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.541477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.541493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.541506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.541520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.541536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.541551] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.543521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.543539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.543556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.543574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.545080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.545098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.545115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.546632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.546649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.548455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.551388] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.551465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.551489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.551509] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.551546] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.551564] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.551607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.551629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.551662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.601633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.601653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.601674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.601730] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.601829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.601846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.601865] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.601881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.601897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.601916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.601936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.601940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.601960] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.601964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.601984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.602004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.602023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.602043] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.602062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.602082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.602102] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.602122] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.602142] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.602162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.602183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.618247] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.618271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.618307] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.637169] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.637191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.637208] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.637227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.637244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.637259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.637274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.637289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.637305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.637322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.637339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.637355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.637369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.637383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.637410] [drm:intel_power_well_disable [i915]] disabling display
>[  953.637431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.637447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.637464] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.637481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.637495] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.637851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.637873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.637898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.637924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.637945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.637968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.637990] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.638012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.638033] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.638054] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.638073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.638078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.638099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.638104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.638125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.638144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.638164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.638183] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.638206] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.638224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.638246] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.638264] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.638284] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.638306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.638329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.638393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.638415] [drm:intel_power_well_enable [i915]] enabling display
>[  953.638437] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.638472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.638493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.638514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.638534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.638555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.638575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.638598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.638621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.638644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.638663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.638684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.638855] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  953.638877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.640864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.640880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.640895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.640909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.642411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.642426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.642439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.643934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.643950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.645751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.648666] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  953.648761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.648786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  953.648806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.648842] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  953.648857] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  953.648899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.648921] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.648953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.698913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.698933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.698954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.698975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.698992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.699010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.699028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  953.699045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  953.699062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.699078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.699093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.699097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.699112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.699116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.699131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.699147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.699161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.699176] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  953.699196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.699216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.699237] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.699258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  953.699278] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  953.699299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.699321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  953.715543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  953.715567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.715602] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  953.734469] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  953.734491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  953.734507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.734526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.734546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.734566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.734585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.734604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.734623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.734644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.734665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.734686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.734746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.734771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.734814] [drm:intel_power_well_disable [i915]] disabling display
>[  953.734844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.734862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.734881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.734900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.734915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.735017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.735048] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.735065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.735080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.735095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.735108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.735121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.735135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.735150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.735165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.735179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.735194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.735207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.735220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.735243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  953.735261] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.735401] [drm:drm_mode_addfb2] [FB:77]
>[  953.735425] [drm:drm_mode_addfb2] [FB:78]
>[  953.758416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  953.758502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  953.758559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  953.758614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  953.758623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  953.758674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.758726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.758754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.758783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.758807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.758832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.758856] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.758880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.758904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.758925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.758946] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.758952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.758971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.758977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.758998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.759020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.759041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.759062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.759086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.759107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.759127] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  953.759148] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.759169] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.759193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.759218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.761840] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.761855] [drm:intel_power_well_enable [i915]] enabling display
>[  953.761869] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.761898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.761914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.761929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.761943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.761957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.761971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.761987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.762002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.762016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.762029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.762042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.762058] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  953.762073] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.764049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.764065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.764079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.764094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.765596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.765612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.765626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.767116] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.767132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.768931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.771874] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  953.771941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.771958] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  953.771981] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.788685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.788728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.788763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.805482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.805501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.805520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.805540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.805555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.805572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.805589] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.805605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.805621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.805636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.805654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.805658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.805677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.805718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.805745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.805768] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.805793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.805816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.805842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.805865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.805890] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.805912] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.805936] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.805963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.805989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.806058] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  953.806088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.806144] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  953.824473] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  953.824492] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.824513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.824530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.824546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.824561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.824576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.824592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.824612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.824633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.824653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.824672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.824689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.824769] [drm:intel_power_well_disable [i915]] disabling display
>[  953.824804] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.824833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.824853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.824872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.824887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.824974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.824991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.825009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.825028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.825044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.825068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.825083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.825098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.825112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.825126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.825138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.825143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.825155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.825159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.825172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.825185] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.825198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.825210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.825227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.825246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.825264] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.825282] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.825300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.825319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.825338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.825383] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.825397] [drm:intel_power_well_enable [i915]] enabling display
>[  953.825411] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.825440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.825458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.825476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.825494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.825512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.825530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.825549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.825568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.825587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.825604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.825622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.825641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  953.825659] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.827649] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.827666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.827681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.827729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.829240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.829255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.829269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.830769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.830785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.832588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.835523] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  953.835598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.835615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  953.835640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.835745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.835780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.835832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.885767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.885789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.885810] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.885834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.885854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.885875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.885895] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.885915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.885936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.885956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.885976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.885980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.886000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.886004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.886024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.886044] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.886064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.886084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.886105] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.886124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.886145] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.886166] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.886186] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.886207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.886228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.886285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  953.886309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.886347] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  953.903181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  953.903200] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.903220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.903239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.903259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.903278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.903297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.903317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.903337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.903358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.903378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.903397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.903414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.903441] [drm:intel_power_well_disable [i915]] disabling display
>[  953.903463] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.903483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.903504] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.903525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.903540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.904044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.904069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.904095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.904123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.904146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.904170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.904194] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.904216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.904239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.904261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.904283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.904288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.904309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.904314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.904336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.904357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.904376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.904397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.904421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.904442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.904464] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.904485] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.904504] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.904527] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.904552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.904617] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.904639] [drm:intel_power_well_enable [i915]] enabling display
>[  953.904661] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.904698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.904748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.904771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.904794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.904817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.904841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.904867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.904892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.904916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.904938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.904960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.904986] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  953.905009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.907230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.907247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.907261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.907276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.908849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.908865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.908878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.910371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.910387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.912206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.915139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  953.915214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.915231] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  953.915253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.915310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.915332] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.915364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.965385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.965407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.965428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.965452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.965472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.965493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.965513] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.965533] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.965554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.965574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.965594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.965599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.965619] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.965622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.965643] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.965663] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.965683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.965703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.965758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.965784] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.965810] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.965833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.965855] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.965881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.965907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.965988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  953.966009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  953.966053] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  953.982875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  953.982894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  953.982914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.982931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.982947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.982962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.982976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.982994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.983016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.983036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.983057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.983076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.983092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.983119] [drm:intel_power_well_disable [i915]] disabling display
>[  953.983142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  953.983162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.983182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.983203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.983218] [drm:intel_power_well_disable [i915]] disabling always-on
>[  953.983435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  953.983455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  953.983475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  953.983497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  953.983516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  953.983535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  953.983555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  953.983573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  953.983593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  953.983611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  953.983630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  953.983634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.983653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  953.983657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  953.983676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  953.983695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  953.983764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  953.983786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  953.983810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  953.983831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  953.983853] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  953.983873] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  953.983893] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  953.983917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  953.983940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  953.984164] [drm:intel_power_well_enable [i915]] enabling always-on
>[  953.984178] [drm:intel_power_well_enable [i915]] enabling display
>[  953.984191] [drm:hsw_set_power_well [i915]] Enabling power well
>[  953.984218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  953.984234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  953.984249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  953.984263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  953.984276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  953.984291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  953.984307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  953.984322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  953.984337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  953.984350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  953.984363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  953.984379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  953.984394] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  953.986373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  953.986389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  953.986403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.986417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  953.987925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  953.987940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  953.987953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  953.989446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  953.989462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  953.991270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  953.994204] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  953.994280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  953.994297] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  953.994319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  953.994398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  953.994432] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  953.994482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.044444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.044466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.044488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.044511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.044532] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.044552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.044573] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.044593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.044614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.044634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.044654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.044658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.044678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.044682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.044702] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.044755] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.044781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.044805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.044830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.044853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.044876] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.044898] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.044920] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.044945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.044971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.045051] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.045076] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.045119] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.061942] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.061963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.061985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.062004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.062024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.062043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.062062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.062081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.062102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.062123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.062143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.062162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.062181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.062208] [drm:intel_power_well_disable [i915]] disabling display
>[  954.062230] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.062251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.062271] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.062292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.062307] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.062616] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.062633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.062650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.062670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.062687] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.062710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.062758] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.062776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.062791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.062805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.062820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.062824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.062838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.062842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.062857] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.062870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.062884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.062897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.062913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.062927] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.062942] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.062955] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.062969] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.062985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.063003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.063047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.063068] [drm:intel_power_well_enable [i915]] enabling display
>[  954.063090] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.063128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.063152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.063174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.063196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.063218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.063241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.063266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.063289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.063313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.063334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.063353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.063370] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.063385] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.065357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.065373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.065388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.065403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.066907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.066922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.066936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.068429] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.068445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.070251] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.073184] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.073261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.073278] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.073300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.073378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.073412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.073461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.123423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.123445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.123467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.123490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.123511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.123531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.123552] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.123572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.123593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.123614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.123633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.123637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.123657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.123661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.123682] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.123702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.123756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.123781] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.123806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.123829] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.123854] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.123876] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.123898] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.123924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.123950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.124030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.124061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.124229] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.140442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.140461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.140481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.140497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.140513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.140528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.140543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.140562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.140583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.140603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.140624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.140642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.140659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.140686] [drm:intel_power_well_disable [i915]] disabling display
>[  954.140708] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.140776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.140803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.140832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.140953] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.141231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.141249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.141267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.141287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.141303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.141320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.141336] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.141352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.141367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.141382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.141396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.141400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.141414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.141417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.141432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.141446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.141469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.141481] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.141496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.141509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.141527] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.141544] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.141562] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.141580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.141599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.141641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.141655] [drm:intel_power_well_enable [i915]] enabling display
>[  954.141669] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.141696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.141721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.141771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.141793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.141815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.141836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.141860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.141884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.141906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.141926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.141946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.141970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.141991] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.144179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.144197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.144215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.144233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.145767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.145784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.145798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.147296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.147312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.149123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.151526] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.151576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.151593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.151615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.151675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.151695] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.151774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.201785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.201806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.201826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.201847] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.201863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.201882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.201902] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.201922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.201943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.201963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.201983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.201987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.202007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.202010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.202031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.202051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.202071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.202091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.202112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.202131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.202152] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.202172] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.202193] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.202214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.202235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.202287] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.202311] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.202349] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.220483] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.220502] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.220522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.220539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.220555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.220570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.220584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.220600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.220617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.220633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.220648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.220663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.220677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.220703] [drm:intel_power_well_disable [i915]] disabling display
>[  954.220775] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.220804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.220832] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.220859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.220884] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.221239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.221256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.221274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.221293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.221309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.221326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.221349] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.221363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.221377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.221390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.221403] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.221407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.221419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.221423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.221436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.221448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.221461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.221474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.221488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.221505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.221524] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.221541] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.221559] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.221577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.221596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.221628] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.221642] [drm:intel_power_well_enable [i915]] enabling display
>[  954.221656] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.221683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.221701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.221718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.221770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.221797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.221822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.221849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.221874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.221899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.221921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.221943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.221969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.221993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.223991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.224007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.224022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.224040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.225554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.225573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.225590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.227086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.227103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.228907] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.231850] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.231917] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.231934] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.231956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.232015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.232036] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.232069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.282063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.282084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.282104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.282125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.282142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.282160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.282178] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.282196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.282213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.282229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.282244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.282248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.282264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.282267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.282283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.282298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.282313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.282328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.282345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.282360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.282376] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.282391] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.282406] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.282423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.282442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.282497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.282518] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.282551] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.300486] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.300505] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.300526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.300543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.300558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.300574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.300588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.300604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.300621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.300637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.300652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.300666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.300680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.300707] [drm:intel_power_well_disable [i915]] disabling display
>[  954.300786] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.300813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.300839] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.300865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.300881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.301118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.301135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.301154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.301174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.301190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.301210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.301237] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.301254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.301273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.301291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.301308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.301313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.301330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.301333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.301351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.301369] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.301388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.301405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.301423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.301441] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.301457] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.301475] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.301492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.301511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.301530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.301572] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.301586] [drm:intel_power_well_enable [i915]] enabling display
>[  954.301600] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.301628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.301646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.301664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.301682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.301700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.301719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.301765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.301790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.301814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.301834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.301854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.301879] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.301901] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.303889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.303905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.303919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.303933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.305434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.305450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.305463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.306959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.306975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.308779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.311703] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.311766] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.311785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.311809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.311888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.311923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.311973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.361905] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.361926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.361946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.361967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.361984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.362002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.362022] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.362043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.362063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.362083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.362103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.362108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.362128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.362131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.362152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.362172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.362192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.362212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.362233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.362253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.362274] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.362294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.362314] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.362335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.362356] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.362413] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.362438] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.362483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.379302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.379321] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.379341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.379358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.379374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.379389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.379403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.379419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.379437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.379453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.379469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.379487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.379505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.379533] [drm:intel_power_well_disable [i915]] disabling display
>[  954.379555] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.379575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.379596] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.379616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.379631] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.380351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.380368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.380386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.380403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.380418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.380434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.380449] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.380464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.380479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.380492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.380505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.380509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.380522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.380525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.380538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.380551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.380564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.380576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.380591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.380604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.380617] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.380630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.380642] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.380657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.380674] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.380714] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.380763] [drm:intel_power_well_enable [i915]] enabling display
>[  954.380785] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.380825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.380849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.380872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.380896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.380918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.380942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.380967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.380991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.381016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.381037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.381060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.381085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.381108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.383099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.383115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.383129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.383143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.384675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.384690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.384703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.386233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.386249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.388145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.391077] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.391154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.391170] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.391192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.391270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.391311] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.391356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.441306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.441326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.441346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.441368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.441387] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.441408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.441429] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.441450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.441470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.441491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.441511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.441515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.441535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.441539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.441559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.441580] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.441600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.441620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.441640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.441660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.441681] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.441702] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.441722] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.441774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.441807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.441888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.441920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.442107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.458431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.458449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.458469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.458486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.458502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.458521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.458540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.458559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.458580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.458601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.458621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.458640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.458656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.458683] [drm:intel_power_well_disable [i915]] disabling display
>[  954.458706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.458726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.458789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.458820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.458846] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.459315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.459331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.459348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.459366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.459381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.459397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.459412] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.459429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.459447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.459465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.459482] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.459485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.459502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.459506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.459524] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.459541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.459558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.459576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.459593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.459610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.459628] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.459645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.459663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.459681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.459700] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.459772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.459796] [drm:intel_power_well_enable [i915]] enabling display
>[  954.459819] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.459858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.459883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.459905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.459929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.459949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.459973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.459998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.460023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.460047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.460283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.460303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.460328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.460350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.462347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.462364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.462379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.462394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.463918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.463935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.463950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.465445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.465462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.467273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.470214] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.470282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.470298] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.470323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.470383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.470406] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.470441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.520452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.520472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.520493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.520517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.520537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.520558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.520579] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.520599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.520619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.520640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.520659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.520664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.520683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.520687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.520708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.520728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.520783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.520808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.520834] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.520857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.520882] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.520904] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.520926] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.520952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.520978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.521060] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.521091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.521252] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.537465] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.537483] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.537504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.537520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.537535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.537550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.537564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.537580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.537597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.537613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.537629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.537643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.537656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.537683] [drm:intel_power_well_disable [i915]] disabling display
>[  954.537704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.537719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.537779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.537806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.537832] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.538171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.538196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.538223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.538252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.538276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.538302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.538327] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.538351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.538375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.538398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.538420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.538426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.538448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.538454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.538476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.538498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.538519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.538540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.538565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.538588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.538609] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.538631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.538651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.538675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.538701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.538792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.538817] [drm:intel_power_well_enable [i915]] enabling display
>[  954.538841] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.538888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.538913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.538936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.538959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.538981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.539004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.539030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.539054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.539077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.539100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.539121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.539146] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.539169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.541158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.541174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.541188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.541203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.542712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.542727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.542776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.544274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.544290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.546159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.549093] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.549167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.549183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.549203] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.549256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.549276] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.549306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.599332] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.599353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.599373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.599394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.599411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.599429] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.599447] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.599467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.599488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.599508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.599529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.599533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.599553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.599556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.599577] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.599597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.599617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.599637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.599658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.599677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.599699] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.599719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.599739] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.599797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.599826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.599911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.599943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.599994] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.616847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.616866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.616886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.616903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.616919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.616934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.616949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.616966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.616983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.616999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.617015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.617029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.617044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.617070] [drm:intel_power_well_disable [i915]] disabling display
>[  954.617092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.617112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.617133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.617154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.617169] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.617418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.617438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.617458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.617480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.617499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.617519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.617538] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.617557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.617577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.617596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.617614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.617618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.617637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.617641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.617660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.617679] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.617698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.617724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.617741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.617800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.617824] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.617848] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.617872] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.617897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.617924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.617990] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.618012] [drm:intel_power_well_enable [i915]] enabling display
>[  954.618034] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.618072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.618095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.618117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.618137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.618159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.618181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.618206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.618230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.618253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.618275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.618296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.618321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.618344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.620348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.620364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.620378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.620393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.621899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.621914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.621927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.623419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.623436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.625245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.628182] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.628254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.628271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.628292] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.628349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.628371] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.628403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.678427] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.678449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.678471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.678494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.678514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.678535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.678555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.678576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.678596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.678617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.678636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.678641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.678660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.678664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.678685] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.678705] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.678726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.678745] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.678802] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.678831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.678857] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.678883] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.678909] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.678938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.678967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.679048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.679079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.679130] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.695953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.695972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.695992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.696010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.696026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.696041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.696060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.696079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.696100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.696121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.696141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.696160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.696177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.696204] [drm:intel_power_well_disable [i915]] disabling display
>[  954.696227] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.696247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.696267] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.696288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.696303] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.696519] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.696539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.696559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.696588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.696604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.696621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.696639] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.696656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.696673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.696691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.696708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.696711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.696728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.696732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.696794] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.696819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.696843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.696867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.696892] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.696915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.696940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.696962] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.696985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.697011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.697037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.697102] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.697125] [drm:intel_power_well_enable [i915]] enabling display
>[  954.697147] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.697184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.697207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.697230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.697252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.697274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.697296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.697321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.697345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.697368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.697389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.697410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.697435] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.697458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.699453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.699469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.699483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.699498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.701005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.701020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.701034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.702529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.702545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.704354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.707290] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.707363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.707379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.707402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.707461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.707485] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.707521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.757530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.757551] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.757571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.757592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.757609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.757627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.757645] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.757662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.757679] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.757695] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.757714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.757719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.757739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.757772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.757798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.757823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.757850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.757876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.757903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.757928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.757954] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.757979] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.758003] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.758031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.758059] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.758140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.758171] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.758220] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.775045] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.775064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.775084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.775101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.775117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.775136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.775155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.775175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.775195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.775216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.775236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.775255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.775274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.775301] [drm:intel_power_well_disable [i915]] disabling display
>[  954.775323] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.775344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.775364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.775385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.775400] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.775649] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.775669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.775689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.775711] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.775730] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.775750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.775814] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.775839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.775866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.775892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.775916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.775923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.775947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.775954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.775978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.776002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.776027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.776050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.776077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.776100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.776126] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.776149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.776173] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.776200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.776228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.776300] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.776324] [drm:intel_power_well_enable [i915]] enabling display
>[  954.776348] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.776388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.776414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.776442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.776464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.776483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.776506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.776530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.776554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.776577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.776598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.776617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.776642] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.776665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.778660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.778676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.778690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.778704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.780210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.780225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.780238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.781733] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.781749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.783585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.786521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.786595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.786612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.786635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.786699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.786719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.786749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.836751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.836785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.836807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.836830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.836850] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.836871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.836892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.836912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.836933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.836953] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.836973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.836977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.836997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.837001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.837022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.837042] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.837062] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.837083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.837103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.837123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.837144] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.837164] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.837184] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.837206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.837227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.837284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.837308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.837345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.854162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.854181] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.854201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.854218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.854234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.854249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.854264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.854280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.854297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.854313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.854329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.854343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.854357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.854384] [drm:intel_power_well_disable [i915]] disabling display
>[  954.854405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.854421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.854437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.854454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.854468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.854684] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.854704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.854724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.854746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.854808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.854836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.854863] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.854887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.854912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.854934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.854958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.854965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.854988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.854994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.855019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.855041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.855065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.855087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.855113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.855135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.855160] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.855182] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.855204] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.855230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.855258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.855335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.855357] [drm:intel_power_well_enable [i915]] enabling display
>[  954.855378] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.855416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.855438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.855458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.855480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.855499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.855521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.855545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.855567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.855590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.855609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.855630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.855652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.855674] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.857667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.857683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.857697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.857712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.859218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.859236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.859253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.860749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.860779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.862583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.865517] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.865590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.865606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.865626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.865679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.865699] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.865729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.915760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.915792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.915812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.915832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.915849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.915867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.915885] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.915902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.915919] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.915936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.915956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.915960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.915980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.915984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.916005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.916025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.916046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.916066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.916086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.916106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.916127] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.916148] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.916168] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.916189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.916211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.916268] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.916293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.916330] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  954.933148] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  954.933167] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  954.933188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.933208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.933227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.933247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.933266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.933285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.933306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.933326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.933347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.933366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.933382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.933409] [drm:intel_power_well_disable [i915]] disabling display
>[  954.933432] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  954.933452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.933472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.933493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.933508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  954.933752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.933816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.933844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.933873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.933896] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.933921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.933946] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.933969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.933993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.934015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.934037] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.934043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.934066] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.934072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.934095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.934117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.934139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.934161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.934189] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.934203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.934216] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.934229] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.934242] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.934257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.934273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.934315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  954.934329] [drm:intel_power_well_enable [i915]] enabling display
>[  954.934341] [drm:hsw_set_power_well [i915]] Enabling power well
>[  954.934367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  954.934381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  954.934395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  954.934409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  954.934422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  954.934436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  954.934451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  954.934465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  954.934480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.934493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  954.934505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  954.934521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  954.934536] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  954.936516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  954.936532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  954.936546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.936561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  954.938067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  954.938084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  954.938102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  954.939596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  954.939614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  954.941423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  954.944344] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  954.944387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  954.944403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  954.944423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  954.944476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  954.944495] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  954.944525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  954.994529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  954.994551] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  954.994572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  954.994595] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  954.994616] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  954.994636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  954.994657] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  954.994677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  954.994697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  954.994718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  954.994738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  954.994742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.994762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  954.994794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  954.994823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  954.994848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  954.994871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  954.994895] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  954.994919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  954.994942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  954.994966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  954.994988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  954.995009] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  954.995036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  954.995063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  954.995144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  954.995176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  954.995325] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.013557] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.013576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.013596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.013613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.013628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.013643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.013658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.013674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.013691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.013707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.013723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.013737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.013751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.013827] [drm:intel_power_well_disable [i915]] disabling display
>[  955.013861] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.013888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.013916] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.013943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.013967] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.014307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.014323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.014340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.014358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.014372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.014387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.014402] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.014417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.014431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.014444] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.014457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.014460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.014473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.014476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.014488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.014501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.014513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.014526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.014540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.014553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.014566] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.014578] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.014590] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.014605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.014621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.014661] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.014675] [drm:intel_power_well_enable [i915]] enabling display
>[  955.014689] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.014717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.014735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.014753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.014803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.014829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.014854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.014881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.014906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.014931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.014953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.014976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.015003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.015026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.017018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.017034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.017048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.017062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.018570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.018585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.018599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.020095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.020110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.021915] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.024855] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.024924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.024942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.024963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.025021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.025042] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.025074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.075092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.075113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.075133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.075154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.075174] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.075195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.075215] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.075236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.075256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.075277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.075297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.075301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.075321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.075324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.075345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.075365] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.075385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.075406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.075426] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.075446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.075467] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.075488] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.075508] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.075529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.075551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.075608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.075633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.075671] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.092499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.092518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.092538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.092555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.092571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.092586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.092601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.092617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.092634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.092650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.092666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.092681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.092695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.092721] [drm:intel_power_well_disable [i915]] disabling display
>[  955.092742] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.092758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.092821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.092852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.092877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.093220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.093244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.093271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.093298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.093322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.093346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.093371] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.093394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.093418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.093440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.093461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.093467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.093489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.093494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.093516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.093538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.093557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.093579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.093603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.093625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.093646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.093667] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.093689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.093711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.093736] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.093820] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.093844] [drm:intel_power_well_enable [i915]] enabling display
>[  955.093868] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.093915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.093939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.093962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.093985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.094007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.094030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.094055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.094079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.094103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.094124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.094145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.094170] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.094193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.096182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.096198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.096212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.096227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.097733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.097749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.097763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.099301] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.099317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.101141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.104093] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.104148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.104164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.104185] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.104240] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.104260] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.104291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.154335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.154363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.154390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.154419] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.154443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.154468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.154494] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.154517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.154541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.154564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.154585] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.154591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.154613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.154618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.154640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.154662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.154684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.154705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.154729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.154751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.154774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.154825] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.154849] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.154874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.154901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.154981] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.155011] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.155057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.171884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.171902] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.171923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.171940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.171956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.171971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.171986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.172002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.172020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.172036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.172052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.172066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.172080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.172107] [drm:intel_power_well_disable [i915]] disabling display
>[  955.172128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.172144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.172161] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.172181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.172196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.172501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.172518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.172537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.172556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.172571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.172588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.172605] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.172620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.172636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.172650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.172664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.172668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.172682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.172685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.172700] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.172713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.172735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.172747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.172763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.172819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.172840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.172863] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.172882] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.172907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.172933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.172999] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.173020] [drm:intel_power_well_enable [i915]] enabling display
>[  955.173042] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.173079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.173100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.173122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.173142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.173163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.173186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.173210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.173233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.173256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.173275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.173295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.173318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.173340] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.175347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.175364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.175378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.175393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.176892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.176908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.176922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.178412] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.178428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.180232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.183170] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.183241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.183257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.183283] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.183363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.183397] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.183446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.233412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.233433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.233453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.233476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.233496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.233517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.233537] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.233558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.233578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.233598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.233618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.233622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.233642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.233646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.233666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.233687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.233707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.233727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.233747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.233767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.233818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.233849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.233872] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.233901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.233930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.234011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.234041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.234268] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.250467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.250486] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.250506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.250523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.250539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.250554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.250569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.250585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.250602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.250618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.250634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.250649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.250663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.250690] [drm:intel_power_well_disable [i915]] disabling display
>[  955.250711] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.250727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.250744] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.250760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.250774] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.251143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.251167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.251194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.251223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.251246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.251272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.251295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.251320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.251342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.251366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.251387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.251393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.251414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.251420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.251443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.251464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.251486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.251507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.251531] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.251552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.251575] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.251596] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.251625] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.251646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.251670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.251733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.251754] [drm:intel_power_well_enable [i915]] enabling display
>[  955.251776] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.251835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.251859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.251880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.251902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.251922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.251945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.251971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.251995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.252020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.252040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.252061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.252087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.252108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.254098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.254115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.254129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.254144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.255647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.255662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.255676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.257169] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.257186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.258991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.261901] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.261949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.261965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.261986] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.262042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.262062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.262093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.312114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.312136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.312158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.312181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.312201] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.312222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.312243] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.312263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.312284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.312304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.312324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.312328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.312348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.312352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.312372] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.312393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.312413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.312433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.312453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.312473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.312495] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.312515] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.312535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.312557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.312578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.312636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.312660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.312697] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.329476] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.329495] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.329515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.329532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.329547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.329562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.329576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.329592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.329609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.329626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.329641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.329656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.329670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.329695] [drm:intel_power_well_disable [i915]] disabling display
>[  955.329717] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.329732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.329749] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.329765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.329779] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.330185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.330202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.330221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.330240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.330256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.330272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.330289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.330304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.330327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.330351] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.330379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.330382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.330395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.330399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.330412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.330425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.330437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.330449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.330464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.330477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.330490] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.330503] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.330515] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.330529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.330545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.330587] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.330600] [drm:intel_power_well_enable [i915]] enabling display
>[  955.330612] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.330637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.330651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.330664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.330677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.330690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.330707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.330726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.330745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.330763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.330781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.330824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.330851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.330873] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.332864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.332880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.332894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.332909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.334411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.334425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.334439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.335932] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.335947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.337752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.339686] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.339749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.339766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.339818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.339903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.339935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.339981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.389912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.389932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.389952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.389972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.389989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.390006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.390025] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.390042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.390058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.390074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.390089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.390093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.390108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.390112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.390127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.390147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.390168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.390188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.390208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.390228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.390249] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.390269] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.390290] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.390311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.390332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.390389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.390413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.390450] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.408569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.408588] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.408608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.408625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.408641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.408656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.408670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.408686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.408704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.408720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.408736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.408750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.408764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.408830] [drm:intel_power_well_disable [i915]] disabling display
>[  955.408865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.408892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.408921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.408948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.408972] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.409314] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.409337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.409362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.409388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.409408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.409432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.409454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.409476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.409496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.409517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.409536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.409542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.409562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.409567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.409588] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.409607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.409627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.409645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.409668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.409687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.409708] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.409726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.409747] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.409770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.409795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.409881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.409904] [drm:intel_power_well_enable [i915]] enabling display
>[  955.409927] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.409965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.409988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.410011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.410033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.410055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.410078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.410103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.410127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.410151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.410172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.410192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.410215] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.410237] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.412228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.412246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.412263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.412281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.413793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.413822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.413836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.415334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.415350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.417162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.420088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.420119] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.420138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.420164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.420226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.420251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.420286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.470287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.470307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.470327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.470348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.470365] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.470383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.470401] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.470418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.470435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.470450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.470466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.470470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.470485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.470488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.470504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.470519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.470534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.470548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.470568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.470589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.470610] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.470630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.470650] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.470671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.470692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.470749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.470774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.470978] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.487454] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.487473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.487493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.487510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.487526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.487541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.487556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.487572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.487589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.487605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.487620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.487635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.487649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.487675] [drm:intel_power_well_disable [i915]] disabling display
>[  955.487697] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.487712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.487729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.487744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.487759] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.488167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.488189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.488215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.488242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.488263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.488286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.488308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.488330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.488350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.488371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.488390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.488396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.488416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.488421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.488442] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.488461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.488482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.488500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.488523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.488542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.488563] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.488582] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.488602] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.488626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.488648] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.488712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.488733] [drm:intel_power_well_enable [i915]] enabling display
>[  955.488755] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.488791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.488833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.488856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.488876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.488898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.488919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.488944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.488968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.488992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.489012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.489034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.489059] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.489081] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.491070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.491088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.491105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.491123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.492631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.492647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.492661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.494158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.494177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.495983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.498891] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.498941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.498957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.498979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.499037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.499059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.499091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.549089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.549109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.549130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.549150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.549167] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.549185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.549203] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.549221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.549237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.549253] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.549269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.549273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.549288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.549291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.549311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.549332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.549352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.549372] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.549393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.549413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.549433] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.549454] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.549474] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.549496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.549517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.549574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.549599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.549636] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.566452] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.566471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.566491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.566508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.566524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.566539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.566553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.566569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.566586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.566602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.566618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.566632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.566646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.566673] [drm:intel_power_well_disable [i915]] disabling display
>[  955.566696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.566716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.566737] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.566757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.566772] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.567153] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.567180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.567207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.567234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.567256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.567280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.567303] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.567325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.567347] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.567368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.567388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.567393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.567413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.567419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.567440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.567460] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.567481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.567500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.567523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.567543] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.567565] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.567584] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.567605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.567626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.567651] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.567717] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.567740] [drm:intel_power_well_enable [i915]] enabling display
>[  955.567762] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.567800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.567843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.567866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.567895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.567916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.567938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.567963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.567988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.568013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.568033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.568054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.568080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.568102] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.570093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.570110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.570128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.570146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.571653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.571672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.571689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.573187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.573204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.575012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.577955] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.578021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.578038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.578060] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.578118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.578147] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.578178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.628189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.628209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.628229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.628250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.628266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.628284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.628303] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.628320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.628336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.628352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.628367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.628371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.628387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.628390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.628406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.628421] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.628440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.628461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.628481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.628501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.628523] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.628543] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.628564] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.628585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.628607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.628664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.628689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.628726] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.645600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.645619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.645640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.645660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.645679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.645699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.645718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.645737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.645758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.645779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.645799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.645860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.645885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.645929] [drm:intel_power_well_disable [i915]] disabling display
>[  955.645964] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.645992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.646020] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.646047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.646072] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.646306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.646322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.646341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.646360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.646376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.646393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.646410] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.646427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.646442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.646458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.646472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.646477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.646490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.646494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.646509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.646523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.646538] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.646551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.646569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.646582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.646598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.646612] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.646626] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.646642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.646661] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.646709] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.646722] [drm:intel_power_well_enable [i915]] enabling display
>[  955.646735] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.646760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.646775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.646788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.646824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.646846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.646866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.646889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.646912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.646934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.646953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.646972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.646995] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.647017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.649006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.649024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.649042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.649060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.650565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.650582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.650596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.652091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.652107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.653913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.656860] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.656921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.656939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.656962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.657019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.657041] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.657074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.707135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.707167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.707198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.707231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.707257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.707284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.707312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.707338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.707364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.707388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.707412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.707418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.707441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.707446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.707470] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.707493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.707517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.707540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.707567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.707591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.707615] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.707638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.707661] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.707687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.707716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.707799] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.707885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.708125] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.724528] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.724548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.724568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.724585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.724600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.724615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.724630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.724646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.724663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.724679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.724695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.724709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.724723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.724750] [drm:intel_power_well_disable [i915]] disabling display
>[  955.724771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.724786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.724803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.724864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.724887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.725256] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.725275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.725293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.725315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.725334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.725354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.725373] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.725392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.725412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.725431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.725449] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.725453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.725472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.725475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.725495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.725520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.725536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.725551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.725567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.725584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.725602] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.725619] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.725636] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.725655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.725673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.725716] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.725730] [drm:intel_power_well_enable [i915]] enabling display
>[  955.725743] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.725771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.725789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.725812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.725860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.725883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.725905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.725930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.725952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.725974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.725994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.726014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.726038] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.726060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.728046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.728062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.728077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.728092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.729591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.729607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.729620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.731115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.731131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.732931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.735866] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.735940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.735956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.735979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.736037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.736058] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.736090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.786110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.786130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.786150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.786171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.786187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.786205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.786223] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.786240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.786256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.786272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.786287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.786291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.786307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.786310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.786326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.786341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.786360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.786381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.786401] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.786421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.786442] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.786463] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.786483] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.786504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.786525] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.786583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.786608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.786645] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.804785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.804803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.804870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.804897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.804922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.804946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.804964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.804981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.804999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.805020] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.805041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.805060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.805079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.805108] [drm:intel_power_well_disable [i915]] disabling display
>[  955.805131] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.805151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.805173] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.805194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.805210] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.805436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.805455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.805475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.805498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.805516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.805536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.805556] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.805575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.805594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.805613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.805632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.805636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.805655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.805659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.805678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.805697] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.805716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.805735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.805754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.805773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.805793] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.805812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.805858] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.805885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.805912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.805980] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.806002] [drm:intel_power_well_enable [i915]] enabling display
>[  955.806024] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.806066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.806092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.806116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.806140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.806163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.806188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.806215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.806241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.806267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.806290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.806313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.806341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.806372] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.808362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.808379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.808392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.808407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.809918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.809934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.809948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.811441] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.811457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.813267] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.816213] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.816276] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.816294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.816316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.816373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.816395] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.816427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.866441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.866461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.866481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.866502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.866520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.866542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.866562] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.866583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.866603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.866623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.866643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.866648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.866667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.866671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.866692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.866712] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.866732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.866752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.866773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.866793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.866814] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.866866] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.866892] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.866918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.866945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.867028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.867060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.867230] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.883515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.883534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.883554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.883570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.883586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.883601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.883615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.883634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.883655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.883675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.883696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.883715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.883731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.883758] [drm:intel_power_well_disable [i915]] disabling display
>[  955.883780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.883801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.883864] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.883898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.883924] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.884301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.884318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.884335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.884353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.884370] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.884388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.884405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.884423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.884441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.884458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.884475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.884479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.884496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.884499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.884516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.884534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.884551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.884568] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.884586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.884603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.884621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.884638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.884655] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.884673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.884692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.884734] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.884748] [drm:intel_power_well_enable [i915]] enabling display
>[  955.884761] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.884789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.884807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.884857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.884880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.884905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.884931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.884958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.884983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.885008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.885030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.885052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.885078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.885102] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.887093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.887109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.887123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.887138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.888641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.888656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.888669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.890160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.890176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.891980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.894885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.894938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.894955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.894977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.895034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.895056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.895091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.945110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.945130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.945150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.945171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.945188] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.945208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.945229] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.945249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.945270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.945290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.945310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.945314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.945334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.945337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.945358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.945378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.945399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.945418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.945439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.945458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.945480] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.945500] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.945520] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.945541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.945562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.945620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  955.945644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  955.945682] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  955.962496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  955.962515] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  955.962536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.962552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.962568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.962583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.962598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.962614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.962631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.962647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.962662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.962681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.962698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.962726] [drm:intel_power_well_disable [i915]] disabling display
>[  955.962748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  955.962769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.962789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.962810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.962870] [drm:intel_power_well_disable [i915]] disabling always-on
>[  955.963213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  955.963238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  955.963264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  955.963291] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  955.963314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  955.963338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  955.963363] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  955.963386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  955.963410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  955.963432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  955.963453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  955.963459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.963479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  955.963485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  955.963506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  955.963528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  955.963547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  955.963568] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  955.963592] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  955.963613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  955.963636] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  955.963657] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  955.963676] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  955.963699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  955.963725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  955.963790] [drm:intel_power_well_enable [i915]] enabling always-on
>[  955.963812] [drm:intel_power_well_enable [i915]] enabling display
>[  955.963853] [drm:hsw_set_power_well [i915]] Enabling power well
>[  955.963893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  955.963917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  955.963941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  955.963964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  955.963987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  955.964011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  955.964036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  955.964061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  955.964085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  955.964107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  955.964129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  955.964155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  955.964179] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  955.966167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  955.966183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  955.966197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.966211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  955.967714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  955.967732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  955.967749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  955.969247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  955.969263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  955.971066] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  955.973973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  955.974024] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  955.974040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  955.974062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  955.974119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  955.974143] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  955.974179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.024190] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.024211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.024231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.024252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.024272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.024293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.024314] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.024334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.024355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.024375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.024394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.024399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.024418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.024422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.024443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.024463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.024483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.024503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.024524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.024544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.024565] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.024585] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.024605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.024627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.024647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.024704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.024729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.024766] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.041590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.041609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.041629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.041646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.041662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.041677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.041692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.041708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.041725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.041741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.041757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.041771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.041785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.041812] [drm:intel_power_well_disable [i915]] disabling display
>[  956.041883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.041910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.041939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.041966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.041991] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.042351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.042368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.042386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.042407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.042426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.042446] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.042465] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.042484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.042504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.042523] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.042541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.042545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.042564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.042568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.042587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.042606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.042625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.042644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.042663] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.042682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.042702] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.042721] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.042740] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.042760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.042781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.042857] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.042887] [drm:intel_power_well_enable [i915]] enabling display
>[  956.042912] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.042953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.042978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.043002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.043026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.043049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.043073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.043099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.043124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.043148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.043170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.043190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.043216] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.043240] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.045232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.045248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.045262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.045276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.046782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.046797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.046810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.048330] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.048346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.050179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.053112] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.053188] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.053204] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.053226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.053282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.053304] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.053336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.103344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.103366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.103387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.103411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.103431] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.103452] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.103472] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.103492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.103513] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.103533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.103553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.103557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.103577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.103580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.103601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.103621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.103641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.103661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.103682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.103702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.103722] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.103743] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.103763] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.103784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.103806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.103912] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.103946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.104129] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.120552] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.120571] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.120591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.120608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.120624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.120639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.120653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.120669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.120686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.120702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.120718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.120732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.120746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.120772] [drm:intel_power_well_disable [i915]] disabling display
>[  956.120793] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.120809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.120826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.120888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.120915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.121267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.121294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.121321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.121351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.121376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.121402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.121428] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.121453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.121478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.121501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.121524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.121531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.121554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.121559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.121583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.121606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.121629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.121652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.121678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.121701] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.121725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.121746] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.121769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.121794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.121828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.121914] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.121937] [drm:intel_power_well_enable [i915]] enabling display
>[  956.121960] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.121999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.122022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.122044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.122065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.122085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.122106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.122130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.122154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.122177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.122199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.122220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.122245] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.122268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.124255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.124271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.124285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.124299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.125802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.125817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.125861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.127369] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.127387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.129210] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.132159] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.132219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.132236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.132258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.132316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.132338] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.132370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.182385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.182405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.182425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.182446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.182462] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.182480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.182498] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.182515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.182532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.182548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.182563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.182567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.182582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.182586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.182601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.182616] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.182631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.182645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.182662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.182678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.182694] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.182709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.182723] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.182744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.182766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.182823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.182883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.183065] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.199534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.199553] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.199573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.199592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.199612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.199631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.199650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.199669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.199690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.199711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.199731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.199750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.199766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.199794] [drm:intel_power_well_disable [i915]] disabling display
>[  956.199816] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.199836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.199903] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.199934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.199960] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.200337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.200355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.200373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.200393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.200408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.200425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.200443] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.200459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.200474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.200489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.200503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.200507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.200520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.200524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.200538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.200552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.200566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.200579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.200596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.200622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.200636] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.200649] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.200662] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.200677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.200693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.200734] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.200747] [drm:intel_power_well_enable [i915]] enabling display
>[  956.200760] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.200784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.200798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.200812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.200825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.200872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.200894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.200920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.200944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.200969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.200991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.201013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.201039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.201063] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.203056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.203072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.203086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.203100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.204604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.204619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.204633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.206127] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.206143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.207948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.210846] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.210906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.210922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.210944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.211002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.211023] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.211055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.261053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.261073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.261093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.261114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.261131] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.261149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.261167] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.261184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.261202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.261222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.261242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.261247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.261267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.261270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.261291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.261312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.261332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.261352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.261373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.261392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.261414] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.261434] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.261454] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.261475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.261496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.261553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.261578] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.261615] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.278432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.278451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.278471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.278488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.278503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.278518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.278533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.278549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.278566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.278582] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.278598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.278616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.278635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.278663] [drm:intel_power_well_disable [i915]] disabling display
>[  956.278685] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.278705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.278726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.278746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.278761] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.279144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.279172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.279200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.279230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.279255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.279282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.279308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.279333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.279359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.279383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.279406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.279413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.279436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.279442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.279473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.279494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.279515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.279537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.279560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.279582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.279605] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.279626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.279647] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.279672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.279696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.279759] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.279781] [drm:intel_power_well_enable [i915]] enabling display
>[  956.279803] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.279840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.279889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.279913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.279936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.279959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.279982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.280008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.280032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.280056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.280078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.280100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.280126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.280149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.282138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.282156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.282173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.282192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.283697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.283713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.283728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.285224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.285240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.287043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.289948] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.290000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.290016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.290038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.290094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.290115] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.290147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.340171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.340191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.340211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.340232] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.340249] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.340267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.340285] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.340302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.340319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.340334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.340354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.340358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.340378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.340382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.340402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.340423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.340443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.340463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.340484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.340503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.340524] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.340545] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.340565] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.340586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.340608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.340665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.340689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.340727] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.357511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.357529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.357550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.357566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.357582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.357597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.357612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.357628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.357645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.357661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.357677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.357691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.357705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.357732] [drm:intel_power_well_disable [i915]] disabling display
>[  956.357753] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.357768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.357785] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.357800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.357815] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.358191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.358217] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.358245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.358274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.358298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.358330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.358354] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.358377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.358400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.358423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.358445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.358452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.358472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.358478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.358499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.358521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.358542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.358561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.358585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.358606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.358628] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.358650] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.358670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.358695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.358720] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.358784] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.358807] [drm:intel_power_well_enable [i915]] enabling display
>[  956.358829] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.358886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.358911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.358934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.358957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.358979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.359003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.359029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.359053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.359078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.359100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.359122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.359148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.359172] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.361162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.361177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.361191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.361206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.362711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.362729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.362746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.364244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.364261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.366066] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.368972] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.369024] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.369041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.369062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.369121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.369146] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.369181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.419184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.419205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.419224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.419245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.419262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.419280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.419298] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.419315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.419334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.419354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.419374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.419378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.419398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.419402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.419423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.419443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.419463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.419483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.419503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.419523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.419545] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.419565] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.419585] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.419606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.419627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.419684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.419709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.419746] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.436584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.436603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.436622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.436639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.436655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.436670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.436684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.436700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.436717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.436733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.436749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.436763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.436777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.436803] [drm:intel_power_well_disable [i915]] disabling display
>[  956.436824] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.436840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.436902] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.436933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.436959] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.437326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.437342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.437359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.437376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.437390] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.437406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.437421] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.437435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.437449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.437462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.437475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.437478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.437490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.437494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.437511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.437529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.437546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.437563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.437581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.437598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.437616] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.437633] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.437650] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.437669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.437687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.437729] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.437743] [drm:intel_power_well_enable [i915]] enabling display
>[  956.437757] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.437784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.437802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.437820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.437837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.437886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.437909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.437938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.437964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.437989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.438012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.438035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.438061] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.438085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.440078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.440094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.440108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.440123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.441627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.441642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.441655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.443150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.443166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.444970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.447902] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.447978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.447994] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.448016] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.448072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.448094] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.448126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.498149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.498169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.498189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.498212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.498233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.498254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.498274] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.498295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.498315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.498335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.498355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.498359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.498379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.498383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.498404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.498424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.498444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.498464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.498485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.498505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.498526] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.498546] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.498566] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.498587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.498608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.498665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.498690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.498726] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.515595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.515614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.515634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.515651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.515667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.515681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.515696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.515715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.515736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.515757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.515777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.515796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.515812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.515840] [drm:intel_power_well_disable [i915]] disabling display
>[  956.515911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.515943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.515980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.516008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.516033] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.516352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.516369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.516387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.516405] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.516420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.516437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.516454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.516469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.516484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.516498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.516511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.516515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.516528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.516531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.516545] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.516558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.516572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.516585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.516600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.516614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.516628] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.516641] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.516654] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.516670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.516687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.516729] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.516742] [drm:intel_power_well_enable [i915]] enabling display
>[  956.516755] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.516781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.516796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.516810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.516824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.516838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.516852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.516905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.516932] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.516958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.516982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.517010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.517037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.517061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.519054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.519070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.519085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.519100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.520603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.520618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.520632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.522128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.522144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.523948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.526880] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.526905] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.526922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.526943] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.527000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.527022] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.527054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.577072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.577093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.577113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.577134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.577150] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.577168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.577186] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.577203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.577220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.577235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.577250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.577254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.577270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.577273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.577289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.577309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.577329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.577349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.577370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.577390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.577411] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.577431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.577451] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.577473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.577494] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.577552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.577576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.577613] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.594430] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.594449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.594469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.594486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.594502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.594517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.594532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.594548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.594565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.594581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.594601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.594620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.594637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.594665] [drm:intel_power_well_disable [i915]] disabling display
>[  956.594687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.594707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.594728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.594748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.594763] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.595150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.595177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.595204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.595233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.595257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.595283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.595308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.595333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.595357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.595380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.595403] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.595410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.595431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.595437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.595460] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.595483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.595506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.595528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.595553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.595576] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.595598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.595620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.595642] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.595668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.595694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.595760] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.595784] [drm:intel_power_well_enable [i915]] enabling display
>[  956.595807] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.595846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.595897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.595920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.595942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.595965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.595989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.596015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.596039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.596064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.596086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.596108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.596134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.596157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.598147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.598165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.598182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.598200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.599708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.599725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.599739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.601234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.601250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.603054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.605986] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.606062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.606079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.606107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.606160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.606179] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.606209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.656227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.656247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.656267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.656288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.656305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.656323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.656341] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.656358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.656375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.656390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.656406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.656410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.656425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.656428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.656444] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.656459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.656474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.656488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.656506] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.656521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.656537] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.656552] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.656572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.656593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.656614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.656672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.656696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.656733] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.673546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.673565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.673585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.673602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.673617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.673632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.673647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.673663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.673684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.673704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.673725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.673744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.673761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.673788] [drm:intel_power_well_disable [i915]] disabling display
>[  956.673811] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.673831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.673851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.673917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.673946] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.674288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.674315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.674343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.674372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.674397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.674423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.674450] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.674475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.674499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.674523] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.674547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.674553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.674576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.674582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.674605] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.674629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.674652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.674676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.674702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.674732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.674755] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.674774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.674795] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.674819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.674844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.674927] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.674950] [drm:intel_power_well_enable [i915]] enabling display
>[  956.674973] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.675011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.675035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.675058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.675081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.675103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.675126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.675150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.675173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.675197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.675218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.675239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.675263] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.675287] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.677277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.677293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.677307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.677322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.678830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.678845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.678859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.680397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.680413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.682237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.685184] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.685246] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.685263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.685284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.685341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.685363] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.685395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.735414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.735434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.735454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.735475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.735492] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.735510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.735530] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.735550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.735571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.735591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.735611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.735615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.735635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.735639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.735660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.735680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.735701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.735721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.735741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.735761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.735782] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.735802] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.735822] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.735843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.735864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.735976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.736009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.736193] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.752566] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.752585] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.752605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.752622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.752637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.752653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.752667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.752683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.752704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.752725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.752745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.752764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.752781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.752809] [drm:intel_power_well_disable [i915]] disabling display
>[  956.752831] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.752851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.752872] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.752933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.752963] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.753355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.753373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.753392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.753411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.753427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.753444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.753461] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.753476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.753492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.753507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.753521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.753525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.753545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.753549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.753562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.753574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.753591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.753609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.753626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.753644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.753662] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.753680] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.753697] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.753715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.753734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.753776] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.753791] [drm:intel_power_well_enable [i915]] enabling display
>[  956.753804] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.753832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.753850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.753868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.753920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.753946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.753972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.753999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.754024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.754049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.754072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.754094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.754121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.754145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.756143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.756159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.756173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.756188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.757692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.757709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.757726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.759224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.759240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.761045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.763952] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.764003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.764019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.764041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.764099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.764120] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.764152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.814150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.814171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.814193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.814216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.814237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.814258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.814278] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.814298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.814319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.814339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.814359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.814363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.814383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.814387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.814407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.814428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.814448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.814468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.814488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.814508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.814529] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.814550] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.814570] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.814591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.814613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.814670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.814695] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.814732] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.831561] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.831582] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.831603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.831623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.831643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.831662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.831681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.831700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.831721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.831741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.831762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.831781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.831797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.831824] [drm:intel_power_well_disable [i915]] disabling display
>[  956.831847] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.831867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.831933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.831967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.831992] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.832356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.832383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.832411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.832441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.832472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.832496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.832520] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.832543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.832566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.832588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.832609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.832615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.832636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.832642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.832663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.832685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.832706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.832727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.832750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.832771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.832791] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.832812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.832833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.832855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.832879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.832972] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.832995] [drm:intel_power_well_enable [i915]] enabling display
>[  956.833017] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.833056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.833079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.833102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.833124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.833146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.833167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.833191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.833215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.833239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.833260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.833281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.833305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.833328] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.835330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.835347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.835361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.835376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.836892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.836907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.836921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.838420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.838437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.840316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.843243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.843274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.843294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.843320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.843380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.843404] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.843440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.893442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.893462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.893483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.893507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.893527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.893548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.893569] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.893589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.893609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.893630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.893649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.893654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.893674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.893677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.893698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.893718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.893738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.893758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.893779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.893798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.893820] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.893840] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.893860] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.893881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.893938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.894019] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.894224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.894277] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.911102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.911121] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.911142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.911161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.911181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.911200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.911219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.911238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.911259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.911280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.911300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.911319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.911335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.911363] [drm:intel_power_well_disable [i915]] disabling display
>[  956.911385] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.911405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.911425] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.911446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.911461] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.911696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.911716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.911736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.911757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.911777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.911796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.911815] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.911835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.911854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.911873] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.911939] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.911947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.911973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.911980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.912006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.912032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.912058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.912082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.912110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.912135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.912162] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.912186] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.912210] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.912238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.912267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.912343] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.912365] [drm:intel_power_well_enable [i915]] enabling display
>[  956.912387] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.912424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.912447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.912470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.912492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.912512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.912534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.912557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.912580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.912604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.912626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.912647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.912672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.912695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.914685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.914702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.914716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.914731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.916237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.916252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.916266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.917759] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.917777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.919587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  956.922521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  956.922597] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  956.922613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  956.922636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  956.922694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.922716] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.922751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.972815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.972848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.972881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.972974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.973016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.973064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.973110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.973153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.973193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.973233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.973271] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.973282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.973319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.973328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.973367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.973406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.973444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.973481] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.973520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.973559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.973598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.973637] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.973671] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.973712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.973757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.973889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  956.973963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  956.974022] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  956.990865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  956.990884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  956.990949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.990978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.991004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.991028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.991052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.991077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.991105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.991131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.991158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.991181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.991204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.991247] [drm:intel_power_well_disable [i915]] disabling display
>[  956.991281] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  956.991306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  956.991333] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  956.991359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.991383] [drm:intel_power_well_disable [i915]] disabling always-on
>[  956.991627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  956.991644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  956.991662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  956.991682] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  956.991697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  956.991714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  956.991730] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  956.991746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  956.991761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  956.991779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  956.991798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  956.991803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.991821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  956.991825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  956.991845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  956.991864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  956.991883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  956.991937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  956.991968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  956.991994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  956.992019] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  956.992042] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  956.992064] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  956.992090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  956.992116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  956.992180] [drm:intel_power_well_enable [i915]] enabling always-on
>[  956.992203] [drm:intel_power_well_enable [i915]] enabling display
>[  956.992226] [drm:hsw_set_power_well [i915]] Enabling power well
>[  956.992263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  956.992286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  956.992308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  956.992327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  956.992348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  956.992369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  956.992394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  956.992418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  956.992441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  956.992462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  956.992484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  956.992509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  956.992531] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  956.994520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  956.994536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  956.994550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.994565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  956.996072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  956.996087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  956.996100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  956.997593] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  956.997609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  956.999415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.002348] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  957.002424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.002441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  957.002466] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.002527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.002551] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.002586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.052593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.052614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.052634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.052655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.052672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.052692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.052713] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  957.052733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  957.052754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.052774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.052794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.052798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.052818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.052822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.052843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.052863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.052884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.052939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.052968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.052996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.053025] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.053051] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  957.053076] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  957.053104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.053132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  957.053214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  957.053245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.053296] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  957.070117] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  957.070136] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.070157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.070177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.070197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.070216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.070235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.070254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.070275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.070295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.070316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.070334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.070351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.070378] [drm:intel_power_well_disable [i915]] disabling display
>[  957.070401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.070421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.070442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.070462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.070477] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.070701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.070721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.070741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.070771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.070788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.070805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.070821] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  957.070836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  957.070850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.070863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.070876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.070914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.070936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.070943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.070967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.070990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.071013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.071035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.071060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.071082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.071106] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.071128] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  957.071150] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  957.071175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.071201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  957.071267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.071289] [drm:intel_power_well_enable [i915]] enabling display
>[  957.071312] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.071349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.071372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.071393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.071413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.071434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.071458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.071483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.071506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.071530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.071551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.071572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.071598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  957.071622] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.073614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.073631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.073645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.073660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.075166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.075181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.075195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.076688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.076704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.078512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.081446] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  957.081522] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.081539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  957.081561] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.081618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.081642] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.081677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.131686] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.131707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.131727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.131750] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.131770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.131791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.131812] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  957.131832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  957.131852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.131872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.131892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.131926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.131954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.131962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.131992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.132019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.132045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.132070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.132098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.132123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.132150] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.132174] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  957.132197] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  957.132224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.132252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  957.132334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  957.132365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.132556] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  957.150665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  957.150684] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.150706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.150726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.150745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.150764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.150784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.150803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.150824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.150844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.150865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.150883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.150946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.150989] [drm:intel_power_well_disable [i915]] disabling display
>[  957.151024] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.151052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.151080] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.151107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.151132] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.151277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.151328] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.151357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.151383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.151409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.151433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.151456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.151481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.151507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.151533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.151559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.151585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.151608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.151631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.151664] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.151697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.151925] [drm:drm_mode_addfb2] [FB:77]
>[  957.151949] [drm:drm_mode_addfb2] [FB:78]
>[  957.177784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  957.177871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  957.177989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  957.178084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  957.178099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  957.178170] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.178195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.178218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.178237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.178251] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.178267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.178282] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.178297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.178311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.178325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.178338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.178341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.178354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.178358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.178371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.178384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.178396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.178409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.178424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.178437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.178449] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  957.178466] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.178484] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.178503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.178522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.181041] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.181057] [drm:intel_power_well_enable [i915]] enabling display
>[  957.181072] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.181102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.181119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.181135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.181151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.181165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.181181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.181201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.181221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.181241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.181260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.181276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.181296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.181315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.183311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.183327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.183341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.183356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.184866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.184881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.184927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.186431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.186446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.188264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.191218] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.191274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.191290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.191313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.208017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.208043] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.208078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.224799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.224821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.224843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.224866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.224886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.224945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.224971] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.224998] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.225021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.225044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.225067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.225074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.225090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.225093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.225108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.225123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.225137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.225151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.225168] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.225183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.225198] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.225212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.225226] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.225242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.225263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.225312] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.225336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.225389] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.243678] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.243696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.243717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.243733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.243749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.243764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.243782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.243802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.243823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.243843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.243864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.243883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.243898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.243975] [drm:intel_power_well_disable [i915]] disabling display
>[  957.244010] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.244039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.244069] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.244097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.244121] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.244274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.244300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.244328] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.244358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.244383] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.244409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.244435] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.244460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.244485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.244508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.244529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.244535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.244558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.244564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.244587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.244610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.244633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.244656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.244690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.244712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.244734] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.244755] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.244775] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.244798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.244823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.244888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.244931] [drm:intel_power_well_enable [i915]] enabling display
>[  957.244952] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.244991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.245015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.245038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.245061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.245083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.245104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.245130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.245155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.245180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.245202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.245224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.245249] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.245271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.247261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.247277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.247291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.247306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.248810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.248825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.248839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.250336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.250354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.252159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.255095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.255168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.255184] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.255206] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.255285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.255320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.255369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.305335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.305355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.305375] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.305399] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.305419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.305440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.305460] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.305481] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.305501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.305521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.305541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.305545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.305565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.305569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.305589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.305610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.305630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.305650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.305671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.305690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.305712] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.305732] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.305752] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.305773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.305795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.305852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.305877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.305953] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.322764] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.322783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.322804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.322821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.322836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.322851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.322870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.322889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.322952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.322982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.323010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.323033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.323057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.323101] [drm:intel_power_well_disable [i915]] disabling display
>[  957.323134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.323159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.323186] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.323212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.323236] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.323527] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.323543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.323560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.323578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.323592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.323607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.323623] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.323637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.323651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.323664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.323676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.323680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.323692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.323695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.323713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.323730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.323748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.323765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.323782] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.323799] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.323817] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.323835] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.323852] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.323870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.323889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.323971] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.323994] [drm:intel_power_well_enable [i915]] enabling display
>[  957.324017] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.324055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.324077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.324101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.324122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.324144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.324165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.324189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.324213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.324237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.324257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.324277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.324299] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.324322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.326313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.326329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.326343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.326357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.327863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.327879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.327894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.329438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.329457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.331268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.334217] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.334278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.334294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.334316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.334395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.334430] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.334480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.384512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.384546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.384579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.384613] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.384641] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.384671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.384702] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.384735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.384769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.384802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.384835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.384842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.384874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.384880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.384914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.384996] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.385044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.385083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.385128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.385166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.385208] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.385245] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.385285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.385326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.385372] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.385503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.385552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.385858] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.401603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.401622] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.401642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.401659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.401675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.401690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.401704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.401720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.401737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.401753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.401769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.401783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.401797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.401823] [drm:intel_power_well_disable [i915]] disabling display
>[  957.401845] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.401864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.401885] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.401906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.401965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.402301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.402324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.402348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.402375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.402396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.402419] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.402441] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.402464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.402484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.402506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.402525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.402530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.402550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.402555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.402577] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.402596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.402617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.402636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.402659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.402678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.402700] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.402719] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.402740] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.402761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.402785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.402849] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.402870] [drm:intel_power_well_enable [i915]] enabling display
>[  957.402892] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.402952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.402974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.402996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.403017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.403039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.403060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.403085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.403110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.403135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.403155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.403176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.403202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.403223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.406306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.406325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.406341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.406361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.410072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.410092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.410111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.412685] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.412704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.415582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.418512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.418539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.418555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.418575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.418631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.418651] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.418682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.468708] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.468728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.468748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.468769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.468786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.468804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.468822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.468838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.468855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.468871] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.468886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.468890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.468905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.468934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.468956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.468984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.469006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.469030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.469054] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.469078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.469105] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.469127] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.469150] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.469177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.469205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.469286] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.469315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.469498] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.487515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.487534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.487554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.487571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.487586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.487601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.487616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.487632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.487649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.487665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.487681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.487695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.487708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.487735] [drm:intel_power_well_disable [i915]] disabling display
>[  957.487756] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.487772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.487789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.487805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.487819] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.488170] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.488189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.488215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.488233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.488247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.488264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.488279] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.488295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.488313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.488331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.488348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.488352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.488370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.488373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.488391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.488409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.488428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.488445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.488463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.488481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.488500] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.488518] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.488535] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.488553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.488573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.488615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.488630] [drm:intel_power_well_enable [i915]] enabling display
>[  957.488644] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.488672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.488690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.488709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.488727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.488745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.488763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.488782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.488801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.488821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.488838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.488856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.488875] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.488893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.491996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.492016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.492035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.492055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.494630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.494648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.494663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.497238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.497255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.500127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.503078] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.503138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.503154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.503176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.503235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.503258] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.503291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.553269] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.553288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.553307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.553329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.553348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.553368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.553387] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.553406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.553425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.553444] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.553463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.553467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.553485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.553489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.553508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.553527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.553546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.553565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.553584] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.553602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.553622] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.553642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.553660] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.553680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.553701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.553756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.553779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.553815] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.570645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.570664] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.570684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.570701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.570717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.570732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.570747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.570763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.570780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.570796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.570815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.570834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.570853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.570881] [drm:intel_power_well_disable [i915]] disabling display
>[  957.570903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.570964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.570996] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.571025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.571057] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.571400] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.571423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.571449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.571476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.571497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.571522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.571544] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.571566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.571587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.571609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.571629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.571634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.571654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.571659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.571681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.571701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.571721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.571740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.571764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.571783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.571805] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.571825] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.571845] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.571869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.571894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.571981] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.572005] [drm:intel_power_well_enable [i915]] enabling display
>[  957.572028] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.572075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.572099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.572120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.572143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.572163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.572186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.572211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.572235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.572259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.572280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.572302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.572328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.572351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.575449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.575468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.575484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.575501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.579218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.579235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.579250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.581810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.581829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.584702] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.587626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.587660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.587676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.587698] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.587756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.587778] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.587810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.637830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.637851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.637871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.637892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.637909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.637957] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.637988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.638012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.638038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.638060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.638084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.638090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.638114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.638120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.638145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.638166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.638190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.638210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.638235] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.638256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.638279] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.638300] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.638322] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.638348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.638375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.638455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.638485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.638535] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.655356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.655375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.655395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.655412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.655428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.655443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.655458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.655474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.655491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.655507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.655523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.655537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.655551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.655578] [drm:intel_power_well_disable [i915]] disabling display
>[  957.655599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.655615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.655632] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.655648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.655663] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.655884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.655900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.655916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.655968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.655989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.656012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.656034] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.656055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.656076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.656096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.656115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.656122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.656141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.656147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.656167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.656186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.656206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.656225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.656247] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.656266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.656289] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.656309] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.656329] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.656352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.656376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.656420] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.656433] [drm:intel_power_well_enable [i915]] enabling display
>[  957.656446] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.656471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.656485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.656499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.656512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.656525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.656539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.656554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.656568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.656583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.656600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.656618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.656637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.656654] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.659723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.659740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.659755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.659770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.663448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.663465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.663480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.666145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.666164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.669013] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.671964] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.672023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.672040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.672062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.672119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.672149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.672180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.722176] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.722196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.722217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.722240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.722261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.722282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.722302] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.722322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.722343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.722363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.722383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.722387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.722407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.722411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.722431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.722452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.722472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.722493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.722513] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.722533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.722554] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.722574] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.722594] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.722616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.722637] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.722695] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.722720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.722758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.739573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.739592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.739612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.739629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.739645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.739660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.739675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.739691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.739708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.739724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.739739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.739754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.739768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.739795] [drm:intel_power_well_disable [i915]] disabling display
>[  957.739816] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.739832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.739849] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.739865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.739880] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.740272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.740296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.740324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.740353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.740375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.740400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.740424] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.740448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.740471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.740494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.740515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.740522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.740543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.740549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.740572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.740593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.740615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.740635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.740660] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.740681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.740704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.740725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.740747] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.740777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.740802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.740864] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.740886] [drm:intel_power_well_enable [i915]] enabling display
>[  957.740907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.740967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.740989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.741012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.741033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.741054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.741076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.741101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.741125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.741149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.741169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.741191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.741217] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.741238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.744335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.744354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.744370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.744386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.748098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.748118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.748137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.750700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.750719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.753593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.756531] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.756603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.756622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.756648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.756709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.756734] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.756770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.806771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.806791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.806812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.806832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.806849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.806867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.806885] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.806902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.806918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.806963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.806987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.806996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.807019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.807026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.807051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.807073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.807098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.807120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.807147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.807168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.807193] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.807214] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.807235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.807258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.807284] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.807364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.807394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.807442] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.824262] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.824281] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.824302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.824319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.824334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.824350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.824364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.824380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.824397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.824417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.824438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.824457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.824474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.824501] [drm:intel_power_well_disable [i915]] disabling display
>[  957.824523] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.824543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.824564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.824584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.824599] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.824817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.824835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.824854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.824875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.824892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.824911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.824929] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.825019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.825044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.825067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.825090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.825096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.825118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.825124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.825146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.825169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.825192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.825213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.825238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.825260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.825279] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.825293] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.825306] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.825321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.825340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.825385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.825399] [drm:intel_power_well_enable [i915]] enabling display
>[  957.825414] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.825442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.825461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.825479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.825498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.825516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.825534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.825554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.825573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.825592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.825610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.825628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.825648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.825666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.828750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.828770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.828789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.828809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.832517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.832535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.832551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.835119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.835137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.838038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.840990] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.841049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.841073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.841093] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.841147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.841167] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.841197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.891213] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.891235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.891256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.891280] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.891300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.891321] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.891341] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.891362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.891382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.891403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.891423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.891427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.891446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.891450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.891471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.891491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.891511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.891531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.891552] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.891572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.891593] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.891613] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.891633] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.891655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.891676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.891733] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.891758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.891795] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.908273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.908292] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.908312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.908328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.908343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.908358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.908372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.908388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.908405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.908421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.908437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.908452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.908466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.908492] [drm:intel_power_well_disable [i915]] disabling display
>[  957.908513] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.908529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.908546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.908562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.908576] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.908873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.908890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.908907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.908928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.908985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.909013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.909037] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.909061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.909082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.909104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.909124] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.909131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.909152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.909158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.909180] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.909200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.909222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.909241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.909265] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.909285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.909308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.909327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.909349] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.909374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.909398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.909462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.909484] [drm:intel_power_well_enable [i915]] enabling display
>[  957.909507] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.909545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.909567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.909587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.909608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.909630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.909650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.909674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.909697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.909720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.909740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.909760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.909782] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.909804] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.912888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.912907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.912925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.913064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.915642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.915661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.915681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.918251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.918271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.921145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.924096] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.924156] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.924173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.924195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.924253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.924275] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.924307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.974326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.974346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.974367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.974387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.974404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.974422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.974440] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.974457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.974474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.974491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.974512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.974516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.974536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.974540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.974561] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.974581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.974601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.974621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.974642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.974662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.974683] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.974703] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.974723] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.974745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.974766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.974823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  957.974848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.974886] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  957.991706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  957.991725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.991745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.991762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.991778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.991793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.991808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.991824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.991841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.991857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.991873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.991887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.991905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.991933] [drm:intel_power_well_disable [i915]] disabling display
>[  957.992000] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.992026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.992056] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.992084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.992109] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.992431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.992449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.992468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.992487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.992503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.992520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.992537] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.992553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.992568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.992583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.992604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.992607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.992620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.992623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.992635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.992648] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.992660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.992672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.992687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.992699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.992713] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  957.992725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.992737] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.992752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.992768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.992809] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.992822] [drm:intel_power_well_enable [i915]] enabling display
>[  957.992834] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.992859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.992873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.992887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.992900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.992913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.992927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.992966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.992988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.993013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.993033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.993054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.993080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.993101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.996188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.996207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.996222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.996239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.999957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.999986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.000006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.002602] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.002622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.005497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.008432] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.008507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.008523] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.008549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.008610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.008634] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.008670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.058670] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.058691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.058711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.058732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.058749] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.058767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.058786] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.058803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.058820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.058836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.058852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.058856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.058871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.058874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.058890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.058905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.058920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.058935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.058982] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.059007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.059033] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.059056] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.059078] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.059104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.059134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.059215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.059244] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.059438] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.077716] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.077735] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.077755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.077772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.077787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.077802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.077817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.077833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.077850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.077866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.077881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.077900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.077918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.077945] [drm:intel_power_well_disable [i915]] disabling display
>[  958.078014] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.078043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.078072] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.078101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.078126] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.078474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.078492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.078510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.078530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.078553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.078568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.078584] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.078598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.078613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.078627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.078640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.078643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.078660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.078663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.078681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.078699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.078716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.078733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.078751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.078768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.078786] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.078804] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.078821] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.078839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.078857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.078899] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.078913] [drm:intel_power_well_enable [i915]] enabling display
>[  958.078927] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.078982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.079008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.079030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.079053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.079074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.079098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.079123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.079148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.079172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.079192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.079213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.079237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.079260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.082345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.082364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.082380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.082396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.086088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.086108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.086127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.088695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.088721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.091593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.094519] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.094551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.094568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.094590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.094647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.094669] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.094702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.144707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.144728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.144748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.144769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.144786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.144804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.144825] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.144845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.144866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.144886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.144906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.144910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.144930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.144934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.144955] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.145004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.145034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.145057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.145085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.145108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.145135] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.145158] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.145182] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.145210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.145238] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.145319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.145350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.145534] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.162839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.162858] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.162878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.162895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.162911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.162925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.162940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.162998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.163027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.163053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.163080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.163101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.163125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.163169] [drm:intel_power_well_disable [i915]] disabling display
>[  958.163202] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.163227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.163254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.163279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.163303] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.163588] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.163604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.163620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.163638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.163652] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.163668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.163683] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.163697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.163711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.163724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.163737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.163740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.163753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.163756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.163769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.163782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.163794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.163806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.163821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.163834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.163848] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.163860] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.163873] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.163888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.163904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.163943] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.163985] [drm:intel_power_well_enable [i915]] enabling display
>[  958.164007] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.164045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.164067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.164090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.164111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.164133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.164154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.164179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.164203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.164228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.164247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.164269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.164295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.164317] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.167426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.167445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.167461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.167477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.170109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.170128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.170144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.172710] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.172728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.175603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.178528] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.178560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.178576] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.178598] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.178656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.178678] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.178711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.228729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.228749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.228769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.228790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.228807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.228825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.228843] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.228860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.228880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.228901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.228921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.228925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.228945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.228974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.228999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.229029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.229052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.229076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.229101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.229127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.229151] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.229175] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.229197] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.229223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.229251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.229332] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.229363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.229413] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.246262] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.246281] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.246301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.246318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.246334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.246349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.246363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.246382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.246403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.246424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.246444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.246463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.246479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.246507] [drm:intel_power_well_disable [i915]] disabling display
>[  958.246529] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.246549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.246570] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.246590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.246606] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.246848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.246868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.246888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.246910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.246929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.246948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.247009] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.247035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.247063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.247086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.247110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.247117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.247140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.247146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.247171] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.247193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.247217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.247238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.247265] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.247286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.247312] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.247333] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.247357] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.247384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.247412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.247483] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.247507] [drm:intel_power_well_enable [i915]] enabling display
>[  958.247538] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.247577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.247601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.247623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.247645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.247667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.247690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.247715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.247739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.247761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.247780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.247801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.247824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.247846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.250932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.250951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.251009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.251036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.253614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.253638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.253653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.256218] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.256236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.259113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.262064] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.262122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.262139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.262161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.262219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.262241] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.262274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.312270] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.312291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.312311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.312332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.312348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.312369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.312389] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.312410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.312431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.312451] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.312471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.312475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.312495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.312499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.312519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.312539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.312560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.312580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.312600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.312620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.312641] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.312661] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.312681] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.312703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.312724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.312782] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.312807] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.312844] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.329705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.329724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.329744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.329761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.329776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.329791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.329806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.329822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.329839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.329855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.329870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.329885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.329898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.329925] [drm:intel_power_well_disable [i915]] disabling display
>[  958.329947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.329967] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.330028] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.330058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.330083] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.330444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.330460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.330477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.330495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.330510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.330525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.330541] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.330555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.330569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.330583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.330596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.330600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.330612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.330615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.330628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.330646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.330663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.330681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.330698] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.330715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.330734] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.330751] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.330769] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.330787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.330804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.330846] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.330860] [drm:intel_power_well_enable [i915]] enabling display
>[  958.330874] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.330902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.330920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.330938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.330956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.330999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.331024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.331051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.331076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.331101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.331121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.331143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.331169] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.331191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.334279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.334298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.334313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.334329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.336917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.336936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.336952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.339567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.339592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.342485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.345423] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.345495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.345512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.345534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.345593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.345615] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.345647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.395663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.395684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.395706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.395729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.395749] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.395770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.395791] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.395811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.395832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.395852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.395871] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.395876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.395895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.395899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.395920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.395940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.395960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.396010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.396041] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.396065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.396093] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.396116] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.396142] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.396168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.396196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.396277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.396307] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.396489] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.412697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.412715] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.412735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.412752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.412768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.412783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.412798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.412814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.412830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.412846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.412862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.412876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.412891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.412917] [drm:intel_power_well_disable [i915]] disabling display
>[  958.412938] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.412954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.413011] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.413042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.413068] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.413421] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.413444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.413468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.413495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.413516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.413540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.413562] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.413583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.413604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.413625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.413644] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.413649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.413669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.413674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.413695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.413714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.413734] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.413753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.413776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.413795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.413816] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.413835] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.413855] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.413878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.413903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.413966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.414118] [drm:intel_power_well_enable [i915]] enabling display
>[  958.414139] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.414177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.414201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.414222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.414244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.414264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.414286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.414311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.414334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.414357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.414376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.414396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.414421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.414442] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.417539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.417558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.417577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.417597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.421296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.421315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.421331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.423910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.423929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.426808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.429751] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.429817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.429833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.429854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.429909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.429929] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.429960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.479976] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.480007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.480028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.480048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.480065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.480083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.480102] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.480122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.480143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.480163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.480183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.480187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.480207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.480211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.480231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.480252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.480272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.480292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.480312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.480332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.480353] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.480374] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.480394] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.480415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.480437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.480494] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.480519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.480556] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.497369] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.497388] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.497408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.497425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.497441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.497456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.497470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.497486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.497503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.497519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.497535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.497549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.497567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.497595] [drm:intel_power_well_disable [i915]] disabling display
>[  958.497617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.497637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.497658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.497679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.497694] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.497947] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.497965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.498029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.498060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.498084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.498112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.498137] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.498163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.498186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.498210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.498232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.498240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.498262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.498268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.498291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.498312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.498342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.498361] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.498385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.498404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.498426] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.498445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.498466] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.498487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.498511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.498576] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.498598] [drm:intel_power_well_enable [i915]] enabling display
>[  958.498620] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.498656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.498677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.498698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.498718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.498738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.498758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.498782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.498805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.498828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.498847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.498866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.498889] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.498911] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.502007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.502026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.502042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.502058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.504627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.504644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.504659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.507224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.507242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.510109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.513060] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.513120] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.513139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.513165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.513227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.513251] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.513287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.563291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.563313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.563334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.563358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.563377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.563398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.563419] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.563439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.563460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.563480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.563500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.563504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.563524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.563528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.563548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.563569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.563589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.563609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.563629] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.563649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.563670] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.563690] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.563710] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.563731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.563753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.563810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.563835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.563872] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.580676] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.580695] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.580715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.580732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.580748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.580763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.580778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.580794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.580811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.580827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.580842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.580856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.580870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.580897] [drm:intel_power_well_disable [i915]] disabling display
>[  958.580918] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.580933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.580950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.580966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.581025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.581364] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.581396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.581422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.581448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.581469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.581492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.581514] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.581537] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.581557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.581578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.581598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.581604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.581623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.581628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.581650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.581669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.581689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.581708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.581731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.581749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.581772] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.581791] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.581811] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.581832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.581856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.581918] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.581940] [drm:intel_power_well_enable [i915]] enabling display
>[  958.581962] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.582017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.582039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.582062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.582082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.582104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.582125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.582150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.582174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.582199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.582219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.582241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.582266] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.582288] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.585366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.585383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.585398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.585413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.589108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.589127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.589143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.591725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.591744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.594619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.597544] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.597577] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.597593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.597615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.597673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.597695] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.597728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.647744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.647764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.647784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.647805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.647822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.647840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.647858] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.647875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.647892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.647908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.647923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.647927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.647943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.647946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.647962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.647977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.648022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.648049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.648073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.648097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.648124] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.648146] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.648170] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.648197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.648225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.648307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.648337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.648522] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.665820] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.665839] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.665861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.665880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.665900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.665919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.665938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.665957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.665978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.666043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.666073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.666097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.666122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.666163] [drm:intel_power_well_disable [i915]] disabling display
>[  958.666196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.666222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.666249] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.666275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.666299] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.666661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.666688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.666715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.666745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.666770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.666796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.666822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.666845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.666867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.666889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.666908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.666914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.666934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.666939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.666960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.666980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.667024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.667044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.667068] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.667089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.667111] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.667131] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.667152] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.667175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.667201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.667267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.667289] [drm:intel_power_well_enable [i915]] enabling display
>[  958.667311] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.667348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.667369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.667391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.667411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.667431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.667451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.667475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.667498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.667520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.667539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.667559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.667582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.667604] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.670687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.670706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.670722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.670738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.674433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.674453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.674469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.677047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.677068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.679955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.682899] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.682964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.682981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.683049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.683236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.683260] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.683293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.733129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.733149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.733169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.733191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.733212] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.733233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.733253] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.733274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.733294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.733314] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.733334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.733338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.733358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.733362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.733382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.733403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.733423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.733443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.733463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.733483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.733504] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.733525] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.733545] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.733566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.733588] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.733646] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.733670] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.733708] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.750523] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.750542] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.750563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.750580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.750596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.750611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.750626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.750642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.750659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.750674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.750690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.750704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.750718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.750745] [drm:intel_power_well_disable [i915]] disabling display
>[  958.750766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.750781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.750797] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.750813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.750828] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.751116] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.751143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.751169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.751199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.751222] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.751248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.751271] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.751295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.751318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.751347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.751366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.751372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.751392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.751397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.751418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.751437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.751457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.751476] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.751498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.751517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.751538] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.751557] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.751577] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.751598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.751622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.751686] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.751707] [drm:intel_power_well_enable [i915]] enabling display
>[  958.751729] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.751766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.751787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.751807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.751828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.751847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.751868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.751892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.751915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.751938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.751957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.751977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.752020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.752044] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.755106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.755131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.755154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.755178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.758849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.758868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.758884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.761441] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.761459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.764348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.767299] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.767359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.767376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.767398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.767456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.767478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.767511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.817524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.817545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.817565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.817586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.817603] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.817621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.817639] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.817659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.817680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.817700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.817720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.817724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.817744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.817748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.817769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.817789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.817809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.817830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.817850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.817870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.817891] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.817911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.817932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.817953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.817974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.818076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.818109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.818295] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.834715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.834733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.834753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.834770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.834785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.834800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.834815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.834831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.834848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.834863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.834879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.834893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.834907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.834933] [drm:intel_power_well_disable [i915]] disabling display
>[  958.834955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.834970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.834986] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.835076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.835101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.835459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.835475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.835492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.835510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.835523] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.835539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.835554] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.835568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.835582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.835596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.835608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.835612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.835625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.835628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.835641] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.835654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.835666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.835679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.835694] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.835706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.835720] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.835732] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.835744] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.835759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.835775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.835816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.835829] [drm:intel_power_well_enable [i915]] enabling display
>[  958.835842] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.835866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.835881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.835894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.835908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.835921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.835934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.835949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.835964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.835978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.835991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.836030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.836056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.836078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.839164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.839182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.839197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.839213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.842913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.842933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.842952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.845540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.845558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.848477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.851428] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.851487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.851504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.851526] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.851593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.851614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.851644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.901634] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.901656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.901677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.901701] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.901721] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.901741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.901762] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.901782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.901803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.901823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.901843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.901847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.901867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.901870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.901891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.901911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.901931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.901951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.901972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.901992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.902042] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.902073] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.902098] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.902126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.902155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.902237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.902267] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.902458] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  958.918711] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  958.918730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  958.918750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.918767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.918786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.918806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.918825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.918844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.918865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.918886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.918906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.918925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.918941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.918969] [drm:intel_power_well_disable [i915]] disabling display
>[  958.918991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  958.919056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.919086] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.919116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.919141] [drm:intel_power_well_disable [i915]] disabling always-on
>[  958.919484] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.919507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.919531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.919558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.919579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.919602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.919623] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.919645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.919666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.919686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.919705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.919711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.919730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.919735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.919756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.919775] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.919796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.919814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.919837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.919855] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.919877] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.919896] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.919915] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.919937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.919960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.920047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  958.920071] [drm:intel_power_well_enable [i915]] enabling display
>[  958.920093] [drm:hsw_set_power_well [i915]] Enabling power well
>[  958.920132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  958.920155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  958.920176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  958.920198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  958.920218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  958.920240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  958.920265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  958.920288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  958.920311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.920331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  958.920353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  958.920377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  958.920398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  958.923469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  958.923487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  958.923502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.923518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  958.927252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  958.927271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  958.927287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  958.929846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  958.929864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  958.932739] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  958.935674] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  958.935749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  958.935766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  958.935788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  958.935845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  958.935868] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  958.935900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  958.985916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  958.985938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  958.985960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  958.985983] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  958.986003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  958.986054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  958.986086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  958.986111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  958.986137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  958.986159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  958.986184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  958.986190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.986213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  958.986218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  958.986271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  958.986313] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  958.986357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  958.986401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  958.986451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  958.986495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  958.986541] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  958.986584] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  958.986626] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  958.986673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  958.986719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  958.986863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  958.986917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  958.987006] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.003963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.003982] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.004003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.004063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.004089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.004116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.004139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.004165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.004193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.004220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.004246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.004268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.004291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.004332] [drm:intel_power_well_disable [i915]] disabling display
>[  959.004367] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.004392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.004418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.004445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.004470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.004750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.004768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.004786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.004805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.004821] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.004837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.004854] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.004870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.004885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.004900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.004914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.004918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.004932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.004935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.004950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.004964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.004978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.004991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.005037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.005059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.005083] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.005107] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.005129] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.005161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.005185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.005249] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.005271] [drm:intel_power_well_enable [i915]] enabling display
>[  959.005294] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.005330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.005351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.005373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.005392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.005413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.005433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.005456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.005479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.005502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.005521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.005542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.005564] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.005586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.008659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.008679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.008699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.008719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.012408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.012426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.012442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.015039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.015060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.017955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.020881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.020913] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.020929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.020951] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.021044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.021079] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.021131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.071077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.071099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.071121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.071144] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.071164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.071185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.071206] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.071226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.071246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.071267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.071287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.071291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.071311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.071314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.071335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.071356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.071376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.071396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.071416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.071436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.071457] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.071478] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.071498] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.071519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.071541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.071599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.071623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.071660] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.088522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.088541] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.088561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.088578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.088595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.088609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.088624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.088640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.088657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.088673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.088689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.088703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.088717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.088744] [drm:intel_power_well_disable [i915]] disabling display
>[  959.088765] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.088781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.088797] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.088814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.088828] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.089452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.089469] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.089486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.089506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.089524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.089542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.089559] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.089577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.089594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.089611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.089629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.089632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.089649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.089653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.089671] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.089688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.089705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.089722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.089739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.089756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.089775] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.089792] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.089810] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.089828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.089847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.089890] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.089904] [drm:intel_power_well_enable [i915]] enabling display
>[  959.089917] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.089945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.089963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.089980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.089998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.090048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.090074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.090101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.090128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.090154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.090174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.090197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.090223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.090245] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.093316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.093334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.093349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.093366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.097058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.097077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.097093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.099672] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.099692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.102611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.105547] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.105619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.105635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.105656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.105709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.105730] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.105761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.155825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.155845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.155865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.155887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.155904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.155921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.155942] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.155962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.155983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.156003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.156059] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.156068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.156093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.156100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.156126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.156152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.156178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.156204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.156231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.156256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.156282] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.156306] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.156328] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.156354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.156382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.156466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.156497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.156547] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.173417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.173436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.173456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.173473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.173488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.173503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.173517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.173533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.173550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.173566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.173582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.173596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.173614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.173642] [drm:intel_power_well_disable [i915]] disabling display
>[  959.173665] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.173685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.173705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.173726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.173741] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.174072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.174098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.174128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.174158] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.174188] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.174213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.174236] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.174259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.174280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.174303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.174322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.174329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.174349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.174355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.174377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.174398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.174419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.174438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.174461] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.174481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.174504] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.174523] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.174543] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.174565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.174589] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.174654] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.174676] [drm:intel_power_well_enable [i915]] enabling display
>[  959.174697] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.174734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.174756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.174776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.174796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.174816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.174837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.174861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.174884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.174907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.174926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.174947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.174970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.174992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.178094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.178112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.178126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.178142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.181789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.181806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.181821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.184400] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.184417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.187287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.190238] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.190297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.190314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.190336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.190415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.190450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.190504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.240463] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.240483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.240503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.240524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.240541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.240559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.240577] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.240594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.240611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.240627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.240642] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.240646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.240662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.240665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.240681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.240696] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.240710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.240725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.240745] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.240765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.240786] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.240807] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.240827] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.240848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.240870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.240928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.240952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.240998] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.257839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.257858] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.257879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.257896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.257911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.257926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.257941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.257960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.257981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.258001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.258022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.258081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.258106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.258151] [drm:intel_power_well_disable [i915]] disabling display
>[  959.258329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.258357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.258384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.258411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.258435] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.258701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.258718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.258736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.258756] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.258771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.258788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.258807] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.258826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.258846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.258865] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.258884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.258888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.258907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.258911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.258930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.258950] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.258968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.258987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.259006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.259055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.259089] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.259111] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.259134] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.259160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.259185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.259459] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.259481] [drm:intel_power_well_enable [i915]] enabling display
>[  959.259503] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.259541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.259563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.259585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.259605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.259625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.259646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.259670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.259693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.259716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.259735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.259756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.259779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.259801] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.262885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.262904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.262920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.262936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.266647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.266666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.266682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.269257] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.269276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.272165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.275118] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.275175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.275193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.275215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.275294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.275329] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.275379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.325346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.325367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.325388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.325411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.325431] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.325452] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.325473] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.325493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.325514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.325534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.325554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.325558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.325577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.325581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.325602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.325622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.325642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.325662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.325682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.325702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.325723] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.325743] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.325763] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.325785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.325807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.325864] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.325888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.325934] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.342761] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.342779] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.342800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.342817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.342833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.342848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.342862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.342878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.342895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.342911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.342927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.342941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.342955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.342981] [drm:intel_power_well_disable [i915]] disabling display
>[  959.343003] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.343018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.343075] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.343102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.343128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.343457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.343475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.343493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.343512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.343528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.343544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.343561] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.343577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.343592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.343606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.343620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.343624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.343638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.343641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.343660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.343680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.343699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.343718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.343738] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.343756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.343776] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.343796] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.343815] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.343835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.343855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.343902] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.343917] [drm:intel_power_well_enable [i915]] enabling display
>[  959.343932] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.343962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.343981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.344001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.344020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.344065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.344101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.344128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.344154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.344179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.344200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.344222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.344248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.344270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.347357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.347376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.347392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.347408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.351088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.351106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.351121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.353678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.353695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.356573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.359496] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.359530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.359546] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.359568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.359647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.359682] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.359730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.409697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.409717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.409737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.409758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.409775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.409793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.409811] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.409828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.409845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.409861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.409875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.409879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.409895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.409898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.409913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.409928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.409943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.409958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.409975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.409991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.410007] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.410021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.410070] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.410096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.410121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.410203] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.410227] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.410270] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.427089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.427107] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.427128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.427145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.427161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.427176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.427190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.427209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.427230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.427251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.427271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.427290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.427306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.427334] [drm:intel_power_well_disable [i915]] disabling display
>[  959.427357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.427377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.427397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.427418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.427433] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.427681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.427701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.427721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.427742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.427761] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.427781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.427800] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.427819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.427838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.427857] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.427876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.427880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.427898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.427902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.427921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.427940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.427959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.427978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.427997] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.428016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.428081] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.428113] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.428134] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.428158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.428182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.428247] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.428438] [drm:intel_power_well_enable [i915]] enabling display
>[  959.428451] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.428478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.428493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.428508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.428522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.428540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.428557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.428577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.428596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.428615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.428632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.428650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.428669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.428687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.431755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.431774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.431792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.431812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.435493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.435511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.435527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.438112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.438132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.441012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.443984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.444022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.444084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.444165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.444245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.444280] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.444329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.494179] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.494199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.494219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.494240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.494257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.494275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.494293] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.494310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.494327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.494343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.494358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.494362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.494377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.494381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.494399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.494420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.494440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.494460] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.494481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.494501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.494522] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.494542] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.494563] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.494583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.494605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.494662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.494686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.494732] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.511553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.511572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.511592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.511609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.511625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.511640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.511655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.511670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.511688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.511704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.511720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.511734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.511748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.511774] [drm:intel_power_well_disable [i915]] disabling display
>[  959.511796] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.511812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.511828] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.511844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.511859] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.512167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.512183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.512200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.512218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.512233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.512248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.512264] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.512279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.512293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.512307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.512320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.512323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.512336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.512339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.512352] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.512365] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.512379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.512391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.512406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.512419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.512433] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.512446] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.512459] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.512476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.512496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.512538] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.512552] [drm:intel_power_well_enable [i915]] enabling display
>[  959.512566] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.512594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.512612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.512629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.512647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.512665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.512683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.512703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.512722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.512742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.512759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.512777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.512797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.512815] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.515884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.515903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.515919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.515935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.518512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.518530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.518545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.521116] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.521134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.524004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.526941] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.527014] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.527031] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.527099] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.527269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.527298] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.527329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.577193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.577215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.577237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.577261] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.577281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.577302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.577323] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.577343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.577364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.577384] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.577404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.577409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.577428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.577432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.577453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.577472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.577493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.577513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.577533] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.577553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.577575] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.577595] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.577615] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.577637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.577659] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.577725] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.577752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.577793] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.594613] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.594634] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.594656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.594676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.594696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.594715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.594734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.594754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.594775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.594795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.594816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.594834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.594851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.594879] [drm:intel_power_well_disable [i915]] disabling display
>[  959.594902] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.594922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.594942] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.594963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.594978] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.595376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.595404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.595433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.595463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.595481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.595499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.595518] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.595538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.595559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.595579] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.595597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.595603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.595621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.595626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.595646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.595665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.595684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.595703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.595723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.595742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.595762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.595782] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.595802] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.595822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.595843] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.595894] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.595907] [drm:intel_power_well_enable [i915]] enabling display
>[  959.595920] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.595947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.595966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.595984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.596001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.596019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.596042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.596173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.596199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.596224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.596246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.596269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.596294] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.596319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.599372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.599389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.599405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.599421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.603107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.603124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.603139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.605702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.605720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.608591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.611529] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.611601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.611618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.611644] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.611708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.611732] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.611769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.661749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.661769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.661789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.661812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.661832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.661853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.661874] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.661894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.661915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.661935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.661955] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.661960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.661980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.661984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.662004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.662025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.662045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.662098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.662125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.662149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.662174] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.662197] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.662219] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.662245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.662271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.662352] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.662385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.662547] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.680814] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.680834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.680857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.680876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.680896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.680915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.680935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.680954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.680975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.680995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.681016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.681034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.681098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.681274] [drm:intel_power_well_disable [i915]] disabling display
>[  959.681296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.681316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.681336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.681353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.681369] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.681666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.681685] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.681703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.681725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.681744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.681764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.681783] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.681802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.681821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.681840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.681859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.681863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.681882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.681885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.681905] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.681924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.681943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.681961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.681980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.682006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.682024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.682045] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.682516] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.682543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.682569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.682635] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.682657] [drm:intel_power_well_enable [i915]] enabling display
>[  959.682679] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.682717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.682740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.682763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.682785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.682807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.682830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.682855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.682879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.682902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.682924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.682945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.682970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.682993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.686087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.686106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.686122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.686138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.688710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.688727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.688742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.691303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.691320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.694190] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.697127] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.697199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.697215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.697237] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.697296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.697321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.697357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.747378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.747399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.747419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.747441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.747458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.747477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.747494] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.747512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.747528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.747544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.747559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.747563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.747578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.747581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.747596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.747611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.747631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.747651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.747672] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.747692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.747713] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.747734] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.747754] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.747775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.747798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.747860] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.747887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.747927] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.764732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.764752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.764772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.764789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.764805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.764820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.764835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.764851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.764869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.764885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.764901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.764919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.764937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.764966] [drm:intel_power_well_disable [i915]] disabling display
>[  959.764989] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.765009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.765030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.765051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.765109] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.765431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.765450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.765469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.765489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.765505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.765522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.765539] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.765556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.765572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.765588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.765602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.765607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.765621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.765624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.765639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.765654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.765668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.765682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.765701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.765721] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.765741] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.765761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.765780] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.765801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.765822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.765874] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.765888] [drm:intel_power_well_enable [i915]] enabling display
>[  959.765900] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.765927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.765943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.765958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.765972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.765989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.766007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.766025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.766047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.766092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.766114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.766135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.766159] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.766181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.769263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.769282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.769301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.769321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.773003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.773023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.773045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.775711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.775730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.778601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.781539] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.781612] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.781631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.781657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.781719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.781743] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.781779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.831771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.831792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.831812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.831833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.831849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.831867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.831885] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.831905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.831926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.831946] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.831965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.831970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.831990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.831993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.832014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.832034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.832054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.832109] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.832136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.832160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.832185] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.832208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.832229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.832255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.832281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.832362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.832389] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.832432] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.849264] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.849285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.849307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.849327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.849346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.849366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.849385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.849404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.849425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.849446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.849466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.849485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.849501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.849529] [drm:intel_power_well_disable [i915]] disabling display
>[  959.849552] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.849572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.849592] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.849613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.849628] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.849872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.849888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.849905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.849924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.849942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.849959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.849977] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.849995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.850013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.850030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.850047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.850088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.850111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.850117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.850140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.850161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.850182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.850202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.850224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.850244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.850266] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.850286] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.850305] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.850328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.850352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.850417] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.850440] [drm:intel_power_well_enable [i915]] enabling display
>[  959.850462] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.850490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.850505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.850519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.850533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.850546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.850560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.850576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.850590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.850604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.850617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.850630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.850646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.850661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.853716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.853733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.853747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.853761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.857478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.857497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.857513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.860103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.860122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.863014] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.865950] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.866023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.866040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.866108] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.866193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.866225] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.866270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.916194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.916215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.916235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.916259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.916279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.916300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.916321] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.916341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.916362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.916382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.916402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.916406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.916426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.916430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.916450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.916471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.916491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.916511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.916531] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.916551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.916572] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.916593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.916613] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.916634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.916655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.916712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  959.916737] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  959.916783] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  959.933618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  959.933636] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  959.933656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.933676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.933696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.933715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.933734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.933753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.933774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.933795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.933815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.933834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.933850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.933878] [drm:intel_power_well_disable [i915]] disabling display
>[  959.933900] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  959.933920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.933940] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.933961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.933976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  959.934505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  959.934524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  959.934543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  959.934563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  959.934579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  959.934595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  959.934613] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  959.934629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  959.934644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  959.934659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  959.934673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  959.934677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.934691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  959.934694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  959.934709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  959.934723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  959.934736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  959.934749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  959.934766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  959.934779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  959.934794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  959.934808] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  959.934821] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  959.934844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  959.934860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  959.934900] [drm:intel_power_well_enable [i915]] enabling always-on
>[  959.934913] [drm:intel_power_well_enable [i915]] enabling display
>[  959.934925] [drm:hsw_set_power_well [i915]] Enabling power well
>[  959.934950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  959.934963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  959.934977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  959.934990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  959.935003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  959.935016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  959.935031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  959.935045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  959.935092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  959.935114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  959.935136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  959.935160] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  959.935183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  959.938267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  959.938286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  959.938302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.938318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  959.942012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  959.942029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  959.942044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  959.944660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  959.944679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  959.947592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  959.950530] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  959.950603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  959.950620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  959.950642] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  959.950721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  959.950756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  959.950805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.000766] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.000786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.000807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.000828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.000844] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.000863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.000881] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.000898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.000918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.000939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.000959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.000963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.000983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.000987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.001007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.001028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.001048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.001068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.001119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.001150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.001175] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.001201] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.001224] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.001252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.001280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.001361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.001390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.001440] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.018290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.018309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.018329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.018346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.018361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.018376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.018391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.018407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.018423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.018439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.018455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.018469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.018483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.018510] [drm:intel_power_well_disable [i915]] disabling display
>[  960.018531] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.018546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.018563] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.018579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.018593] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.018830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.018849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.018867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.018887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.018904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.018922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.018940] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.018957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.018975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.018992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.019009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.019013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.019030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.019034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.019051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.019106] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.019130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.019154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.019177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.019201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.019223] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.019245] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.019265] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.019290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.019316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.019382] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.019404] [drm:intel_power_well_enable [i915]] enabling display
>[  960.019426] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.019462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.019483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.019504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.019524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.019544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.019565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.019588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.019611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.019634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.019653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.019673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.019696] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.019718] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.022789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.022806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.022821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.022839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.026578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.026596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.026613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.029220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.029239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.032218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.035167] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.035228] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.035245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.035274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.035327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.035347] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.035377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.085391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.085411] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.085431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.085453] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.085470] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.085488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.085506] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.085523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.085539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.085555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.085570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.085574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.085593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.085597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.085618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.085638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.085658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.085679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.085699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.085719] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.085740] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.085761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.085781] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.085802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.085824] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.085882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.085907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.085944] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.102753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.102772] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.102793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.102809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.102825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.102840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.102854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.102870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.102888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.102904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.102919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.102934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.102948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.102974] [drm:intel_power_well_disable [i915]] disabling display
>[  960.102996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.103011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.103028] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.103044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.103058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.103402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.103420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.103440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.103459] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.103475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.103492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.103509] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.103525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.103540] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.103555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.103569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.103573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.103587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.103591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.103606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.103620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.103634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.103648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.103665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.103679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.103695] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.103709] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.103723] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.103739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.103757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.103801] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.103816] [drm:intel_power_well_enable [i915]] enabling display
>[  960.103830] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.103857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.103876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.103896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.103916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.103936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.103955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.103977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.104005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.104024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.104041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.104060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.104109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.104133] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.107212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.107231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.107247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.107263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.110939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.110956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.110972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.113548] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.113567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.116443] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.119394] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.119451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.119467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.119488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.119544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.119564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.119595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.169619] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.169640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.169660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.169684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.169704] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.169725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.169746] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.169766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.169787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.169807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.169827] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.169831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.169851] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.169854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.169875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.169896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.169916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.169936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.169957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.169976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.169997] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.170018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.170038] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.170059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.170113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.170196] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.170229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.170408] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.186771] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.186790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.186810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.186827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.186843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.186858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.186873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.186889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.186906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.186922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.186938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.186952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.186966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.186993] [drm:intel_power_well_disable [i915]] disabling display
>[  960.187015] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.187034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.187055] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.187076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.187138] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.187532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.187559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.187587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.187617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.187642] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.187668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.187695] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.187720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.187745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.187769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.187792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.187798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.187821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.187827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.187850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.187873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.187896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.187919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.187943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.187966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.187990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.188013] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.188042] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.188065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.188114] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.188180] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.188202] [drm:intel_power_well_enable [i915]] enabling display
>[  960.188225] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.188263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.188286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.188310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.188331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.188353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.188375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.188399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.188423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.188446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.188468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.188488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.188513] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.188536] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.191640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.191659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.191675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.191692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.195403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.195422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.195438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.198015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.198033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.200911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.203849] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.203921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.203938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.203960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.204018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.204040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.204073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.254067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.254101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.254123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.254146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.254166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.254187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.254208] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.254228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.254248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.254269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.254288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.254293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.254312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.254316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.254337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.254356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.254376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.254396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.254417] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.254436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.254458] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.254478] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.254498] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.254519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.254541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.254599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.254623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.254660] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.271512] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.271531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.271551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.271568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.271584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.271600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.271615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.271631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.271648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.271664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.271680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.271694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.271709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.271736] [drm:intel_power_well_disable [i915]] disabling display
>[  960.271757] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.271773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.271789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.271805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.271819] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.272044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.272061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.272079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.272140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.272162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.272187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.272213] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.272237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.272260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.272283] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.272305] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.272312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.272333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.272339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.272361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.272383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.272406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.272427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.272452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.272473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.272497] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.272519] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.272541] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.272565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.272590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.272653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.272676] [drm:intel_power_well_enable [i915]] enabling display
>[  960.272698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.272736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.272759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.272779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.272801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.272823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.272846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.272870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.272894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.272917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.272938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.272958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.272982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.273005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.276076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.276106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.276123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.276141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.278724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.278743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.278758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.281349] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.281367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.284239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.287177] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.287249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.287265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.287287] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.287345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.287367] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.287414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.337416] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.337437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.337461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.337490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.337506] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.337524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.337541] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.337556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.337572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.337586] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.337600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.337605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.337618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.337622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.337636] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.337650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.337663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.337677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.337693] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.337707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.337722] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.337736] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.337749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.337765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.337783] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.337836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.337856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.337887] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.354714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.354741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.354770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.354795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.354818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.354841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.354863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.354887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.354913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.354938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.354962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.354984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.355005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.355046] [drm:intel_power_well_disable [i915]] disabling display
>[  960.355088] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.355393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.355411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.355428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.355443] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.355729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.355746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.355764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.355783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.355798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.355815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.355831] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.355846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.355860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.355874] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.355887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.355891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.355905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.355908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.355922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.355935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.355949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.355962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.355978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.355991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.356005] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.356018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.356031] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.356047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.356064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.356542] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.356556] [drm:intel_power_well_enable [i915]] enabling display
>[  960.356569] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.356595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.356610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.356625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.356638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.356652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.356666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.356682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.356696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.356711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.356724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.356736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.356753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.356767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.359845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.359865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.359884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.359904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.363566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.363584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.363599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.366184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.366204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.369129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.372066] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.372183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.372212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.372249] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.372323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.372345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.372379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.422327] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.422348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.422370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.422393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.422414] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.422434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.422455] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.422475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.422496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.422516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.422536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.422540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.422560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.422564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.422584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.422604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.422625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.422645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.422665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.422685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.422706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.422726] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.422746] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.422767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.422789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.422848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.422873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.422911] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.439349] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.439367] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.439388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.439405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.439420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.439436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.439450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.439466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.439483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.439499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.439515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.439529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.439543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.439570] [drm:intel_power_well_disable [i915]] disabling display
>[  960.439591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.439607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.439624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.439639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.439654] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.439867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.439884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.439902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.439921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.439937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.439954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.439970] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.439986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.440001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.440015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.440029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.440033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.440054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.440057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.440070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.440083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.440134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.440154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.440175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.440195] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.440216] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.440236] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.440255] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.440278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.440301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.440353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.440375] [drm:intel_power_well_enable [i915]] enabling display
>[  960.440395] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.440434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.440457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.440479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.440500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.440521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.440544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.440568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.440592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.440616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.440637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.440658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.440682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.440699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.443775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.443794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.443812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.443832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.447543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.447562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.447578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.450168] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.450187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.453059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.455996] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.456069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.456086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.456150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.456369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.456391] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.456422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.506239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.506259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.506280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.506301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.506321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.506342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.506363] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.506383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.506404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.506424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.506444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.506448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.506468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.506472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.506492] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.506512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.506533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.506553] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.506574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.506593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.506615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.506635] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.506656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.506677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.506699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.506758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.506782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.506820] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.523672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.523691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.523712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.523732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.523752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.523771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.523790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.523809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.523830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.523851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.523871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.523890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.523909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.523936] [drm:intel_power_well_disable [i915]] disabling display
>[  960.523958] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.523978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.523999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.524020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.524035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.524380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.524406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.524433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.524462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.524485] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.524511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.524536] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.524560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.524583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.524606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.524627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.524634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.524655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.524661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.524684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.524706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.524728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.524749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.524774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.524795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.524818] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.524839] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.524862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.524885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.524912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.524988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.525009] [drm:intel_power_well_enable [i915]] enabling display
>[  960.525031] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.525068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.525088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.525128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.525148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.525172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.525193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.525218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.525243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.525267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.525288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.525310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.525334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  960.525357] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.528439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.528458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.528477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.528497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.532214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.532233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.532249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.534817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.534836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.537708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.540646] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  960.540718] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.540735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  960.540757] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.540816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.540838] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.540870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.590883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.590905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.590926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.590949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.590969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.590990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.591011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  960.591031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  960.591052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.591072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.591091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.591121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.591150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.591158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.591186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.591209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.591234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.591257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  960.591284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.591306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.591332] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  960.591354] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  960.591378] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  960.591405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.591432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  960.591512] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  960.591543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  960.591591] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  960.608442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  960.608461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  960.608481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.608498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.608514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.608529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.608543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.608559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.608576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.608592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.608608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.608626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.608644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.608671] [drm:intel_power_well_disable [i915]] disabling display
>[  960.608694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  960.608714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.608735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.608755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.608770] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.608874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.608906] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.608926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.608942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.608958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.608972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.608986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.609002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.609018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.609034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.609050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.609065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.609083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.609102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.609166] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  960.609192] [drm:intel_power_well_disable [i915]] disabling always-on
>[  960.611759] [IGT] kms_flip: exiting, ret=0
>[  960.631600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  960.631620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  960.631639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  960.631660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  960.631676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  960.631694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  960.631712] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  960.631728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  960.631744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  960.631760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  960.631778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  960.631784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.631803] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  960.631806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.631826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  960.631846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  960.631865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  960.631885] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  960.631905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  960.631924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  960.631944] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  960.631964] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  960.631983] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  960.632004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  960.632026] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  960.632092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  960.632124] [drm:intel_power_well_enable [i915]] enabling display
>[  960.632140] [drm:hsw_set_power_well [i915]] Enabling power well
>[  960.632173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  960.632194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  960.632214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  960.632234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  960.632254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  960.632281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  960.632302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  960.632319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  960.632335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.632350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  960.632363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  960.632380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  960.632396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  960.634381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  960.634395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  960.634409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.634423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  960.638082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  960.638106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  960.638134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  960.640711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  960.640728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  960.643624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  960.646641] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  960.646682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  960.646698] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  960.646720] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  960.646765] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  960.646783] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  960.663433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  960.663457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  960.663494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  960.663619] Console: switching to colour frame buffer device 240x75
>[  960.796883] Console: switching to colour dummy device 80x25
>[  960.796977] [IGT] kms_flip: executing
>[  960.806645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  960.806674] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  960.808172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  960.808192] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  960.810177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  960.810183] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  960.812171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  960.812192] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  960.814171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  960.814177] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  960.814181] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  960.814197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  960.814220] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  960.815256] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  960.816155] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  960.816179] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  960.816202] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  960.816222] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  960.817209] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  960.817224] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  960.818350] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  960.818353] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  960.818431] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  960.818433] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  960.818437] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  960.818439] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  960.818443] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  960.818445] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  960.818452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  960.818455] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  960.818458] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  960.818460] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  960.818463] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  960.818465] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  960.818468] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  960.818470] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  960.818473] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  960.818475] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  960.818477] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  960.818480] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  960.818482] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  960.818485] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  960.818487] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  960.818489] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  960.818492] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  960.818494] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  960.818497] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  960.818499] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  960.818502] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  960.818504] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  960.818507] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  960.818509] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  960.818511] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  960.818514] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  960.818516] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  960.818519] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  960.818521] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  960.818523] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  960.818526] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  960.818555] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  960.818573] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  960.820160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  960.820177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  960.822183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  960.822190] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  960.824175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  960.824196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  960.826180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  960.826186] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  960.826190] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  960.827419] [IGT] kms_flip: starting subtest 2x-wf_vblank-interruptible
>[  960.828760] [IGT] kms_flip: exiting, ret=77
>[  960.863704] Console: switching to colour frame buffer device 240x75
>[  960.995003] Console: switching to colour dummy device 80x25
>[  960.995094] [IGT] kms_flip: executing
>[  961.008698] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  961.008727] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  961.010202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  961.010222] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  961.012182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  961.012188] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  961.014182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  961.014203] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  961.016188] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  961.016194] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  961.016199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  961.016214] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  961.016238] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  961.017272] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  961.018170] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  961.018194] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  961.018216] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  961.018236] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  961.019230] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  961.019254] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  961.020306] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  961.020309] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  961.020388] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  961.020390] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  961.020394] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  961.020396] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  961.020400] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  961.020402] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  961.020410] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  961.020412] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  961.020415] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.020417] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.020420] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  961.020422] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  961.020425] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  961.020427] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  961.020430] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.020432] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.020434] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  961.020437] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  961.020439] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  961.020442] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  961.020444] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  961.020446] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  961.020449] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  961.020451] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  961.020454] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  961.020456] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  961.020459] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  961.020461] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  961.020463] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  961.020466] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  961.020468] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  961.020471] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  961.020473] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  961.020476] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  961.020478] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  961.020480] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  961.020483] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  961.020513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  961.020530] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  961.022189] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  961.022210] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  961.024183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  961.024189] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  961.026191] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  961.026211] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  961.028183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  961.028189] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  961.028193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  961.029432] [IGT] kms_flip: starting subtest 2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
>[  961.030751] [IGT] kms_flip: exiting, ret=77
>[  961.063911] Console: switching to colour frame buffer device 240x75
>[  961.190967] Console: switching to colour dummy device 80x25
>[  961.191064] [IGT] kms_flip: executing
>[  961.200716] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  961.200746] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  961.202196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  961.202216] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  961.204201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  961.204207] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  961.206194] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  961.206214] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  961.208196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  961.208202] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  961.208206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  961.208223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  961.208247] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  961.209279] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  961.210196] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  961.210223] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  961.210243] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  961.210257] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  961.211250] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  961.211266] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  961.212319] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  961.212322] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  961.212403] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  961.212405] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  961.212409] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  961.212411] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  961.212415] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  961.212417] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  961.212425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  961.212427] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  961.212430] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.212432] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.212435] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  961.212437] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  961.212440] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  961.212442] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  961.212445] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.212447] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  961.212450] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  961.212452] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  961.212454] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  961.212457] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  961.212459] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  961.212462] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  961.212464] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  961.212467] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  961.212469] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  961.212471] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  961.212474] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  961.212476] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  961.212479] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  961.212481] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  961.212483] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  961.212486] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  961.212488] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  961.212491] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  961.212493] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  961.212496] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  961.212498] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  961.212528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  961.212546] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  961.214197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  961.214217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  961.216193] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  961.216199] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  961.218198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  961.218218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  961.220293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  961.220299] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  961.220303] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  961.221533] [IGT] kms_flip: starting subtest blocking-absolute-wf_vblank-interruptible
>[  961.222031] [drm:drm_mode_addfb2] [FB:75]
>[  961.222053] [drm:drm_mode_addfb2] [FB:79]
>[  961.264713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  961.264766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  961.280642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  961.280666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  961.280705] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  961.298913] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  961.298940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  961.298956] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  961.298976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  961.298993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  961.299011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  961.299027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  961.299041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  961.299057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  961.299075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  961.299091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  961.299111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  961.299132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  961.299192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  961.299215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  961.299260] [drm:intel_power_well_disable [i915]] disabling display
>[  961.299296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  961.299331] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  961.299361] [drm:intel_power_well_disable [i915]] disabling always-on
>[  961.299412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  961.299476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  961.299531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  961.299541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  961.299583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  961.299600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  961.299619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  961.299639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  961.299654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  961.299672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  961.299689] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  961.299706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  961.299721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  961.299736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  961.299750] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  961.299755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  961.299768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  961.299772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  961.299787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  961.299801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  961.299815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  961.299839] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  961.299854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  961.299867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  961.299880] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  961.299892] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  961.299905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  961.299920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  961.299937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  961.302456] [drm:intel_power_well_enable [i915]] enabling always-on
>[  961.302471] [drm:intel_power_well_enable [i915]] enabling display
>[  961.302484] [drm:hsw_set_power_well [i915]] Enabling power well
>[  961.302510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  961.302528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  961.302546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  961.302565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  961.302589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  961.302611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  961.302635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  961.302651] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  961.302665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  961.302678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  961.302691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  961.302707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  961.302724] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  961.305800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  961.305818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  961.305836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  961.305855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  961.309539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  961.309557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  961.309572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  961.312175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  961.312193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  961.315089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  961.318030] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  961.318099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  961.318116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  961.318138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  961.318236] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  961.318260] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  961.334840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  961.334864] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  961.334899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  971.360523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  971.377143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  971.377168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  971.377217] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  971.396076] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  971.396100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  971.396116] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  971.396136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  971.396153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  971.396171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  971.396186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  971.396201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  971.396217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  971.396236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  971.396252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  971.396272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  971.396293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  971.396312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  971.396331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  971.396361] [drm:intel_power_well_disable [i915]] disabling display
>[  971.396384] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  971.396410] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  971.396436] [drm:intel_power_well_disable [i915]] disabling always-on
>[  971.396642] [drm:drm_mode_addfb2] [FB:75]
>[  971.396672] [drm:drm_mode_addfb2] [FB:78]
>[  971.419730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  971.419876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  971.419935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  971.419989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  971.419999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  971.420046] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  971.420063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  971.420080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  971.420098] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  971.420113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  971.420128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  971.420144] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  971.420158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  971.420172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  971.420189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  971.420207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  971.420210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  971.420228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  971.420231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  971.420249] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  971.420266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  971.420284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  971.420301] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  971.420319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  971.420336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  971.420354] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  971.420372] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  971.420389] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  971.420407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  971.420427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  971.422929] [drm:intel_power_well_enable [i915]] enabling always-on
>[  971.422943] [drm:intel_power_well_enable [i915]] enabling display
>[  971.422957] [drm:hsw_set_power_well [i915]] Enabling power well
>[  971.422985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  971.423003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  971.423021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  971.423039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  971.423057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  971.423074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  971.423093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  971.423112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  971.423131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  971.423148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  971.423163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  971.423182] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  971.423199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  971.425179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  971.425195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  971.425209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  971.425224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  971.426734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  971.426749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  971.426800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  971.428303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  971.428319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  971.430148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  971.433098] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  971.433159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  971.433182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  971.433203] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  971.449901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  971.449928] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  971.449965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  981.475581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  981.475632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  981.475658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  981.475700] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  981.493897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  981.493918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  981.493942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  981.493962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  981.493984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  981.494003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  981.494023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  981.494042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  981.494064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  981.494084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  981.494105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  981.494125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  981.494144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  981.494163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  981.494192] [drm:intel_power_well_disable [i915]] disabling display
>[  981.494216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  981.494242] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  981.494258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  981.494510] [drm:drm_mode_addfb2] [FB:75]
>[  981.494544] [drm:drm_mode_addfb2] [FB:78]
>[  981.520172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  981.520253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  981.520302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  981.520383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  981.520399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  981.520474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  981.520499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  981.520526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  981.520554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  981.520576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  981.520600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  981.520625] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  981.520648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  981.520671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  981.520693] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  981.520715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  981.520721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  981.520741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  981.520747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  981.520769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  981.520790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  981.520811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  981.520832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  981.520857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  981.520878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  981.520898] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  981.520919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  981.520938] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  981.520961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  981.520987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  981.523624] [drm:intel_power_well_enable [i915]] enabling always-on
>[  981.523641] [drm:intel_power_well_enable [i915]] enabling display
>[  981.523655] [drm:hsw_set_power_well [i915]] Enabling power well
>[  981.523685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  981.523703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  981.523719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  981.523737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  981.523756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  981.523775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  981.523796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  981.523816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  981.523836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  981.523862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  981.523880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  981.523901] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  981.523918] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  981.527075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  981.527095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  981.527114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  981.527134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  981.530831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  981.530850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  981.530866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  981.533444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  981.533464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  981.536340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  981.539308] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  981.539349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  981.539405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  981.539443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  981.556085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  981.556113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  981.556151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  991.581771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  991.581823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  991.581850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  991.581893] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  991.600758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  991.600777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  991.600803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  991.600829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  991.600848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  991.600864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  991.600879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  991.600896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  991.600914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  991.600931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  991.600947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  991.600963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  991.601022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  991.601045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  991.601091] [drm:intel_power_well_disable [i915]] disabling display
>[  991.601125] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  991.601158] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  991.601183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  991.602584] [IGT] kms_flip: exiting, ret=0
>[  991.623457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  991.623476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  991.623496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  991.623517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  991.623533] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  991.623550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  991.623568] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  991.623584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  991.623601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  991.623616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  991.623631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  991.623635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  991.623649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  991.623652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  991.623667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  991.623681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  991.623695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  991.623709] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  991.623726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  991.623741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  991.623755] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  991.623774] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  991.623794] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  991.623815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  991.623838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  991.623902] [drm:intel_power_well_enable [i915]] enabling always-on
>[  991.623920] [drm:intel_power_well_enable [i915]] enabling display
>[  991.623936] [drm:hsw_set_power_well [i915]] Enabling power well
>[  991.623969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  991.624004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  991.624024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  991.624044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  991.624064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  991.624084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  991.624106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  991.624128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  991.624149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  991.624169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  991.624188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  991.624209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  991.624228] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  991.626225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  991.626241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  991.626255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  991.626269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  991.629948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  991.629966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  991.629993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  991.632573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  991.632592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  991.635497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  991.638512] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  991.638557] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  991.638573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  991.638596] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  991.638641] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  991.638657] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  991.655306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  991.655331] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  991.655368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  991.655495] Console: switching to colour frame buffer device 240x75
>[  991.792134] Console: switching to colour dummy device 80x25
>[  991.792227] [IGT] kms_flip: executing
>[  991.813221] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  991.813250] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  991.815321] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  991.815340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  991.817406] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  991.817412] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  991.819486] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  991.819506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  991.821580] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  991.821586] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  991.821591] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  991.821607] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  991.821631] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  991.822665] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  991.823563] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  991.823580] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  991.823595] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  991.823609] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  991.824600] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  991.824617] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  991.825671] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  991.825674] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  991.825759] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  991.825761] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  991.825765] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  991.825767] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  991.825771] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  991.825773] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  991.825780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  991.825783] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  991.825786] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  991.825788] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  991.825791] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  991.825793] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  991.825796] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  991.825798] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  991.825800] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  991.825803] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  991.825805] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  991.825808] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  991.825810] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  991.825813] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  991.825815] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  991.825817] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  991.825820] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  991.825822] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  991.825825] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  991.825827] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  991.825829] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  991.825832] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  991.825834] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  991.825837] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  991.825839] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  991.825842] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  991.825844] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  991.825846] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  991.825849] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  991.825851] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  991.825854] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  991.825884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  991.825902] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  991.827971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  991.828001] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  991.830037] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  991.830043] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  991.832036] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  991.832056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  991.834038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  991.834044] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  991.834049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  991.835364] [IGT] kms_flip: starting subtest 2x-flip-vs-modeset-interruptible
>[  991.836701] [IGT] kms_flip: exiting, ret=77
>[  991.872266] Console: switching to colour frame buffer device 240x75
>[  992.001682] Console: switching to colour dummy device 80x25
>[  992.001774] [IGT] kms_flip: executing
>[  992.015523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  992.015553] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  992.017634] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  992.017655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  992.019728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  992.019735] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  992.021810] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  992.021830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  992.023904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  992.023910] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  992.023914] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  992.023930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  992.023953] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  992.024981] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  992.025878] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  992.025897] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  992.025914] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  992.025931] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  992.026917] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  992.026934] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  992.027999] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  992.028002] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  992.028086] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  992.028088] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  992.028092] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  992.028094] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  992.028098] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  992.028100] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  992.028107] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  992.028110] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  992.028113] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.028115] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.028118] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  992.028120] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  992.028122] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  992.028125] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  992.028127] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.028130] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.028132] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  992.028135] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  992.028137] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  992.028140] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  992.028142] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  992.028144] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  992.028147] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  992.028149] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  992.028152] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  992.028154] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  992.028157] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  992.028159] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  992.028161] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  992.028164] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  992.028166] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  992.028169] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  992.028171] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  992.028173] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  992.028176] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  992.028178] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  992.028181] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  992.028210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  992.028228] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  992.030039] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  992.030058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  992.032050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  992.032055] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  992.034054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  992.034072] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  992.036055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  992.036061] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  992.036065] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  992.037324] [IGT] kms_flip: starting subtest 2x-flip-vs-panning-interruptible
>[  992.038683] [IGT] kms_flip: exiting, ret=77
>[  992.072437] Console: switching to colour frame buffer device 240x75
>[  992.204530] Console: switching to colour dummy device 80x25
>[  992.204622] [IGT] kms_flip: executing
>[  992.218537] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  992.218566] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  992.220647] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  992.220668] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  992.222743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  992.222749] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  992.224824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  992.224844] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  992.226918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  992.226924] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  992.226929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  992.226946] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  992.226969] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  992.228000] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  992.228895] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  992.228912] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  992.228926] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  992.228940] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  992.229926] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  992.229942] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  992.230991] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  992.231004] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  992.231087] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  992.231089] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  992.231093] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  992.231095] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  992.231099] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  992.231101] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  992.231108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  992.231111] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  992.231114] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.231116] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.231119] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  992.231121] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  992.231124] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  992.231126] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  992.231129] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.231131] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  992.231133] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  992.231136] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  992.231138] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  992.231141] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  992.231143] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  992.231145] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  992.231148] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  992.231150] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  992.231153] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  992.231155] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  992.231158] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  992.231160] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  992.231163] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  992.231165] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  992.231167] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  992.231170] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  992.231172] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  992.231175] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  992.231177] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  992.231179] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  992.231182] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  992.231213] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  992.231230] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  992.233055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  992.233074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  992.235061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  992.235067] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  992.237067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  992.237087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  992.239062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  992.239068] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  992.239072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  992.239287] [IGT] kms_flip: starting subtest flip-vs-blocking-wf-vblank
>[  992.239694] [drm:drm_mode_addfb2] [FB:77]
>[  992.239718] [drm:drm_mode_addfb2] [FB:79]
>[  992.282024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  992.282076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  992.289206] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  992.289236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  992.289280] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  992.308155] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  992.308179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  992.308199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  992.308221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  992.308241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  992.308263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  992.308283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  992.308302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  992.308321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  992.308343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  992.308364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  992.308384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  992.308404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  992.308424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  992.308440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  992.308469] [drm:intel_power_well_disable [i915]] disabling display
>[  992.308492] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  992.308519] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  992.308537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  992.308591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  992.308673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  992.308734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  992.308745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  992.308791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  992.308811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  992.308831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  992.308853] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  992.308872] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  992.308892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  992.308911] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  992.308930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  992.308949] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  992.308968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  992.308987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  992.308991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  992.309010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  992.309053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  992.309085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  992.309113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  992.309139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  992.309165] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  992.309192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  992.309218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  992.309243] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  992.309268] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  992.309292] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  992.309317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  992.309346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  992.311926] [drm:intel_power_well_enable [i915]] enabling always-on
>[  992.311943] [drm:intel_power_well_enable [i915]] enabling display
>[  992.311957] [drm:hsw_set_power_well [i915]] Enabling power well
>[  992.311986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  992.312003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  992.312062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  992.312085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  992.312108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  992.312131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  992.312157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  992.312180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  992.312196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  992.312209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  992.312223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  992.312239] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  992.312254] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  992.315338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  992.315356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  992.315371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  992.315386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  992.319091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  992.319110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  992.319125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  992.321690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  992.321708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  992.324601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  992.327535] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  992.327611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  992.327628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  992.327650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  992.327692] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  992.327709] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  992.344356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  992.344382] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  992.344416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1002.654049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1002.670328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1002.670375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1002.670444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1002.689321] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1002.689345] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1002.689362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1002.689382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1002.689399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1002.689417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1002.689433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1002.689448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1002.689464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1002.689482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1002.689499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1002.689519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1002.689540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1002.689559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1002.689578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1002.689608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1002.689631] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1002.689705] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1002.689736] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1002.689982] [drm:drm_mode_addfb2] [FB:77]
>[ 1002.690026] [drm:drm_mode_addfb2] [FB:78]
>[ 1002.715814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.715894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1002.715944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1002.715998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1002.716008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.716057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1002.716073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1002.716091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1002.716110] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1002.716124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1002.716140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1002.716155] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1002.716170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1002.716185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1002.716198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1002.716212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1002.716215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1002.716228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1002.716231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1002.716245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1002.716258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1002.716270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1002.716283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1002.716298] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1002.716311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1002.716324] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1002.716337] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1002.716349] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1002.716364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1002.716381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1002.718905] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1002.718921] [drm:intel_power_well_enable [i915]] enabling display
>[ 1002.718936] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1002.718966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1002.718983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1002.719000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1002.719018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1002.719037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1002.719056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1002.719076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1002.719096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1002.719116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1002.719135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1002.719150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1002.719170] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1002.719189] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1002.722280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1002.722299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1002.722315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1002.722331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1002.726055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1002.726073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1002.726088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1002.728675] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1002.728695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1002.731565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1002.734514] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1002.734575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1002.734592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1002.734615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1002.751319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1002.751345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1002.751379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1013.060732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1013.060810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1013.060850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1013.060916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1013.077729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1013.077749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1013.077769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1013.077789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1013.077811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1013.077831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1013.077850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1013.077870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1013.077891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1013.077913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1013.077933] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1013.077954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1013.077973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1013.077992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1013.078020] [drm:intel_power_well_disable [i915]] disabling display
>[ 1013.078043] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1013.078068] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1013.078085] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1013.078325] [drm:drm_mode_addfb2] [FB:77]
>[ 1013.078364] [drm:drm_mode_addfb2] [FB:78]
>[ 1013.101359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1013.101447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.101503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1013.101556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1013.101565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.101614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1013.101630] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1013.101648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1013.101667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1013.101685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1013.101703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1013.101721] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1013.101738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1013.101756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1013.101773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1013.101790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1013.101794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1013.101811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1013.101814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1013.101832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1013.101849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1013.101867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1013.101883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1013.101902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1013.101918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1013.101936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1013.101954] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1013.101971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1013.101990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1013.102009] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1013.104534] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1013.104552] [drm:intel_power_well_enable [i915]] enabling display
>[ 1013.104568] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1013.104599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1013.104618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1013.104637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1013.104656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1013.104675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1013.104693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1013.104714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1013.104734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1013.104754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1013.104772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1013.104788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1013.104808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1013.104827] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1013.106819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1013.106837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1013.106854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1013.106873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1013.109474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1013.109493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1013.109508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1013.112094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1013.112113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1013.114993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1013.117931] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1013.118001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1013.118017] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1013.118038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1013.134746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1013.134772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1013.134808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.444048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1023.444101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1023.444129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1023.444176] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1023.463034] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1023.463055] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1023.463078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1023.463098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1023.463120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1023.463139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1023.463159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1023.463178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1023.463199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1023.463220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1023.463241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1023.463261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.463280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1023.463299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1023.463328] [drm:intel_power_well_disable [i915]] disabling display
>[ 1023.463351] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1023.463376] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1023.463393] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1023.465934] [IGT] kms_flip: exiting, ret=0
>[ 1023.485389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1023.485409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1023.485429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1023.485449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1023.485466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1023.485483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1023.485501] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1023.485517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1023.485533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1023.485548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1023.485563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1023.485568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.485582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1023.485585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.485600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1023.485614] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1023.485629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1023.485643] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1023.485662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1023.485682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1023.485702] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1023.485721] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1023.485741] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1023.485762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1023.485784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1023.485840] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1023.485858] [drm:intel_power_well_enable [i915]] enabling display
>[ 1023.485874] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1023.485922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1023.485943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1023.485963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1023.485983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1023.486002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1023.486022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1023.486045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1023.486066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1023.486087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.486107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1023.486126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1023.486148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1023.486174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1023.489266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1023.489284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1023.489300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1023.489319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1023.493020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1023.493036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1023.493054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1023.495654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1023.495672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1023.498585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1023.501607] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1023.501643] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1023.501658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1023.501680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1023.501723] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1023.501737] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1023.518402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1023.518427] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1023.518467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.518600] Console: switching to colour frame buffer device 240x75
>[ 1023.650956] Console: switching to colour dummy device 80x25
>[ 1023.651053] [IGT] kms_flip: executing
>[ 1023.660469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1023.660499] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1023.661952] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1023.661972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1023.663957] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1023.663964] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1023.665942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1023.665960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1023.667953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1023.667959] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1023.667963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1023.667979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1023.668002] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1023.669036] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1023.669941] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1023.669959] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1023.669974] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1023.669989] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1023.670983] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1023.671005] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1023.672066] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1023.672070] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1023.672149] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1023.672151] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1023.672155] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1023.672157] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1023.672161] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1023.672163] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1023.672171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1023.672173] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.672176] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.672178] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.672181] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1023.672183] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1023.672186] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1023.672188] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1023.672191] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.672193] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.672196] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1023.672198] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1023.672201] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1023.672203] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1023.672205] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1023.672208] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1023.672210] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1023.672213] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1023.672215] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1023.672217] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1023.672220] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1023.672222] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1023.672225] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1023.672227] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1023.672230] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1023.672232] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1023.672234] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1023.672237] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1023.672239] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1023.672242] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1023.672244] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1023.672274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1023.672292] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1023.673949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1023.673968] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1023.675956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1023.675962] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1023.677952] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1023.677972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1023.679951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1023.679957] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1023.679961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1023.681227] [IGT] kms_flip: starting subtest 2x-dpms-vs-vblank-race-interruptible
>[ 1023.682554] [IGT] kms_flip: exiting, ret=77
>[ 1023.718677] Console: switching to colour frame buffer device 240x75
>[ 1023.846676] Console: switching to colour dummy device 80x25
>[ 1023.846769] [IGT] kms_flip: executing
>[ 1023.857432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1023.857461] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1023.858956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1023.858974] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1023.860958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1023.860963] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1023.862965] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1023.862985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1023.864965] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1023.864972] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1023.864975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1023.864992] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1023.865015] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1023.866057] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1023.866956] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1023.866974] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1023.866990] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1023.867008] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1023.868000] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1023.868025] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1023.869081] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1023.869084] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1023.869164] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1023.869167] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1023.869171] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1023.869173] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1023.869177] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1023.869179] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1023.869186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1023.869189] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.869191] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.869194] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.869196] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1023.869199] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1023.869201] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1023.869204] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1023.869206] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.869209] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1023.869211] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1023.869214] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1023.869216] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1023.869218] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1023.869221] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1023.869223] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1023.869226] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1023.869228] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1023.869231] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1023.869233] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1023.869235] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1023.869238] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1023.869240] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1023.869243] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1023.869245] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1023.869248] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1023.869250] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1023.869253] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1023.869255] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1023.869257] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1023.869260] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1023.869290] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1023.869308] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1023.870961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1023.870979] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1023.872965] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1023.872971] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1023.874967] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1023.874988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1023.876964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1023.876970] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1023.876974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1023.878219] [IGT] kms_flip: starting subtest flip-vs-panning-interruptible
>[ 1023.878717] [drm:drm_mode_addfb2] [FB:77]
>[ 1023.878739] [drm:drm_mode_addfb2] [FB:79]
>[ 1023.939115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1023.939170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1023.952109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1023.952135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1023.952184] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1023.971043] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1023.971066] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1023.971082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1023.971102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1023.971119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1023.971141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1023.971161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1023.971180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1023.971200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1023.971221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1023.971242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1023.971262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1023.971282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.971301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1023.971320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1023.971349] [drm:intel_power_well_disable [i915]] disabling display
>[ 1023.971371] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1023.971397] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1023.971415] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1023.971480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1023.971540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.971589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1023.971598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.971638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1023.971654] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1023.971672] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1023.971692] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1023.971709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1023.971727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1023.971745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1023.971763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1023.971780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1023.971798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1023.971815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1023.971818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.971835] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1023.971839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1023.971856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1023.971874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1023.971891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1023.971909] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1023.971966] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1023.971990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1023.972011] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1023.972033] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1023.972053] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1023.972077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1023.972101] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1023.977035] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1023.977050] [drm:intel_power_well_enable [i915]] enabling display
>[ 1023.977063] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1023.977090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1023.977106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1023.977121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1023.977135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1023.977148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1023.977162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1023.977178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1023.977193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1023.977208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1023.977221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1023.977234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1023.977250] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1023.977265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1023.980339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1023.980358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1023.980374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1023.980390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1023.984073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1023.984091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1023.984106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1023.986668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1023.986686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1023.989562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1023.991995] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1023.992067] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1023.992087] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1023.992113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1023.992157] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1023.992176] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1024.008818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1024.008844] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1024.008879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1024.025549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.025558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.058964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.058973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.092304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.092313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.125669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.125678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.159057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.159070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.192403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.192418] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.225751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.225760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.259112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.259121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.292482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.292491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.325845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.325854] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.359216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.359230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.392571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.392579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.425959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.425969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.459299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.459308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.492652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.492661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.526048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.526057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.559379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.559388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.592749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.592758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.626137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.626146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.659501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.659510] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.692864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.692873] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.726230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.726238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.759581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.759590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.792944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.792988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.826316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.826324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.859677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.859686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.893038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.893047] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.926385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.926393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.959747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.959756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.993112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1024.993121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.026466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.026475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.059829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.059838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.093202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.093211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.126562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.126571] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.159917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.159925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.193290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.193298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.226657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.226666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.260008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.260017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.293376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.293391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.326732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.326741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.360120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.360129] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.393467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.393476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.426829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.426838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.460193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.460202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.493579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.493588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.526920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.526929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.560277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.560286] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.593639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.593648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.627056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.627065] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.660381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.660396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.693736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.693745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.727116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.727125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.760484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.760493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.793828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.793837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.827181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.827190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.860545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.860554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.893937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.893946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.927299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.927308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.960640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.960649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.994004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1025.994013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.027376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.027385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.060754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.060763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.094121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.094130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.127450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.127459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.160820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.160829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.194184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.194193] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.227547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.227556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.260908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.260917] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.294274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.294282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.327636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.327644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.360991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.361000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.394357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.394366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.427726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.427735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.461104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.461113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.494471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.494480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.527844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.527853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.561181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.561190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.594563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.594572] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.627900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.627909] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.661262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.661271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.694630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.694639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.728008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.728017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.761357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.761366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.794742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.794751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.828106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.828115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.861449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.861457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.894803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.894812] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.928188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.928197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.961536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.961545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.994896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1026.994905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.028261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.028270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.061646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.061655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.094996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.095005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.128361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.128370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.161707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.161716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.195071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.195080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.228442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.228451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.261804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.261813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.295191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.295199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.328538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.328547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.361893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.361902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.395278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.395287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.428610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.428619] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.461976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.461985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.495346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.495355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.528718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.528727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.562072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.562081] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.595457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.595466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.628800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.628809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.662180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.662188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.695525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.695534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.728888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.728897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.762251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.762260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.795612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.795621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.828981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.828990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.862341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.862350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.895735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.895744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.929097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.929106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.962423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.962431] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.995807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1027.995815] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.029172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.029181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.062527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.062536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.095888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.095897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.129267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.129276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.162613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.162622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.196011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.196025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.229335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.229344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.262699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.262708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.296069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.296077] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.329453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.329462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.362787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.362796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.396150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.396159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.429522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.429531] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.462906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.462915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.496255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.496264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.529613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.529622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.562968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.562976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.596360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.596369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.629700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.629709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.663064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.663073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.696428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.696436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.729813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.729821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.763145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.763154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.796507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.796516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.829879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.829887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.863257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.863266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.896607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.896616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.929969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.929980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.963334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.963343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.996696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1028.996705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.030073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.030082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.063414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.063423] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.096784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.096793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.130147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.130156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.163509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.163518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.196873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.196882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.230252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.230261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.263600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.263608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.296957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.296966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.330355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.330364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.363689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.363697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.397052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.397061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.430415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.430424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.463802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.463811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.497142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.497151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.530507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.530516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.563883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.563891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.597259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.597268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.630611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.630620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.663957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.663966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.697335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.697344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.730684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.730693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.764049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.764058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.797412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.797421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.830766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.830775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.864128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.864137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.897500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.897509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.930861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.930870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.964235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.964244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.997610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1029.997620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.030953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.030962] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.064333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.064341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.097671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.097680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.131034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.131043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.164406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.164415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.197767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.197776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.231129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.231138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.264493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.264502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.297878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.297887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.331215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.331224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.364576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.364586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.397960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.397969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.431346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.431355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.464672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.464681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.498034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.498043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.531418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.531427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.564763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.564772] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.598125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.598134] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.631480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.631489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.664865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.664874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.698224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.698233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.731578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.731587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.764961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.764970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.798304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.798395] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.831670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.831678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.865033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.865042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.898402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.898411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.931749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.931758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.965118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.965127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.998482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.998491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.031845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.031854] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.065209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.065218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.098595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.098604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.131937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.131946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.165291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.165300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.198654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.198663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.232024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.232033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.265403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.265411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.298750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.298759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.332113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.332122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.365478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.365487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.398857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.398866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.432196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.432205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.465560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.465568] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.498951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.498960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.532292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.532301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.565657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.565665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.599019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.599028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.632399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.632408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.665769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.665777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.699099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.699108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.732499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.732507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.765842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.765851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.799218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.799227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.832561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.832570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.865925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.865934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.899289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.899298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.932653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.932661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.966006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.966015] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.999368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.999377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.032740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.032749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.066101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.066110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.099490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.099498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.132849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.132858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.166194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.166203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.199558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.199567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.232912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.232921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.266298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.266306] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.299645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.299654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.333008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.333017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.366370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.366379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.399735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.399743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.433100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.433109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.466485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.466493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.499817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.499826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.533181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.533189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.566552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.566561] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.599914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.599922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.633276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.633285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.666662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.666671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.700031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.700040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.733366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.733374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.766722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.766730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.800085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.800094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.833477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.833486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.866818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.866828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.900189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.900197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.933582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.933591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1032.966910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1032.966918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.000272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.000281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.033627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.033636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.066989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.066998] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.100359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.100368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.133730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.133738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.167085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.167094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.200480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.200489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.233815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.233823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.267178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.267187] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.300548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.300557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.333900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.333909] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.367266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.367275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.400628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.400637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.433991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.434000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.467353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.467362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.500721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.500730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.534086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.534095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.567413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.567422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.600801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.600815] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.634172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.634180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.667551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.667560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.700888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.700897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.734251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.734260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.767621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.767630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.800976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.800985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.834329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.834338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.867696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.867705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.901065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.901074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.934433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.934442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.967796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.967805] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.001157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1034.001166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.034516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1034.051108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1034.051134] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1034.051182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1034.069078] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1034.069103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1034.069123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1034.069145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1034.069165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1034.069187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1034.069206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1034.069226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1034.069245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1034.069267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1034.069288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1034.069309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1034.069330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1034.069349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1034.069368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1034.069396] [drm:intel_power_well_disable [i915]] disabling display
>[ 1034.069419] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1034.069444] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1034.069461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1034.069731] [drm:drm_mode_addfb2] [FB:77]
>[ 1034.069772] [drm:drm_mode_addfb2] [FB:78]
>[ 1034.117126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1034.117216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.117267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1034.117315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.117324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.117372] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1034.117389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1034.117407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1034.117425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1034.117440] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1034.117455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1034.117471] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1034.117486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1034.117500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1034.117513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1034.117559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1034.117566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1034.117585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1034.117591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1034.117612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1034.117633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1034.117653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1034.117674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1034.117697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1034.117720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1034.117740] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1034.117760] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1034.117782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1034.117806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1034.117833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1034.122962] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1034.122977] [drm:intel_power_well_enable [i915]] enabling display
>[ 1034.122990] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1034.123018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1034.123034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1034.123051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1034.123069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1034.123087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1034.123104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1034.123124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1034.123142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1034.123161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1034.123178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1034.123193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1034.123212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1034.123229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1034.125226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1034.125245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1034.125262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1034.125280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1034.128999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1034.129020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1034.129044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1034.131611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1034.131629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1034.134515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1034.137472] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1034.137577] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1034.137596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1034.137620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1034.154281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1034.154305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1034.154339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1034.170985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.170995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.204437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.204449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.237797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.237811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.271159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.271173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.304548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.304558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.337887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.337901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.371236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.371250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.404613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.404627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.437973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.437987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.471334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.471348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.504700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.504714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.538066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.538080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.571428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.571442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.604791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.604805] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.638140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.638154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.671506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.671520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.704878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.704892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.738239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.738254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.771621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.771634] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.804968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.804982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.838332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.838345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.871711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.871725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.905053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.905062] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.938408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.938417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1034.971777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1034.971786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.005133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.005142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.038498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.038507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.071867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.071876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.105252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.105261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.138609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.138618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.171970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.171979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.205310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.205319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.238697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.238705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.272051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.272060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.305428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.305437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.338773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.338782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.372138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.372147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.405520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.405529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.438854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.438863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.472217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.472226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.505586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.505675] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.538948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.538957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.572313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.572322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.605691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.605700] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.639041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.639050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.672405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.672414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.705760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.705769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.739124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.739133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.772514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.772523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.805854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.805863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.839218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.839227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.872581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.872590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.905947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.905956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.939309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.939318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1035.972679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1035.972688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.006052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.006061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.039397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.039406] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.072762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.072771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.106124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.106133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.139509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.139518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.172852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.172860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.206236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.206244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.239569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.239578] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.272933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.272941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.306302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.306311] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.339680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.339689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.373029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.373038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.406393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.406402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.439774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.439783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.473120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.473129] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.506475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.506484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.539838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.539847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.573207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.573216] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.606591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.606600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.639934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.639943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.673296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.673305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.706690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.706699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.740047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.740056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.773399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.773408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.806770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.806779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.840134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.840143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.873475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.873484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.906840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.906849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.940225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.940234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.973565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.973574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.006951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.006960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.040284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.040292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.073669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.073678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.107017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.107026] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.140401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.140410] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.173760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.173769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.207130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.207139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.240471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.240480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.273836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.273845] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.307189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.307198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.340552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.340560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.373922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.373931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.407282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.407291] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.440650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.440659] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.474015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.474024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.507377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.507386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.540755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.540764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.574091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.574100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.607458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.607467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.640846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.640855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.674189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.674198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.707554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.707563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.740917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.740926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.774294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.774303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.807666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.807675] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.841000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.841009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.874364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.874373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.907733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.907824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.941097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.941105] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1037.974459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1037.974468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.007839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.007848] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.041208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.041217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.074549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.074558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.107905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.107914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.141284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.141293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.174639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.174648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.208022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.208031] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.241365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.241374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.274729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.274738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.308092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.308101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.341477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.341486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.374825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.374834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.408172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.408181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.441541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.441550] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.474905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.474914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.508263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.508272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.541633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.541642] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.574998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.575007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.608361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.608370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.641716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.641724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.675079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.675087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.708448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.708457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.741826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.741835] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.775175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.775184] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.808559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.808568] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.841929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.841938] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.875263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.875272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.908621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.908630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.942005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.942014] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1038.975355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1038.975364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.008717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.008726] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.042080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.042089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.075467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.075476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.108811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.108839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.142190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.142199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.175546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.175555] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.208926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.208934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.242281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.242290] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.275622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.275632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.308987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.308996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.342330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.342339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.375713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.375722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.409077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.409086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.442434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.442443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.475793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.475801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.509164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.509173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.542527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.542536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.575912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.575921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.609255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.609264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.642624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.642633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.675982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.675991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.709336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.709345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.742698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.742707] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.776093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.776102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.809432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.809441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.842795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.842804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.876159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.876168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.909522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.909531] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.942901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.942910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1039.976243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1039.976252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.009604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.009613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.042992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.043000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.076337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.076345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.109684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.109693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.143060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.143074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.176428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.176438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.209791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.209800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.243167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.243176] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.276507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.276516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.309914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.309923] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.343261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.343270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.376606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.376615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.409983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.409992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.443332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.443341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.476695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.476704] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.510050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.510059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.543413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.543422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.576807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.576816] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.610146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.610155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.643515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.643524] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.676873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.676882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.710259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.710268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.743603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.743612] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.776970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.776979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.810322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.810331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.843710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.843719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.877074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.877082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.910432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.910440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.943778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.943787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1040.977165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1040.977174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.010520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.010534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.043833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.043842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.077250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.077264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.110617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.110626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.143992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.144001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.177320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.177329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.210685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.210694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.244065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.244073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.277413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.277422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.310766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.310775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.344151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.344160] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.377498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.377507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.410865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.410873] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.444230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.444239] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.477590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.477599] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.510991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.511000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.544339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.544348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.577695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.577704] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.611049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.611058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.644405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.644413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.677767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.677776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.711132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.711141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.744486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.744495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.777847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.777856] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.811211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.811219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.844573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.844581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.877931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.877940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.911298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.911307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.944661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.944670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1041.978041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1041.978050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.011390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.011399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.044753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.044762] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.078117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.078126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.111472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.111481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.144835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.144844] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.178206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.178214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.211568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.211577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.244983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.244992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.278326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.278334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.311670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.311679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.345049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.345058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.378388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.378397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.411771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.411780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.445137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.445145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.478502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.478511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.511850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.511859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.545233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.545241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.578578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.578586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.611961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.611971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.645292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.645301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.678655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.678663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.712063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.712072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.745387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.745396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.778751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.778760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.812141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.812150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.845478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.845487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.878841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.878850] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.912203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.912212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.945567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.945576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1042.978942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1042.978951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.012315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.012324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.045680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.045689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.079043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.079091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.112384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.112393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.145747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.145755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.179118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.179127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.212465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.212474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.245834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.245843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.279197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.279206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.312561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.312569] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.345918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.345927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.379289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.379298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.412652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.412661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.446007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.446016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.479370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.479379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.512740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.512749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.546119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.546128] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.579466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.579475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.612831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.612840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.646210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.646219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.679556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.679565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.712919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.712928] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.746296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.746304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.779647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.779656] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.813029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.813038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.846371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.846380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.879757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.879766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.913099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.913125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.946464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.946473] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1043.979840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1043.979849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.013196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.013204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.046550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.046559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.079923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.079932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.113298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.113307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.146642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.146651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.180013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1044.180060] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1044.180085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1044.180128] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1044.196997] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1044.197016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1044.197037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1044.197054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1044.197072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1044.197088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1044.197108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1044.197134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1044.197202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1044.197230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1044.197257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1044.197283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1044.197307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1044.197322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1044.197350] [drm:intel_power_well_disable [i915]] disabling display
>[ 1044.197373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1044.197394] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1044.197410] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1044.197582] [drm:drm_mode_addfb2] [FB:77]
>[ 1044.197607] [drm:drm_mode_addfb2] [FB:78]
>[ 1044.237983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1044.238074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1044.238155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.238237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.238253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.238322] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1044.238339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1044.238358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1044.238376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1044.238390] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1044.238406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1044.238422] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1044.238436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1044.238451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1044.238464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1044.238477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1044.238481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1044.238493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1044.238497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1044.238510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1044.238523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1044.238536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1044.238548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1044.238564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1044.238577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1044.238590] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1044.238602] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1044.238615] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1044.238630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1044.238648] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1044.243565] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1044.243580] [drm:intel_power_well_enable [i915]] enabling display
>[ 1044.243594] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1044.243622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1044.243637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1044.243652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1044.243666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1044.243679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1044.243693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1044.243709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1044.243724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1044.243739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1044.243752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1044.243764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1044.243781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1044.243795] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1044.245781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1044.245799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1044.245816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1044.245835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1044.247345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1044.247361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1044.247376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1044.248870] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1044.248885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1044.250699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1044.253636] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1044.253710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1044.253726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1044.253748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1044.270449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1044.270474] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1044.270508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1044.287212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.287222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.320606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.320615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.353958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.353967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.387320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.387329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.420685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.420694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.454048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.454057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.487402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.487411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.520764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.520773] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.554136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.554162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.587520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.587529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.620884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.620892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.654239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.654248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.687585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.687599] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.720950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.720964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.754298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.754312] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.787670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.787684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.821037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.821051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.854398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.854412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.887762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.887776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.921127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.921141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.954490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.954503] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1044.987854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1044.987867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.021219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.021233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.054577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.054585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.087931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.087945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.121323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.121337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.154679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.154692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.188041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.188055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.221407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.221421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.254770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.254783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.288117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.288131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.321481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.321494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.354855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.354868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.388239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.388251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.421596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.421609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.454946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.454960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.488321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.488334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.521674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.521687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.555024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.555038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.588386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.588399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.621762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.621776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.655124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.655137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.688488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.688502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.721851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.721865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.755237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.755247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.788580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.788592] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.821928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.821943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.855307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.855321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.888666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.888680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.922029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.922043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.955393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.955407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1045.988756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1045.988770] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.022121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.022135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.055485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.055499] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.088832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.088845] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.122195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.122209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.155573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.155587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.188935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.188949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.222314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.222328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.255663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.255676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.289026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.289040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.322406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.322420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.355739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.355753] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.389102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.389115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.422476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.422490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.455839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.455852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.489204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.489218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.522577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.522587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.555932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.555946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.589316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.589326] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.622644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.622658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.656008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.656022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.689398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.689412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.722745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.722759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.756108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.756122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.789472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.789485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.822835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.822849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.856201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.856215] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.889548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.889562] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.922911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.922924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.956307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.956321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1046.989649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1046.989663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.023013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.023027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.056392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.056406] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.089742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.089755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.123104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.123118] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.156453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.156467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.189823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.189837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.223190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.223201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.256555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.256569] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.289919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.289933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.323282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.323296] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.356649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.356662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.390010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.390024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.423375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.423388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.456722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.456735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.490094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.490108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.523473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.523486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.556819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.556833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.590188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.590199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.623538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.623547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.656900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.656909] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.690255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.690264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.723620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.723629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.756988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.756997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.790366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.790375] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.823714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.823723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.857077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.857085] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.890456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.890465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.923805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.923814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.957211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.957220] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.990553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.990562] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.023922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.023931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.057265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.057274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.090627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.090636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.123992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.124001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.157391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.157400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.190719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.190728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.224072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.224081] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.257450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.257459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.290812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.290821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.324194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.324203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.357534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.357543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.390896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.390905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.424260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.424269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.457624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.457633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.490979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.490988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.524342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.524350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.557712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.557720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.591073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.591082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.624453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.624462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.657815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.657824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.691183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.691195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.724530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.724539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.757883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.757892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.791268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.791276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.824617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.824626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.857980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.857989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.891342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.891351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.924705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.924714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.958059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.958068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1048.991432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1048.991440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.024768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.024776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.058133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.058141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.091557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.091566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.124884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.124893] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.158242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.158251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.191619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.191628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.224997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.225006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.258361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.258370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.291716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.291725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.325057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.325066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.358463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.358472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.391790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.391799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.425153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.425162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.458533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.458541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.491881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.491890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.525243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.525252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.558599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.558608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.591976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.591985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.625355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.625364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.658713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.658722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.692081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.692090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.725443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.725528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.758788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.758797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.792148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.792157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.825520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.825529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.858864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.858873] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.892235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.892244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.925598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.925607] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.958987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.959001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1049.992324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1049.992338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.025687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.025701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.059056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.059068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.092399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.092412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.125763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.125776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.159137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.159151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.192519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.192533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.225867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.225880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.259227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.259241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.292610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.292624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.325956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.325970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.359305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.359318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.392670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.392683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.426042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.426056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.459405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.459419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.492770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.492784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.526133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.526146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.559496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.559530] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.592861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.592875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.626209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.626222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.659598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.659611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.692947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.692961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.726310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.726324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.759675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.759689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.793038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.793052] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.826403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.826416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.859767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.859781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.893115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.893124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.926478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.926486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.959858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.959867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1050.993218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1050.993227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.026622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.026631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.059993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.060001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.093336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.093344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.126699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.126708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.160033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.160042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.193392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.193401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.226763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.226772] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.260124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.260133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.293490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.293499] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.326852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.326861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.360203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.360212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.393619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.393628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.426935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.426944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.460299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.460307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.493684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.493693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.527030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.527038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.560378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.560387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.593758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.593766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.627143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.627152] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.660484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.660493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.693861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.693870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.727201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.727210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.760608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.760618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.793957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.793966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.827323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.827332] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.860690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.860699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.894018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.894027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.927379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.927388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.960735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.960744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1051.994098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1051.994106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.027468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.027477] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.060830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.060839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.094195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.094204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.127567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.127576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.160923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.160932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.194316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.194325] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.227690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.227699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.261012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.261021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.294383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.294392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.327746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.327755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.361108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.361116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.394471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.394480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.427836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.427845] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.461201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.461210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.494555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.494563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.527918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.527927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.561308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.561317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.594667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.594676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.628015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.628024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.661378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.661387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.694757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.694766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.728105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.728114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.761458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.761467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.794822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.794831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.828189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.828203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.861551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.861564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.894915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.894929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.928267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.928276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.961628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.961637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1052.995010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1052.995019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.028372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.028381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.061742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.061751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.095098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.095107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.128459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.128468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.161825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.161834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.195211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.195224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.228553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.228562] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.261915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.261924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.295270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.295278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.328632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.328640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.362004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.362013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.395365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.395374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.428745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.428754] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.462093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.462102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.495456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.495464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.528821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.528829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.562213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.562227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.595539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.595548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.628908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.628917] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.662271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.662280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.695635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.695644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.728999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.729007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.762362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.762370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.795741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.795750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.829080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.829089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.862442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.862451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.895850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.895858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.929175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.929184] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.962541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.962550] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1053.995903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1053.995911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.029267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.029276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.062658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.062668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.095988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.095997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.129369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.129378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.162736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.162745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.196102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.196110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.229444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.229453] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.262846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.262855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.296204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.296251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1054.296276] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1054.296323] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1054.315207] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1054.315226] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1054.315247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.315264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.315282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.315298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.315313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.315329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.315347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.315364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.315379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.315395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.315409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.315422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.315450] [drm:intel_power_well_disable [i915]] disabling display
>[ 1054.315472] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1054.315493] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1054.315509] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1054.316926] [IGT] kms_flip: exiting, ret=0
>[ 1054.337348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1054.337366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.337385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.337404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.337419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.337436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.337452] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1054.337468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1054.337484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.337498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1054.337512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.337517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.337530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.337533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.337548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1054.337562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.337580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.337598] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1054.337617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1054.337635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.337654] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1054.337672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1054.337691] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1054.337711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.337734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1054.337810] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1054.337825] [drm:intel_power_well_enable [i915]] enabling display
>[ 1054.337839] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1054.337870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.337886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.337901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.337916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.337930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.337945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.337962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.337977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.337993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.338006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.338020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.338037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1054.338052] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1054.341135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1054.341153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.341169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.341185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.344872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1054.344888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1054.344902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.347502] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.347520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.350425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.353440] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1054.353485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1054.353501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1054.353524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1054.353571] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1054.353586] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1054.370236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.370262] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1054.370301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.370434] Console: switching to colour frame buffer device 240x75
>[ 1054.504717] Console: switching to colour dummy device 80x25
>[ 1054.504873] [IGT] kms_flip: executing
>[ 1054.519285] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1054.519314] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1054.520824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1054.520846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1054.522809] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1054.522816] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1054.524808] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1054.524830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1054.526809] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1054.526816] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1054.526820] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1054.526838] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1054.526861] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1054.527895] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1054.528800] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1054.528817] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1054.528832] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1054.528846] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1054.529843] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1054.529866] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1054.530921] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1054.530924] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1054.531009] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1054.531011] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1054.531015] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1054.531017] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1054.531021] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1054.531024] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1054.531031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1054.531034] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.531037] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1054.531039] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1054.531042] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1054.531044] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1054.531046] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1054.531049] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1054.531051] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1054.531054] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1054.531056] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1054.531059] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1054.531061] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1054.531063] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1054.531066] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1054.531068] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1054.531071] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1054.531073] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1054.531076] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1054.531078] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1054.531081] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1054.531083] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1054.531085] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1054.531088] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1054.531090] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1054.531092] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1054.531095] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1054.531097] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1054.531100] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1054.531102] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1054.531104] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1054.531136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1054.531154] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1054.532813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1054.532835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1054.534815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1054.534821] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1054.536818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1054.536838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1054.538912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1054.538918] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1054.538922] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1054.539151] [IGT] kms_flip: starting subtest vblank-vs-dpms-suspend
>[ 1054.539557] [drm:drm_mode_addfb2] [FB:75]
>[ 1054.539579] [drm:drm_mode_addfb2] [FB:79]
>[ 1054.581955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1054.582006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.587130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1054.587157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1054.587202] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1054.606074] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1054.606097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1054.606114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1054.606134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.606152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.606170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.606185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.606200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.606216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.606234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.606251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.606267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.606283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.606297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.606311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.606340] [drm:intel_power_well_disable [i915]] disabling display
>[ 1054.606361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1054.606384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1054.606401] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1054.606445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1054.606519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1054.606581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1054.606592] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1054.606634] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1054.606650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.606669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.606688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.606704] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.606720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.606737] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1054.606752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1054.606812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.606835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1054.606856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.606862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.606884] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.606890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.606912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1054.606933] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.606955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.606976] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1054.607000] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1054.607021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.607043] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1054.607064] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1054.607085] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1054.607110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.607142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1054.609759] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1054.609785] [drm:intel_power_well_enable [i915]] enabling display
>[ 1054.609798] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1054.609825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.609841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.609855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.609869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.609882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.609896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.609912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.609926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.609944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.609962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.609978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.609996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1054.610014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1054.611994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1054.612011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.612025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.612040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.613547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1054.613563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1054.613576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.615073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.615091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.616902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.619840] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1054.619911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1054.619928] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1054.619950] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1054.619991] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1054.620008] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1054.636665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.636690] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1054.636725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.670109] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1054.670129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.670150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.670171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.670196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.670222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.670247] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1054.670263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1054.670279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.670294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1054.670308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.670312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.670326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.670330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1054.670345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1054.670359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.670373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.670386] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1054.670403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1054.670417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.670436] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.670456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1054.670475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1054.670495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.670516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1054.686690] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1054.686714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1054.686762] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1054.705645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1054.705667] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1054.705683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1054.705702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.705719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.705734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.705753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.705813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.705838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.705867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.705895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.705921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.705942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.705967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.706008] [drm:intel_power_well_disable [i915]] disabling display
>[ 1054.706041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1054.706065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.706092] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1054.706120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.706143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1054.785108] PM: Syncing filesystems ... done.
>[ 1054.793789] PM: Preparing system for sleep (mem)
>[ 1054.794108] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1054.795588] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1054.796921] PM: Suspending system (mem)
>[ 1054.797005] Suspending console(s) (use no_console_suspend to debug)
>[ 1054.798235] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1054.799262] e1000e: EEE TX LPI TIMER: 00000011
>[ 1054.799386] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1054.799436] [drm:intel_power_well_enable [i915]] enabling display
>[ 1054.799459] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1054.800947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1054.801020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1054.801043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1054.801069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1054.801090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1054.801111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1054.801133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1054.801159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1054.801182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1054.801205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1054.801229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1054.801245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1054.801258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1054.801274] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1054.807428] sd 3:0:0:0: [sda] Stopping disk
>[ 1054.913799] hpet1: lost 6 rtc interrupts
>[ 1054.929865] PM: suspend of devices complete after 132.134 msecs
>[ 1054.931311] [drm:intel_power_well_disable [i915]] disabling display
>[ 1054.931336] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1054.931348] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1054.931366] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1054.942827] PM: late suspend of devices complete after 12.957 msecs
>[ 1054.944277] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1054.944633] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1054.944725] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1054.955850] PM: noirq suspend of devices complete after 13.016 msecs
>[ 1054.956109] ACPI: Preparing to enter system sleep state S3
>[ 1054.978392] PM: Saving platform NVS memory
>[ 1054.978526] Disabling non-boot CPUs ...
>[ 1054.990150] smpboot: CPU 1 is now offline
>[ 1055.003034] Broke affinity for irq 42
>[ 1055.003049] Broke affinity for irq 44
>[ 1055.004343] smpboot: CPU 2 is now offline
>[ 1055.015294] Broke affinity for irq 8
>[ 1055.015297] Broke affinity for irq 9
>[ 1055.015301] Broke affinity for irq 23
>[ 1055.015305] Broke affinity for irq 42
>[ 1055.015307] Broke affinity for irq 43
>[ 1055.015310] Broke affinity for irq 44
>[ 1055.016357] smpboot: CPU 3 is now offline
>[ 1055.018515] ACPI: Low-level resume complete
>[ 1055.018640] PM: Restoring platform NVS memory
>[ 1055.019135] Suspended for 15.783 seconds
>[ 1055.019214] Enabling non-boot CPUs ...
>[ 1055.019323] x86: Booting SMP configuration:
>[ 1055.019328] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1055.021041]  cache: parent cpu1 should not be sleeping
>[ 1055.022209] CPU1 is up
>[ 1055.022302] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1055.023513]  cache: parent cpu2 should not be sleeping
>[ 1055.024209] CPU2 is up
>[ 1055.024264] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1055.025378]  cache: parent cpu3 should not be sleeping
>[ 1055.026459] CPU3 is up
>[ 1055.032554] ACPI: Waking up from system sleep state S3
>[ 1055.045136] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1055.057123] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1055.057151] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1055.057155] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1055.057425] PM: noirq resume of devices complete after 12.567 msecs
>[ 1055.057631] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1055.057694] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1055.057715] [drm:intel_power_well_enable [i915]] enabling display
>[ 1055.059331] PM: early resume of devices complete after 1.877 msecs
>[ 1055.059558] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1055.059604] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1055.059626] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1055.060586] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1055.062272] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1055.064821] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1055.064840] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1055.064856] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1055.064872] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1055.065023] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1055.065043] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1055.065065] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1055.065085] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1055.065106] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1055.065127] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1055.065147] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1055.065479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1055.065539] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1055.065559] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1055.065583] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1055.065604] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1055.065627] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1055.065657] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1055.065678] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1055.065698] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1055.065718] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1055.065736] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1055.065755] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1055.065773] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1055.065817] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1055.065835] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1055.065849] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1055.065863] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1055.065875] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1055.065892] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1055.065907] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1055.065923] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1055.065943] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1055.065958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1055.065972] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1055.065985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.065989] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.066005] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066018] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1055.066031] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1055.066048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.066065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.066083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.066100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.066118] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1055.066135] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1055.066153] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1055.066172] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1055.066189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1055.066206] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1055.066223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.066226] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.066246] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066263] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1055.066280] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1055.066297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.066314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.066331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.066348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.066366] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1055.066383] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1055.066400] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1055.066419] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1055.066436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1055.066452] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1055.066469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.066472] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.066492] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1055.066509] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1055.066526] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1055.066543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.066560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.066577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.066594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.066611] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1055.066628] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1055.066646] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1055.066665] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1055.066683] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1055.066700] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1055.066742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1055.066760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1055.066778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1055.066809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1055.066826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1055.066844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.066861] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1055.066878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1055.066896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1055.066913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1055.066930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.066933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.066950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.066953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.066971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1055.066988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1055.067005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.067022] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1055.067040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.067056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.067073] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1055.067090] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1055.067108] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1055.067126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1055.067146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1055.067221] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1055.069319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1055.069341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1055.069362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1055.069383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1055.069403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1055.069424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1055.069444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1055.069467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1055.069489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1055.069511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1055.069532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1055.069554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.069574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1055.069594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1055.069617] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1055.069640] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1055.069665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.069687] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1055.069712] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1055.069836] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1055.070036] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1055.070158] sd 3:0:0:0: [sda] Starting disk
>[ 1055.071910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1055.071927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1055.073988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1055.073994] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1055.076092] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1055.076112] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1055.078175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1055.078181] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1055.078186] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1055.078207] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1055.079238] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1055.080133] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1055.080148] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1055.080162] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1055.080176] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1055.081165] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1055.081179] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1055.082103] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1055.082121] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1055.084190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1055.084209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1055.086283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1055.086288] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1055.088365] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1055.088384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1055.090458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1055.090463] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1055.090467] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1055.375399] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1055.416354] ata4.00: configured for UDMA/133
>[ 1055.428280] ahci 0000:00:1f.2: port does not support device sleep
>[ 1055.587828] PM: resume of devices complete after 528.461 msecs
>[ 1055.588689] PM: Finishing wakeup.
>[ 1055.588692] Restarting tasks ... 
>[ 1055.588933] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1055.588937] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1055.589014] [drm:intel_power_well_disable [i915]] disabling display
>[ 1055.589037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1055.589050] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1055.596824] done.
>[ 1055.601011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1055.601029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1055.601047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1055.601066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1055.601081] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1055.601096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.601112] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1055.601127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1055.601141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1055.601155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1055.601167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.601172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.601184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.601187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.601200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1055.601213] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1055.601226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.601238] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1055.601259] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.601281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.601303] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1055.601324] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1055.601345] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1055.601369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1055.601394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1055.601459] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1055.601483] [drm:intel_power_well_enable [i915]] enabling display
>[ 1055.601505] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1055.601545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1055.601568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1055.601590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1055.601611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1055.601632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1055.601654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1055.601678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1055.601701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1055.601724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.601745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1055.601765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1055.601790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1055.601813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1055.603865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1055.603891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1055.603914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1055.603937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1055.605599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1055.605625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1055.605647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1055.607268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1055.607295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1055.609133] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1055.611977] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1055.612052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1055.612076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1055.612110] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1055.612172] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1055.612196] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1055.612261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1055.612291] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1055.612340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.628921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1055.628943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1055.628963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1055.628985] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1055.629002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1055.629020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.629039] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1055.629056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1055.629073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1055.629092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1055.629113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.629118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.629138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.629142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1055.629162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1055.629182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1055.629203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.629223] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1055.629243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1055.629263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.629285] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1055.629305] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1055.629326] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1055.629347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1055.629370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1055.645460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1055.645486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1055.645529] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1055.664381] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1055.664405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1055.664421] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1055.664441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1055.664458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1055.664474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1055.664489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1055.664504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1055.664520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1055.664537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1055.664553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1055.664569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.664583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1055.664597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1055.664626] [drm:intel_power_well_disable [i915]] disabling display
>[ 1055.664649] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1055.664670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1055.664690] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1055.664712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.664728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1055.744144] PM: Syncing filesystems ... done.
>[ 1055.768218] PM: Preparing system for sleep (mem)
>[ 1055.768545] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1055.770036] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
>[ 1055.770953] PM: Suspending system (mem)
>[ 1055.771036] Suspending console(s) (use no_console_suspend to debug)
>[ 1055.772286] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1055.773224] e1000e: EEE TX LPI TIMER: 00000011
>[ 1055.773326] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1055.773347] [drm:intel_power_well_enable [i915]] enabling display
>[ 1055.773368] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1055.773655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1055.773733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1055.773757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1055.773783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1055.773805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1055.773826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1055.773867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1055.773894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1055.773918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1055.773941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1055.773964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1055.773985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1055.774005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1055.774031] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1055.781644] sd 3:0:0:0: [sda] Stopping disk
>[ 1055.886980] PM: suspend of devices complete after 115.225 msecs
>[ 1055.888177] [drm:intel_power_well_disable [i915]] disabling display
>[ 1055.888199] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1055.888212] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1055.888230] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1055.899919] PM: late suspend of devices complete after 12.933 msecs
>[ 1055.901353] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1055.901591] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1055.901713] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1055.912921] PM: noirq suspend of devices complete after 12.998 msecs
>[ 1055.913181] ACPI: Preparing to enter system sleep state S3
>[ 1055.935487] PM: Saving platform NVS memory
>[ 1055.935621] Disabling non-boot CPUs ...
>[ 1055.947415] smpboot: CPU 1 is now offline
>[ 1055.964091] Broke affinity for irq 42
>[ 1055.964098] Broke affinity for irq 44
>[ 1055.965163] smpboot: CPU 2 is now offline
>[ 1055.976093] Broke affinity for irq 8
>[ 1055.976097] Broke affinity for irq 9
>[ 1055.976102] Broke affinity for irq 23
>[ 1055.976105] Broke affinity for irq 42
>[ 1055.976108] Broke affinity for irq 43
>[ 1055.976111] Broke affinity for irq 44
>[ 1055.977147] smpboot: CPU 3 is now offline
>[ 1055.978923] ACPI: Low-level resume complete
>[ 1055.979055] PM: Restoring platform NVS memory
>[ 1055.979539] Suspended for 16.041 seconds
>[ 1055.979626] Enabling non-boot CPUs ...
>[ 1055.979734] x86: Booting SMP configuration:
>[ 1055.979739] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1055.981449]  cache: parent cpu1 should not be sleeping
>[ 1055.982604] CPU1 is up
>[ 1055.982696] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1055.983924]  cache: parent cpu2 should not be sleeping
>[ 1055.984580] CPU2 is up
>[ 1055.984633] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1055.985690]  cache: parent cpu3 should not be sleeping
>[ 1055.987072] CPU3 is up
>[ 1055.995136] ACPI: Waking up from system sleep state S3
>[ 1056.006334] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1056.018104] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1056.018110] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1056.018156] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1056.018479] PM: noirq resume of devices complete after 12.434 msecs
>[ 1056.018694] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1056.018757] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1056.018777] [drm:intel_power_well_enable [i915]] enabling display
>[ 1056.020423] PM: early resume of devices complete after 1.910 msecs
>[ 1056.020630] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1056.020675] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1056.020697] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1056.021809] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1056.022642] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1056.026780] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1056.026797] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1056.026815] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1056.026832] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1056.027002] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1056.027019] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1056.027042] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1056.027065] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1056.027086] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1056.027105] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1056.027122] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1056.027148] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1056.027216] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1056.027234] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1056.027254] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1056.027269] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1056.027290] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1056.027307] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1056.027325] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1056.027343] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1056.027358] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1056.027371] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1056.027386] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1056.027401] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1056.027417] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1056.027433] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1056.027448] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1056.027463] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1056.027480] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1056.027498] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1056.027514] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1056.027532] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1056.027555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1056.027572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1056.027587] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1056.027601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.027606] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.027620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.027624] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.027639] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1056.027655] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1056.027668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.027682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1056.027699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.027717] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.027731] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1056.027745] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1056.027760] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1056.027777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1056.027790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1056.027805] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1056.027819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.027822] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.027839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.027850] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.027866] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1056.027882] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1056.027895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.027909] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1056.027926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.027939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.027952] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1056.027967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1056.027983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1056.027997] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1056.028012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1056.028027] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1056.028039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.028043] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.028056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.028059] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1056.028074] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1056.028086] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1056.028098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.028112] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1056.028128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.028141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.028153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1056.028165] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1056.028177] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1056.028194] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1056.028207] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1056.028220] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1056.028258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1056.028272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1056.028289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1056.028310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1056.028327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1056.028345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1056.028363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1056.028380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1056.028397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1056.028414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1056.028431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.028434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.028451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.028454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.028471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1056.028488] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1056.028506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.028523] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1056.028540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.028556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.028573] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1056.028590] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1056.028607] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1056.028626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1056.028645] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1056.028710] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1056.030770] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1056.030789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1056.030808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1056.030827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1056.030846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1056.030881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1056.030900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1056.030922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1056.030944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1056.030965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1056.030985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1056.031005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.031024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1056.031043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1056.031067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1056.031098] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1056.031132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.031158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1056.031186] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1056.031222] sd 3:0:0:0: [sda] Starting disk
>[ 1056.031299] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1056.031345] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1056.033052] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1056.033069] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1056.035142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1056.035148] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1056.037224] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1056.037243] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1056.039317] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1056.039323] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1056.039328] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1056.039348] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1056.040379] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1056.041270] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1056.041285] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1056.041300] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1056.041313] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1056.042300] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1056.042314] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1056.043236] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1056.043254] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1056.045331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1056.045352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1056.047425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1056.047430] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1056.049507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1056.049526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1056.051600] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1056.051605] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1056.051609] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1056.337580] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1056.378533] ata4.00: configured for UDMA/133
>[ 1056.390486] ahci 0000:00:1f.2: port does not support device sleep
>[ 1056.545377] PM: resume of devices complete after 524.909 msecs
>[ 1056.546232] PM: Finishing wakeup.
>[ 1056.546235] Restarting tasks ... 
>[ 1056.546443] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1056.546447] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1056.546519] [drm:intel_power_well_disable [i915]] disabling display
>[ 1056.546540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1056.546552] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1056.549089] done.
>[ 1056.556524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1056.556580] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1056.556609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1056.556633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1056.556658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1056.556680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1056.556702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1056.556725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1056.556750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1056.556775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1056.556800] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1056.556824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.556846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1056.556867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1056.556922] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1056.556949] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1056.557266] [drm:drm_mode_addfb2] [FB:75]
>[ 1056.557301] [drm:drm_mode_addfb2] [FB:78]
>[ 1056.590623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1056.590710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1056.590770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1056.590826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1056.590836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1056.590884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1056.590939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1056.590968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1056.590998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1056.591022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1056.591047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1056.591072] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1056.591097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1056.591120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1056.591142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1056.591161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.591167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.591188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.591193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.591215] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1056.591236] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1056.591258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.591279] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1056.591303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.591325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.591347] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1056.591368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1056.591387] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1056.591411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1056.591437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1056.593967] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1056.593982] [drm:intel_power_well_enable [i915]] enabling display
>[ 1056.593995] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1056.594023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1056.594038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1056.594053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1056.594067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1056.594080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1056.594095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1056.594114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1056.594133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1056.594152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.594169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1056.594184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1056.594203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1056.594221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1056.596201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1056.596217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1056.596231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1056.596246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1056.597750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1056.597766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1056.597780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1056.599275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1056.599291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1056.601095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1056.604032] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1056.604105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1056.604122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1056.604145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1056.620849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1056.620875] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1056.620960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.654311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1056.654333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1056.654353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1056.654375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1056.654392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1056.654410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1056.654429] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1056.654446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1056.654464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1056.654480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1056.654497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1056.654503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.654523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1056.654527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1056.654548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1056.654568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1056.654589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1056.654609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1056.654630] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1056.654650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1056.654671] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1056.654692] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1056.654712] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1056.654734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1056.654755] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1056.654810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1056.654837] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1056.654880] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1056.671735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1056.671753] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1056.671774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1056.671791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1056.671807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1056.671822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1056.671837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1056.671853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1056.671870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1056.671932] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1056.671960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.671983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1056.672007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1056.672049] [drm:intel_power_well_disable [i915]] disabling display
>[ 1056.672083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1056.672107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1056.672134] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1056.672160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.672184] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1056.748309] PM: Syncing filesystems ... done.
>[ 1056.758108] PM: Preparing system for sleep (mem)
>[ 1056.758428] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1056.759860] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1056.761143] PM: Suspending system (mem)
>[ 1056.761226] Suspending console(s) (use no_console_suspend to debug)
>[ 1056.762487] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1056.763428] e1000e: EEE TX LPI TIMER: 00000011
>[ 1056.763485] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1056.763497] [drm:intel_power_well_enable [i915]] enabling display
>[ 1056.763510] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1056.765003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1056.765066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1056.765085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1056.765105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1056.765120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1056.765135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1056.765151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1056.765169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1056.765185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1056.765201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1056.765216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1056.765230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1056.765244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1056.765262] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1056.771514] sd 3:0:0:0: [sda] Stopping disk
>[ 1057.660050] hpet1: lost 55 rtc interrupts
>[ 1057.676019] PM: suspend of devices complete after 913.981 msecs
>[ 1057.677386] [drm:intel_power_well_disable [i915]] disabling display
>[ 1057.677410] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1057.677422] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1057.677442] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1057.689007] PM: late suspend of devices complete after 12.982 msecs
>[ 1057.690470] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1057.690726] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1057.690825] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1057.702043] PM: noirq suspend of devices complete after 13.030 msecs
>[ 1057.702306] ACPI: Preparing to enter system sleep state S3
>[ 1057.724634] PM: Saving platform NVS memory
>[ 1057.724769] Disabling non-boot CPUs ...
>[ 1057.736563] smpboot: CPU 1 is now offline
>[ 1057.750186] Broke affinity for irq 42
>[ 1057.750193] Broke affinity for irq 44
>[ 1057.751489] smpboot: CPU 2 is now offline
>[ 1057.762158] Broke affinity for irq 8
>[ 1057.762161] Broke affinity for irq 9
>[ 1057.762165] Broke affinity for irq 23
>[ 1057.762168] Broke affinity for irq 42
>[ 1057.762171] Broke affinity for irq 43
>[ 1057.762174] Broke affinity for irq 44
>[ 1057.763206] smpboot: CPU 3 is now offline
>[ 1057.764844] ACPI: Low-level resume complete
>[ 1057.764970] PM: Restoring platform NVS memory
>[ 1057.765460] Suspended for 15.216 seconds
>[ 1057.765547] Enabling non-boot CPUs ...
>[ 1057.765657] x86: Booting SMP configuration:
>[ 1057.765662] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1057.767369]  cache: parent cpu1 should not be sleeping
>[ 1057.768522] CPU1 is up
>[ 1057.768615] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1057.769829]  cache: parent cpu2 should not be sleeping
>[ 1057.770519] CPU2 is up
>[ 1057.770573] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1057.771628]  cache: parent cpu3 should not be sleeping
>[ 1057.772711] CPU3 is up
>[ 1057.778777] ACPI: Waking up from system sleep state S3
>[ 1057.791382] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1057.803174] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1057.803179] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1057.803229] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1057.803433] PM: noirq resume of devices complete after 12.347 msecs
>[ 1057.803708] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1057.803770] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1057.803791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1057.805375] PM: early resume of devices complete after 1.908 msecs
>[ 1057.805585] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1057.805630] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1057.805652] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1057.806775] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1057.807558] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1057.810956] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1057.810976] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1057.810994] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1057.811011] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1057.811172] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1057.811192] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1057.811215] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1057.811238] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1057.811257] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1057.811278] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1057.811297] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1057.811324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1057.811396] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1057.811416] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1057.811438] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1057.811456] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1057.811487] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1057.811505] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1057.811523] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1057.811538] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1057.811552] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1057.811568] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1057.811583] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1057.811597] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1057.811614] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1057.811630] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1057.811643] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1057.811656] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1057.811670] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1057.811689] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1057.811708] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1057.811725] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1057.811746] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1057.811760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1057.811776] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1057.811791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1057.811796] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.811811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1057.811814] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.811829] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1057.811843] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1057.811858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1057.811872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1057.811888] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1057.811902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1057.811918] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1057.811946] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1057.811961] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1057.811977] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1057.811989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1057.812004] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1057.812018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1057.812021] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.812033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1057.812037] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.812051] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1057.812065] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1057.812079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1057.812092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1057.812106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1057.812120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1057.812134] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1057.812149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1057.812163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1057.812177] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1057.812191] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1057.812206] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1057.812218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1057.812221] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.812235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1057.812237] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1057.812249] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1057.812261] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1057.812275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1057.812290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1057.812305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1057.812320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1057.812335] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1057.812348] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1057.812362] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1057.812381] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1057.812397] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1057.812412] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1057.812454] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1057.812468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1057.812487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1057.812507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1057.812523] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1057.812540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1057.812555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1057.812571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1057.812584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1057.812597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1057.812611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1057.812614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1057.812629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1057.812632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1057.812647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1057.812660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1057.812674] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1057.812686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1057.812701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1057.812715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1057.812731] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1057.812744] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1057.812758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1057.812775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1057.812795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1057.812872] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1057.814927] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1057.814957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1057.814972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1057.814986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1057.815000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1057.815014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1057.815033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1057.815055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1057.815076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1057.815097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1057.815118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1057.815138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1057.815157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1057.815175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1057.815198] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1057.815222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1057.815244] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1057.815268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1057.815288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1057.815391] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1057.815427] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1057.816128] sd 3:0:0:0: [sda] Starting disk
>[ 1057.817438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1057.817459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1057.819534] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1057.819540] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1057.821616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1057.821636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1057.823709] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1057.823715] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1057.823719] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1057.823740] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1057.824775] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1057.825664] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1057.825680] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1057.825693] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1057.825707] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1057.826693] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1057.826707] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1057.827630] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1057.827650] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1057.829728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1057.829748] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1057.831822] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1057.831827] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1057.833904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1057.833923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1057.835994] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1057.836002] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1057.836007] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1058.123490] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1058.164478] ata4.00: configured for UDMA/133
>[ 1058.176396] ahci 0000:00:1f.2: port does not support device sleep
>[ 1058.325976] PM: resume of devices complete after 520.566 msecs
>[ 1058.326804] PM: Finishing wakeup.
>[ 1058.326806] Restarting tasks ... 
>[ 1058.327039] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1058.327043] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1058.327115] [drm:intel_power_well_disable [i915]] disabling display
>[ 1058.327135] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1058.327147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1058.327997] done.
>[ 1058.334640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1058.334667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1058.334694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1058.334722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1058.334744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1058.334769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1058.334793] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1058.334815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1058.334830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1058.334844] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1058.334857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.334861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.334874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.334877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.334890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1058.334903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1058.334915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.334928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.334943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.334961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.335307] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1058.335331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1058.335355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1058.335380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1058.335407] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1058.335482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1058.335505] [drm:intel_power_well_enable [i915]] enabling display
>[ 1058.335528] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1058.335570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1058.335592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1058.335615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1058.335637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1058.335658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1058.335681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1058.335706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1058.335730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1058.335753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.335775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1058.335796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1058.335822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1058.335844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1058.339524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1058.339551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1058.339573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1058.339598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1058.341133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1058.341158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1058.341181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1058.342736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1058.342763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1058.344602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1058.347227] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1058.347268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1058.347291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1058.347325] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1058.347418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1058.347450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1058.347499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.364131] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1058.364153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1058.364174] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1058.364195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1058.364213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1058.364231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1058.364249] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1058.364266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1058.364283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1058.364299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1058.364314] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.364319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.364334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.364337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.364353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1058.364368] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1058.364382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.364397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.364415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.364430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.364446] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1058.364461] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1058.364476] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1058.364494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1058.364514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1058.364567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1058.364590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1058.364631] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1058.382726] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1058.382745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1058.382766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1058.382783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1058.382799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1058.382814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1058.382829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1058.382845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1058.382862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1058.382878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1058.382893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.382907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1058.382921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1058.382949] [drm:intel_power_well_disable [i915]] disabling display
>[ 1058.383018] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1058.383044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1058.383071] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1058.383098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.383124] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1058.462027] PM: Syncing filesystems ... done.
>[ 1058.470568] PM: Preparing system for sleep (mem)
>[ 1058.470887] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1058.472372] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1058.473640] PM: Suspending system (mem)
>[ 1058.473721] Suspending console(s) (use no_console_suspend to debug)
>[ 1058.475063] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1058.476028] e1000e: EEE TX LPI TIMER: 00000011
>[ 1058.476102] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1058.476118] [drm:intel_power_well_enable [i915]] enabling display
>[ 1058.476132] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1058.478130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1058.478185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1058.478201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1058.478224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1058.478247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1058.478262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1058.478277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1058.478295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1058.478311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1058.478327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1058.478342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.478357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1058.478370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1058.478389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1058.484216] sd 3:0:0:0: [sda] Stopping disk
>[ 1058.545093] PM: suspend of devices complete after 70.643 msecs
>[ 1058.546467] [drm:intel_power_well_disable [i915]] disabling display
>[ 1058.546493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1058.546505] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1058.546525] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1058.558039] PM: late suspend of devices complete after 12.932 msecs
>[ 1058.559500] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1058.559775] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1058.559866] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1058.571062] PM: noirq suspend of devices complete after 13.018 msecs
>[ 1058.571326] ACPI: Preparing to enter system sleep state S3
>[ 1058.593669] PM: Saving platform NVS memory
>[ 1058.593804] Disabling non-boot CPUs ...
>[ 1058.605589] smpboot: CPU 1 is now offline
>[ 1058.619229] Broke affinity for irq 42
>[ 1058.619236] Broke affinity for irq 44
>[ 1058.620291] smpboot: CPU 2 is now offline
>[ 1058.633145] Broke affinity for irq 8
>[ 1058.633148] Broke affinity for irq 9
>[ 1058.633152] Broke affinity for irq 23
>[ 1058.633156] Broke affinity for irq 42
>[ 1058.633158] Broke affinity for irq 43
>[ 1058.633162] Broke affinity for irq 44
>[ 1058.634202] smpboot: CPU 3 is now offline
>[ 1058.635847] ACPI: Low-level resume complete
>[ 1058.635969] PM: Restoring platform NVS memory
>[ 1058.636450] Suspended for 16.131 seconds
>[ 1058.636538] Enabling non-boot CPUs ...
>[ 1058.636646] x86: Booting SMP configuration:
>[ 1058.636651] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1058.638341]  cache: parent cpu1 should not be sleeping
>[ 1058.639495] CPU1 is up
>[ 1058.639586] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1058.640784]  cache: parent cpu2 should not be sleeping
>[ 1058.641470] CPU2 is up
>[ 1058.641523] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1058.642607]  cache: parent cpu3 should not be sleeping
>[ 1058.643310] CPU3 is up
>[ 1058.646698] ACPI: Waking up from system sleep state S3
>[ 1058.657995] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1058.669186] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1058.669191] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1058.669241] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1058.669462] PM: noirq resume of devices complete after 11.780 msecs
>[ 1058.669629] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1058.669692] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1058.669711] [drm:intel_power_well_enable [i915]] enabling display
>[ 1058.671570] PM: early resume of devices complete after 2.079 msecs
>[ 1058.671769] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1058.671813] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1058.671827] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1058.672014] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1058.673757] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1058.677939] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1058.677968] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1058.677985] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1058.678002] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1058.678160] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1058.678179] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1058.678200] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1058.678222] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1058.678245] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1058.678265] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1058.678281] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1058.678306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1058.678364] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1058.678382] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1058.678403] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1058.678420] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1058.678438] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1058.678453] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1058.678470] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1058.678487] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1058.678504] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1058.678520] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1058.678533] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1058.678548] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1058.678566] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1058.678583] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1058.678597] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1058.678611] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1058.678624] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1058.678641] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1058.678658] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1058.678676] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1058.678700] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1058.678716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1058.678732] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1058.678747] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.678752] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.678765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.678768] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.678781] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1058.678796] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1058.678812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.678826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.678842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.678858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.678871] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1058.678883] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1058.678899] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1058.678916] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1058.678928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1058.678951] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1058.678965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.678968] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.678983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.678985] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.679000] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1058.679012] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1058.679024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.679036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.679051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.679062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.679074] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1058.679086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1058.679098] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1058.679111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1058.679123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1058.679135] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1058.679151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.679154] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.679171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.679174] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1058.679192] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1058.679209] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1058.679226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.679243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.679261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.679277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.679295] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1058.679312] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1058.679330] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1058.679349] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1058.679367] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1058.679384] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1058.679427] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1058.679445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1058.679463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1058.679483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1058.679500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1058.679518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1058.679535] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1058.679552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1058.679570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1058.679587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1058.679604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1058.679607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.679624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1058.679627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1058.679645] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1058.679662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1058.679679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1058.679696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1058.679713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1058.679730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1058.679747] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1058.679764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1058.679781] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1058.679799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1058.679820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1058.679886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1058.681954] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1058.681973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1058.681990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1058.682005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1058.682020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1058.682034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1058.682051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1058.682080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1058.682108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1058.682134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1058.682159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1058.682184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.682200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1058.682221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1058.682227] sd 3:0:0:0: [sda] Starting disk
>[ 1058.682247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1058.682266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1058.682283] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1058.682302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1058.682317] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1058.682413] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1058.682456] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1058.684481] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1058.684498] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1058.686560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1058.686564] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1058.688639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1058.688659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1058.690734] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1058.690740] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1058.690744] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1058.690764] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1058.691791] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1058.692679] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1058.692695] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1058.692709] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1058.692722] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1058.693709] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1058.693723] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1058.694644] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1058.694661] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1058.695990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1058.696006] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1058.698045] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1058.698049] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1058.700126] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1058.700146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1058.702221] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1058.702226] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1058.702230] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1058.989501] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1059.030432] ata4.00: configured for UDMA/133
>[ 1059.042417] ahci 0000:00:1f.2: port does not support device sleep
>[ 1059.198541] PM: resume of devices complete after 526.935 msecs
>[ 1059.199298] PM: Finishing wakeup.
>[ 1059.199300] Restarting tasks ... done.
>[ 1059.205328] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1059.205334] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1059.205451] [drm:intel_power_well_disable [i915]] disabling display
>[ 1059.205486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1059.205506] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1059.206235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1059.206290] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1059.206320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1059.206344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1059.206369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1059.206392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1059.206413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1059.206436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1059.206461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1059.206486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1059.206510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1059.206534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.206555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1059.206576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1059.206609] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1059.206633] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1059.207458] [drm:drm_mode_addfb2] [FB:75]
>[ 1059.207494] [drm:drm_mode_addfb2] [FB:78]
>[ 1059.247456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1059.247587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1059.247690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1059.247789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1059.247804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1059.247872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1059.247900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1059.247926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1059.247954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1059.247977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1059.248039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1059.248065] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1059.248087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1059.248110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1059.248133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1059.248153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.248160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.248180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.248185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.248206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1059.248227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1059.248249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.248269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.248291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.248311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.248330] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1059.248351] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1059.248370] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1059.248393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1059.248419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1059.251013] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1059.251028] [drm:intel_power_well_enable [i915]] enabling display
>[ 1059.251042] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1059.251072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1059.251089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1059.251104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1059.251118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1059.251132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1059.251147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1059.251163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1059.251178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1059.251193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.251206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1059.251218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1059.251235] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1059.251250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1059.253251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1059.253268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1059.253282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1059.253297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1059.254800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1059.254816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1059.254830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1059.256322] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1059.256338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1059.258141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1059.261536] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1059.261604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1059.261620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1059.261641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1059.278364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1059.278390] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1059.278426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.311821] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1059.311843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1059.311865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1059.311889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1059.311909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1059.311930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1059.311951] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1059.311971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1059.312037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1059.312063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1059.312089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.312097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.312122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.312128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.312153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1059.312176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1059.312200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.312221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.312247] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.312272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.312295] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1059.312316] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1059.312338] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1059.312365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1059.312392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1059.312462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1059.312493] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1059.312548] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1059.329376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1059.329395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1059.329415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1059.329432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1059.329448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1059.329463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1059.329478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1059.329494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1059.329511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1059.329527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1059.329543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.329557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1059.329571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1059.329598] [drm:intel_power_well_disable [i915]] disabling display
>[ 1059.329620] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1059.329635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1059.329652] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1059.329668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.329683] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1059.404032] PM: Syncing filesystems ... done.
>[ 1059.430267] PM: Preparing system for sleep (mem)
>[ 1059.430585] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1059.432076] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1059.433113] PM: Suspending system (mem)
>[ 1059.433195] Suspending console(s) (use no_console_suspend to debug)
>[ 1059.434479] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1059.435559] e1000e: EEE TX LPI TIMER: 00000011
>[ 1059.435664] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1059.435687] [drm:intel_power_well_enable [i915]] enabling display
>[ 1059.435710] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1059.435986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1059.436083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1059.436106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1059.436132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1059.436154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1059.436175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1059.436197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1059.436224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1059.436247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1059.436270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1059.436293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.436314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1059.436334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1059.436362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1059.444143] sd 3:0:0:0: [sda] Stopping disk
>[ 1059.550191] PM: suspend of devices complete after 116.273 msecs
>[ 1059.551531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1059.551553] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1059.551565] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1059.551583] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1059.563279] PM: late suspend of devices complete after 13.083 msecs
>[ 1059.564879] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1059.565088] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1059.565178] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1059.577048] PM: noirq suspend of devices complete after 13.761 msecs
>[ 1059.577312] ACPI: Preparing to enter system sleep state S3
>[ 1059.599678] PM: Saving platform NVS memory
>[ 1059.599814] Disabling non-boot CPUs ...
>[ 1059.611383] smpboot: CPU 1 is now offline
>[ 1059.624254] Broke affinity for irq 42
>[ 1059.624261] Broke affinity for irq 44
>[ 1059.625560] smpboot: CPU 2 is now offline
>[ 1059.637147] Broke affinity for irq 8
>[ 1059.637150] Broke affinity for irq 9
>[ 1059.637154] Broke affinity for irq 23
>[ 1059.637157] Broke affinity for irq 42
>[ 1059.637160] Broke affinity for irq 43
>[ 1059.637163] Broke affinity for irq 44
>[ 1059.638194] smpboot: CPU 3 is now offline
>[ 1059.639924] ACPI: Low-level resume complete
>[ 1059.640049] PM: Restoring platform NVS memory
>[ 1059.640534] Suspended for 15.997 seconds
>[ 1059.640623] Enabling non-boot CPUs ...
>[ 1059.640733] x86: Booting SMP configuration:
>[ 1059.640737] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1059.642450]  cache: parent cpu1 should not be sleeping
>[ 1059.643623] CPU1 is up
>[ 1059.643713] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1059.644923]  cache: parent cpu2 should not be sleeping
>[ 1059.645630] CPU2 is up
>[ 1059.645682] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1059.646737]  cache: parent cpu3 should not be sleeping
>[ 1059.648081] CPU3 is up
>[ 1059.655528] ACPI: Waking up from system sleep state S3
>[ 1059.665640] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1059.677242] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1059.677247] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1059.677300] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1059.677533] PM: noirq resume of devices complete after 12.181 msecs
>[ 1059.677704] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1059.677767] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1059.677789] [drm:intel_power_well_enable [i915]] enabling display
>[ 1059.679645] PM: early resume of devices complete after 2.079 msecs
>[ 1059.679849] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1059.679891] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1059.679906] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1059.681276] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1059.682813] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1059.685381] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1059.685410] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1059.685436] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1059.685461] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1059.685687] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1059.685716] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1059.685756] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1059.685788] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1059.685822] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1059.685858] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1059.685885] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1059.685928] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1059.686049] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1059.686074] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1059.686111] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1059.686139] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1059.686175] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1059.686202] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1059.686235] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1059.686264] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1059.686301] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1059.686321] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1059.686344] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1059.686367] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1059.686393] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1059.686417] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1059.686436] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1059.686459] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1059.686482] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1059.686510] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1059.686542] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1059.686568] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1059.686599] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1059.686623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1059.686647] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1059.686670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.686680] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.686699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.686707] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.686726] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1059.686745] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1059.686764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.686787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.686817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.686839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.686858] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1059.686881] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1059.686903] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1059.686928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1059.686950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1059.686966] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1059.686984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.687008] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.687026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.687035] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.687054] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1059.687076] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1059.687099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.687121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.687150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.687172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.687195] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1059.687218] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1059.687240] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1059.687265] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1059.687288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1059.687312] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1059.687331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.687335] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.687357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.687366] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1059.687384] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1059.687407] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1059.687431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.687453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.687476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.687494] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.687513] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1059.687536] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1059.687559] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1059.687590] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1059.687614] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1059.687638] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1059.687702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1059.687726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1059.687757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1059.687786] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1059.687810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1059.687835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1059.687856] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1059.687880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1059.687904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1059.687927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1059.687948] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1059.687953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.687971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1059.687976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1059.687996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1059.688028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1059.688047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1059.688069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1059.688094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1059.688117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1059.688132] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1059.688144] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1059.688160] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1059.688179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1059.688200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1059.688266] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1059.690322] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1059.690339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1059.690355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1059.690369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1059.690384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1059.690398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1059.690413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1059.690435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1059.690456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1059.690476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1059.690497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1059.690517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.690536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1059.690554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1059.690577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1059.690601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1059.690624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1059.690649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1059.690684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1059.690777] sd 3:0:0:0: [sda] Starting disk
>[ 1059.690820] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1059.690866] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1059.692506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1059.692523] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1059.694578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1059.694583] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1059.696658] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1059.696678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1059.698720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1059.698726] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1059.698730] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1059.698751] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1059.699777] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1059.700666] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1059.700682] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1059.700696] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1059.700709] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1059.701696] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1059.701711] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1059.702633] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1059.702651] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1059.704708] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1059.704723] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1059.706774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1059.706777] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1059.708853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1059.708873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1059.710945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1059.710951] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1059.710954] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1059.999404] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1060.040361] ata4.00: configured for UDMA/133
>[ 1060.052305] ahci 0000:00:1f.2: port does not support device sleep
>[ 1060.204154] PM: resume of devices complete after 524.473 msecs
>[ 1060.204889] PM: Finishing wakeup.
>[ 1060.204892] Restarting tasks ... done.
>[ 1060.218991] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1060.218997] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1060.219149] [drm:intel_power_well_disable [i915]] disabling display
>[ 1060.219182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1060.219202] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1060.225368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1060.225395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1060.225422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1060.225450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1060.225473] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1060.225497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1060.225522] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1060.225544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1060.225567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1060.225588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1060.225608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.225615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.225636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.225641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.225662] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1060.225683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1060.225704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.225725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.225748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.225769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.225792] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1060.225812] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1060.225833] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1060.225857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1060.225883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1060.225949] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1060.225971] [drm:intel_power_well_enable [i915]] enabling display
>[ 1060.225994] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1060.226035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1060.226089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1060.226112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1060.226135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1060.226156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1060.226180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1060.226207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1060.226232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1060.226256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.226278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1060.226299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1060.226323] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1060.226347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1060.231549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1060.231577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1060.231599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1060.231624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1060.233277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1060.233304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1060.233327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1060.234849] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1060.234876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1060.236719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1060.239226] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1060.239285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1060.239309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1060.239342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1060.239429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1060.239460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1060.239510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.256166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1060.256186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1060.256205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1060.256225] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1060.256241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1060.256258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1060.256276] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1060.256292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1060.256314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1060.256328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1060.256340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.256345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.256358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.256362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.256375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1060.256388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1060.256400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.256413] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.256428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.256441] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.256455] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1060.256468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1060.256480] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1060.256496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1060.256513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1060.256562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1060.256583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1060.256618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1060.274559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1060.274579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1060.274600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1060.274618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1060.274633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1060.274649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1060.274664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1060.274680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1060.274705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1060.274724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1060.274742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.274760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1060.274775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1060.274804] [drm:intel_power_well_disable [i915]] disabling display
>[ 1060.274825] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1060.274844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1060.274863] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1060.274883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.274897] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1060.355351] PM: Syncing filesystems ... done.
>[ 1060.363994] PM: Preparing system for sleep (mem)
>[ 1060.364399] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1060.365814] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1060.367072] PM: Suspending system (mem)
>[ 1060.367153] Suspending console(s) (use no_console_suspend to debug)
>[ 1060.368461] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[ 1060.369452] e1000e: EEE TX LPI TIMER: 00000011
>[ 1060.369544] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1060.369565] [drm:intel_power_well_enable [i915]] enabling display
>[ 1060.369586] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1060.377771] sd 3:0:0:0: [sda] Stopping disk
>[ 1060.379254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1060.379313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1060.379334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1060.379356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1060.379377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1060.379397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1060.379417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1060.379440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1060.379462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1060.379483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1060.379504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.379524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1060.379544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1060.379569] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1060.484077] hpet1: lost 6 rtc interrupts
>[ 1060.502615] PM: suspend of devices complete after 134.740 msecs
>[ 1060.503905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1060.503937] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1060.503956] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1060.503981] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1060.516117] PM: late suspend of devices complete after 13.496 msecs
>[ 1060.517665] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1060.517941] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1060.518028] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[ 1060.529132] PM: noirq suspend of devices complete after 13.011 msecs
>[ 1060.529391] ACPI: Preparing to enter system sleep state S3
>[ 1060.551726] PM: Saving platform NVS memory
>[ 1060.551869] Disabling non-boot CPUs ...
>[ 1060.563823] smpboot: CPU 1 is now offline
>[ 1060.576277] Broke affinity for irq 42
>[ 1060.576284] Broke affinity for irq 44
>[ 1060.577583] smpboot: CPU 2 is now offline
>[ 1060.582267] Broke affinity for irq 8
>[ 1060.582270] Broke affinity for irq 9
>[ 1060.582274] Broke affinity for irq 23
>[ 1060.582277] Broke affinity for irq 42
>[ 1060.582280] Broke affinity for irq 43
>[ 1060.582283] Broke affinity for irq 44
>[ 1060.583315] smpboot: CPU 3 is now offline
>[ 1060.584978] ACPI: Low-level resume complete
>[ 1060.585105] PM: Restoring platform NVS memory
>[ 1060.585588] Suspended for 16.056 seconds
>[ 1060.585675] Enabling non-boot CPUs ...
>[ 1060.585784] x86: Booting SMP configuration:
>[ 1060.585788] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1060.587503]  cache: parent cpu1 should not be sleeping
>[ 1060.588674] CPU1 is up
>[ 1060.588766] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1060.590002]  cache: parent cpu2 should not be sleeping
>[ 1060.590711] CPU2 is up
>[ 1060.590764] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1060.591819]  cache: parent cpu3 should not be sleeping
>[ 1060.593005] CPU3 is up
>[ 1060.600009] ACPI: Waking up from system sleep state S3
>[ 1060.610058] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[ 1060.622272] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1060.623218] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1060.623222] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1060.623372] PM: noirq resume of devices complete after 13.533 msecs
>[ 1060.623534] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1060.623592] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1060.623606] [drm:intel_power_well_enable [i915]] enabling display
>[ 1060.625329] PM: early resume of devices complete after 1.927 msecs
>[ 1060.625545] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2c9a018
>[ 1060.625590] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1060.625612] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1060.626693] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1060.627512] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1060.630882] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1060.630907] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1060.630929] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1060.630951] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1060.631172] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1060.631197] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1060.631227] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1060.631257] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1060.631286] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1060.631314] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1060.631337] [drm:intel_guc_setup [i915]] GuC fw status: path (null), fetch NONE, load NONE
>[ 1060.631373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1060.631467] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1060.631492] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1060.631520] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1060.631543] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1060.631570] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1060.631593] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1060.631618] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1060.631642] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1060.631666] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1060.631687] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1060.631708] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1060.631729] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1060.631752] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1060.631776] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1060.631796] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1060.631816] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1060.631837] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1060.631872] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1060.631895] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1060.631916] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1060.631947] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1060.631967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1060.631987] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1060.632006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.632012] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.632051] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632071] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1060.632090] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1060.632109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.632128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.632150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.632169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.632188] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1060.632207] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1060.632225] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1060.632246] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1060.632263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1060.632282] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1060.632300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.632304] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.632327] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632346] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1060.632364] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1060.632382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.632399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.632420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.632439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.632457] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1060.632476] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1060.632495] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1060.632515] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1060.632534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1060.632552] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1060.632570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.632574] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.632595] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1060.632614] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1060.632633] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1060.632651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.632669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.632690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.632709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.632727] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1060.632746] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1060.632764] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1060.632788] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1060.632808] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1060.632828] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1060.632885] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1060.632905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1060.632928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1060.632953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1060.632974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1060.632995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1060.633010] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1060.633023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1060.633037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1060.633060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1060.633073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1060.633076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.633088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1060.633091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1060.633103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1060.633115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1060.633132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1060.633149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1060.633167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1060.633184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1060.633201] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1060.633218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1060.633235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1060.633253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1060.633275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1060.633339] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1060.635436] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1060.635458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1060.635479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1060.635499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1060.635520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1060.635540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1060.635560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1060.635584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1060.635605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1060.635627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1060.635649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1060.635671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.635690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1060.635710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1060.635734] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1060.635760] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1060.635785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1060.635808] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1060.635832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1060.635970] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1060.636038] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1060.636046] sd 3:0:0:0: [sda] Starting disk
>[ 1060.638136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1060.638153] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1060.640226] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1060.640232] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1060.642309] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1060.642329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1060.644393] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1060.644399] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1060.644403] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1060.644422] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1060.645451] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1060.646343] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1060.646359] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1060.646376] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1060.646394] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1060.647383] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1060.647399] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1060.648321] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1060.648339] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1060.650404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1060.650419] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1060.652493] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1060.652499] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1060.654575] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1060.654594] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1060.656667] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1060.656672] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1060.656676] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1060.945618] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1060.986572] ata4.00: configured for UDMA/133
>[ 1060.998508] ahci 0000:00:1f.2: port does not support device sleep
>[ 1061.149546] PM: resume of devices complete after 524.181 msecs
>[ 1061.150404] PM: Finishing wakeup.
>[ 1061.150407] Restarting tasks ... 
>[ 1061.150595] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1061.150598] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1061.150671] [drm:intel_power_well_disable [i915]] disabling display
>[ 1061.150692] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1061.150704] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1061.151166] done.
>[ 1061.160072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1061.160161] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1061.160191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1061.160216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1061.160242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1061.160263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1061.160285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1061.160308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1061.160332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1061.160357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1061.160381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1061.160404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1061.160425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1061.160446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1061.160478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1061.160502] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1061.164552] [IGT] kms_flip: exiting, ret=0
>[ 1061.165073] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[ 1061.183446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1061.183463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1061.183479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1061.183497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1061.183511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1061.183526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1061.183541] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1061.183558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1061.183575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1061.183592] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1061.183608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1061.183613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.183629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1061.183632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.183649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1061.183666] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1061.183691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1061.183708] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1061.183725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1061.183741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1061.183755] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1061.183770] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1061.183784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1061.183800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1061.183819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1061.183873] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1061.183888] [drm:intel_power_well_enable [i915]] enabling display
>[ 1061.183901] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1061.183930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1061.183945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1061.183960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1061.183974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1061.183988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1061.184002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1061.184019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1061.184034] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1061.184050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1061.184064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1061.184110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1061.184127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1061.184143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1061.186138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1061.186152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1061.186165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1061.186179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1061.187694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1061.187708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1061.187720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1061.189229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1061.189243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1061.191062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1061.194104] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1061.194172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1061.194188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1061.194211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1061.194256] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1061.194272] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1061.210928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1061.210952] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1061.210991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1061.211146] Console: switching to colour frame buffer device 240x75
>[ 1061.353919] Console: switching to colour dummy device 80x25
>[ 1061.354012] [IGT] kms_flip: executing
>[ 1061.364530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1061.364560] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1061.366161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.366188] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.368136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.368142] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1061.370138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.370156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.372147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.372153] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.372157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1061.372175] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1061.372197] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1061.373231] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1061.374142] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1061.374169] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1061.374192] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1061.374208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1061.375201] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1061.375219] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1061.376273] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1061.376277] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1061.376355] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.376357] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.376361] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1061.376363] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1061.376367] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.376369] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.376376] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1061.376379] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.376381] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.376384] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.376386] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.376389] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.376391] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.376394] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1061.376396] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.376399] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.376401] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.376403] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.376406] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.376408] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1061.376411] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.376413] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.376415] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1061.376418] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.376420] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.376423] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1061.376425] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1061.376428] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1061.376430] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1061.376432] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1061.376435] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1061.376437] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.376440] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.376442] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1061.376444] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.376447] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.376449] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1061.376479] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1061.376497] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1061.378149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.378168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.380164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.380170] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1061.382246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.382267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.384333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.384338] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.384342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1061.385589] [IGT] kms_flip: starting subtest 2x-flip-vs-expired-vblank-interruptible
>[ 1061.386959] [IGT] kms_flip: exiting, ret=77
>[ 1061.411208] Console: switching to colour frame buffer device 240x75
>[ 1061.543579] Console: switching to colour dummy device 80x25
>[ 1061.543672] [IGT] kms_flip: executing
>[ 1061.558602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1061.558633] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1061.560157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.560175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.562148] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.562153] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1061.564157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.564178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.566158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.566164] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.566168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1061.566183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1061.566207] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1061.567245] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1061.568145] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1061.568169] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1061.568192] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1061.568212] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1061.569205] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1061.569229] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1061.570302] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1061.570305] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1061.570388] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.570390] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.570394] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1061.570396] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1061.570400] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.570402] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.570410] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1061.570412] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.570415] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.570417] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.570420] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.570422] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.570425] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.570427] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1061.570430] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.570432] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.570435] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.570437] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.570439] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.570442] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1061.570444] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.570447] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.570449] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1061.570452] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.570454] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.570456] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1061.570459] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1061.570461] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1061.570464] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1061.570466] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1061.570468] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1061.570471] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.570473] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.570476] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1061.570478] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.570481] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.570483] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1061.570513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1061.570531] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1061.572156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.572175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.574157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.574162] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1061.576155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.576174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.578158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.578163] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.578167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1061.578388] [IGT] kms_flip: starting subtest 2x-dpms-vs-vblank-race
>[ 1061.580730] [IGT] kms_flip: exiting, ret=77
>[ 1061.611344] Console: switching to colour frame buffer device 240x75
>[ 1061.741127] Console: switching to colour dummy device 80x25
>[ 1061.741221] [IGT] kms_flip: executing
>[ 1061.751637] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1061.751666] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1061.753091] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.753115] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.755212] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.755218] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1061.757295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.757315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.759379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.759384] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.759388] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1061.759405] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1061.759426] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1061.760447] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1061.761330] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1061.761347] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1061.761361] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1061.761375] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1061.762356] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1061.762374] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1061.763420] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1061.763423] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1061.763505] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.763508] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.763512] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1061.763514] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1061.763517] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.763519] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.763527] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1061.763530] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.763532] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.763535] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.763537] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.763540] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.763542] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.763545] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1061.763547] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.763549] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.763552] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.763554] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.763557] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.763559] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1061.763562] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.763564] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.763566] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1061.763569] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.763571] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.763574] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1061.763576] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1061.763579] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1061.763581] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1061.763583] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1061.763586] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1061.763588] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.763591] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.763593] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1061.763595] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.763598] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.763600] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1061.763629] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1061.763647] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1061.765164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.765186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.767143] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.767148] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1061.769172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.769191] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.771174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.771180] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.771184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1061.771397] [IGT] kms_flip: starting subtest 2x-flip-vs-rmfb
>[ 1061.773722] [IGT] kms_flip: exiting, ret=77
>[ 1061.794897] Console: switching to colour frame buffer device 240x75
>[ 1061.926443] Console: switching to colour dummy device 80x25
>[ 1061.926537] [IGT] kms_flip: executing
>[ 1061.951344] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1061.951372] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1061.953170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.953190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.955182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1061.955187] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1061.957181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.957201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1061.959181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1061.959187] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.959191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1061.959207] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1061.959231] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1061.960271] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1061.961174] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1061.961192] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1061.961208] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1061.961225] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1061.962222] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1061.962247] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1061.963322] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1061.963326] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1061.963408] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.963411] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.963415] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1061.963417] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1061.963422] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1061.963424] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1061.963431] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1061.963434] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1061.963437] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.963439] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.963442] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.963444] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1061.963446] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.963449] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1061.963451] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.963454] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1061.963456] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1061.963459] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.963461] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1061.963463] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1061.963466] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.963468] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1061.963471] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1061.963473] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.963475] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1061.963478] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1061.963480] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1061.963483] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1061.963485] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1061.963488] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1061.963490] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1061.963492] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.963495] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1061.963497] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1061.963500] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.963502] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1061.963504] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1061.963535] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1061.963553] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1061.965178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.965198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.967169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1061.967174] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1061.969180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.969201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1061.971180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1061.971185] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1061.971189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1061.971415] [IGT] kms_flip: starting subtest 2x-nonexisting-fb
>[ 1061.973752] [IGT] kms_flip: exiting, ret=77
>[ 1061.995075] Console: switching to colour frame buffer device 240x75
>[ 1062.128845] Console: switching to colour dummy device 80x25
>[ 1062.128939] [IGT] kms_flip: executing
>[ 1062.138656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1062.138686] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1062.140766] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1062.140787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1062.142861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1062.142867] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1062.144942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1062.144962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1062.147035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1062.147041] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1062.147046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1062.147062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1062.147085] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1062.148110] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1062.148996] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1062.149013] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1062.149027] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1062.149041] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1062.150024] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1062.150040] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1062.151092] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1062.151095] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1062.151212] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1062.151215] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1062.151219] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1062.151221] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1062.151225] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1062.151227] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1062.151235] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1062.151238] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1062.151240] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1062.151243] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1062.151245] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1062.151248] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1062.151250] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1062.151253] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1062.151256] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1062.151258] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1062.151260] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1062.151263] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1062.151265] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1062.151268] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1062.151270] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1062.151273] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1062.151275] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1062.151278] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1062.151280] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1062.151283] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1062.151285] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1062.151288] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1062.151290] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1062.151293] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1062.151295] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1062.151298] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1062.151300] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1062.151302] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1062.151305] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1062.151307] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1062.151310] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1062.151339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1062.151357] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1062.153182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1062.153207] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1062.155281] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1062.155287] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1062.157363] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1062.157383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1062.159456] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1062.159462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1062.159466] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1062.159672] [IGT] kms_flip: starting subtest blocking-wf_vblank
>[ 1062.160078] [drm:drm_mode_addfb2] [FB:77]
>[ 1062.160101] [drm:drm_mode_addfb2] [FB:79]
>[ 1062.202203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1062.202256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1062.211840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1062.211866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1062.211908] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1062.230763] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1062.230786] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1062.230802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1062.230822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1062.230839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1062.230857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1062.230873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1062.230888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1062.230904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1062.230921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1062.230938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1062.230954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1062.230969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1062.230983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1062.230997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1062.231025] [drm:intel_power_well_disable [i915]] disabling display
>[ 1062.231047] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1062.231070] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1062.231087] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1062.231173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1062.231273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1062.231337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1062.231348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1062.231390] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1062.231408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1062.231426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1062.231447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1062.231466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1062.231486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1062.231506] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1062.231526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1062.231546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1062.231566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1062.231585] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1062.231590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1062.231608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1062.231612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1062.231630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1062.231649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1062.231669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1062.231688] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1062.231708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1062.231727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1062.231747] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1062.231766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1062.231785] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1062.231806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1062.231826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1062.234452] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1062.234469] [drm:intel_power_well_enable [i915]] enabling display
>[ 1062.234483] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1062.234512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1062.234531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1062.234550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1062.234569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1062.234588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1062.234607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1062.234627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1062.234647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1062.234667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1062.234685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1062.234701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1062.234721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1062.234739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1062.236748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1062.236766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1062.236781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1062.236796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1062.238310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1062.238326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1062.238340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1062.239837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1062.239853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1062.241665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1062.244590] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1062.244622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1062.244639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1062.244660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1062.244699] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1062.244719] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1062.261393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1062.261419] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1062.261457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1064.022360] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[ 1072.570648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1072.587256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1072.587282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1072.587323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1072.606180] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1072.606203] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1072.606220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1072.606240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1072.606257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1072.606275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1072.606290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1072.606306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1072.606322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1072.606340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1072.606357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1072.606373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1072.606393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1072.606412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1072.606432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1072.606461] [drm:intel_power_well_disable [i915]] disabling display
>[ 1072.606484] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1072.606511] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1072.606529] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1072.606737] [drm:drm_mode_addfb2] [FB:77]
>[ 1072.606805] [drm:drm_mode_addfb2] [FB:78]
>[ 1072.632593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1072.632674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1072.632726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1072.632813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1072.632829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1072.632901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1072.632926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1072.632952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1072.632980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1072.633001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1072.633026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1072.633048] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1072.633071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1072.633092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1072.633113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1072.633132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1072.633137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1072.633157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1072.633162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1072.633183] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1072.633202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1072.633223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1072.633242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1072.633265] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1072.633284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1072.633304] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1072.633323] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1072.633344] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1072.633365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1072.633390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1072.636007] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1072.636022] [drm:intel_power_well_enable [i915]] enabling display
>[ 1072.636035] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1072.636062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1072.636078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1072.636093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1072.636106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1072.636120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1072.636134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1072.636150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1072.636164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1072.636179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1072.636192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1072.636205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1072.636223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1072.636241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1072.638243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1072.638261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1072.638276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1072.638291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1072.639825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1072.639841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1072.639855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1072.641356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1072.641372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1072.643189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1072.646130] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1072.646199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1072.646215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1072.646238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1072.662931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1072.662954] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1072.662988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1082.972218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1082.972271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1082.972298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1082.972340] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1082.991205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1082.991225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1082.991246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1082.991263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1082.991281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1082.991300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1082.991320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1082.991339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1082.991361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1082.991382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1082.991445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1082.991474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1082.991498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1082.991520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1082.991566] [drm:intel_power_well_disable [i915]] disabling display
>[ 1082.991601] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1082.991634] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1082.991660] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1082.991896] [drm:drm_mode_addfb2] [FB:77]
>[ 1082.991921] [drm:drm_mode_addfb2] [FB:78]
>[ 1083.017486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1083.017572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1083.017628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1083.017683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1083.017693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1083.017740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1083.017757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1083.017775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1083.017794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1083.017808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1083.017824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1083.017840] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1083.017855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1083.017873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1083.017890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1083.017908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1083.017911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1083.017928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1083.017932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1083.017950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1083.017967] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1083.017985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1083.018002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1083.018020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1083.018037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1083.018055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1083.018072] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1083.018090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1083.018108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1083.018128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1083.020750] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1083.020766] [drm:intel_power_well_enable [i915]] enabling display
>[ 1083.020781] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1083.020811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1083.020829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1083.020845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1083.020860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1083.020875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1083.020890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1083.020909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1083.020928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1083.020948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1083.020967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1083.020992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1083.021012] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1083.021029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1083.023190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1083.023208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1083.023222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1083.023238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1083.024745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1083.024761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1083.024777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1083.026270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1083.026287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1083.028094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1083.031032] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1083.031104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1083.031121] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1083.031144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1083.047848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1083.047875] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1083.047913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.357202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1093.357285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1093.357325] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1093.357391] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1093.374235] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1093.374257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1093.374279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1093.374299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1093.374321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1093.374341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1093.374360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1093.374380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1093.374401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1093.374421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1093.374442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1093.374462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.374481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1093.374500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1093.374529] [drm:intel_power_well_disable [i915]] disabling display
>[ 1093.374552] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1093.374577] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1093.374594] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1093.377060] [IGT] kms_flip: exiting, ret=0
>[ 1093.396488] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1093.396508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1093.396528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1093.396552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1093.396571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1093.396592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1093.396612] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1093.396631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1093.396651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1093.396671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1093.396690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1093.396695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1093.396715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1093.396718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1093.396738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1093.396758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1093.396778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1093.396797] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1093.396817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1093.396837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1093.396856] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1093.396876] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1093.396896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1093.396924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1093.396945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1093.397000] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1093.397030] [drm:intel_power_well_enable [i915]] enabling display
>[ 1093.397045] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1093.397076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1093.397096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1093.397115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1093.397135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1093.397154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1093.397173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1093.397195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1093.397216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1093.397236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.397255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1093.397274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1093.397295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1093.397314] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1093.399319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1093.399336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1093.399350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1093.399367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1093.403103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1093.403119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1093.403136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1093.405730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1093.405749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1093.408652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1093.411667] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1093.411713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1093.411729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1093.411752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1093.411796] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1093.411812] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1093.428461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1093.428486] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1093.428523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.428648] Console: switching to colour frame buffer device 240x75
>[ 1093.735688] Console: switching to colour dummy device 80x25
>[ 1093.735782] [IGT] kms_flip: executing
>[ 1093.749577] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1093.749602] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1093.751101] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1093.751122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1093.753096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1093.753102] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1093.755082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1093.755103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1093.757091] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1093.757097] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1093.757101] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1093.757115] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1093.757136] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1093.758169] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1093.759080] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1093.759097] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1093.759112] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1093.759126] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1093.760121] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1093.760145] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1093.761226] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1093.761229] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1093.761307] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1093.761309] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1093.761313] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1093.761315] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1093.761319] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1093.761321] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1093.761328] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1093.761331] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1093.761334] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1093.761336] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1093.761339] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1093.761341] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1093.761344] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1093.761346] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1093.761348] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1093.761351] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1093.761353] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1093.761356] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1093.761358] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1093.761361] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1093.761363] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1093.761365] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1093.761368] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1093.761370] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1093.761373] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1093.761375] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1093.761378] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1093.761380] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1093.761382] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1093.761385] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1093.761387] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1093.761390] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1093.761392] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1093.761394] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1093.761397] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1093.761399] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1093.761402] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1093.761431] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1093.761449] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1093.763087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1093.763108] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1093.765102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1093.765109] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1093.767184] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1093.767204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1093.769279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1093.769285] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1093.769289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1093.769508] [IGT] kms_flip: starting subtest dpms-off-confusion
>[ 1093.769915] [drm:drm_mode_addfb2] [FB:75]
>[ 1093.769939] [drm:drm_mode_addfb2] [FB:79]
>[ 1093.812121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1093.812176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1093.828805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1093.828829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1093.828867] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1093.847730] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1093.847755] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1093.847775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1093.847797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1093.847817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1093.847839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1093.847859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1093.847878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1093.847897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1093.847919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1093.847940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1093.847960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1093.847980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.847999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1093.848015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1093.848134] [drm:intel_power_well_disable [i915]] disabling display
>[ 1093.848169] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1093.848194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1093.848211] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1093.848253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1093.848317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1093.848373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1093.848383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1093.848423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1093.848439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1093.848456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1093.848474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1093.848489] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1093.848505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1093.848521] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1093.848536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1093.848551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1093.848564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1093.848578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1093.848582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1093.848595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1093.848598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1093.848611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1093.848624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1093.848637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1093.848649] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1093.848665] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1093.848678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1093.848691] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1093.848704] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1093.848716] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1093.848731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1093.848748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1093.851256] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1093.851273] [drm:intel_power_well_enable [i915]] enabling display
>[ 1093.851287] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1093.851315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1093.851333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1093.851349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1093.851364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1093.851378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1093.851394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1093.851411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1093.851427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1093.851443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1093.851456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1093.851470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1093.851487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1093.851503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1093.854586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1093.854607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1093.854626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1093.854646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1093.858355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1093.858372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1093.858388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1093.860948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1093.860967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1093.863841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1093.866764] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1093.866800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1093.866819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1093.866844] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1093.866885] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1093.866905] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1093.883544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1093.883569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1093.883604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1103.909219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1103.925845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1103.925871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1103.925911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1103.944767] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1103.944790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1103.944807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1103.944826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1103.944843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1103.944861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1103.944877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1103.944892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1103.944908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1103.944926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1103.944943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1103.944959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1103.944975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1103.944989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1103.945004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1103.945031] [drm:intel_power_well_disable [i915]] disabling display
>[ 1103.945054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1103.945081] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1103.945100] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1103.945310] [drm:drm_mode_addfb2] [FB:75]
>[ 1103.945334] [drm:drm_mode_addfb2] [FB:78]
>[ 1103.971148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.971234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1103.971290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1103.971343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1103.971353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.971401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1103.971418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1103.971436] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1103.971455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1103.971469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1103.971485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1103.971501] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1103.971515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1103.971529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1103.971543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1103.971556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1103.971559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1103.971576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1103.971580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1103.971597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1103.971615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1103.971632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1103.971650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1103.971700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1103.971724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1103.971748] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1103.971769] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1103.971790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1103.971813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1103.971840] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1103.974458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1103.974473] [drm:intel_power_well_enable [i915]] enabling display
>[ 1103.974486] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1103.974514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1103.974530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1103.974544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1103.974558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1103.974575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1103.974593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1103.974613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1103.974632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1103.974650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1103.974703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1103.974728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1103.974754] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1103.974776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1103.976778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1103.976794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1103.976810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1103.976828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1103.980512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1103.980531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1103.980546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1103.983131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1103.983151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1103.986053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1103.988996] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1103.989063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1103.989079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1103.989101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1104.005814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1104.005841] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1104.005879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1114.031587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1114.031665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1114.031709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1114.031779] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1114.048606] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1114.048625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1114.048646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1114.048663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1114.048684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1114.048704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1114.048724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1114.048743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1114.048765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1114.048786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1114.048806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1114.048825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1114.048844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1114.048863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1114.048893] [drm:intel_power_well_disable [i915]] disabling display
>[ 1114.048916] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1114.048942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1114.048958] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1114.049124] [drm:drm_mode_addfb2] [FB:75]
>[ 1114.049147] [drm:drm_mode_addfb2] [FB:78]
>[ 1114.074288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1114.074385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.074442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1114.074498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1114.074509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.074557] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1114.074574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1114.074591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1114.074610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1114.074624] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1114.074639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1114.074655] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1114.074670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1114.074684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1114.074698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1114.074711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1114.074714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1114.074727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1114.074730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1114.074743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1114.074756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1114.074769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1114.074781] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1114.074796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1114.074809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1114.074822] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1114.074835] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1114.074847] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1114.074863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1114.074883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1114.077509] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1114.077526] [drm:intel_power_well_enable [i915]] enabling display
>[ 1114.077542] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1114.077573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1114.077592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1114.077611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1114.077630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1114.077648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1114.077667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1114.077688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1114.077707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1114.077727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1114.077746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1114.077764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1114.077784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1114.077803] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1114.079801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1114.079818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1114.079832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1114.079847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1114.081367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1114.081385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1114.081400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1114.082896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1114.082913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1114.084717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1114.087664] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1114.087727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1114.087744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1114.087774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1114.104478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1114.104504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1114.104539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.130157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1124.130204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1124.130229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1124.130269] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1124.149133] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1124.149152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1124.149173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1124.149191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1124.149209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1124.149224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1124.149240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1124.149256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1124.149274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1124.149290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1124.149306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1124.149322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.149336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1124.149350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1124.149379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1124.149401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1124.149423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1124.149439] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1124.151864] [IGT] kms_flip: exiting, ret=0
>[ 1124.171320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1124.171338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1124.171356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1124.171376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1124.171392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1124.171412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1124.171431] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1124.171449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1124.171468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1124.171486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1124.171504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1124.171509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.171527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1124.171530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.171549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1124.171567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1124.171586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1124.171604] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1124.171623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1124.171641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1124.171659] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1124.171678] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1124.171696] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1124.171716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1124.171737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1124.171790] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1124.171805] [drm:intel_power_well_enable [i915]] enabling display
>[ 1124.171820] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1124.171852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1124.171893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1124.171912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1124.171931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1124.171957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1124.171973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1124.171990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1124.172005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1124.172019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.172032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1124.172044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1124.172059] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1124.172074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1124.174064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1124.174078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1124.174092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1124.174105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1124.177760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1124.177776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1124.177792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1124.180378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1124.180395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1124.183308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1124.186321] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1124.186365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1124.186380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1124.186403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1124.186448] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1124.186467] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1124.203113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1124.203137] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1124.203172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.203302] Console: switching to colour frame buffer device 240x75
>[ 1124.337299] Console: switching to colour dummy device 80x25
>[ 1124.337390] [IGT] kms_flip: executing
>[ 1124.347404] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1124.347433] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1124.348944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1124.348964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1124.350934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1124.350940] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1124.352933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1124.352953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1124.354935] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1124.354941] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1124.354945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1124.354961] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1124.354984] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1124.356017] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1124.356929] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1124.356955] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1124.356976] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1124.356990] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1124.357979] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1124.357995] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1124.359068] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1124.359071] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1124.359150] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1124.359152] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1124.359156] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1124.359158] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1124.359162] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1124.359164] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1124.359171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1124.359174] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.359177] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.359179] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.359182] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1124.359184] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1124.359187] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1124.359189] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1124.359191] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.359194] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.359196] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1124.359199] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1124.359201] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1124.359204] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1124.359206] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1124.359208] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1124.359211] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1124.359213] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1124.359216] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1124.359218] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1124.359220] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1124.359223] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1124.359225] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1124.359228] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1124.359230] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1124.359233] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1124.359235] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1124.359237] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1124.359240] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1124.359242] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1124.359245] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1124.359274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1124.359292] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1124.360928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1124.360946] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1124.362932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1124.362937] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1124.364932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1124.364953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1124.366933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1124.366938] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1124.366942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1124.367175] [IGT] kms_flip: starting subtest 2x-flip-vs-dpms-off-vs-modeset
>[ 1124.369490] [IGT] kms_flip: exiting, ret=77
>[ 1124.403399] Console: switching to colour frame buffer device 240x75
>[ 1124.541310] Console: switching to colour dummy device 80x25
>[ 1124.541402] [IGT] kms_flip: executing
>[ 1124.553370] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1124.553395] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1124.554950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1124.554970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1124.556947] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1124.556953] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1124.558954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1124.558975] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1124.560948] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1124.560954] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1124.560958] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1124.560975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1124.560998] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1124.562032] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1124.562936] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1124.562953] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1124.562969] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1124.562983] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1124.563975] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1124.563998] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1124.565053] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1124.565056] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1124.565135] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1124.565138] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1124.565142] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1124.565144] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1124.565148] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1124.565150] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1124.565157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1124.565159] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.565162] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.565165] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.565167] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1124.565170] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1124.565172] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1124.565174] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1124.565177] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.565179] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1124.565182] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1124.565184] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1124.565187] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1124.565189] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1124.565191] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1124.565194] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1124.565196] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1124.565199] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1124.565201] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1124.565204] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1124.565206] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1124.565208] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1124.565211] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1124.565213] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1124.565216] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1124.565218] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1124.565221] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1124.565223] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1124.565225] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1124.565228] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1124.565230] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1124.565263] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1124.565280] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1124.566944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1124.566964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1124.568953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1124.568959] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1124.570948] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1124.570970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1124.572948] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1124.572954] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1124.572958] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1124.573177] [IGT] kms_flip: starting subtest flip-vs-panning
>[ 1124.573584] [drm:drm_mode_addfb2] [FB:75]
>[ 1124.573606] [drm:drm_mode_addfb2] [FB:79]
>[ 1124.633439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.633494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1124.636830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1124.636854] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1124.636894] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1124.655802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1124.655825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1124.655842] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1124.655862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1124.655879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1124.655939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1124.655964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1124.655990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1124.656014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1124.656042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1124.656069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1124.656094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1124.656120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.656141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1124.656162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1124.656205] [drm:intel_power_well_disable [i915]] disabling display
>[ 1124.656238] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1124.656271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1124.656298] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1124.656371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1124.656488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.656560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.656570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.656613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1124.656631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1124.656649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1124.656669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1124.656685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1124.656701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1124.656718] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1124.656734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1124.656749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1124.656764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1124.656778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1124.656781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.656795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1124.656798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1124.656813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1124.656826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1124.656848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1124.656860] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1124.656875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1124.656888] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1124.656929] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1124.656953] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1124.656972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1124.656996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1124.657022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1124.661956] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1124.661971] [drm:intel_power_well_enable [i915]] enabling display
>[ 1124.661984] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1124.662011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1124.662026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1124.662041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1124.662055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1124.662072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1124.662090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1124.662109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1124.662128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1124.662146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.662164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1124.662179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1124.662198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1124.662215] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1124.665271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1124.665289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1124.665305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1124.665321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1124.669027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1124.669046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1124.669062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1124.671623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1124.671641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1124.674521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1124.677443] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1124.677479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1124.677496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1124.677518] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1124.677557] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1124.677573] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1124.694224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1124.694249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1124.694284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1124.710970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.710979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.744346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.744355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.777713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.777722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.811075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.811084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.844437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.844446] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.877873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.877887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.911240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.911255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.944906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.945037] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.977971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1124.977985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.011238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.011247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.044607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.044616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.077986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.077995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.111458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.111476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.145147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.145181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.178157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.178172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.211434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.211442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.244973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.244997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.278151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.278160] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.311621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.311636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.345011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.345025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.378314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.378327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.412099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.412135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.444994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.445004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.478342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.478352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.511870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.511892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.545245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.545267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.578424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.578433] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.611871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.611884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.645514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.645549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.678537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.678548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.712072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.712089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.745243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.745252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.778629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.778638] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.812070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.812084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.845464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.845495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.878725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.878733] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.912100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.912108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.945452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.945461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.978786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1125.978795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.012149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.012158] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.045504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.045513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.078897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.078906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.112266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.112275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.145630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.145639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.179011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.179019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.212357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.212366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.245720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.245729] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.279100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.279109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.312439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.312448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.345834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.345847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.379352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.379361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.412534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.412543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.445898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.445907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.479263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.479272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.512723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.512739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.546248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.546282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.579355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.579366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.612831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.612849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.646091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.646100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.679498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.679512] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.712927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.712939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.746196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.746208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.779531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.779540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.812932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.812945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.846249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.846258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.879668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.879682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.913010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.913147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.946364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.946376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.979781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1126.979797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.013089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.013098] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.046436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.046445] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.079895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.079910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.113209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.113223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.146563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.146576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.179999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.180016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.213380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.213399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.246643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.246657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.280035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.280184] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.313319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.313328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.346683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.346692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.380076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.380085] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.413543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.413559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.446873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.446888] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.480172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.480181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.513601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.513617] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.546862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.546871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.580282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.580295] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.613632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.613644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.646976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.646987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.680340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.680351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.713793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.713809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.747186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.747202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.780423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.780432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.813884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.813900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.847168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.847177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.880493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.880502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.913947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.913962] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.947548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.947579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.980638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1127.980651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.014212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.014235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.047329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.047337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.080672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.080681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.114132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.114141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.147419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.147428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.180829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.180842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.214410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.214434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.247700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.247709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.281023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.281043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.314587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.314600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.347645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.347658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.380961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.380970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.414504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.414525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.447679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.447688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.481087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.481099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.514432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.514444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.547811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.547823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.581386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.581409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.614586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.614602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.647846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.647855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.681394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.681413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.714564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.714573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.747936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.747946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.781305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.781314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.814661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.814670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.848092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.848105] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.881466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.881480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.914750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.914759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.948114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.948123] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.981460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1128.981469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.014958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.014977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.048629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.048663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.081934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.081968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.115393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.115428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.148398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.148413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.181656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.181664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.215019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.215028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.248374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.248383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.281812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.281826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.315253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.315270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.348493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.348501] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.381913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.381927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.415214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.415223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.448560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.448569] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.481924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.481933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.515572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.515600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.548642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.548651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.582012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.582021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.615376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.615385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.648738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.648747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.682102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.682111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.715597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.715613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.748830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.748838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.782362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.782380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.815547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.815556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.848916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.848925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.882461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.882476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.915734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.915749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.949008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.949017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.982450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.982464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.015734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.015743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.049117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.049132] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.082453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.082462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.116277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.116287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.149185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.149194] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.182549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.182558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.215964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.215973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.249291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.249300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.282718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.282732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.316001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.316016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.349364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.349379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.382721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.382735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.416085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.416099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.449450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.449464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.482896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.482918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.516176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.516190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.549702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.549737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.582916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.582930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.616276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.616289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.649637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.649651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.683129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.683154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.716382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.716396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.749903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.749931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.783092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.783106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.816457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.816470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.849866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.849885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.883330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.883355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.916543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.916557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.949905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.949919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.983293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.983307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.016634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.016648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.050128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.050153] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.083525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.083548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.116711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.116725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.150074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.150088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.183446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.183460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.216810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.216825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.250339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.250351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.283672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.283697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.317032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.317057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.350267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.350280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.383615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.383629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.416980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.416993] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.450517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.450543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.483716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.483730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.517080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.517094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.550545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.550568] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.583853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.583871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.617218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.617235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.650521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.650535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.683884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.683898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.717367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.717387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.750621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.750635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.783985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.783999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.817369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.817381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.850713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.850727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.884164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.884185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.917527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.917548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.950789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.950803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.984163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.984177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.017525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.017539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.050964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.050985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.084424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.084447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.117749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.117774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.150984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.150997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.184330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.184424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.217694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.217708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.251067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.251081] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.284546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.284567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.317894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.317916] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.351260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.351283] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.384523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.384537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.417887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.417901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.451235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.451249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.484679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.484708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.518121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.518148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.551336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.551350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.584787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.584808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.618152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.618167] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.651541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.651562] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.684908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.684931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.718142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.718156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.751504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.751518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.784961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.784983] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.818354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.818476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.851607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.851621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.884974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.884989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.918338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.918353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.951696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.951710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.985224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.985255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.018623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.018654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.051787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.051801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.085276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.085301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.118646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.118670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.151874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.151888] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.185238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.185252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.218732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.218755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.251951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.251965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.285394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.285478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.318834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.318861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.352052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.352066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.385487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.385507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.418865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.418887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.452233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.452252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.485623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.485644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.519187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.519227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.552510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.552546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.586056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.586080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.619070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.619094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.652855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.652908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.685800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.685825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.719049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.719063] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.752543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.752557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.785831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.785851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.819262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.819289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.852994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.853048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.885866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.885880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.919357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.919404] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.952589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.952603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.985953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.985967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.019371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.019389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.052717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.052736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.086160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.086195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.119402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.119416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.152767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.152781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.186229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.186252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.220019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.220070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.252981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.252995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.286359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.286372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.319589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.319603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.353005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.353025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.386307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.386321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.419747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.419767] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.453587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.453624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.486520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.486541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.519858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.519880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.553682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.553718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.586524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.586540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.619863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.619879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.653237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.653255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.686634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.686651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.719938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.736553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1134.736590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.736648] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1134.755512] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1134.755551] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1134.755568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.755587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.755604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.755622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.755637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.755652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.755668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.755686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.755702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.755718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.755738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.755757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.755776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.755805] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.755828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.755853] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1134.755871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.756093] [drm:drm_mode_addfb2] [FB:75]
>[ 1134.756116] [drm:drm_mode_addfb2] [FB:78]
>[ 1134.803466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1134.803612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.803691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1134.803746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.803756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.803804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.803820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.803839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.803859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.803877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.803895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.803913] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.803930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.803948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.803965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.803982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.803986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.804003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.804006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.804024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.804041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.804058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.804075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.804093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.804110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.804128] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.804146] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.804163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.804182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.804201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.809335] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.809352] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.809366] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.809396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.809416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.809435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.809454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.809473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.809491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.809550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.809575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.809601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.809622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.809643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.809669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.809693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.811694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.811710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.811724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.811739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.813244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.813259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.813273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.814770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.814786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.816594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.819548] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.819603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.819622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.819647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.836344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.836369] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.836403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.853096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.853111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.886480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.886494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.919851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.919866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.953215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.953229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.986594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.986608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.019918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.019927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.053330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.053342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.086698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.086710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.120042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.120054] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.153410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.153421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.186781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.186793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.220144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.220156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.253515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.253654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.286823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.286832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.320186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.320195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.353567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.353576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.386905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.386914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.420268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.420277] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.453653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.453661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.487038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.487048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.520537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.520591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.554160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.554195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.587142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.587154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.620506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.620517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.653859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.653870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.687528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.687840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.721032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.721067] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.754341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.754376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.787385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.787399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.820741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.820754] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.854013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.854022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.887377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.887386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.920849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.920866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.954094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.954103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.987465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.987474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.020811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.020820] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.054191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.054200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.087650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.087664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.120978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.120991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.154342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.154354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.187726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.187740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.221400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.221434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.254844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.254879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.288156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.288191] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.321203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.321213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.354475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.354485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.387828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.387837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.421307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.421324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.455005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.455039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.488004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.488020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.521375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.521391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.554671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.554681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.588012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.588022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.621504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.621521] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.654729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.654738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.688113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.688122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.721544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.721559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.754908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.754924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.788270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.788285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.822025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.822060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.855010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.855025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.888340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.888353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.922114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.922157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.954997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.955006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.988352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.988361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.021732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.021741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.055084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.055093] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.088527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.088541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.122168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.122198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.155268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.155283] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.188554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.188568] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.221962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.221975] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.255258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.255266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.288620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.288629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.322119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.322137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.355375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.355383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.388732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.388741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.422080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.422089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.455443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.455452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.488888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.488901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.522290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.522299] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.555526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.555535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.588895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.588904] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.622349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.622363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.655713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.655726] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.689412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.689447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.722454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.722469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.755817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.755831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.789095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.789105] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.822624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.822645] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.856053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.856087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.889266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.889282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.922529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.922538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.955982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.955996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.989324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1137.989337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.023105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.023140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.056378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.056412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.089411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.089425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.122787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.122799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.156425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.156456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.189511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.189525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.222893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.222902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.256159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.256168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.289603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.289616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.322953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.322967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.356638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.356672] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.389744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.389760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.423064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.423079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.456337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.456346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.489700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.489709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.523065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.523073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.556535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.556551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.589798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.589806] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.623146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.623155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.656516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.656525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.689971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.689986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.723333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.723348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.756699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.756714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.790049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.790063] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.823392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.823405] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.857067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.857094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.890298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.890323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.923650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.923674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.956800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.956809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.990147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1138.990156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.023616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.023631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.056983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.056998] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.090239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.090248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.123593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.123602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.156956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.156965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.190325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.190334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.223876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.223894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.257081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.257095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.290415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.290424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.323965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.323984] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.357249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.357264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.390596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.390612] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.423968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.423982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.457323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.457338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.490683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.490698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.524037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.524051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.557497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.557517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.590781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.590837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.624153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.624162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.657403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.657411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.690766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.690775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.724214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.724228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.757603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.757618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.790982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.790996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.824306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.824320] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.857695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.857710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.891058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.891073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.924395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.924409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.957756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.957771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.991131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1139.991145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.024404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.024413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.057871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.057885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.091131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.091140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.124698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.124719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.158024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.158048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.191313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.191328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.224662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.224676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.258037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.258052] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.291400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.291414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.324747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.324756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.358076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.358090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.391399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.391408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.424952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.424970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.458218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.458233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.491582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.491597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.524866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.524875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.558249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.558262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.591599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.591608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.625022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.625034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.658728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.658762] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.691771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.691780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.725023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.725032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.758520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.758541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.791756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.791765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.825198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.825212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.858553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.858566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.891937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.891950] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.925517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.925544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.958757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.958780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.992054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.992069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.025695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.025730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.058711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.058723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.092067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.092079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.125653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.125678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.159309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.159343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.192221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.192236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.225479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.225488] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.258938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.258952] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.292196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.292205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.325645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.325658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.358992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.359002] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.392293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.392302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.425657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.425666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.459021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.459030] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.492384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.492393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.525815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.525828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.559154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.559166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.592539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.592552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.626145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.626170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.659225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.659234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.692566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.692575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.726078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.726094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.759288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.759296] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.792643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.792652] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.826084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.826096] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.859397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.859406] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.892741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.892750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.926183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.926196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.959582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.959598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1141.992831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1141.992839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.026274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.026287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.059715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.059735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.093104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.093113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.126282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.126290] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.159721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.159735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.193024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.193033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.226451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.226465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.260039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.260071] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.293105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.293114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.326458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.326467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.359928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.359944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.393186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.393195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.426632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.426646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.459913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.459921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.493276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.493285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.526733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.526748] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.560119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.560133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.593360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.593369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.626722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.626731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.660111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.660120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.693476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.693485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.726943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.726961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.760566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.760600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.793552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.793566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.826916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.826929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.860255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.860263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.893721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.893744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.927024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.927036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.960365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.960379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1142.993728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1142.993743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.027111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.027125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.060457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.060470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.093898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.093918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.127348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.127379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.160909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.160924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.193923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.193937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.227301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.227318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.260664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.260680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.294201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.294230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.327385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.327401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.360750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.360765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.394093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.394107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.427438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.427452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.460812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.460826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.494324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.494350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.527539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.527553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.560935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.560956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.594267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.594281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.627720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.627741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.661172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.661201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.694521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.694552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.727885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.727914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.761279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.761293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.794445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.794459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.827807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.827821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.861190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.861204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.894688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.894714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.928022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.928095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.961248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.961261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1143.994622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1143.994636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.027985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.027999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.061348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.061362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.094865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.094891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.128262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.128288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.161906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.161922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.194818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.194835] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.228388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.228421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.261746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.261780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.294891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.294905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.328341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.328363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.361694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.361715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.394982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.394996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.428497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.428523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.461696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.461710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.495058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.495072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.528579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.528606] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.561944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.561971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.595176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.595190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.628523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.628537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.661887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.661901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.695338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.695360] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.728669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.728689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.761955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.761969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.795338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.795362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.828731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.828747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.862082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1144.862200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1144.862243] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1144.862309] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1144.879157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1144.879177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1144.879197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1144.879214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1144.879232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1144.879248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1144.879263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1144.879281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1144.879304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1144.879325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1144.879345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1144.879366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1144.879385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1144.879404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1144.879433] [drm:intel_power_well_disable [i915]] disabling display
>[ 1144.879456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1144.879481] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1144.879497] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1144.879698] [drm:drm_mode_addfb2] [FB:75]
>[ 1144.879721] [drm:drm_mode_addfb2] [FB:78]
>[ 1144.920319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1144.920410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1144.920467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1144.920524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1144.920534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1144.920585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1144.920602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1144.920621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1144.920641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1144.920657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1144.920674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1144.920691] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1144.920706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1144.920722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1144.920736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1144.920754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1144.920757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1144.920776] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1144.920779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1144.920798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1144.920817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1144.920835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1144.920854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1144.920873] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1144.920891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1144.920909] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1144.920928] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1144.920946] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1144.920966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1144.920987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1144.925927] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1144.925944] [drm:intel_power_well_enable [i915]] enabling display
>[ 1144.925960] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1144.925991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1144.926010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1144.926029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1144.926048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1144.926067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1144.926086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1144.926106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1144.926167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1144.926192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1144.926216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1144.926237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1144.926265] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1144.926289] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1144.929392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1144.929412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1144.929431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1144.929452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1144.933159] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1144.933178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1144.933194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1144.935785] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1144.935805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1144.938700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1144.941637] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1144.941710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1144.941730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1144.941756] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1144.958433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1144.958458] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1144.958493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1144.975202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1144.975212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.008575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.008584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.041940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.041949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.075303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.075312] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.108682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.108697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.142187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.142204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.175410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.175424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.208775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.208789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.242151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.242166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.275487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.275501] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.308946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.308968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.342692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.342743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.375588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.375602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.408954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.408969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.442315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.442329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.475680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.475694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.509120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.509207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.542393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.542407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.575765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.575780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.609128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.609143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.642492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.642506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.675856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.675871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.709238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.709253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.742584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.742598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.775933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.775947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.809297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.809311] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.842669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.842684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.876229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.876258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.909497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.909520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.942763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.942778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1145.976126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1145.976141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.009493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.009507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.042839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.042853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.076396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.076424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.109680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.109698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.142956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.142966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.176319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.176328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.209683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.209692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.243104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.243119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.276807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.276843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.310109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.310125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.343230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.343246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.376458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.376467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.409839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.409848] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.443218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.443227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.476701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.476720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.510034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.510050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.543410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.543426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.576702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.576715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.610067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.610080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.643471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.643480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.676743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.676753] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.710127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.710136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.743590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.743607] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.776855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.776865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.810236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.810245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.843574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.843584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.877082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.877102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.910492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.910513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.944064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.944101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1146.977033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1146.977042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.010397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.010407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.043760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.043769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.077195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.077210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.110522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.110537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.143882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.143897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.177211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.177220] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.210538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.210547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.243902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.243911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.277410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.277428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.310762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.310780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.344031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.344040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.377393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.377403] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.410757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.410767] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.444228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.444246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.477872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.477908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.510961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.510977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.544207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.544216] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.577569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.577579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.610934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.610944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.644307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.644316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.677758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.677776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.711134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.711152] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.744525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.744543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.777747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.777756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.811112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.811121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.844475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.844485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.877876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.877889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.911220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.911233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.944562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.944573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1147.977925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1147.977934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.011306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.011315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.044713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.044728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.078388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.078421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.111441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.111455] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.144784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.144797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.178233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.178246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.211728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.211757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.244810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.244820] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.278242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.278264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.311711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.311731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.345389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.345427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.378265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.378274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.411621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.411630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.445106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.445126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.478760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.478796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.512110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.512147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.545538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.545574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.578535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.578551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.611828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.611837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.645249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.645263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.678956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.679003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.712106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.712130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.745311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.745320] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.778641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.778651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.811985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.811994] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.845364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.845373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.878732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.878743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.912100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.912109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.945476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.945486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1148.978982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1148.979004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.012345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.012408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.045678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.045697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.079042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.079061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.112424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.112441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.145722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.145738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.178979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.178989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.212344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.212353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.245699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.245708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.279062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.279071] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.312596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.312614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.345794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.345803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.379157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.379166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.412522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.412532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.445886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.445896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.479248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.479257] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.512715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.512732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.545987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.545998] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.579465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.579482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.612753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.612766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.646085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.646094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.679497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.679509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.712839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.712852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.746175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.746184] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.779598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.779614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.812893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.812902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.846319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.846333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.880017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.880053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.913381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.913504] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.946462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.946478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1149.979695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1149.979705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.013080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.013089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.046407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.046434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.079861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.079877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.113301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.113322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.146689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.146705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.179962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.179978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.213327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.213343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.246989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.247026] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.280055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.280070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.313495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.313515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.346682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.346691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.380050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.380060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.413414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.413424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.446897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.446914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.480261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.480278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.513650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.513665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.546949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.546963] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.580223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.580233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.613588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.613598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.646956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.646965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.680320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.680329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.713683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.713693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.747047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.747056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.780503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.780517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.813843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.813857] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.847256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.847265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.880522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.880532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.913939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.913953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.947241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.947251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.980678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.980694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.014151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.014173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.047644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.047660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.081100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.081136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.114428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.114465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.147523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.147539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.181176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.181212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.214235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.214251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.247610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.247625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.281212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.281244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.314697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.314734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.347711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.347727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.381332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.381368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.414430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.414448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.447671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.447680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.481093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.481106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.514477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.514491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.547953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.547969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.581608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.581645] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.615013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.615049] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.647948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.647964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.681352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.681371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.714991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.715027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.748043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.748059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.781450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.781470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.815083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.815120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.848111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.848126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.881694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.881710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.914749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.914758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.948279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.948300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1151.981479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1151.981489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.014845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.014855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.048208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.048217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.081587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.081596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.114936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.114945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.148299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.148309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.181783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.181802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.215018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.215027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.248469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.248478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.281780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.281789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.315192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.315207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.348955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.348991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.381977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.382013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.415364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.415383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.448648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.448662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.481987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.482001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.515443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.515462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.549076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.549113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.582433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.582469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.615485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.615494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.648745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.648755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.682189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.682204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.715919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.715955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.749225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.749261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.782300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.782316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.815692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.815708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.849341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.849377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.882771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.882807] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.916074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.916110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.949441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.949485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1152.982370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1152.982379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.015756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.015766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.049204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.049220] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.082939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.082976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.115832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.115842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.149195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.149204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.182677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.182693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.215921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.215930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.249276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.249285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.282655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.282664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.316007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.316017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.349370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.349379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.382734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.382744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.416097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.416107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.449462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.449471] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.482827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.482836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.516201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.516210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.549543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.549552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.582969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.582983] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.616430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.616449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.649880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.649902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.683025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.683035] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.716367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.716376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.749747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.749756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.783170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.783185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.816535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.816550] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.850191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.850207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.883202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.883211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.916565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.916574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.950326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.950362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1153.983299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1153.983310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.017126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.017173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.050030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.050042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.083378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.083389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.116814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.116828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.150505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.150541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.183554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.183570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.216814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.216823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.250177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.250186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.283562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.283571] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.316994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.317011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.350258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.350268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.383627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.383637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.416991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.417000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.450354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.450364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.483733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.483743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.517082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.517091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.550445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.550454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.583800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.583810] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.617163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.617172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.650532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.650541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.683896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.683906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.717260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.717270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.750623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.750632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.783987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.783997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.817470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.817487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.850754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.850764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.884070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.884079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.917458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.917467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.950836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1154.950846] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1154.984295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1154.984376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1154.984419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1154.984491] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1155.001387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1155.001406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.001427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.001444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.001463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.001478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.001493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.001510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.001527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.001544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.001560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.001576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.001590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.001604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.001632] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.001654] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.001675] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1155.001691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.004011] [IGT] kms_flip: exiting, ret=0
>[ 1155.024253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.024271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.024289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.024308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.024323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.024340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.024356] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.024371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.024386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.024400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.024414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.024418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.024431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.024434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.024453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.024471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.024490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.024508] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.024527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.024546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.024564] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.024583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.024601] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.024621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.024642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.024697] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.024713] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.024752] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.024785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.024802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.024817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.024832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.024845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.024861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.024878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.024894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.024909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.024923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.024936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.024953] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.024969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.026960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.026975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.026988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.027005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.028515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.028529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.028542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.030037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.030054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.031866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.034714] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.034775] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.034791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.034814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.034861] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.034877] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.051521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.051545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.051580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.051707] Console: switching to colour frame buffer device 240x75
>[ 1155.184954] Console: switching to colour dummy device 80x25
>[ 1155.185045] [IGT] kms_flip: executing
>[ 1155.199223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1155.199252] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1155.201332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1155.201352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1155.203426] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1155.203433] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1155.205509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1155.205529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1155.207603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1155.207608] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1155.207613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1155.207628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1155.207652] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1155.208678] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1155.209567] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1155.209585] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1155.209603] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1155.209620] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1155.210605] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1155.210622] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1155.211672] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1155.211675] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1155.211803] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1155.211807] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1155.211815] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1155.211818] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1155.211825] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1155.211828] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1155.211840] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1155.211845] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.211849] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1155.211853] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1155.211858] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1155.211862] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1155.211873] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1155.211878] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1155.211882] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1155.211886] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1155.211891] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1155.211895] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1155.211899] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1155.211904] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1155.211908] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1155.211912] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1155.211916] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1155.211920] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1155.211925] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1155.211929] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1155.211933] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1155.211938] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1155.211942] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1155.211946] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1155.211950] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1155.211955] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1155.211959] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1155.211963] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1155.211967] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1155.211972] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1155.211976] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1155.212024] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1155.212048] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1155.213790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1155.213808] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1155.215793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1155.215798] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1155.217794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1155.217812] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1155.219795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1155.219800] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1155.219804] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1155.221068] [IGT] kms_flip: starting subtest modeset-vs-vblank-race-interruptible
>[ 1155.221562] [drm:drm_mode_addfb2] [FB:77]
>[ 1155.221584] [drm:drm_mode_addfb2] [FB:79]
>[ 1155.264164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.264217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.268377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.268403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.268443] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.287304] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.287326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.287343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.287362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.287379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.287397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.287413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.287428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.287444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.287462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.287478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.287494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.287510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.287525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.287538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.287566] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.287587] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.287609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.287627] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.287688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1155.287815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1155.287913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.287929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.287995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.288018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.288037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.288057] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.288073] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.288090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.288106] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.288122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.288138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.288152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.288165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.288169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.288183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.288186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.288200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.288214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.288233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.288251] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.288271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.288289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.288309] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.288328] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.288347] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.288367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.288387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.290977] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.290993] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.291006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.291044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.291060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.291075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.291089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.291103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.291117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.291133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.291148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.291162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.291176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.291188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.291204] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.291219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.294309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.294328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.294346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.294367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.296973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.296992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.297007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.299573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.299592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.302468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.305391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.305426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.305443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.305465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.305505] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.305522] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.322172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.322198] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.322235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.338921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.338964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.355523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.355546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.355594] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.373425] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.373448] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.373464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.373483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.373500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.373517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.373532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.373547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.373562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.373580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.373596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.373611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.373627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.373641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.373654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.373681] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.373702] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.373724] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.373740] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.373857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.373871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.373940] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.373965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.373992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.374022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.374046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.374072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.374098] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.374123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.374148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.374172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.374195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.374202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.374224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.374230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.374253] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.374277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.374300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.374323] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.374349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.374372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.374395] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.374416] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.374439] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.374466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.374493] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.374568] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.374591] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.374612] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.374649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.374672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.374695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.374717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.374737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.374780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.374804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.374829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.374854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.374875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.374898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.374924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.374947] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.378026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.378044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.378060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.378077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.381784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.381804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.381823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.384329] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.384348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.387268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.390203] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.390279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.390296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.390319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.390359] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.390378] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.407013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.407038] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.407074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.440414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.440459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.457063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.457087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.457133] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.476008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.476030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.476046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.476065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.476082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.476100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.476116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.476130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.476149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.476171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.476192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.476212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.476232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.476251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.476268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.476295] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.476318] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.476342] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.476361] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.476412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.476421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.476468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.476487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.476507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.476529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.476548] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.476568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.476587] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.476606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.476625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.476644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.476663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.476667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.476685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.476697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.476714] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.476730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.476744] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.476798] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.476821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.476841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.476862] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.476882] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.476902] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.476925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.476948] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.477013] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.477036] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.477056] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.477095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.477117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.477140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.477162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.477184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.477207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.477232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.477256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.477280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.477301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.477322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.477339] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.477354] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.480433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.480452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.480468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.480485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.484197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.484216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.484232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.485734] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
>[ 1155.485764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.489673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.493691] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.493746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.493808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.493846] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.494001] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.494019] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.510489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.510514] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.510549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.543867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.543911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.560523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.560549] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.560597] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.580540] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.580562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.580578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.580598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.580614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.580632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.580647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.580662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.580681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.580703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.580723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.580744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.580806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.580830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.580853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.580898] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.580934] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.580967] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.580996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.581062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.581072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.581116] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.581132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.581152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.581174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.581193] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.581214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.581234] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.581254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.581274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.581294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.581312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.581317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.581336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.581340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.581360] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.581379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.581398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.581417] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.581437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.581456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.581476] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.581495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.581515] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.581535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.581557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.581604] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.581621] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.581636] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.581666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.581686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.581705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.581725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.581745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.581792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.581820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.581845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.581871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.581893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.581914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.581947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.581969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.585034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.585050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.585065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.585079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.588755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.588786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.588802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.591369] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.591387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.594263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.597209] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.597271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.597286] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.597307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.597342] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.597357] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.614014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.614038] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.614071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.647426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.647470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.664057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.664082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.664131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.682994] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.683016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.683033] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.683052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.683069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.683087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.683102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.683121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.683141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.683162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.683183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.683203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.683224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.683243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.683259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.683287] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.683309] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.683334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.683352] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.683406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.683415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.683460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.683480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.683500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.683522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.683541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.683560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.683580] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.683599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.683618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.683637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.683655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.683659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.683678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.683681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.683701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.683720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.683739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.683757] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.683820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.683846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.683873] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.683896] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.683921] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.683948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.683976] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.684046] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.684071] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.684096] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.684136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.684162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.684184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.684213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.684233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.684254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.684278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.684301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.684324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.684343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.684363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.684387] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.684408] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.687502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.687521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.687537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.687554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.691295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.691321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.691336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.693918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.693938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.696830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.699762] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.699840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.699860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.699886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.699927] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.699946] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.716583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.716609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.716647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.749990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.750034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.766616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.766641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.766683] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.785547] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.785569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.785585] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.785605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.785621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.785639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.785655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.785670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.785685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.785703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.785720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.785735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.785751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.785765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.785823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.785867] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.785903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.785937] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.785966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.786038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.786047] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.786091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.786107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.786125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.786145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.786161] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.786178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.786195] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.786210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.786226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.786241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.786255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.786259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.786273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.786277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.786296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.786316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.786336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.786355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.786376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.786395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.786421] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.786438] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.786453] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.786470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.786488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.786531] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.786545] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.786557] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.786583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.786598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.786612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.786626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.786639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.786654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.786670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.786685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.786699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.786712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.786725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.786741] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.786756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.788761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.788789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.788803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.788818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.792485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.792504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.792520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.795082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.795102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.797982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.800930] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.800992] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.801008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.801030] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.801069] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.801085] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.817734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.817760] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.817843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.851141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.851184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.867775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.867815] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.867861] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.886719] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.886742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.886762] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.886828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.886850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.886868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.886884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.886903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.886923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.886945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.886967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.886988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.887008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.887025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.887044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.887072] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.887094] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.887119] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.887137] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.887191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.887200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.887247] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.887267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.887287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.887310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.887329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.887349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.887368] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.887388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.887408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.887428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.887447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.887451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.887470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.887473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.887494] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.887513] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.887534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.887552] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.887572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.887591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.887611] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.887637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.887654] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.887671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.887689] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.887731] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.887745] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.887758] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.887810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.887832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.887852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.887873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.887893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.887914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.887937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.887960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.887982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.888001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.888021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.888045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.888066] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.891134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.891152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.891167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.891183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.894903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.894922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.894941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.897507] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.897526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1155.900408] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1155.903330] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1155.903365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1155.903381] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1155.903403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1155.903442] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1155.903458] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1155.920111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.920137] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.920174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.953508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.953551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.970152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1155.970175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1155.970221] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1155.988519] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1155.988542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1155.988561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1155.988583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.988602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.988623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.988643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.988662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.988681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1155.988703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.988723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.988744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.988764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.988783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.988845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.988889] [drm:intel_power_well_disable [i915]] disabling display
>[ 1155.988924] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1155.988948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1155.988967] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1155.989015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1155.989023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1155.989063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1155.989079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1155.989095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1155.989114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1155.989129] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1155.989147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1155.989165] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1155.989183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1155.989201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1155.989219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1155.989237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1155.989241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.989258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1155.989262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1155.989280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1155.989298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1155.989316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1155.989334] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1155.989352] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1155.989368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1155.989386] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1155.989404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1155.989422] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1155.989440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1155.989460] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1155.989502] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1155.989517] [drm:intel_power_well_enable [i915]] enabling display
>[ 1155.989531] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1155.989559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1155.989577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1155.989595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1155.989613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1155.989631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1155.989648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1155.989668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1155.989687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1155.989706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1155.989724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1155.989739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1155.989758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1155.989776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1155.992895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1155.992914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1155.992932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.992951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1155.996630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1155.996649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1155.996665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1155.999245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1155.999263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.002135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.005084] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.005144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.005161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.005182] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.005221] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.005238] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.021888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.021913] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.021947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.055272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.055322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.071929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.071952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.071997] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.090850] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.090874] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.090893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.090915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.090935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.090956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.090975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.090995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.091014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.091035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.091056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.091076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.091097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.091115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.091132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.091159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.091182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.091206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.091224] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.091269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.091290] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.091340] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.091356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.091373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.091391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.091405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.091420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.091436] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.091450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.091467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.091485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.091502] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.091505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.091522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.091526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.091543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.091561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.091578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.091595] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.091613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.091630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.091647] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.091665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.091682] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.091700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.091719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.091762] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.091776] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.091830] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.091869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.091891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.091913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.091934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.091954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.091976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.091999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.092022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.092044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.092064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.092084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.092108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.092129] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.095211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.095229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.095247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.095265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.098969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.098988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.099004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.101570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.101589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.104483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.107417] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.107493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.107510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.107532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.107570] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.107595] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.124237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.124263] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.124300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.157616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.157660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.174271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.174295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.174341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.192867] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.192891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.192911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.192932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.192952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.192974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.192993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.193013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.193032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.193054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.193074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.193094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.193115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.193133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.193150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.193177] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.193199] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.193224] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.193242] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.193294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.193304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.193349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.193369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.193389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.193411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.193430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.193456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.193474] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.193489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.193503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.193516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.193529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.193532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.193545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.193548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.193562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.193574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.193587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.193599] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.193614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.193627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.193640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.193652] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.193664] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.193679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.193695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.193737] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.193750] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.193763] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.193787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.193844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.193868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.193892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.193915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.193939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.193965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.193990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.194015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.194037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.194059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.194085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.194109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.197201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.197220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.197236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.197256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.200954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.200974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.200993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.203562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.203582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.206460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.209384] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.209417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.209433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.209455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.209493] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.209509] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.226164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.226190] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.226225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.259547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.259590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.276198] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.276224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.276271] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.295057] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.295079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.295095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.295115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.295131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.295149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.295165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.295180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.295195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.295213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.295229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.295245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.295261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.295275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.295289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.295315] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.295337] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.295359] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.295376] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.295424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.295433] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.295474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.295490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.295508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.295527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.295542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.295558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.295574] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.295589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.295604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.295618] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.295632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.295635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.295649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.295652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.295674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.295686] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.295698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.295710] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.295725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.295738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.295750] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.295762] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.295775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.295790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.295848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.295916] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.295941] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.295963] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.296000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.296024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.296047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.296070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.296092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.296115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.296139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.296163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.296187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.296208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.296229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.296254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.296277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.299326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.299345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.299364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.299384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.303091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.303110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.303126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.305689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.305707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.308589] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.311509] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.311546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.311562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.311584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.311621] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.311637] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.328291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.328317] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.328351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.361674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.361718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.378333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.378361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.378407] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.397269] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.397291] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.397308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.397327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.397344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.397362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.397377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.397393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.397409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.397426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.397443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.397458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.397474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.397492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.397510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.397538] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.397560] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.397585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.397603] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.397654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.397664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.397710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.397730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.397749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.397771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.397790] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.397851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.397880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.397908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.397934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.397960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.397984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.397991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.398014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.398021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.398051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.398073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.398096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.398117] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.398142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.398164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.398187] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.398208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.398231] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.398256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.398281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.398346] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.398369] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.398391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.398428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.398451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.398473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.398493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.398514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.398536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.398560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.398584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.398607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.398629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.398650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.398675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.398698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.401750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.401770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.401786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.401803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.404441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.404461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.404480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.407049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.407068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.409940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.412527] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.412596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.412613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.412635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.412675] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.412691] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.429348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.429374] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.429409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.462759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.462803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.479386] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.479412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.479454] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.497455] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.497477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.497494] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.497513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.497530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.497548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.497563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.497582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.497602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.497630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.497651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.497672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.497692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.497711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.497730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.497758] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.497780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.497805] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.497868] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.498158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.498172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.498243] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.498270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.498297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.498327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.498352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.498384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.498408] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.498431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.498454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.498475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.498496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.498501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.498522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.498527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.498549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.498570] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.498591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.498612] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.498633] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.498654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.498675] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.498696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.498716] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.498739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.498764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.498849] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.498872] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.498895] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.498933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.498957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.498980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.499003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.499026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.499049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.499074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.499099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.499123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.499145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.499350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.499367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.499382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.502463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.502483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.502502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.502522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.506225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.506244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.506260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.508849] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.508867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.511754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.514688] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.514761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.514777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.514797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.514976] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.514994] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.531506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.531532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.531567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.564883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.564927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.581543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.581567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.581614] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.600468] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.600491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.600507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.600527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.600543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.600560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.600576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.600590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.600606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.600624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.600640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.600656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.600672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.600686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.600700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.600727] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.600748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.600769] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.600786] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.600891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.600906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.600974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.600999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.601026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.601056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.601080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.601106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.601132] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.601156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.601181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.601204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.601228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.601234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.601256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.601262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.601285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.601308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.601331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.601354] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.601379] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.601402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.601425] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.601449] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.601470] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.601495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.601523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.601594] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.601619] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.601644] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.601683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.601708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.601739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.601760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.601780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.601802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.601845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.601868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.601893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.601915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.601938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.601964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.601987] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.605076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.605095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.605111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.605127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.608846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.608865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.608880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.611471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.611491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.614398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.617335] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.617408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.617425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.617446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.617495] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.617520] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.634159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.634185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.634219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.667563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.667607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.684204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.684227] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.684279] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.703143] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.703166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.703186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.703207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.703227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.703249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.703268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.703287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.703306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.703328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.703348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.703369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.703389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.703408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.703424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.703452] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.703474] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.703498] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.703516] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.703570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.703580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.703625] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.703645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.703665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.703687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.703705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.703725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.703745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.703764] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.703783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.703802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.703821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.703861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.703889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.703896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.703924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.703948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.703973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.703996] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.704023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.704051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.704074] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.704094] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.704115] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.704140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.704166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.704230] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.704253] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.704275] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.704311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.704333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.704353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.704374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.704393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.704415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.704440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.704463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.704486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.704505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.704525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.704547] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.704569] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.707611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.707631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.707646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.707663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.711360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.711379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.711395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.713983] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.714003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.716878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.719813] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.719887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.719904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.719926] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.719964] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.719981] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.736631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.736656] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.736691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.770018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.770062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.786668] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.786694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.786741] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.805563] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.805585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.805601] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.805621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.805638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.805655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.805671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.805686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.805705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.805727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.805748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.805768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.805788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.805807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.805825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.805898] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.805932] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.805968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.805996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.806065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.806079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.806147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.806172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.806197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.806226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.806248] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.806280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.806302] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.806324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.806345] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.806365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.806384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.806390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.806409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.806414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.806435] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.806455] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.806475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.806493] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.806516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.806535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.806555] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.806574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.806594] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.806615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.806638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.806701] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.806724] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.806745] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.806781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.806803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.806823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.806862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.806883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.806906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.806931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.806956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.806980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.807000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.807021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.807047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.807068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.810156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.810174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.810190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.810206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.813910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.813929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.813945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.816518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.816537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.819415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.822336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.822374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.822393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.822419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.822459] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.822479] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.839109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.839133] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.839169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.872509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.872558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.889161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.889183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.889229] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1156.908082] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1156.908104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1156.908120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1156.908140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.908156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.908173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.908189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.908203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.908219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.908237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.908253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.908269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.908285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.908299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.908313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.908339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1156.908361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1156.908385] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.908403] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1156.908447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.908457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1156.908502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1156.908529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1156.908546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1156.908565] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1156.908579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1156.908595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1156.908611] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1156.908625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1156.908640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1156.908654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1156.908667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1156.908670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.908683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1156.908686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1156.908703] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1156.908721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1156.908738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1156.908755] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1156.908773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1156.908789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1156.908807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1156.908824] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1156.908879] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1156.908908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.908933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1156.908998] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1156.909022] [drm:intel_power_well_enable [i915]] enabling display
>[ 1156.909044] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1156.909081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1156.909104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1156.909124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1156.909147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1156.909167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1156.909190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1156.909214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1156.909238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1156.909261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.909280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1156.909300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1156.909323] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1156.909345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1156.912455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1156.912472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1156.912487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.912501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1156.916233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1156.916252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1156.916268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1156.918869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1156.918888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1156.921774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1156.924733] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1156.924783] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1156.924800] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1156.924825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1156.924914] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1156.924938] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1156.941512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1156.941536] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1156.941569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1156.974940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1156.974983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1156.991570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1156.991593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1156.991644] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.010524] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.010545] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.010561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.010581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.010598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.010619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.010639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.010658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.010678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.010699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.010720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.010740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.010761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.010780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.010796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.010824] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.010886] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.010922] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.010951] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.011018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.011028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.011072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.011092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.011112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.011134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.011153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.011174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.011194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.011214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.011234] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.011254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.011273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.011277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.011297] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.011301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.011320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.011340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.011360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.011379] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.011399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.011418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.011437] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.011456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.011476] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.011496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.011517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.011564] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.011581] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.011596] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.011625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.011645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.011665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.011684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.011704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.011731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.011750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.011768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.011787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.011805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.011823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.011843] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.011883] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.014957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.014975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.014991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.015007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.018678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.018697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.018713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.021276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.021293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.024186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.027133] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.027196] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.027213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.027235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.027287] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.027304] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.043941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.043966] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.044001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.077334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.077378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.093979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.094003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.094048] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.112897] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.112919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.112935] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.112956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.112976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.112998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.113017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.113036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.113055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.113077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.113097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.113118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.113138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.113157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.113173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.113200] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.113223] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.113247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.113265] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.113327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.113336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.113381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.113399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.113417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.113437] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.113453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.113470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.113487] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.113503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.113519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.113538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.113557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.113560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.113579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.113583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.113602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.113621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.113640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.113659] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.113678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.113697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.113716] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.113735] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.113754] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.113774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.113794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.113845] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.113900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.113921] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.113959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.113982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.114004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.114025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.114045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.114067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.114090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.114113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.114136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.114155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.114175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.114199] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.114220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.117318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.117338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.117357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.117377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.120021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.120040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.120056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.122609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.122628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.125502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.128424] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.128460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.128476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.128498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.128538] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.128557] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.145204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.145231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.145267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.178600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.178644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.195246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.195268] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.195314] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.214190] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.214212] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.214229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.214248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.214265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.214282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.214297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.214312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.214328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.214346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.214363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.214378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.214394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.214409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.214422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.214449] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.214470] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.214494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.214512] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.214566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.214575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.214621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.214641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.214660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.214683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.214701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.214721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.214740] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.214759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.214779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.214798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.214816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.214820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.214839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.214886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.214911] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.214934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.214955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.214977] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.214999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.215020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.215040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.215060] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.215079] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.215103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.215126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.215191] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.215213] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.215236] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.215263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.215278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.215292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.215306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.215319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.215333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.215349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.215363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.215377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.215390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.215403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.215419] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.215434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.218588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.218607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.218623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.218639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.222354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.222373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.222389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.225018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.225038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.227939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.230887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.230949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.230965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.230988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.231026] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.231043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.247691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.247717] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.247751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.281089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.281135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.297735] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.297758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.297804] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.316633] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.316655] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.316671] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.316691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.316708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.316725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.316741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.316755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.316771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.316789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.316805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.316821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.316836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.316850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.316906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.316948] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.316982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.317015] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.317042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.317122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.317137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.317206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.317236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.317260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.317286] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.317306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.317329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.317350] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.317372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.317392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.317413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.317432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.317437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.317457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.317462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.317483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.317502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.317522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.317540] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.317563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.317582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.317602] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.317620] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.317641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.317662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.317685] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.317748] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.317771] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.317792] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.317828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.317850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.317890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.317910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.317932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.317953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.317977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.318001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.318026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.318045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.318067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.318092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.318114] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.321196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.321215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.321232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.321251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.324954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.324974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.324993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.327571] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.327591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.330486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.333410] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.333445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.333462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.333484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.333521] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.333545] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.350178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.350202] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.350236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.383612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.383657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.400232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.400255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.400302] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.419170] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.419192] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.419209] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.419229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.419245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.419263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.419282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.419301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.419321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.419342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.419363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.419384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.419404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.419423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.419439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.419468] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.419490] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.419515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.419533] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.419586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.419596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.419642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.419662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.419681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.419703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.419722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.419742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.419761] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.419780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.419799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.419818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.419837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.419841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.419859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.419888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.419918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.419945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.419971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.419994] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.420021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.420043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.420067] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.420089] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.420113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.420140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.420168] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.420238] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.420577] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.420599] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.420637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.420660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.420681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.420702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.420721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.420743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.420767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.420790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.420813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.420833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.420853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.420903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.420924] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.424140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.424159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.424175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.424191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.427910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.427929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.427948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.430546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.430566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.433461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.436384] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.436420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.436440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.436465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.436506] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.436526] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.453155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.453179] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.453213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.486520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.486565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.503213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.503239] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.503287] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.522151] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.522173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.522189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.522209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.522225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.522243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.522258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.522273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.522292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.522314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.522334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.522355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.522375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.522394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.522411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.522439] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.522461] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.522485] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.522503] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.522556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.522566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.522619] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.522636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.522653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.522671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.522685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.522700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.522716] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.522730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.522744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.522758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.522771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.522774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.522787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.522790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.522803] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.522820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.522837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.522854] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.522872] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.522924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.522948] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.522970] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.522991] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.523016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.523041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.523106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.523130] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.523152] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.523189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.523212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.523235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.523255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.523276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.523296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.523319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.523342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.523365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.523384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.523404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.523427] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.523449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.526641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.526659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.526681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.526699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.530401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.530420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.530436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.533027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.533047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.535942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.538876] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.538958] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.538976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.539000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.539038] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.539055] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.555695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.555721] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.555755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.589100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.589144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.605732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.605756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.605804] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.624672] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.624694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.624709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.624729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.624745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.624762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.624777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.624792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.624808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.624825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.624842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.624857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.624873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.624930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.624952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.624996] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.625032] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.625071] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.625099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.625165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.625174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.625216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.625233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.625250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.625269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.625285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.625301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.625318] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.625333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.625348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.625363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.625376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.625380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.625394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.625397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.625412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.625425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.625439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.625452] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.625469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.625482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.625496] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.625509] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.625523] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.625538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.625556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.625601] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.625616] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.625630] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.625655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.625670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.625689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.625708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.625727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.625746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.625767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.625788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.625808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.625827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.625845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.625866] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.625909] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.628996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.629013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.629027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.629042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.632715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.632736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.632755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.635336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.635355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.638238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.641171] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.641247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.641263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.641285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.641323] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.641339] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.660090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.660116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.660152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.691380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.691430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.708033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.708057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.708104] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.726960] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.726982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.726999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.727018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.727035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.727056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.727075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.727095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.727114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.727136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.727156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.727177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.727197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.727216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.727232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.727261] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.727283] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.727308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.727325] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.727373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.727383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.727429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.727449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.727469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.727491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.727510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.727530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.727549] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.727568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.727587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.727606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.727624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.727628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.727647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.727651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.727670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.727689] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.727708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.727727] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.727746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.727764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.727783] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.727803] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.727822] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.727842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.727862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.727960] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.727984] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.728006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.728048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.728073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.728096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.728118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.728141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.728164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.728192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.728218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.728243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.728264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.728286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.728320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.728339] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.731415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.731434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.731450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.731466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.734131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.734149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.734165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.736754] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.736775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.739657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.742580] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.742623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.742639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.742659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.742695] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.742710] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.759351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.759376] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.759413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.792740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.792784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.809395] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.809419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.809466] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.828307] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.828329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.828345] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.828364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.828381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.828399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.828414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.828429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.828445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.828463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.828479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.828499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.828520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.828539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.828556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.828584] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.828607] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.828633] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.828650] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.828702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.828711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.828757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.828777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.828797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.828819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.828837] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.828857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.828876] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.828939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.828965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.828988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.829011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.829017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.829039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.829045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.829067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.829089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.829110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.829132] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.829156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.829178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.829199] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.829220] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.829242] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.829267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.829293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.829363] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.829384] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.829399] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.829428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.829448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.829467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.829487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.829506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.829526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.829546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.829567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.829588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.829607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.829626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.829647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.829675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.832747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.832766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.832782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.832798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.836496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.836514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.836530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.839122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.839142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.842023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.844973] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.845038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.845054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.845074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.845112] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.845130] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.861783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.861808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.861843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.895202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.895247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.911848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1157.911871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1157.912043] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1157.930931] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1157.930954] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1157.930970] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1157.930990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.931006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.931024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.931039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.931054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.931070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.931088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.931104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.931120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.931135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.931149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.931163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.931190] [drm:intel_power_well_disable [i915]] disabling display
>[ 1157.931211] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1157.931232] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.931249] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1157.931299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.931308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1157.931349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1157.931365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1157.931384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1157.931407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1157.931426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1157.931445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1157.931464] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1157.931484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1157.931503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1157.931522] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1157.931541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1157.931545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.931563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1157.931567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1157.931586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1157.931605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1157.931624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1157.931643] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1157.931662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1157.931681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1157.931700] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1157.931719] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1157.931738] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1157.931758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1157.931778] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1157.931825] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1157.931840] [drm:intel_power_well_enable [i915]] enabling display
>[ 1157.931856] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1157.931885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1157.931939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1157.931966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1157.931987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1157.932010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1157.932032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1157.932059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1157.932084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1157.932109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.932129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1157.932150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1157.932176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1157.932198] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1157.935290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1157.935309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1157.935325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.935341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1157.939038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1157.939064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1157.939079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1157.941648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1157.941666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1157.944546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1157.947481] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1157.947556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1157.947573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1157.947595] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1157.947642] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1157.947668] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1157.964295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1157.964319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1157.964352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1157.997688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1157.997731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.014348] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.014371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.014422] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.032556] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.032578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.032595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.032615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.032632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.032649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.032664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.032679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.032695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.032713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.032729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.032745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.032761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.032775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.032789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.032816] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.032837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.032858] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.032875] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.032972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.032987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.033051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.033069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.033091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.033120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.033138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.033158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.033178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.033197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.033217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.033237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.033256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.033261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.033279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.033283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.033310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.033326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.033341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.033355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.033371] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.033385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.033399] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.033412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.033425] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.033442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.033458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.033501] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.033515] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.033528] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.033555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.033573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.033591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.033609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.033627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.033645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.033664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.033682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.033702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.033719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.033737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.033756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.033773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.036852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.036871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.036887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.036942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.039548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.039568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.039587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.042159] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.042178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.045063] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.048015] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.048074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.048094] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.048119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.048169] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.048196] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.064816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.064842] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.064879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.098201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.098244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.114848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.114871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.114993] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.133848] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.133870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.133886] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.133905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.133965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.133995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.134019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.134043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.134067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.134094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.134121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.134147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.134172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.134193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.134215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.134257] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.134290] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.134321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.134348] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.134428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.134442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.134508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.134531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.134563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.134589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.134609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.134632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.134653] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.134675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.134695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.134715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.134734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.134740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.134759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.134764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.134786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.134804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.134824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.134843] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.134865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.134884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.134904] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.134947] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.134968] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.134992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.135018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.135081] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.135104] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.135126] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.135162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.135185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.135205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.135225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.135244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.135266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.135289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.135312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.135335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.135354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.135374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.135396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.135418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.138515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.138533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.138550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.138568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.142263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.142282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.142298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.144863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.144880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.147754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.150688] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.150764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.150780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.150803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.150850] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.150876] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.167513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.167537] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.167570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.200892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.200981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.217548] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.217577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.217627] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.236502] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.236525] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.236545] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.236566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.236586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.236607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.236627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.236646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.236665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.236686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.236707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.236727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.236748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.236766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.236785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.236813] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.236835] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.236860] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.236878] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.236970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.236993] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.237058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.237080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.237105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.237133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.237154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.237178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.237200] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.237222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.237243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.237264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.237283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.237288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.237308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.237313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.237334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.237353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.237373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.237392] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.237414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.237433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.237454] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.237473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.237493] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.237514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.237538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.237601] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.237624] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.237645] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.237681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.237702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.237723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.237743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.237763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.237783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.237807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.237830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.237852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.237871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.237891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.237914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.237960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.241044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.241063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.241080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.241106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.244781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.244800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.244815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.247383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.247401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.250300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.253241] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.253310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.253326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.253348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.253400] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.253424] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.270052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.270077] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.270112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.303440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.303483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.320078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.320102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.320151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.339013] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.339037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.339056] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.339078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.339098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.339119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.339138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.339158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.339177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.339198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.339219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.339239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.339260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.339279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.339294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.339322] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.339345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.339370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.339396] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.339445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.339454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.339497] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.339514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.339532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.339551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.339566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.339582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.339599] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.339614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.339629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.339644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.339657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.339661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.339674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.339678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.339692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.339705] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.339719] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.339732] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.339748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.339761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.339775] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.339788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.339801] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.339817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.339834] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.339878] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.339892] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.339905] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.339974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.339997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.340021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.340043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.340066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.340088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.340114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.340139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.340165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.340186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.340209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.340236] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.340258] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.343346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.343363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.343377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.343392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.346093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.346112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.346131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.348699] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.348718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.351597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.354518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.354555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.354571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.354592] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.354640] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.354665] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.371300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.371327] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.371364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.404698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.404741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.421342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.421364] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.421416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.440264] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.440286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.440302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.440322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.440338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.440356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.440372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.440387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.440403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.440421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.440437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.440457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.440477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.440496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.440513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.440541] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.440564] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.440588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.440606] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.440650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.440660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.440705] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.440725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.440745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.440767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.440785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.440805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.440824] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.440843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.440863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.440881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.440900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.440904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.440923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.440962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.440992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.441017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.441043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.441066] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.441093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.441115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.441139] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.441162] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.441185] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.441213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.441241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.441312] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.441336] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.441360] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.441401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.441425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.441451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.441473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.441496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.441518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.441544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.441569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.441602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.441621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.441641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.441664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.441686] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.444775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.444794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.444810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.444826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.448531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.448550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.448566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.451128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.451147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.454027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.456979] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.457036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.457052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.457074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.457121] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.457146] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.473782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.473808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.473845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.507159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.507203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.523815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.523839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.523888] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.542708] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.542730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.542747] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.542766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.542783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.542801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.542816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.542831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.542847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.542865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.542885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.542906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.542927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.542991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.543015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.543057] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.543091] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.543125] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.543154] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.543220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.543234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.543301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.543324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.543351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.543380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.543402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.543427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.543450] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.543474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.543496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.543519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.543540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.543546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.543567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.543572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.543595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.543616] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.543638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.543658] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.543683] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.543703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.543725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.543746] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.543768] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.543799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.543822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.543885] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.543907] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.543929] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.543988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.544010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.544033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.544053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.544075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.544096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.544121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.544145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.544170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.544190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.544211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.544237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.544258] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.547362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.547381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.547397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.547413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.551119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.551138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.551154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.553721] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.553740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.556604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.559537] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.559614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.559631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.559653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.559701] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.559726] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.576358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.576384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.576421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.609735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.609779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.626394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.626418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.626469] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.645298] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.645320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.645336] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.645355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.645372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.645389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.645405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.645424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.645443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.645465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.645485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.645506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.645526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.645545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.645561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.645589] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.645611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.645636] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.645654] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.645705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.645714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.645760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.645780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.645799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.645822] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.645841] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.645860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.645879] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1158.645898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1158.645918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.645944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.646001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.646008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.646029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.646035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.646056] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.646076] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.646097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.646116] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1158.646139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.646158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.646178] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1158.646198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1158.646217] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1158.646241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.646264] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1158.646328] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.646349] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.646372] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.646399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.646414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.646427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.646441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.646454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.646468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.646483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.646497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.646512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.646524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.646537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.646553] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1158.646568] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.649626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.649644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.649659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.649676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.653378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.653398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.653417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.655984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.656003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.658875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.661823] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1158.661885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.661902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1158.661925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.662139] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1158.662164] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1158.678627] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.678654] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.678691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.712052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.728666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1158.728693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.728734] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1158.746789] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1158.746811] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1158.746831] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.746853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.746873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.746895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.746915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.746935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.746997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.747029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.747058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.747085] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.747111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.747133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.747157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.747201] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.747235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.747268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1158.747296] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.747517] [drm:drm_mode_addfb2] [FB:77]
>[ 1158.747541] [drm:drm_mode_addfb2] [FB:78]
>[ 1158.771862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1158.771983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.772072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1158.772155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.772165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.772212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.772229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.772247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.772265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.772280] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.772296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.772311] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1158.772326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1158.772340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.772354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.772368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.772371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.772384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.772387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.772400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.772413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.772429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.772447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1158.772465] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.772483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.772500] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1158.772518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1158.772535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1158.772554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.772574] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1158.775192] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.775209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.775223] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.775254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.775273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.775292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.775311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.775330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.775348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.775369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.775389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.775409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.775427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.775442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.775462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1158.775481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.778601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.778618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.778641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.778658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.782342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.782359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.782374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.784987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.785007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.787883] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.790832] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1158.790891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.790906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1158.790930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.807632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.807656] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1158.807690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.824369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.824413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.824464] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1158.824485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.824532] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1158.843422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1158.843442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.843462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.843479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.843497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.843513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.843527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.843543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.843561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.843577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.843592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.843608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.843622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.843635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.843662] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.843684] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.843708] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1158.843725] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.843777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.843786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.843832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.843852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.843871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.843893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.843912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.843932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.843951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1158.844005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1158.844041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.844062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.844085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.844092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.844113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.844119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.844142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.844162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.844184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.844203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1158.844227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.844246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.844268] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1158.844288] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1158.844309] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1158.844334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.844360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1158.844422] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.844443] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.844466] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.844503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.844525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.844545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.844566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.844585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.844606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.844630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.844653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.844676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.844694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.844714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.844739] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1158.844760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.847859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.847878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.847895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.847911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.850493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.850511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.850526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.853126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.853146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.856028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.858942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1158.859045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.859065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1158.859090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.875787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.875813] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1158.875848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.909182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.909226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.909271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1158.909293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.909343] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1158.928200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1158.928220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1158.928242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.928262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.928284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.928303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.928322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.928341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.928363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.928383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.928404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.928424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.928443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.928459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.928487] [drm:intel_power_well_disable [i915]] disabling display
>[ 1158.928509] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1158.928533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1158.928550] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1158.928595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.928605] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1158.928650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1158.928670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1158.928690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1158.928712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1158.928731] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1158.928751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1158.928777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1158.928794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1158.928810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1158.928824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1158.928837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1158.928841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.928853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1158.928857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1158.928870] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1158.928883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1158.928896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1158.928908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1158.928923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1158.928936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1158.928949] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1158.929002] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1158.929021] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1158.929045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.929069] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1158.929119] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1158.929140] [drm:intel_power_well_enable [i915]] enabling display
>[ 1158.929160] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1158.929198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1158.929221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1158.929241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1158.929261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1158.929281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1158.929304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1158.929328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1158.929351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1158.929375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.929396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1158.929417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1158.929442] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1158.929465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1158.932562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1158.932582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1158.932601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.932621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1158.936321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1158.936340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1158.936357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1158.938927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1158.938945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1158.941862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1158.944785] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1158.944820] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1158.944837] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1158.944858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1158.961558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1158.961581] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1158.961615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1158.994983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1158.995027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1158.995082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1158.995104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1158.995151] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.014020] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.014039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.014059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.014076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.014094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.014109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.014124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.014140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.014157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.014173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.014189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.014205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.014219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.014232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.014259] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.014280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.014302] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.014317] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.014360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.014369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.014410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.014426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.014444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.014465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.014484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.014504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.014523] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.014543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.014562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.014581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.014599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.014603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.014629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.014632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.014649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.014664] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.014678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.014691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.014707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.014721] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.014734] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.014747] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.014759] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.014775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.014791] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.014832] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.014845] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.014858] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.014882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.014896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.014910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.014923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.014936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.014950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.015007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.015030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.015052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.015071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.015091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.015115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.015136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.018233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.018252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.018268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.018287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.021998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.022017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.022034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.024626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.024646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.027524] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.030457] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.030533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.030550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.030575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.047266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.047290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.047324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.080659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.080708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.080760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.080781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.080832] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.099688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.099707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.099727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.099744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.099761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.099777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.099791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.099806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.099824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.099840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.099856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.099871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.099885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.099899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.099926] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.099947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.100009] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.100038] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.100115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.100131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.100200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.100225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.100252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.100282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.100305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.100330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.100354] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.100378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.100401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.100423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.100444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.100450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.100472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.100477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.100508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.100527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.100547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.100566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.100589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.100608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.100629] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.100647] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.100668] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.100689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.100713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.100776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.100798] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.100820] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.100856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.100878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.100898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.100919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.100938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.100960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.101004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.101029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.101054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.101074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.101095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.101121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.101142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.104234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.104253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.104269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.104285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.108008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.108027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.108043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.110638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.110658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.113567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.116502] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.116577] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.116594] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.116616] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.133310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.133335] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.133371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.166740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.166785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.166838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.166859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.166904] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.185781] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.185802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.185824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.185844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.185865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.185884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.185904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.185923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.185944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.185965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.186031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.186060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.186084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.186107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.186145] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.186167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.186189] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.186205] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.186257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.186266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.186308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.186324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.186342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.186362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.186378] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.186395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.186418] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.186433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.186447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.186461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.186474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.186478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.186490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.186494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.186507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.186520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.186533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.186546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.186561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.186574] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.186587] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.186600] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.186612] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.186628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.186644] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.186687] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.186700] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.186714] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.186742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.186760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.186778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.186797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.186815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.186832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.186851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.186870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.186890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.186907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.186925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.186944] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.186962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.190046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.190064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.190079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.190098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.193769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.193787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.193803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.196372] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.196390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.199262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.202216] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.202271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.202288] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.202310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.219013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.219039] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.219073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.252407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.252452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.252503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.252524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.252575] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.271450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.271469] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.271489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.271506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.271524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.271539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.271554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.271570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.271588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.271604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.271619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.271635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.271653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.271672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.271700] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.271723] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.271747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.271764] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.271815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.271825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.271870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.271890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.271910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.271932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.271951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.271970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.272028] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.272053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.272085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.272105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.272125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.272131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.272151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.272156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.272176] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.272196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.272216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.272235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.272258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.272278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.272298] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.272317] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.272337] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.272360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.272383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.272446] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.272464] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.272478] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.272503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.272518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.272531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.272545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.272558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.272572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.272587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.272602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.272616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.272629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.272642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.272658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.272675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.275756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.275775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.275791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.275808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.279510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.279530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.279549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.282221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.282240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.285112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.288041] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.288069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.288086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.288108] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.304823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.304849] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.304884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.338201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.338245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.338299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.338324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.338375] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.357230] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.357249] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.357269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.357286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.357304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.357320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.357334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.357350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.357368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.357384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.357399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.357415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.357429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.357442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.357469] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.357490] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.357511] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.357526] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.357577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.357586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.357627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.357643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.357661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.357679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.357695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.357710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.357729] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.357749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.357768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.357787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.357806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.357810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.357828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.357832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.357851] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.357870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.357889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.357908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.357934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.357951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.357966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.357980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.358034] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.358058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.358082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.358146] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.358166] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.358188] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.358226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.358248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.358270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.358291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.358311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.358333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.358350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.358365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.358379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.358393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.358405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.358421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.358435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.361510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.361529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.361545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.361561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.365343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.365362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.365377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.367942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.367960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.370867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.373788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.373824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.373840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.373862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.390563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.390587] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.390621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.423956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.424044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.424122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.424154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.424210] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.441037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.441056] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.441078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.441098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.441119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.441139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.441158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.441177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.441199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.441220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.441240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.441260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.441279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.441296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.441323] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.441346] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.441371] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.441388] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.441440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.441450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.441496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.441515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.441535] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.441557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.441583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.441601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.441618] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.441632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.441647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.441664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.441681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.441684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.441702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.441705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.441723] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.441741] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.441758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.441775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.441793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.441810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.441828] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.441845] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.441862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.441881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.441899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.441941] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.441955] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.441968] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.442036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.442059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.442081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.442101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.442122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.442143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.442167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.442190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.442213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.442233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.442252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.442276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.442297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.445373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.445391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.445407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.445424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.449118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.449137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.449154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.451722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.451748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.454622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.457556] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.457631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.457648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.457676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.474374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.474403] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.474448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.507772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.507815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.507867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.507888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.507933] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.526782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.526800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.526821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.526837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.526855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.526870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.526885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.526901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.526918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.526935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.526951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.526966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.526980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.527042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.527084] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.527120] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.527154] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.527180] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.527237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.527246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.527288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.527305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.527323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.527343] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.527359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.527375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.527392] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.527411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.527430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.527450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.527477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.527480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.527497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.527501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.527520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.527537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.527555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.527573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.527590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.527608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.527625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.527643] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.527661] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.527679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.527698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.527741] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.527755] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.527769] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.527797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.527815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.527833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.527851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.527869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.527887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.527906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.527925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.527945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.527962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.527980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.528022] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.528045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.531135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.531153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.531169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.531188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.534868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.534885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.534901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.537466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.537484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.540357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.543285] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.543316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.543335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.543361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.560052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.560088] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.560139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.593495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.593540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.593594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.593615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.593662] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.612534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.612553] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.612574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.612591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.612608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.612624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.612638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.612654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.612672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.612688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.612703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.612719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.612733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.612746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.612773] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.612795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.612816] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.612834] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.612888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.612898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.612941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.612957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.612974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.612996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.613057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.613084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.613108] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.613131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.613154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.613176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.613196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.613204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.613224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.613231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.613252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.613273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.613295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.613316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.613340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.613361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.613382] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.613405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.613434] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.613456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.613482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.613547] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.613570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.613592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.613633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.613656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.613680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.613701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.613720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.613735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.613750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.613765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.613779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.613792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.613805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.613821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.613836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.616915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.616934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.616950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.616967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.620689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.620708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.620725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.623296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.623314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.626209] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.629152] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.629219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.629235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.629257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.645960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.645986] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.646069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.679343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.679387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.679441] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.679463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.679513] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.697687] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.697706] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.697726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.697743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.697760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.697775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.697790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.697805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.697823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.697839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.697854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.697874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.697893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.697911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.697938] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.697960] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.697985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.698001] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.698285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.698299] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.698364] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.698389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.698414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.698441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.698463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.698487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.698511] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.698534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.698556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.698578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.698599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.698605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.698626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.698631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.698653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.698674] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.698695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.698716] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.698740] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.698761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.698781] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.698801] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.698822] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.698845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.698870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.698932] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.698954] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.698976] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.699036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.699062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.699086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.699109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.699132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.699155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.699181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.699206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.699231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.699252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.699275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.699300] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.699324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.702659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.702678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.702694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.702710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.705284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.705300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.705314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.707876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.707894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.710770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.713703] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.713779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.713796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.713818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.730520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.730545] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.730580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.763904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.763948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.764002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.764069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.764228] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.782698] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.782716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.782737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.782754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.782772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.782787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.782802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.782818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.782836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.782853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.782868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.782884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.782898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.782912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.782939] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.782960] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.782981] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.782996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.783109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.783120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.783165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.783185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.783206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.783229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.783255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.783273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.783290] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.783306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.783320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.783333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.783346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.783350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.783362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.783365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.783379] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.783392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.783410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.783427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.783446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.783463] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.783482] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.783499] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.783518] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.783536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.783556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.783598] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.783612] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.783627] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.783654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.783672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.783691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.783709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.783728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.783745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.783765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.783785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.783804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.783821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.783839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.783859] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.783876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.786953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.786972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.786988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.787007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.790726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.790745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.790761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.793342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.793361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.796234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.799166] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.799193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.799210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.799231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.815935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.815961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.815995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.849332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.849377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.849428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.849449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.849495] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.868376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.868395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.868416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.868432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.868450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.868465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.868480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.868496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.868514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.868530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.868546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.868561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.868580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.868597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.868625] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.868647] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.868673] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.868689] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.868740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.868750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.868796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.868816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.868835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.868857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.868876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.868894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.868914] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.868933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.868952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.868971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.868990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.868994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.869012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.869053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.869081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.869105] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.869129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.869151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.869183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.869203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.869224] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.869244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.869264] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.869288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.869312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.869376] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.869397] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.869420] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.869459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.869482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.869504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.869526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.869549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.869571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.869596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.869620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.869644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.869667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.869687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.869705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.869720] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.872794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.872813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.872828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.872844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.876544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.876569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.876592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.879169] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.879187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.882075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.885015] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.885086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.885103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.885125] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.901826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.901852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.901886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.935223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.935267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.935330] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1159.935356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1159.935401] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1159.954242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1159.954261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1159.954281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.954298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.954315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.954331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.954345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.954361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.954379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.954395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.954410] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.954426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.954440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.954454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.954481] [drm:intel_power_well_disable [i915]] disabling display
>[ 1159.954503] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1159.954523] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.954538] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1159.954587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1159.954596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1159.954638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1159.954653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1159.954671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1159.954690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1159.954706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1159.954722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1159.954738] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1159.954754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1159.954769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1159.954783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1159.954797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1159.954801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.954814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1159.954818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1159.954832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1159.954846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1159.954859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1159.954880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1159.954895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1159.954907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1159.954924] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1159.954942] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1159.954959] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1159.954977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1159.954996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1159.955083] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1159.955104] [drm:intel_power_well_enable [i915]] enabling display
>[ 1159.955124] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1159.955163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1159.955185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1159.955206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1159.955227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1159.955247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1159.955268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1159.955293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1159.955316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1159.955339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1159.955359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1159.955378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1159.955404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1159.955428] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1159.958516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1159.958535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1159.958553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.958573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1159.962273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1159.962292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1159.962308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1159.964875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1159.964893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1159.967770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1159.970708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1159.970780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1159.970797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1159.970820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1159.987530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1159.987555] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1159.987589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.020919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.020963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.021016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.021074] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.021251] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.039713] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.039731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.039751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.039768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.039786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.039801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.039816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.039832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.039849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.039866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.039882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.039897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.039912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.039925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.039952] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.039973] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.040003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.040026] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.040141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.040156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.040226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.040252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.040275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.040296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.040312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.040329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.040346] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.040362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.040378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.040392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.040407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.040411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.040424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.040428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.040448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.040467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.040487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.040506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.040527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.040546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.040565] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.040585] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.040605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.040625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.040646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.040700] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.040713] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.040727] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.040753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.040770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.040784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.040802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.040819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.040836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.040856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.040875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.040894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.040912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.040929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.040948] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.040967] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.044060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.044081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.044100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.044120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.047800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.047819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.047835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.050424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.050444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.053329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.056277] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.056339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.056357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.056379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.073081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.073107] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.073141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.106479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.106523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.106575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.106596] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.106642] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.125507] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.125526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.125546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.125563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.125580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.125595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.125610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.125626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.125643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.125660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.125676] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.125692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.125706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.125720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.125747] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.125768] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.125789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.125804] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.125855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.125867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.125923] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.125939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.125957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.125976] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.125991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.126008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.126024] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.126077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.126100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.126122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.126144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.126151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.126172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.126178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.126200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.126221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.126243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.126264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.126288] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.126309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.126331] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.126352] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.126373] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.126398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.126423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.126493] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.126517] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.126541] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.126582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.126614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.126636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.126657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.126679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.126701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.126726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.126748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.126764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.126776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.126794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.126814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.126830] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.129899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.129918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.129934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.129950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.133654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.133673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.133690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.136274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.136292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.139165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.142113] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.142175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.142192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.142214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.158916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.158943] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.158980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.192306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.192349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.192403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.192425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.192466] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.210691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.210709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.210729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.210747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.210764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.210779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.210794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.210811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.210829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.210845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.210861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.210877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.210891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.210905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.210932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.210953] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.210975] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.210990] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.211086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.211102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.211157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.211174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.211192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.211212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.211228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.211245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.211262] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.211278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.211294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.211313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.211341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.211345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.211359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.211363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.211377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.211391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.211404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.211417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.211432] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.211445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.211458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.211470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.211483] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.211498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.211514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.211557] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.211570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.211582] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.211613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.211636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.211651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.211665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.211683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.211700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.211721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.211740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.211760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.211777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.211795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.211814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.211831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.214888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.214906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.214921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.214938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.218624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.218640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.218655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.221209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.221227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.224089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.227005] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.227080] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.227098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.227121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.243792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.243819] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.243856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.277213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.277267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.277328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.277351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.277405] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.296215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.296234] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.296255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.296272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.296290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.296305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.296320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.296336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.296354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.296370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.296385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.296401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.296415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.296429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.296457] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.296479] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.296502] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.296517] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.296561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.296574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.296615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.296630] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.296648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.296668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.296683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.296699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.296715] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.296730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.296745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.296760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.296774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.296778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.296792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.296795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.296809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.296823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.296837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.296855] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.296875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.296894] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.296913] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.296932] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.296951] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.296971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.296992] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.297038] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.297097] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.297119] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.297163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.297188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.297211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.297240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.297261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.297282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.297306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.297329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.297352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.297372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.297392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.297416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.297437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.300499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.300519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.300538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.300558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.304272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.304291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.304310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.306789] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.306810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.309695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.312619] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.312652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.312669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.312691] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.329421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.329447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.329481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.362810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.362860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.362907] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.362928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.362974] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.381816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.381835] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.381856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.381873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.381891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.381906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.381921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.381937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.381958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.381979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.381999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.382019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.382038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.382099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.382141] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.382176] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.382209] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.382234] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.382303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.382319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.382386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.382409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.382435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.382464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.382487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.382512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.382535] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.382559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.382581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.382604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.382625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.382631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.382652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.382657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.382680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.382701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.382723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.382743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.382769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.382790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.382813] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.382833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.382856] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.382879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.382905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.382974] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.382997] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.383021] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.383086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.383112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.383134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.383165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.383185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.383207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.383232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.383257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.383281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.383301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.383322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.383348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.383369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.386449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.386467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.386483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.386503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.390192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.390210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.390226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.392795] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.392814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.395692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.398612] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.398650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.398667] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.398688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.415393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.415420] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.415455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.448774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.448818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.448873] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.448895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.448944] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.467762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.467782] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.467803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.467823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.467845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.467864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.467884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.467902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.467924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.467945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.467965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.467985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.468004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.468023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.468095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.468134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.468169] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.468195] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.468273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.468288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.468357] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.468383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.468411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.468441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.468466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.468493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.468518] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.468544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.468569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.468593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.468616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.468622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.468645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.468651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.468675] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.468699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.468723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.468747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.468773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.468796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.468820] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.468843] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.468865] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.468890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.468917] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.468988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.469013] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.469043] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.469105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.469129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.469152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.469175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.469198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.469221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.469247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.469272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.469297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.469319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.469341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.469367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.469391] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.472478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.472496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.472512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.472529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.476236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.476254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.476269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.478833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.478851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.481726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.484649] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.484684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.484700] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.484722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.501426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.501453] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.501490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.534811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.534855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.534908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.534933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.534984] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.553825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.553844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.553864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.553881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.553898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.553913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.553928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.553944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.553961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.553977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.553993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.554008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.554022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.554036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.554107] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.554142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.554175] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.554193] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.554243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.554252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.554294] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.554313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.554334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.554356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.554376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.554396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.554416] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.554436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.554455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.554475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.554495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.554499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.554518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.554522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.554542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.554561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.554582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.554601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.554620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.554639] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.554659] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.554678] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.554698] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.554718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.554739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.554785] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.554800] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.554815] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.554845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.554865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.554884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.554904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.554924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.554944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.554971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.554987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.555003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.555017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.555031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.555047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.555087] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.558173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.558192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.558208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.558224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.560783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.560805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.560819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.563385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.563403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.566280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.569232] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.569289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.569304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.569328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.586031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.586057] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.586139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.619429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.619473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.619526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.619546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.619597] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.637473] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.637492] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.637512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.637529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.637547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.637562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.637576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.637592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.637610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.637626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.637642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.637657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.637672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.637685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.637712] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.637733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.637754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.637770] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.637820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.637830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.637871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.637887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.637904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.637923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.637939] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.637955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.637971] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.637990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.638010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.638029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.638047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.638089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.638115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.638121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.638146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.638168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.638191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.638213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.638237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.638259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.638281] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.638302] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.638324] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.638349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.638374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.638445] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.638469] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.638490] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.638529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.638545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.638560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.638575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.638589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.638604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.638621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.638637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.638656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.638676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.638694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.638715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.638734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.641830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.641850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.641869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.641889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.645588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.645607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.645625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.648208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.648227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.651099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.654038] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.654138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.654166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.654251] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.670850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.670876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.670910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.704235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.704279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.704333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.704358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.704409] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.722892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.722911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.722931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.722948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.722966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.722982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.722996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.723012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.723030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.723046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.723062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.723122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.723145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.723166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.723209] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.723242] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.723275] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.723292] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.723342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.723352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.723393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.723409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.723428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.723448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.723468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.723488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.723508] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.723528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.723555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.723572] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.723587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.723591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.723605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.723609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.723623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.723636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.723649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.723662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.723677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.723691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.723704] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.723717] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.723729] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.723745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.723761] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.723803] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.723816] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.723830] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.723855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.723869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.723884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.723897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.723911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.723925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.723941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.723955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.723970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.723982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.723996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.724011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.724026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.727116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.727135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.727151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.727167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.730821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.730839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.730858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.733428] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.733447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.736303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.739251] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.739313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.739330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.739352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.756051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.756092] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.756126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.789441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.789485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.789539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.789564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.789616] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.808471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.808490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.808510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.808527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.808545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.808560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.808575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.808591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.808609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.808625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.808641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.808657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.808671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.808685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.808711] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.808733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.808754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.808769] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.808819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.808829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.808870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.808886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.808904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.808923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.808939] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.808955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.808971] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.808986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.809001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.809015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.809029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.809033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.809046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.809050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.809064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.809122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.809144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.809165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.809189] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.809210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.809232] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.809253] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.809273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.809298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.809324] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.809393] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.809418] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.809442] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.809474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.809494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.809514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.809541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.809557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.809573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.809590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.809605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.809619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.809632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.809645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.809661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.809677] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.812831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.812850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.812866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.812882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.816581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.816598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.816613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.819297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.819316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.822193] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.825141] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.825203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.825223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.825249] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.841944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.841971] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.842006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.875333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.875377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.875429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.875452] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.875502] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.894355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.894373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.894393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.894410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.894427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.894442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.894457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.894472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.894490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.894506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.894521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.894537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.894551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.894565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.894591] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.894612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.894633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.894648] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.894712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.894722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.894765] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.894781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.894799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.894818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.894834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.894851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.894867] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.894883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.894898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.894912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.894926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.894930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.894944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.894947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.894961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.894975] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.894988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.895001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.895017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.895031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.895045] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.895059] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.895077] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.895138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.895165] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.895232] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.895254] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.895276] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.895318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.895351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.895373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.895394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.895413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.895436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.895454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.895469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.895483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.895497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.895509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.895525] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.895540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.898605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.898624] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.898640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.898656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.901259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.901278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.901297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.903867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.903886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.906767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.909702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.909777] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.909794] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.909816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.926519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.926545] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.926583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.959894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.959943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.959990] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.960013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.960065] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.978950] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.978969] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.978989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.979006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.979024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.979039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.979054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.979070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.979133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.979161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.979189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.979215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.979236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.979258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.979299] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.979339] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.979367] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.979390] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.979452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.979467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.979529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.979550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.979574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.979600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.979621] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.979644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.979665] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1160.979686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1160.979707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.979727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.979746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.979752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.979771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.979776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.979797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.979816] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.979836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.979854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.979877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.979895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.979915] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1160.979934] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1160.979954] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1160.979975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.979999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1160.980049] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.980071] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.980115] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.980153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.980176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.980197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.980219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.980239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.980263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.980287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.980312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.980337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.980356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.980378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.980403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1160.980425] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.983518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.983537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.983553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.983569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.987270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.987289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.987305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.989869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.989887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.992766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.995687] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1160.995723] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.995747] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1160.995770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.012466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.012491] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.012528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.045842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.045892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.045945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.045967] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.046012] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.064314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.064333] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.064353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.064370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.064387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.064403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.064417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.064435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.064464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.064482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.064498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.064514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.064528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.064541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.064568] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.064589] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.064610] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.064626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.064672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.064682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.064729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.064749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.064768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.064790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.064809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.064829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.064848] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.064867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.064886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.064905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.064924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.064928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.064947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.064950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.064970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.064988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.065007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.065026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.065045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.065064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.065083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.065145] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.065172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.065200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.065230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.065295] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.065318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.065341] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.065379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.065400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.065423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.065444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.065464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.065485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.065509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.065533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.065556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.065575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.065595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.065620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.065641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.068735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.068754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.068770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.068786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.072478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.072495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.072509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.075118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.075138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.078026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.080955] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.080984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.081002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.081029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.097728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.097754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.097788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.131124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.131168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.131222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.131247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.131289] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.150140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.150159] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.150179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.150196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.150214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.150229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.150244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.150260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.150277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.150294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.150310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.150325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.150339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.150353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.150379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.150400] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.150422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.150437] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.150486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.150495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.150537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.150553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.150570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.150589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.150604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.150620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.150636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.150651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.150666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.150680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.150694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.150698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.150711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.150714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.150729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.150742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.150756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.150769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.150785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.150804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.150823] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.150842] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.150862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.150882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.150902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.150947] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.150963] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.150978] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.151007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.151027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.151046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.151065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.151085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.151154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.151184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.151210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.151235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.151258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.151280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.151307] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.151330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.154413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.154431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.154447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.154463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.157035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.157051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.157067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.159682] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.159708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.162604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.165551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.165614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.165631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.165653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.182356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.182382] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.182417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.215741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.215785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.215840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.215865] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.215905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.234762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.234781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.234801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.234818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.234835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.234850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.234864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.234880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.234898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.234917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.234938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.234959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.234978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.234995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.235022] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.235045] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.235069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.235086] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.235199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.235214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.235284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.235308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.235335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.235366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.235389] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.235414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.235438] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.235463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.235485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.235508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.235529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.235535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.235556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.235562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.235585] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.235606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.235628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.235649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.235674] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.235694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.235716] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.235737] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.235758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.235782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.235808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.235878] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.235902] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.235925] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.235965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.235990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.236011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.236034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.236055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.236086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.236132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.236156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.236180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.236200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.236221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.236247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.236269] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.239344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.239362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.239379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.239399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.243128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.243148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.243167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.245670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.245690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.248604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.251540] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.251613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.251630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.251652] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.268355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.268381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.268417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.301743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.301787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.301841] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.301864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.301903] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.319875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.319894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.319914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.319931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.319949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.319964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.319978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.319994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.320012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.320028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.320044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.320059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.320073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.320091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.320164] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.320198] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.320420] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.320446] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.320525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.320539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.320585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.320602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.320620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.320640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.320659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.320679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.320699] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.320718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.320737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.320756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.320775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.320779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.320797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.320801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.320820] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.320839] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.320858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.320877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.320896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.320915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.320940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.320955] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.320969] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.320985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.321002] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.321043] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.321056] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.321069] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.321093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.321134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.321160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.321181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.321201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.321224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.321249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.321273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.321297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.321317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.321339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.321364] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.321386] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.324747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.324766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.324782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.324800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.327383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.327400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.327415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.329979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.329996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.332871] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.335792] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.335828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.335844] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.335866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.352573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.352598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.352633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.385961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.386007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.386062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.386085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.386284] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.404876] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.404895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.404915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.404935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.404957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.404976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.404996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.405015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.405036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.405057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.405077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.405098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.405155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.405181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.405223] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.405448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.405482] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.405508] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.405577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.405587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.405630] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.405647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.405665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.405685] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.405701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.405718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.405735] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.405751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.405767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.405788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.405801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.405805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.405817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.405820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.405838] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.405856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.405873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.405890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.405908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.405925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.405942] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.405960] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.405977] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.405995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.406014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.406057] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.406071] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.406085] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.406152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.406175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.406197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.406217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.406238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.406259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.406283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.406306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.406330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.406349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.406370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.406392] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.406415] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.409506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.409526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.409545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.409565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.413267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.413286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.413302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.415867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.415886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.418761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.421682] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.421720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.421740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.421766] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.438461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.438487] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.438521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.471851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.471896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.471949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.471972] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.472018] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.490847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.490866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.490886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.490903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.490920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.490935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.490950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.490966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.490983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.490999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.491015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.491030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.491044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.491058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.491085] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.491106] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.491163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.491190] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.491274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.491288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.491356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.491379] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.491406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.491435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.491457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.491482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.491506] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.491530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.491552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.491574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.491595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.491601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.491623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.491628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.491651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.491672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.491695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.491715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.491746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.491765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.491785] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.491804] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.491824] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.491845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.491869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.491932] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.491954] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.491975] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.492013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.492035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.492055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.492076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.492096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.492135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.492160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.492185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.492209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.492229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.492250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.492276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.492297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.495385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.495404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.495420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.495437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.499152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.499171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.499187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.501759] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.501777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.504652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.507574] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.507609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.507626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.507648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.524353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.524379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.524414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.557740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.557783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.557836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.557859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.557905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.576761] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.576780] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.576800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.576817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.576834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.576850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.576864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.576880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.576898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.576914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.576930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.576949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.576969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.576986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.577014] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.577036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.577062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.577078] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.577178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.577193] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.577252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.577270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.577289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.577309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.577325] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.577342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.577359] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.577375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.577392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.577407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.577422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.577426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.577440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.577444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.577459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.577473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.577487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.577501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.577518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.577533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.577548] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.577567] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.577587] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.577607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.577629] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.577675] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.577696] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.577710] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.577736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.577752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.577766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.577780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.577798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.577818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.577844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.577862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.577876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.577890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.577903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.577920] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.577935] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.581018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.581037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.581055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.581075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.584792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.584811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.584827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.587390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.587409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.590290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.593231] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.593300] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.593317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.593339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.610037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.610062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.610096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.643445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.643489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.643540] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.643561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.643607] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.662468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.662487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.662507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.662524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.662542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.662558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.662573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.662589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.662607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.662624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.662640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.662655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.662670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.662684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.662711] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.662732] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.662753] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.662769] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.662811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.662821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.662862] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.662878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.662896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.662915] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.662930] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.662946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.662962] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.662978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.662993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.663007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.663021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.663025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.663038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.663042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.663056] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.663070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.663084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.663098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.663114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.663166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.663189] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.663211] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.663233] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.663257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.663283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.663351] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.663375] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.663601] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.663637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.663652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.663667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.663681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.663694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.663709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.663730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.663754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.663773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.663786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.663799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.663816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.663831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.666912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.666931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.666947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.666966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.670654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.670672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.670687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.673341] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.673362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.676241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.679185] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.679251] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.679267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.679289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.695992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.696018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.696055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.729373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.729417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.729470] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.729493] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.729539] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.748402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.748421] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.748441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.748458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.748476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.748491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.748506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.748522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.748539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.748556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.748572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.748587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.748601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.748615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.748642] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.748663] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.748684] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.748699] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.748741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.748750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.748792] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.748808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.748825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.748844] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.748859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.748876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.748892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.748910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.748930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.748949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.748968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.748972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.748991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.748994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.749014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.749033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.749052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.749071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.749090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.749109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.749128] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.749185] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.749211] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.749240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.749267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.749337] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.749362] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.749386] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.749427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.749738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.749759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.749781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.749800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.749823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.749847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.749870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.749894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.749913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.749933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.749958] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.749979] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.753069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.753088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.753104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.753120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.756759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.756777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.756793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.759375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.759402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.762292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.765226] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.765302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.765319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.765341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.782043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.782069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.782104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.815424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.815467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.815521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.815546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.815594] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.833905] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.833924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.833944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.833961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.833978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.833997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.834017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.834036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.834057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.834078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.834099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.834119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.834179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.834205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.834249] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.834446] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.834478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.834502] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.834573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.834583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.834624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.834640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.834657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.834676] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.834691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.834707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.834725] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.834743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.834761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.834779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.834796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.834800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.834818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.834822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.834840] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.834858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.834876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.834893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.834911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.834929] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.834947] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.834965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.834983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.835002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.835021] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.835064] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.835078] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.835092] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.835120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.835165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.835193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.835215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.835240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.835262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.835288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.835314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.835348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.835368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.835390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.835415] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.835437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.838799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.838818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.838834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.838850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.842556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.842575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.842592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.845177] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.845197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.848068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.851008] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.851077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.851094] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.851115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.867819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.867846] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.867883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.901206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.901249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.901302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.901324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.901370] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.920233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1161.920251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1161.920272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.920289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.920306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.920322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.920336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.920353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.920370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.920387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.920403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.920418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.920432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.920446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.920473] [drm:intel_power_well_disable [i915]] disabling display
>[ 1161.920494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1161.920515] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.920530] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1161.920581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.920591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1161.920632] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1161.920648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.920665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.920684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.920700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.920716] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.920732] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1161.920747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.920762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.920776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1161.920790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.920794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.920807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.920811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1161.920825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1161.920838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.920852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.920865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.920882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1161.920895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.920909] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1161.920923] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1161.920936] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1161.920952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.920970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1161.921014] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1161.921028] [drm:intel_power_well_enable [i915]] enabling display
>[ 1161.921041] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1161.921067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1161.921083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1161.921097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1161.921112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1161.921125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1161.921179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1161.921207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1161.921234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1161.921259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.921282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1161.921311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1161.921336] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1161.921358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1161.924449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1161.924469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1161.924485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.924501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1161.928211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1161.928230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1161.928246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1161.930748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1161.930768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1161.933668] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1161.936593] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1161.936626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1161.936643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1161.936665] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1161.953359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1161.953384] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1161.953420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1161.986754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1161.986797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1161.986851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1161.986873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1161.986918] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1162.005777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1162.005797] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.005819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.005839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.005860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.005880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.005899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.005918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.005939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.005960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.005980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.006001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.006020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.006038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.006066] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.006089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.006115] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1162.006131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.006426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1162.006441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.006506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.006529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.006554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.006580] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.006601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.006624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.006646] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1162.006668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1162.006689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.006710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.006729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.006735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.006755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.006760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.006782] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.006801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.006822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.006841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.006864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.006883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.006903] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1162.006923] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1162.006943] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1162.006966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.006991] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1162.007053] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.007074] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.007096] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.007133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.007176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.007199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.007221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.007241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.007264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.007289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.007313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.007337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.007357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.007379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.007405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1162.007426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.010518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.010537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.010553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.010570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.014272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.014291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.014307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.016871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.016890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.019771] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.022692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1162.022727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.022742] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1162.022762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.039471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.039498] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1162.039535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.072861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1162.072905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.072959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1162.072981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.073027] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1162.090908] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1162.090927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.090947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.090963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.090981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.090995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.091010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.091026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.091043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.091060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.091075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.091091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.091105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.091118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.091145] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.091211] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.091245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1162.091272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.091539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1162.091553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.091611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.091627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.091645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.091665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.091682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.091700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.091718] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1162.091735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1162.091753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.091770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.091787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.091791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.091808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.091811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.091829] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.091846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.091864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.091881] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.091899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.091916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.091933] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1162.091951] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1162.091968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1162.091986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.092005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1162.092047] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.092061] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.092075] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.092102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.092120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.092137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.092181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.092209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.092231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.092258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.092282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.092306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.092327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.092348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.092375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1162.092396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.095480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.095500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.095519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.095539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.099238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.099257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.099273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.101851] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.101869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.104765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.107700] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1162.107773] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.107789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1162.107812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.124519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.124545] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1162.124581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.157944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.157989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1162.158012] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.158049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1162.175661] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1162.175682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.175704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.175724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.175747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.175766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.175786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.175805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.175827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.175848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.175868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.175888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.175907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.175926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.175955] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.175978] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.176004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1162.176020] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.176241] [drm:drm_mode_addfb2] [FB:77]
>[ 1162.176283] [drm:drm_mode_addfb2] [FB:78]
>[ 1162.199356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1162.199441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1162.199498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.199545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.199556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.199602] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.199619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.199637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.199655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.199669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.199685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.199701] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.199716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.199730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.199743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.199756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.199760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.199772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.199776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.199789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.199806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.199823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.199841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.199859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.199877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.199894] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.199911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.199929] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.199947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.199967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.202493] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.202510] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.202525] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.202555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.202573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.202590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.202609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.202628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.202647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.202667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.202687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.202707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.202726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.202742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.202762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.202781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.206010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.206029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.206045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.206061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.209747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.209764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.209783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.212377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.212397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.215297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.218248] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.218307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.218324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.218346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.235051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.235078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.235116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.251765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.251809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.251861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.251884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.251924] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.269322] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.269341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.269361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.269378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.269395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.269410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.269425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.269441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.269458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.269475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.269490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.269505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.269519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.269533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.269559] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.269580] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.269601] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.269617] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.269665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.269674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.269714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.269730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.269748] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.269767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.269782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.269798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.269814] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.269829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.269844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.269858] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.269872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.269876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.269889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.269892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.269907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.269925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.269944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.269963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.269983] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.270001] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.270020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.270039] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.270058] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.270078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.270099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.270144] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.270205] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.270231] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.270274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.270299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.270331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.270352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.270375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.270396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.270421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.270445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.270470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.270490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.270512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.270538] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.270559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.273652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.273671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.273687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.273704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.277417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.277443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.277458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.280027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.280046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.282922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.285845] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.285880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.285896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.285918] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.302620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.302646] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.302679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.335976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.336017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.336069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.336091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.336128] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.355014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.355032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.355053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.355070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.355088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.355107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.355126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.355146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.355208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.355237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.355264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.355290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.355306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.355321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.355348] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.355369] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.355391] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.355407] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.355457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.355467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.355508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.355525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.355543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.355564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.355580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.355596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.355613] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.355628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.355643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.355658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.355672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.355676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.355689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.355693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.355708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.355721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.355736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.355749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.355766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.355780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.355795] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.355808] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.355822] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.355838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.355856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.355901] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.355915] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.355930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.355956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.355972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.355988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.356002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.356017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.356032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.356049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.356064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.356085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.356105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.356124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.356144] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.356166] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.359282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.359308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.359324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.359340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.361928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.361946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.361961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.364528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.364546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.367426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.370367] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.370435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.370452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.370481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.387169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.387211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.387246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.420575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.420620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.420672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.420694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.420739] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.439586] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.439605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.439625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.439641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.439659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.439678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.439697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.439717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.439739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.439759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.439780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.439800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.439819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.439835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.439863] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.439886] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.439910] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.439926] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.439977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.439987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.440038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.440054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.440072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.440093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.440111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.440129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.440147] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.440165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.440225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.440248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.440269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.440276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.440297] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.440303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.440324] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.440345] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.440366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.440386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.440409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.440429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.440450] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.440470] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.440491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.440515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.440539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.440605] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.440629] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.440647] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.440674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.440689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.440704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.440718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.440731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.440746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.440762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.440777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.440792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.440805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.440818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.440835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.440850] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.443928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.443945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.443960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.443975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.447679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.447697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.447713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.450316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.450335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.453220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.456156] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.456231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.456248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.456270] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.472959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.472982] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.473016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.506359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.506404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.506458] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.506480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.506526] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.525381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.525400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.525420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.525437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.525455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.525470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.525485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.525501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.525519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.525535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.525551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.525567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.525581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.525599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.525626] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.525649] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.525673] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.525690] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.525741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.525751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.525797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.525816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.525836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.525858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.525877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.525897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.525916] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.525935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.525955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.525973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.525992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.525996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.526015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.526018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.526038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.526057] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.526076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.526095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.526114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.526132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.526152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.526171] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.526232] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.526260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.526286] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.526354] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.526376] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.526398] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.526440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.526466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.526490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.526514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.526538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.526563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.526590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.526616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.526642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.526665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.526689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.526717] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.526743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.529916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.529934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.529950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.529966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.533599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.533620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.533639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.536179] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.536211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.539078] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.542002] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.542043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.542058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.542078] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.558778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.558805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.558843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.592219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.592264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.592317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.592338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.592385] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.611251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.611269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.611289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.611306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.611324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.611339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.611354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.611369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.611387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.611403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.611419] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.611435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.611449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.611467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.611495] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.611517] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.611542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.611558] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.611611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.611620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.611666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.611686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.611706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.611728] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.611746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.611766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.611785] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.611804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.611823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.611842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.611861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.611865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.611883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.611887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.611906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.611926] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.611944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.611963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.611982] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.612001] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.612020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.612039] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.612058] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.612078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.612099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.612144] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.612160] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.612175] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.612255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.612280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.612304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.612326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.612349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.612372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.612398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.612423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.612448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.612469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.612491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.612517] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.612547] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.615657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.615676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.615692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.615708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.619429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.619449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.619468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.622031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.622051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.624931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.627862] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.627887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.627903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.627925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.644632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.644658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.644693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.678021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.678065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.678122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.678144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.678227] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.697071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.697090] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.697110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.697126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.697144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.697163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.697182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.697243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.697274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.697301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.697328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.697354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.697378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.697397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.697426] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.697448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.697473] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.697498] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.697547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.697556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.697598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.697617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.697637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.697658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.697676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.697695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.697713] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.697732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.697749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.697767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.697785] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.697789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.697806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.697810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.697828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.697847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.697865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.697883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.697901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.697918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.697937] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.697955] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.697974] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.697993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.698013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.698058] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.698072] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.698087] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.698116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.698134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.698153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.698172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.698213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.698236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.698262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.698286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.698309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.698330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.698351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.698376] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.698398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.701466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.701482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.701496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.701511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.705229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.705248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.705264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.707859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.707878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.710769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.713706] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.713779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.713795] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.713818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.730508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.730532] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.730565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.763908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.763952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.764007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.764031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.764072] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.781883] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.781902] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.781922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.781939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.781957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.781971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.781986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.782002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.782019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.782039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.782060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.782080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.782099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.782116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.782143] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.782166] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.782190] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.782252] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.782319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.782330] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.782394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.782413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.782432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.782452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.782468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.782493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.782509] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.782523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.782538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.782551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.782564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.782568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.782581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.782584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.782603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.782621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.782639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.782657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.782676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.782693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.782711] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.782729] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.782748] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.782766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.782785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.782828] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.782841] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.782856] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.782884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.782902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.782920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.782938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.782957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.782974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.782994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.783013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.783033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.783050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.783068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.783088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.783105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.786190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.786224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.786240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.786256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.789916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.789933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.789949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.792515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.792534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.795410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.798355] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.798419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.798436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.798458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.815182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.815224] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.815259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.848546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.848596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.848648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.848669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.848714] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.867225] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.867243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.867263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.867280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.867297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.867312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.867326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.867342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.867359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.867375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.867391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.867407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.867420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.867434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.867461] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.867482] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.867506] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.867522] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.867566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.867576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.867621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.867641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.867661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.867683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.867702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.867721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.867741] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.867760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.867779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.867798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.867816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.867820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.867839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.867842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.867862] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.867881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.867900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.867919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.867938] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.867956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.867975] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.867994] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.868013] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.868033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.868053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.868099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.868114] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.868129] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.868159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.868178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.868239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.868263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.868284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.868307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.868331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.868355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.868378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.868397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.868417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.868441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.868462] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.871510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.871528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.871543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.871559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.875254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.875274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.875293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.877921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.877940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.880817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.883746] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.883775] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.883792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.883814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.900517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.900544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.900582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.933913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.933962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.934014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1162.934035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1162.934080] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1162.951893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1162.951912] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1162.951932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.951949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.951966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.951981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.951995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.952014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.952036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.952056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.952077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.952097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.952116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.952132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.952160] [drm:intel_power_well_disable [i915]] disabling display
>[ 1162.952182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1162.952247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.952272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1162.952434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1162.952444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1162.952488] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1162.952507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1162.952528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1162.952551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1162.952570] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1162.952590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1162.952610] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1162.952630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1162.952650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1162.952668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1162.952687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1162.952692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.952717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1162.952724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1162.952747] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1162.952763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1162.952778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1162.952793] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1162.952810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1162.952825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1162.952840] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1162.952855] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1162.952869] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1162.952886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1162.952904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1162.952949] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1162.952964] [drm:intel_power_well_enable [i915]] enabling display
>[ 1162.952977] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1162.953005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1162.953028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1162.953042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1162.953055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1162.953068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1162.953082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1162.953101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1162.953120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1162.953140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1162.953157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1162.953175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1162.953194] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1162.953234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1162.956306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1162.956324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.956340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.956356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.960019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1162.960044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1162.960066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.962630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.962648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.965525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.968468] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.968533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1162.968550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1162.968575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1162.985276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1162.985302] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1162.985337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.018669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.018713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.018766] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.018788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.018828] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.036986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.037005] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.037025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.037042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.037059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.037074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.037089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.037104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.037122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.037138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.037153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.037169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.037183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.037197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.037269] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.037303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.037515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.037540] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.037617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.037631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.037695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.037711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.037730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.037749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.037765] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.037781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.037798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.037814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.037829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.037843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.037857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.037861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.037875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.037879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.037893] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.037907] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.037921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.037934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.037950] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.037964] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.037978] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.037999] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.038011] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.038026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.038042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.038083] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.038097] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.038109] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.038134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.038148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.038161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.038174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.038187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.038201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.038243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.038268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.038292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.038312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.038334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.038360] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.038382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.041474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.041493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.041509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.041525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.044108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.044124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.044139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.046715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.046733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.049616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.052562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.052626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.052642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.052664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.069368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.069394] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.069428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.102755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.102798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.102852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.102877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.102919] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.120972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.120993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.121015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.121034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.121056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.121075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.121094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.121113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.121135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.121156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.121176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.121197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.121257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.121282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.121327] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.121545] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.121579] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.121605] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.121672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.121682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.121726] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.121743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.121761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.121780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.121796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.121820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.121836] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.121850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.121864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.121877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.121890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.121894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.121906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.121909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.121922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.121935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.121948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.121960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.121975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.121988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.122000] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.122012] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.122024] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.122039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.122055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.122097] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.122111] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.122125] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.122152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.122170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.122188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.122206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.122249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.122277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.122303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.122329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.122353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.122376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.122396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.122422] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.122443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.125539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.125558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.125574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.125590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.129293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.129312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.129328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.131924] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.131944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.134837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.137773] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.137845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.137862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.137883] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.154597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.154623] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.154659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.188002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.188046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.188101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.188124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.188174] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.206102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.206121] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.206142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.206159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.206176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.206192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.206211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.206273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.206304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.206331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.206358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.206383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.206402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.206421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.206449] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.206472] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.206497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.206514] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.206575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.206584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.206624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.206640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.206657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.206675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.206689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.206705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.206721] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.206735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.206750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.206767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.206784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.206788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.206806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.206809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.206827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.206845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.206863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.206880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.206898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.206915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.206933] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.206951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.206968] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.206987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.207007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.207051] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.207065] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.207079] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.207107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.207125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.207143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.207161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.207179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.207197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.207240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.207266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.207289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.207309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.207330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.207354] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.207375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.210459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.210477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.210492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.210507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.213081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.213098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.213113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.215688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.215706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.218580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.221527] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.221590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.221606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.221628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.238331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.238358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.238393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.271723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.271766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.271819] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.271842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.271889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.290752] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.290771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.290791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.290808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.290826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.290841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.290855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.290871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.290889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.290905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.290920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.290936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.290950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.290964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.290990] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.291012] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.291032] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.291048] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.291097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.291107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.291148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.291164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.291181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.291200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.291215] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.291272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.291297] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.291320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.291343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.291365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.291386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.291393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.291413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.291419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.291441] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.291470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.291489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.291508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.291530] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.291550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.291570] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.291589] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.291608] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.291630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.291655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.291881] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.291895] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.291909] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.291936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.291953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.291975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.292000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.292016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.292031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.292048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.292064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.292079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.292092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.292105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.292121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.292136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.295218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.295247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.295263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.295280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.297860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.297877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.297892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.300458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.300475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.303335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.306268] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.306345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.306364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.306390] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.323086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.323112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.323147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.356485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.356529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.356580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.356601] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.356646] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.375514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.375533] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.375553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.375570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.375587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.375607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.375626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.375645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.375667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.375688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.375710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.375739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.375756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.375771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.375798] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.375819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.375841] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.375857] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.375907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.375916] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.375958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.375974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.375992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.376012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.376027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.376044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.376060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.376079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.376099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.376118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.376137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.376140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.376159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.376163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.376182] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.376201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.376221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.376285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.376310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.376335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.376357] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.376380] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.376400] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.376425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.376451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.376515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.376537] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.376559] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.376596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.376620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.376641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.376662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.376681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.376703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.376727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.376750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.376773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.376792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.376812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.376834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.376857] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.379964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.379983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.379999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.380015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.383730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.383749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.383765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.386354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.386373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.389264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.392193] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.392223] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.392277] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.392315] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.408966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.408992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.409027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.442355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.442398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.442452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.442477] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.442519] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.461383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.461402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.461422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.461439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.461456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.461472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.461487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.461503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.461521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.461537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.461553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.461569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.461583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.461597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.461623] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.461644] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.461665] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.461680] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.461722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.461731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.461772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.461788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.461805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.461825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.461840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.461856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.461872] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.461888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.461903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.461917] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.461931] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.461934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.461948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.461951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.461966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.461980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.461993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.462007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.462023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.462036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.462050] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.462064] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.462077] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.462093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.462110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.462155] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.462169] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.462185] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.462215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.462272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.462298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.462329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.462351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.462374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.462399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.462423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.462448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.462468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.462490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.462514] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.462537] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.465628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.465647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.465666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.465687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.469389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.469407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.469425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.471987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.472005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.474883] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.477819] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.477893] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.477910] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.477932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.494634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.494660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.494697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.528014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.528057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.528111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.528133] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.528172] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.547042] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.547061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.547082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.547099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.547117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.547132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.547147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.547163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.547181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.547197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.547217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.547286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.547312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.547338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.547381] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.547415] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.547448] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.547473] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.547539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.547553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.547621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.547646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.547674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.547703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.547728] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.547754] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.547779] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.547804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.547829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.547853] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.547876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.547882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.547905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.547911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.547935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.547958] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.547981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.548004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.548027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.548050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.548073] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.548096] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.548116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.548149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.548173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.548237] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.548279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.548302] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.548340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.548364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.548387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.548409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.548431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.548455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.548480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.548504] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.548528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.548550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.548572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.548598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.548621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.551711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.551728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.551744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.551760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.555488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.555506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.555523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.558089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.558107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.560965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.563893] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.563922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.563938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.563960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.580674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.580700] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.580736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.614076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.614126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.614171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.614192] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.614243] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.633134] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.633153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.633173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.633190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.633207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.633222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.633237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.633294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.633323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.633351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.633378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.633531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.633553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.633576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.633618] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.633651] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.633683] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.633708] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.633785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.633796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.633838] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.633855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.633873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.633892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.633907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.633924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.633941] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.633956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.633971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.633986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.633999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.634003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.634017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.634020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.634042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.634055] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.634067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.634079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.634094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.634107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.634119] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.634132] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.634145] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.634159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.634175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.634217] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.634230] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.634274] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.634313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.634336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.634360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.634383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.634406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.634431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.634457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.634481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.634505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.634526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.634546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.634572] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.634596] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.637946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.637962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.637977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.637992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.641661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.641679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.641695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.644268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.644285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.647145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.650068] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.650103] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.650119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.650141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.666846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.666872] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.666907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.700221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.700312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.700384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.700405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.700443] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.719296] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.719315] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.719336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.719356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.719377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.719397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.719416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.719435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.719456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.719477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.719498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.719518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.719537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.719555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.719583] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.719605] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.719629] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.719646] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.719696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.719706] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.719751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.719777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.719795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.719813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.719828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.719844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.719859] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.719873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.719887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.719901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.719914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.719917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.719930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.719933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.719946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.719959] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.719971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.719983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.720000] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.720018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.720035] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.720053] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.720070] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.720088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.720107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.720149] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.720163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.720177] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.720204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.720222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.720240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.720298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.720325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.720350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.720377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.720401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.720426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.720448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.720470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.720497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.720520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.723614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.723633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.723651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.723671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.727368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.727387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.727403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.729970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.729989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.732865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.735802] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.735874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.735891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.735913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.752616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.752642] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.752677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.786003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.786047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.786102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.786127] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.786169] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.805030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.805049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.805069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.805086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.805104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.805119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.805134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.805150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.805168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.805184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.805200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.805215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.805229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.805243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.805320] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.805355] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.805546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.805572] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.805651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.805666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.805735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.805768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.805792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.805819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.805842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.805866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.805890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.805912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.805935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.805956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.805977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.805983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.806003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.806009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.806030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.806051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.806072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.806091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.806113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.806134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.806154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.806174] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.806193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.806217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.806241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.806325] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.806348] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.806371] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.806409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.806634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.806653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.806668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.806681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.806696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.806712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.806727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.806742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.806755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.806768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.806784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.806800] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.809893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.809911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.809927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.809943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.813668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.813687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.813703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.816297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.816317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.819200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.822142] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.822210] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.822226] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.822247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.838954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.838981] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.839016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.872366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.872411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.872467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.872489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.872539] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.891415] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.891434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.891454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.891471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.891489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.891504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.891519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.891535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.891552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.891569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.891585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.891601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.891615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.891629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.891656] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.891677] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.891697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.891713] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.891762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.891771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.891812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.891828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.891846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.891864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.891879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.891896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.891912] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.891927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.891942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.891956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.891969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.891973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.891986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.891990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.892004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.892022] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.892042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.892060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.892080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.892098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.892117] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.892137] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.892154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.892174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.892194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.892240] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.892297] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.892320] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.892365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.892393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.892419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.892445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.892470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.892496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.892525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.892553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.892580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.892604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.892628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.892657] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.892683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.896097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.896116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.896132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.896149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.899850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.899866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.899880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.902470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.902491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.905372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.908318] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.908382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.908399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.908421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1163.925125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.925152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.925190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.958504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.958548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.958601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1163.958625] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1163.958666] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1163.977028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1163.977047] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1163.977067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.977084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.977101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.977116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.977130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.977146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1163.977163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.977179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.977195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.977210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.977224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.977238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.977307] [drm:intel_power_well_disable [i915]] disabling display
>[ 1163.977342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1163.977374] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1163.977604] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1163.977677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1163.977688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1163.977728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1163.977743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1163.977760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1163.977780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1163.977797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1163.977815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1163.977833] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1163.977850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1163.977868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1163.977885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1163.977902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1163.977906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.977923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1163.977926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1163.977944] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1163.977962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1163.977979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1163.977996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1163.978014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1163.978031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1163.978048] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1163.978066] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1163.978083] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1163.978101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1163.978120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1163.978162] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1163.978176] [drm:intel_power_well_enable [i915]] enabling display
>[ 1163.978190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1163.978217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1163.978235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1163.978253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1163.978296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1163.978322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1163.978345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1163.978371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1163.978395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1163.978419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1163.978441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1163.978461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1163.978486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1163.978508] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1163.981596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1163.981613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1163.981628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.981643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1163.984228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1163.984246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1163.984288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1163.986885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1163.986903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1163.989804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1163.992742] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1163.992814] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1163.992831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1163.992853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.009555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.009581] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.009616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.042946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.042990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.043044] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.043066] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.043105] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.061966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.061985] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.062005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.062022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.062040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.062055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.062070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.062086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.062104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.062120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.062136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.062152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.062166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.062180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.062207] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.062228] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.062249] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.062305] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.062391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.062405] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.062476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.062497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.062522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.062548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.062569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.062591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.062613] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.062635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.062656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.062677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.062696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.062702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.062721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.062726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.062748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.062767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.062787] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.062806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.062829] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.062848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.062868] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.062887] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.062907] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.062928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.062952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.063015] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.063037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.063058] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.063095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.063117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.063138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.063159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.063179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.063200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.063224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.063247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.063288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.063309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.063331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.063357] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.063379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.066463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.066480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.066496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.066522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.070215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.070234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.070249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.072869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.072889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.075790] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.078729] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.078808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.078831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.078852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.095546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.095571] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.095606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.128956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.129000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.129053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.129076] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.129126] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.148003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.148022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.148042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.148059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.148077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.148092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.148107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.148123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.148140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.148157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.148172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.148188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.148202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.148216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.148242] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.148263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.148332] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.148356] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.148420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.148430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.148473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.148490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.148508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.148527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.148544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.148560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.148577] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.148593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.148609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.148623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.148638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.148642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.148656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.148660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.148674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.148688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.148703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.148722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.148742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.148761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.148781] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.148800] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.148821] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.148841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.148863] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.148909] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.148924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.148940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.148970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.148990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.149010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.149029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.149049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.149068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.149089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.149110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.149130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.149149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.149168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.149189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.149209] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.152303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.152321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.152335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.152350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.154963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.154981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.154997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.157573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.157590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.160474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.163416] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.163485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.163502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.163524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.180226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.180253] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.180337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.213599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.213643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.213696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.213718] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.213758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.232034] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.232052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.232072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.232089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.232107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.232126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.232146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.232165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.232186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.232207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.232227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.232248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.232266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.232329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.232371] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.232406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.232596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.232621] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.232683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.232697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.232763] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.232787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.232813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.232841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.232864] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.232889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.232914] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.232937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.232961] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.232983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.233005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.233010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.233032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.233037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.233059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.233081] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.233100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.233121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.233146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.233167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.233187] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.233209] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.233231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.233255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.233280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.233375] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.233399] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.233423] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.233606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.233623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.233637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.233655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.233673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.233690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.233709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.233728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.233747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.233764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.233780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.233798] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.233816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.236916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.236935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.236951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.236967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.240643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.240659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.240673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.243234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.243252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.246152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.249090] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.249163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.249182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.249208] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.265905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.265931] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.265967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.299296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.299339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.299392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.299415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.299454] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.318337] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.318356] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.318376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.318393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.318410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.318425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.318440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.318456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.318477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.318498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.318519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.318539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.318558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.318575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.318602] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.318625] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.318649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.318666] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.318716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.318725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.318771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.318790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.318810] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.318832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.318851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.318871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.318890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.318909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.318928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.318947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.318965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.318969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.318988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.318992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.319011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.319030] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.319048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.319067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.319086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.319105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.319125] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.319144] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.319162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.319182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.319203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.319249] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.319264] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.319279] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.319352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.319379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.319404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.319427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.319450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.319475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.319500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.319525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.319550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.319572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.319595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.319621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.319645] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.322718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.322736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.322752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.322768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.326473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.326491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.326505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.329068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.329086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.331959] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.334881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.334916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.334932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.334954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.351658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.351684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.351719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.385049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.385093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.385147] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.385172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.385214] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.404086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.404105] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.404125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.404142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.404160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.404179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.404198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.404218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.404239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.404260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.404280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.404346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.404375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.404401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.404446] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.404639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.404673] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.404698] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.404775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.404786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.404829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.404846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.404864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.404884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.404900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.404917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.404934] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.404950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.404965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.404980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.404994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.404998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.405012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.405015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.405030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.405044] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.405057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.405071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.405087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.405101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.405115] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.405133] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.405152] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.405172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.405193] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.405239] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.405261] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.405275] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.405336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.405363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.405386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.405410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.405433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.405458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.405483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.405508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.405532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.405554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.405577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.405604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.405628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.408971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.408990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.409005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.409021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.412725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.412745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.412761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.415436] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.415456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.418390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.421334] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.421400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.421417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.421439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.438142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.438168] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.438203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.471529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.471572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.471625] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.471648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.471687] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.490542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.490561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.490581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.490598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.490616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.490635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.490655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.490674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.490696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.490716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.490736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.490757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.490776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.490792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.490819] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.490842] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.490866] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.490882] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.490934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.490943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.490989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.491009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.491029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.491051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.491070] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.491096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.491114] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.491129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.491144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.491158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.491171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.491174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.491187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.491190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.491203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.491216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.491228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.491241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.491256] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.491273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.491291] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.491346] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.491368] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.491394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.491421] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.491486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.491508] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.491532] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.491569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.491839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.491862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.491885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.491908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.491932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.491957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.491981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.492005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.492026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.492046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.492070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.492094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.495190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.495209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.495224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.495241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.498927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.498944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.498959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.501524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.501542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.504417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.507356] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.507425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.507441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.507462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.524169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.524195] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.524230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.557558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.557601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.557656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.557681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.557722] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.576048] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.576068] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.576090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.576110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.576131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.576151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.576170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.576189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.576210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.576231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.576251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.576271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.576290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.576353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.576396] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.576430] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.576596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.576622] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.576701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.576716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.576785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.576810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.576837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.576867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.576891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.576918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.576944] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.576975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.576998] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.577020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.577041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.577047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.577067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.577073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.577094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.577115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.577136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.577157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.577180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.577201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.577222] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.577241] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.577261] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.577283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.577329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.577392] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.577415] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.577615] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.577642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.577658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.577672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.577686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.577699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.577714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.577729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.577744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.577759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.577771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.577784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.577800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.577815] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.580883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.580902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.580920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.580939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.584662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.584681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.584697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.587288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.587318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.590196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.593121] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.593154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.593171] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.593192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.609898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.609924] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.609959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.643285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.643345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.643399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.643424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.643466] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.662307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.662343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.662363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.662380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.662398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.662414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.662428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.662444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.662462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.662478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.662494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.662510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.662524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.662537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.662564] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.662585] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.662609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.662625] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.662677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.662687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.662736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.662752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.662769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.662788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.662802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.662818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.662834] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.662851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.662870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.662888] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.662905] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.662909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.662926] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.662930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.662948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.662966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.662984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.663002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.663020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.663037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.663055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.663073] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.663091] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.663110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.663129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.663172] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.663186] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.663201] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.663228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.663247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.663265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.663283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.663301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.663352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.663379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.663406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.663434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.663457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.663480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.663508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.663532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.666606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.666623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.666637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.666653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.670351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.670371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.670390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.672936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.672954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.675849] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.678788] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.678859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.678878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.678904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.695591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.695615] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.695649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.728988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.729031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.729085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.729107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.729146] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.747070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.747089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.747109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.747127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.747144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.747159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.747174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.747190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.747208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.747224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.747240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.747255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.747269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.747283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.747355] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.747391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.747424] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.747608] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.747689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.747703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.747775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.747799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.747824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.747851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.747873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.747897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.747921] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.747944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.747967] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.747988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.748009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.748015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.748035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.748041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.748062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.748084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.748105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.748125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.748147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.748168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.748189] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.748208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.748229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.748250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.748275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.748360] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.748383] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.748406] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.748445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.748470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.748493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.748516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.748538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.748562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.748587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.748793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.748808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.748826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.748843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.748862] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.748880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.751942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.751959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.751975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.751991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.754570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.754587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.754602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.757166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.757185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.760069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.763009] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.763079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.763095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.763115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.779824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.779852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.779889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.813220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.813264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.813354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.813389] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.813446] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.830271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.830290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.830311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.830370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.830399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.830423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.830449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.830583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.830602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.830619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.830636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.830652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.830666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.830680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.830706] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.830727] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.830748] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.830764] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.830805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.830815] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.830856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.830872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.830890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.830910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.830929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.830949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.830968] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.830987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.831007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.831026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.831044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.831048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.831067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.831071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.831090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.831109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.831128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.831147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.831166] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.831185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.831205] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.831224] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.831243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.831263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.831284] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.831365] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.831390] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.831420] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.831460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.831485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.831506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.831529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.831549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.831572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.831598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.831623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.831648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.831668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.831689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.831715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.831737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.835150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.835169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.835186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.835202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.838916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.838936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.838955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.841540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.841560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.844438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.847374] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.847449] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.847468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.847494] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.864192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.864216] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.864250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.897598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.897642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.897697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.897722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.897770] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1164.916654] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1164.916673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1164.916693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.916710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.916728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.916743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.916757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.916773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.916791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.916808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.916824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.916840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.916854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.916868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.916894] [drm:intel_power_well_disable [i915]] disabling display
>[ 1164.916915] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1164.916936] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.916952] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1164.917006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.917018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1164.917060] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1164.917076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1164.917094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1164.917113] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1164.917128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1164.917144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1164.917160] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1164.917175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1164.917190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1164.917204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1164.917218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1164.917221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.917235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1164.917238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1164.917252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1164.917266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1164.917279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1164.917293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1164.917311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1164.917375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1164.917395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1164.917415] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1164.917434] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1164.917457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.917480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1164.917545] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1164.917567] [drm:intel_power_well_enable [i915]] enabling display
>[ 1164.917587] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1164.917624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1164.917639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1164.917653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1164.917666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1164.917680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1164.917694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1164.917710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1164.917725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1164.917739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.917753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1164.917770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1164.917789] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1164.917807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1164.920907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1164.920926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1164.920942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.920958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1164.924651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1164.924669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1164.924685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1164.927256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1164.927276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1164.930159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1164.932551] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1164.932611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1164.932626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1164.932646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1164.949354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1164.949380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1164.949417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1164.982737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1164.982783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1164.982837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1164.982860] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1164.982910] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.000909] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.000927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.000948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.000965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.000982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.000997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.001012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.001027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.001045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.001062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.001078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.001093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.001108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.001121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.001148] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.001170] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.001191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.001206] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.001255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.001264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.001306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.001321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.001384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.001413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.001436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.001461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.001484] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.001508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.001531] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.001553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.001574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.001581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.001602] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.001608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.001632] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.001654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.001676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.001697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.001720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.001743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.001762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.001776] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.001790] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.001806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.001825] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.001870] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.001884] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.001899] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.001925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.001945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.001964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.001984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.002003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.002023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.002044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.002065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.002085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.002104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.002124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.002144] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.002171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.005247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.005266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.005282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.005298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.007931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.007950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.007966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.010541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.010562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.013459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.016403] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.016475] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.016491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.016511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.033207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.033232] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.033266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.066590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.066632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.066686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.066710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.066758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.085618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.085637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.085657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.085674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.085691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.085710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.085730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.085749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.085770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.085791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.085811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.085831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.085850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.085867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.085894] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.085917] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.085941] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.085957] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.086008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.086018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.086063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.086082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.086102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.086124] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.086143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.086163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.086182] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.086201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.086220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.086239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.086257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.086261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.086280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.086283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.086303] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.086322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.086384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.086409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.086435] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.086458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.086481] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.086504] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.086525] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.086551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.086577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.086646] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.086670] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.086695] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.086725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.086745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.086770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.086787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.086802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.086817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.086834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.086851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.086871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.086896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.086910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.086927] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.086942] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.090124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.090143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.090159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.090175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.092756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.092773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.092788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.095411] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.095429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.098317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.101262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.101299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.101321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.101382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.118036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.118061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.118095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.151422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.151466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.151521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.151545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.151592] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.170429] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.170448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.170469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.170486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.170503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.170519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.170538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.170557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.170578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.170599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.170619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.170639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.170658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.170675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.170703] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.170725] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.170750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.170766] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.170817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.170827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.170879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.170896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.170913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.170931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.170945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.170960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.170976] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.170990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.171004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.171017] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.171030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.171034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.171046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.171049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.171062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.171075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.171087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.171100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.171115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.171127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.171140] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.171152] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.171164] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.171178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.171195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.171236] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.171249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.171263] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.171290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.171308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.171326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.171383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.171406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.171428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.171452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.171475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.171498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.171518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.171538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.171562] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.171583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.174673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.174692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.174709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.174729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.177305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.177324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.177371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.180031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.180058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.182936] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.185872] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.185946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.185962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.185984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.202686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.202713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.202751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.236079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.236123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.236177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.236200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.236247] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.255055] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.255074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.255096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.255115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.255137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.255156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.255176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.255195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.255216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.255237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.255257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.255278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.255297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.255315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.255386] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.255421] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.255456] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.255482] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.255561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.255576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.255646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.255670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.255697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.255732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.255753] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.255776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.255798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.255821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.255841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.255862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.255881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.255887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.255907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.255913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.255934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.255953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.255974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.255992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.256015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.256034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.256055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.256074] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.256093] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.256116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.256141] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.256204] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.256226] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.256247] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.256284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.256304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.256326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.256364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.256386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.256407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.256432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.256456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.256481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.256500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.256522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.256547] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.256569] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.259652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.259669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.259683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.259698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.263398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.263417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.263433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.266006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.266024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.268917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.271841] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.271875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.271892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.271913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.288602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.288625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.288659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.321999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.322041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.322093] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.322114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.322152] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.340988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.341007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.341028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.341045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.341062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.341078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.341092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.341108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.341126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.341142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.341158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.341173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.341187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.341200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.341226] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.341247] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.341268] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.341283] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.341373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.341388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.341458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.341484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.341511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.341541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.341573] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.341597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.341621] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.341644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.341667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.341689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.341710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.341716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.341736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.341741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.341763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.341784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.341806] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.341827] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.341850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.341873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.341895] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.341917] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.341939] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.341962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.341988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.342052] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.342075] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.342097] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.342135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.342158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.342180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.342202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.342224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.342244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.342269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.342293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.342316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.342337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.342375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.342402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.342426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.345508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.345526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.345544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.345562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.349249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.349267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.349285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.351857] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.351876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.354783] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.357724] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.357792] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.357809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.357830] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.374537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.374564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.374600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.407931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.407975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.408029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.408052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.408092] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.426956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.426975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.426997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.427017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.427038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.427058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.427077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.427096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.427117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.427138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.427158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.427178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.427197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.427213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.427241] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.427263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.427288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.427304] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.427401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.427417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.427490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.427517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.427551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.427579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.427602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.427626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.427650] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.427674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.427697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.427719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.427740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.427746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.427766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.427772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.427794] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.427815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.427837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.427858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.427881] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.427903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.427924] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.427944] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.427965] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.427988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.428013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.428079] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.428101] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.428123] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.428162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.428184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.428207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.428229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.428249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.428272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.428296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.428320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.428344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.428382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.428405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.428429] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.428453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.431538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.431555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.431572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.431591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.435293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.435312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.435328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.437934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.437952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.440859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.443796] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.443869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.443896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.443919] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.460610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.460636] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.460673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.494000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.494043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.494097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.494119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.494158] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.512103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.512124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.512146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.512166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.512187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.512206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.512226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.512245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.512266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.512287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.512307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.512327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.512346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.512408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.512450] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.512485] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.512650] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.512673] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.512734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.512747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.512812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.512836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.512861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.512888] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.512910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.512934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.512958] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.512981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.513003] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.513025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.513046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.513051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.513072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.513077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.513099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.513120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.513141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.513161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.513183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.513204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.513225] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.513244] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.513264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.513285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.513309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.513392] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.513417] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.513440] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.513478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.513502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.513525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.513549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.513571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.513595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.513620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.513645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.513669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.513691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.513713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.513738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.513762] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.517055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.517073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.517088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.517104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.520790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.520806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.520820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.523389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.523408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.526286] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.529209] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.529243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.529259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.529281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.545986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.546013] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.546050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.579382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.579426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.579480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.579503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.579549] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.598418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.598437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.598457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.598474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.598491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.598506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.598521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.598536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.598554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.598571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.598586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.598602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.598616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.598629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.598656] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.598677] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.598698] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.598714] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.598756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1165.598765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1165.598806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.598822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.598840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.598859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.598874] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.598890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.598906] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1165.598921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1165.598936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.598950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.598964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.598968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.598981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.598985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.598999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.599013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.599026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.599040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1165.599056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.599070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.599083] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1165.599097] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1165.599110] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1165.599126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.599143] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1165.599187] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.599201] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.599216] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.599246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.599265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.599285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.599305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.599324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.599343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.599408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.599447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.599473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.599496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.599519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.599545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1165.599570] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.602662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.602682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.602701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.602721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.606420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.606438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.606454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.609029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.609048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.611955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.614898] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1165.614963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.614978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1165.614999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.631714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.631742] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.631779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.665109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.665154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1165.665177] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1165.665214] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1165.683132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1165.683151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1165.683171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.683188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.683206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.683221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.683235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.683251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.683269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.683285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.683300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.683316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.683330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.683344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.683417] [drm:intel_power_well_disable [i915]] disabling display
>[ 1165.683453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1165.683486] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1165.683513] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1165.684843] [IGT] kms_flip: exiting, ret=0
>[ 1165.709767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1165.709786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1165.709806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1165.709828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1165.709847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1165.709868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1165.709888] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1165.709907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1165.709927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1165.709947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1165.709966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1165.709971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.709990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1165.709993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.710013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1165.710033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1165.710053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1165.710072] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1165.710092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1165.710111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1165.710131] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1165.710151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1165.710170] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1165.710192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1165.710214] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1165.710269] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1165.710287] [drm:intel_power_well_enable [i915]] enabling display
>[ 1165.710303] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1165.710336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1165.710356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1165.710390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1165.710410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1165.710430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1165.710450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1165.710472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1165.710494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1165.710515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.710534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1165.710554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1165.710575] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1165.710595] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1165.712600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1165.712616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1165.712630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.712645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1165.715226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1165.715244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1165.715263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1165.717841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1165.717858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1165.720757] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1165.723782] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1165.723817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1165.723833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1165.723856] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1165.723902] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1165.723918] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1165.740567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1165.740591] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1165.740630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1165.740765] Console: switching to colour frame buffer device 240x75
>[ 1165.871043] Console: switching to colour dummy device 80x25
>[ 1165.871135] [IGT] kms_flip: executing
>[ 1165.880936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1165.880967] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1165.882440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1165.882460] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1165.884434] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1165.884440] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1165.886433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1165.886453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1165.888432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1165.888438] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1165.888443] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1165.888460] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1165.888484] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1165.889522] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1165.890418] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1165.890437] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1165.890455] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1165.890470] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1165.891479] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1165.891505] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1165.892565] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1165.892568] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1165.892646] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1165.892648] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1165.892652] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1165.892654] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1165.892658] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1165.892660] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1165.892667] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1165.892670] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1165.892673] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1165.892675] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1165.892678] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1165.892680] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1165.892683] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1165.892685] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1165.892687] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1165.892690] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1165.892692] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1165.892695] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1165.892697] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1165.892700] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1165.892702] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1165.892704] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1165.892707] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1165.892709] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1165.892712] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1165.892714] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1165.892717] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1165.892719] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1165.892722] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1165.892724] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1165.892726] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1165.892729] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1165.892731] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1165.892734] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1165.892736] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1165.892738] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1165.892741] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1165.892770] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1165.892788] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1165.894423] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1165.894441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1165.896434] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1165.896440] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1165.898453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1165.898472] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1165.900440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1165.900446] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1165.900450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1165.901698] [IGT] kms_flip: starting subtest 2x-flip-vs-dpms-off-vs-modeset-interruptible
>[ 1165.903017] [IGT] kms_flip: exiting, ret=77
>[ 1165.940838] Console: switching to colour frame buffer device 240x75
>[ 1166.073865] Console: switching to colour dummy device 80x25
>[ 1166.073957] [IGT] kms_flip: executing
>[ 1166.083927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1166.083956] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1166.085449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1166.085469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1166.087451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1166.087457] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1166.089445] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1166.089465] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1166.091452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1166.091458] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1166.091462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1166.091478] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1166.091501] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1166.092531] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1166.093438] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1166.093466] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1166.093487] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1166.093505] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1166.094504] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1166.094530] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1166.095587] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1166.095590] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1166.095670] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1166.095672] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1166.095676] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1166.095678] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1166.095682] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1166.095684] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1166.095692] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1166.095695] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1166.095697] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1166.095700] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1166.095702] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1166.095705] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1166.095707] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1166.095710] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1166.095712] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1166.095714] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1166.095717] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1166.095719] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1166.095722] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1166.095724] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1166.095727] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1166.095729] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1166.095732] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1166.095734] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1166.095736] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1166.095739] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1166.095741] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1166.095744] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1166.095746] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1166.095749] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1166.095751] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1166.095753] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1166.095756] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1166.095758] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1166.095761] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1166.095763] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1166.095766] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1166.095796] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1166.095814] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1166.097444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1166.097466] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1166.099456] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1166.099462] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1166.101447] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1166.101466] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1166.103446] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1166.103451] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1166.103455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1166.103669] [IGT] kms_flip: starting subtest flip-vs-expired-vblank
>[ 1166.104080] [drm:drm_mode_addfb2] [FB:77]
>[ 1166.104103] [drm:drm_mode_addfb2] [FB:79]
>[ 1166.146290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1166.146344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1166.157632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1166.157658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1166.157708] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1166.176574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1166.176597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1166.176614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1166.176634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1166.176651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1166.176668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1166.176683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1166.176703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1166.176722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1166.176744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1166.176765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1166.176785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1166.176806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1166.176825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1166.176841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1166.176870] [drm:intel_power_well_disable [i915]] disabling display
>[ 1166.176893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1166.176919] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1166.176937] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1166.176985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1166.177060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1166.177128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1166.177139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1166.177191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1166.177208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1166.177225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1166.177244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1166.177258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1166.177273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1166.177289] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1166.177304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1166.177318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1166.177332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1166.177345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1166.177349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1166.177361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1166.177365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1166.177378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1166.177429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1166.177451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1166.177474] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1166.177498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1166.177521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1166.177543] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1166.177566] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1166.177588] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1166.177613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1166.177639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1166.180364] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1166.180379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1166.180445] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1166.180484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1166.180506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1166.180529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1166.180549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1166.180571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1166.180592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1166.180615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1166.180639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1166.180662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1166.180681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1166.180702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1166.180724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1166.180747] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1166.183840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1166.183859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1166.183875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1166.183891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1166.187600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1166.187619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1166.187635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1166.190209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1166.190228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1166.193108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1166.196043] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1166.196118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1166.196135] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1166.196157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1166.196197] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1166.196214] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1166.212870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1166.212895] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1166.212930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1176.238626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1176.255178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1176.255212] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1176.255264] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1176.274127] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1176.274150] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1176.274167] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1176.274187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1176.274204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1176.274222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1176.274238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1176.274253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1176.274270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1176.274287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1176.274304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1176.274320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1176.274336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1176.274351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1176.274364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1176.274392] [drm:intel_power_well_disable [i915]] disabling display
>[ 1176.274414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1176.274436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1176.274453] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1176.274654] [drm:drm_mode_addfb2] [FB:77]
>[ 1176.274678] [drm:drm_mode_addfb2] [FB:78]
>[ 1176.300480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1176.300567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1176.300624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1176.300680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1176.300689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1176.300737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1176.300754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1176.300771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1176.300790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1176.300804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1176.300819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1176.300834] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1176.300849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1176.300863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1176.300876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1176.300889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1176.300893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1176.300905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1176.300909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1176.300922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1176.300935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1176.300947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1176.300960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1176.300975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1176.300988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1176.301034] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1176.301056] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1176.301077] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1176.301100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1176.301127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1176.303741] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1176.303756] [drm:intel_power_well_enable [i915]] enabling display
>[ 1176.303771] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1176.303801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1176.303819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1176.303837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1176.303854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1176.303872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1176.303890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1176.303909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1176.303928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1176.303946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1176.303963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1176.303979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1176.303997] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1176.304053] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1176.306056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1176.306072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1176.306086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1176.306101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1176.309780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1176.309799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1176.309815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1176.312405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1176.312425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1176.315309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1176.318248] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1176.318319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1176.318336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1176.318358] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1176.335087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1176.335113] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1176.335148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1186.360876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1186.360974] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1186.361017] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1186.361106] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1186.377980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1186.378000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1186.378021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1186.378038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1186.378056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1186.378071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1186.378086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1186.378102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1186.378120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1186.378136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1186.378152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1186.378168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1186.378182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1186.378196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1186.378224] [drm:intel_power_well_disable [i915]] disabling display
>[ 1186.378246] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1186.378268] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1186.378284] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1186.378495] [drm:drm_mode_addfb2] [FB:77]
>[ 1186.378518] [drm:drm_mode_addfb2] [FB:78]
>[ 1186.404236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1186.404323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1186.404381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1186.404435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1186.404446] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1186.404492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1186.404509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1186.404527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1186.404545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1186.404560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1186.404576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1186.404591] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1186.404606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1186.404654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1186.404676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1186.404697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1186.404702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1186.404722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1186.404728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1186.404750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1186.404771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1186.404792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1186.404812] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1186.404836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1186.404856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1186.404879] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1186.404898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1186.404920] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1186.404942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1186.404967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1186.407581] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1186.407596] [drm:intel_power_well_enable [i915]] enabling display
>[ 1186.407648] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1186.407689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1186.407711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1186.407734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1186.407754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1186.407775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1186.407796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1186.407820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1186.407843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1186.407866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1186.407885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1186.407906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1186.407930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1186.407952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1186.409955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1186.409971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1186.409985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1186.410000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1186.411508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1186.411523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1186.411537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1186.413040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1186.413058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1186.414870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1186.417823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1186.417880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1186.417897] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1186.417925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1186.434647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1186.434674] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1186.434709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.460475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1196.460566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1196.460612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1196.460719] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1196.477554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1196.477573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1196.477595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1196.477615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1196.477637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1196.477657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1196.477677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1196.477696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1196.477718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1196.477739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1196.477759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1196.477779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.477798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1196.477817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1196.477846] [drm:intel_power_well_disable [i915]] disabling display
>[ 1196.477869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1196.477895] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1196.477911] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1196.480339] [IGT] kms_flip: exiting, ret=0
>[ 1196.495700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1196.495720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1196.495740] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1196.495763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1196.495783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1196.495803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1196.495823] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1196.495843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1196.495863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1196.495883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1196.495902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1196.495906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1196.495926] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1196.495929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1196.495949] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1196.495969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1196.495989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1196.496008] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1196.496028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1196.496048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1196.496067] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1196.496087] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1196.496107] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1196.496128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1196.496150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1196.496217] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1196.496258] [drm:intel_power_well_enable [i915]] enabling display
>[ 1196.496275] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1196.496308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1196.496328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1196.496348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1196.496368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1196.496388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1196.496408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1196.496430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1196.496451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1196.496473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.496492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1196.496512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1196.496533] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1196.496553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1196.498548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1196.498565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1196.498581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1196.498599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1196.500110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1196.500126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1196.500143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1196.501640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1196.501656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1196.503469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1196.506513] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1196.506581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1196.506597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1196.506620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1196.506674] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1196.506698] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1196.523326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1196.523350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1196.523387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.523546] Console: switching to colour frame buffer device 240x75
>[ 1196.829358] Console: switching to colour dummy device 80x25
>[ 1196.829453] [IGT] kms_flip: executing
>[ 1196.843742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1196.843771] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1196.845297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1196.845317] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1196.847294] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1196.847300] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1196.849294] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1196.849316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1196.851301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1196.851307] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1196.851311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1196.851327] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1196.851350] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1196.852384] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1196.853287] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1196.853311] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1196.853334] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1196.853350] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1196.854345] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1196.854368] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1196.855428] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1196.855431] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1196.855509] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1196.855511] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1196.855515] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1196.855517] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1196.855521] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1196.855523] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1196.855530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1196.855533] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1196.855536] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1196.855538] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1196.855541] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1196.855543] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1196.855546] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1196.855548] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1196.855551] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1196.855553] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1196.855556] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1196.855558] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1196.855560] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1196.855563] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1196.855565] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1196.855568] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1196.855570] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1196.855573] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1196.855575] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1196.855577] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1196.855580] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1196.855582] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1196.855585] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1196.855587] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1196.855590] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1196.855592] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1196.855594] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1196.855597] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1196.855599] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1196.855602] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1196.855604] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1196.855634] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1196.855652] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1196.857294] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1196.857312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1196.859309] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1196.859316] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1196.861296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1196.861316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1196.863297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1196.863303] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1196.863306] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1196.863522] [IGT] kms_flip: starting subtest flip-vs-absolute-wf_vblank
>[ 1196.863934] [drm:drm_mode_addfb2] [FB:75]
>[ 1196.863956] [drm:drm_mode_addfb2] [FB:79]
>[ 1196.906150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1196.906203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1196.906986] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1196.907009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1196.907045] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1196.925906] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1196.925930] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1196.925946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1196.925966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1196.925986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1196.926008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1196.926027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1196.926047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1196.926066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1196.926088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1196.926108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1196.926129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1196.926149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.926168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1196.926184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1196.926212] [drm:intel_power_well_disable [i915]] disabling display
>[ 1196.926235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1196.926309] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1196.926340] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1196.926416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1196.926520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1196.926619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1196.926635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1196.926703] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1196.926729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1196.926765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1196.926792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1196.926814] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1196.926838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1196.926861] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1196.926884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1196.926907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1196.926929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1196.926948] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1196.926954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1196.926974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1196.926980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1196.927002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1196.927023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1196.927044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1196.927065] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1196.927089] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1196.927110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1196.927131] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1196.927153] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1196.927171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1196.927195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1196.927220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1196.929740] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1196.929754] [drm:intel_power_well_enable [i915]] enabling display
>[ 1196.929767] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1196.929793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1196.929808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1196.929822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1196.929839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1196.929857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1196.929875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1196.929894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1196.929912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1196.929931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1196.929948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1196.929963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1196.929981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1196.929999] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1196.931974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1196.931992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1196.932009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1196.932027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1196.933537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1196.933554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1196.933568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1196.935060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1196.935076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1196.936882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1196.939815] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1196.939891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1196.939907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1196.939930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1196.939971] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1196.939990] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1196.956636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1196.956662] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1196.956699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1207.266051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1207.282560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1207.282604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1207.282671] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1207.299650] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1207.299687] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1207.299713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1207.299745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1207.299772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1207.299801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1207.299826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1207.299850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1207.299950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1207.300002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1207.300048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1207.300091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1207.300133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1207.300172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1207.300218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1207.300262] [drm:intel_power_well_disable [i915]] disabling display
>[ 1207.300296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1207.300330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1207.300358] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1207.300593] [drm:drm_mode_addfb2] [FB:75]
>[ 1207.300617] [drm:drm_mode_addfb2] [FB:78]
>[ 1207.323729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1207.323812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1207.323901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1207.323977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1207.323987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1207.324036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1207.324053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1207.324071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1207.324089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1207.324105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1207.324124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1207.324142] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1207.324160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1207.324178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1207.324196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1207.324214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1207.324218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1207.324235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1207.324239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1207.324257] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1207.324275] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1207.324293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1207.324310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1207.324329] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1207.324345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1207.324364] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1207.324381] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1207.324400] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1207.324419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1207.324440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1207.326942] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1207.326957] [drm:intel_power_well_enable [i915]] enabling display
>[ 1207.326970] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1207.326999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1207.327015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1207.327030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1207.327044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1207.327057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1207.327072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1207.327088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1207.327102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1207.327117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1207.327130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1207.327147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1207.327166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1207.327183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1207.329163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1207.329181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1207.329198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1207.329217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1207.330722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1207.330739] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1207.330753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1207.332250] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1207.332268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1207.334073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1207.337018] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1207.337083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1207.337100] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1207.337122] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1207.353825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1207.353852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1207.353935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.663433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.663811] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1217.663942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.664142] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1217.681340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1217.681373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.681408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.681437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.681467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.681492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.681598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.681640] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.681691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.681737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.681782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.681826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.681863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.681902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.681976] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.682033] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.682088] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1217.682133] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.682386] [drm:drm_mode_addfb2] [FB:75]
>[ 1217.682410] [drm:drm_mode_addfb2] [FB:78]
>[ 1217.705475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.705632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1217.705695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1217.705749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1217.705759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.705806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.705823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.705840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.705858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.705875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.705893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.705911] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1217.705929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1217.705946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.705964] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.705981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.705984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.706001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.706005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.706023] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.706040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.706057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.706074] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1217.706092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.706109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.706127] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1217.706145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1217.706163] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1217.706181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.706201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1217.708713] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.708729] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.708742] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.708771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.708787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.708801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.708815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.708829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.708844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.708860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.708875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.708889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.708902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.708915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.708932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1217.708946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.710931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.710947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.710961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.710976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.712480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.712512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.712529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.714028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.714045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.715865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.718814] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1217.718875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.718892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1217.718914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.735618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.735644] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1217.735680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.045019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.045109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1228.045246] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.045349] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1228.062456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1228.062476] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.062496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.062514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.062532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.062547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.062562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.062579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.062597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.062617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.062638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.062659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.062678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.062697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.062726] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.062749] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.062777] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1228.062794] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.065293] [IGT] kms_flip: exiting, ret=0
>[ 1228.088532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.088552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.088571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.088592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.088608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.088626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.088644] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1228.088661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1228.088677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.088693] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.088708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.088712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.088727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.088730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.088745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.088760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.088774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.088789] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1228.088806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.088821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.088835] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1228.088849] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1228.088863] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1228.088881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.088900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1228.088955] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.088971] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.088987] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.089017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.089033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.089049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.089068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.089088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.089108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.089145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.089167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.089188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.089208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.089227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.089248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1228.089268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.091261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.091276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.091290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.091305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.092816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.092832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.092849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.094349] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.094364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.096177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.098234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1228.098277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.098295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1228.098322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.098371] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1228.098390] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1228.115021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.115044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1228.115080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.115225] Console: switching to colour frame buffer device 240x75
>[ 1228.424963] Console: switching to colour dummy device 80x25
>[ 1228.425054] [IGT] kms_flip: executing
>[ 1228.438671] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1228.438702] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1228.440783] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1228.440804] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1228.442206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1228.442213] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1228.444281] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1228.444300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1228.446374] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1228.446380] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1228.446385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1228.446400] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1228.446424] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1228.447450] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1228.448344] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1228.448361] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1228.448375] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1228.448389] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1228.449370] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1228.449385] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1228.450432] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1228.450435] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1228.450513] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1228.450516] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1228.450520] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1228.450522] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1228.450525] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1228.450527] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1228.450535] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1228.450538] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.450540] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1228.450543] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1228.450545] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1228.450547] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1228.450550] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1228.450552] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1228.450555] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1228.450557] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1228.450560] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1228.450562] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1228.450565] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1228.450567] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1228.450569] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1228.450572] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1228.450574] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1228.450577] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1228.450579] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1228.450581] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1228.450584] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1228.450586] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1228.450589] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1228.450591] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1228.450594] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1228.450596] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1228.450598] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1228.450601] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1228.450603] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1228.450606] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1228.450608] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1228.450637] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1228.450655] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1228.452193] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1228.452212] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1228.454197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1228.454203] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1228.456197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1228.456217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1228.458198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1228.458204] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1228.458208] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1228.459460] [IGT] kms_flip: starting subtest plain-flip-interruptible
>[ 1228.459856] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.459877] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.502103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1228.502188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.515377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1228.515405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.515447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1228.534313] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1228.534336] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1228.534352] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.534372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.534389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.534407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.534423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.534438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.534455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.534473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.534489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.534505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.534521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.534536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.534550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.534578] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.534599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.534621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1228.534639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.534697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.534764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1228.534830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1228.534839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.534878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.534893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.534910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.534928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.534942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.534957] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.534973] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1228.534988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1228.535003] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.535016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.535029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.535033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.535045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.535048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.535061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.535078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.535096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.535113] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1228.535131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.535185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.535209] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1228.535230] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1228.535253] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1228.535278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.535305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1228.537879] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.537896] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.537910] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.537938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.537956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.537972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.537987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.538002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.538018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.538035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.538051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.538067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.538081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.538095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.538113] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1228.538131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.540182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.540199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.540214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.540232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.541753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.541769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.541783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.543278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.543294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.545107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.548048] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1228.548115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.548131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1228.548196] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.548346] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1228.548363] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1228.564853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.564875] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1228.564906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.917924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.934530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1231.934555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.934594] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1231.953436] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1231.953460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1231.953480] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.953503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.953522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.953544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.953564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.953584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.953603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.953625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.953646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.953667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.953686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.953705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.953724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.953753] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.953776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.953802] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1231.953820] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.954042] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.954065] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.977437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1231.977524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.977577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1231.977626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.977636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.977686] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.977704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.977723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.977743] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.977758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.977775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.977794] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.977812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.977832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.977850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.977868] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.977872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.977890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.977894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.977913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.977932] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.977950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.977969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.977988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.978006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.978025] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.978044] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.978062] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.978082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.978103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.980615] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.980630] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.980643] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.980672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.980688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.980703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.980717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.980730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.980745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.980761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.980775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.980790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.980803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.980815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.980832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.980846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.982828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.982844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.982858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.982873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.984408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.984424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.984437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.985929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.985945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.987762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.990721] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.990772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.990789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.990815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.007523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.007549] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.007584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.360598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.360645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1235.360669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.360709] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1235.378641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1235.378661] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.378682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.378699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.378717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.378732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.378747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.378763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.378780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.378797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.378812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.378828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.378841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.378855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.378883] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.378905] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.378926] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1235.378941] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.379152] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.379175] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.402507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1235.402642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1235.402701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.402751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.402760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.402807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.402824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.402841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.402859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.402873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.402889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.402905] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.402920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.402934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.402948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.402960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.402964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.402976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.402980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.402993] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.403006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.403018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.403031] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.403046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.403058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.403071] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.403083] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.403096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.403111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.403128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.405753] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.405769] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.405784] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.405814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.405831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.405847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.405863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.405878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.405894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.405911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.405927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.405943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.405957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.405975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.405995] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.406014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.407995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.408011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.408026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.408041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.409546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.409574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.409587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.411097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.411115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.412935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.415888] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.415946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.415963] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.415986] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.432687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.432713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.432749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.785752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.785822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.785845] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.785893] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.804072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.804091] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.804112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.804128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.804146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.804162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.804181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.804200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.804222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.804243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.804264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.804284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.804303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.804322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.804350] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.804373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.804399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.804416] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.805847] [IGT] kms_flip: exiting, ret=0
>[ 1238.826260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.826282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.826303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.826326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.826345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.826366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.826386] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1238.826406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1238.826426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.826445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.826464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.826469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.826488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.826491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.826511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.826531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.826551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.826570] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1238.826590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.826610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.826629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1238.826649] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1238.826669] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1238.826690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.826712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1238.826789] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.826806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.826823] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.826855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.826876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.826896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.826916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.826943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.826961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.826980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.826996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.827012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.827026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.827039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.827056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1238.827071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.829059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.829074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.829087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.829102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.830614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.830628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.830640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.832142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.832156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.833973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.837015] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1238.837083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.837101] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1238.837128] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.837175] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1238.837194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1238.853839] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.853863] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1238.853900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.854031] Console: switching to colour frame buffer device 240x75
>[ 1239.164993] Console: switching to colour dummy device 80x25
>[ 1239.165109] [IGT] kms_flip: executing
>[ 1239.175295] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1239.175320] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1239.176858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.176878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.178842] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.178849] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1239.180841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.180861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.182842] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.182848] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.182853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1239.182870] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1239.182894] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1239.183922] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1239.184837] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1239.184863] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1239.184887] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1239.184904] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1239.185891] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1239.185914] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1239.186976] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1239.186978] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1239.187057] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.187059] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.187063] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1239.187065] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1239.187069] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.187071] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.187078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1239.187081] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.187084] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.187086] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.187089] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.187091] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.187094] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.187096] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1239.187099] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.187101] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.187103] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.187106] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.187108] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.187111] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1239.187113] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.187115] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.187118] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1239.187120] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.187123] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.187125] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1239.187128] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1239.187130] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1239.187132] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1239.187135] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1239.187137] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1239.187140] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.187142] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.187145] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1239.187147] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.187149] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.187152] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1239.187182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1239.187200] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1239.188831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.188848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.190837] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.190842] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1239.192842] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.192862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.194847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.194853] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.194857] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1239.195077] [IGT] kms_flip: starting subtest 2x-modeset-vs-vblank-race
>[ 1239.197435] [IGT] kms_flip: exiting, ret=77
>[ 1239.220932] Console: switching to colour frame buffer device 240x75
>[ 1239.354724] Console: switching to colour dummy device 80x25
>[ 1239.354868] [IGT] kms_flip: executing
>[ 1239.363444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1239.363469] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1239.364849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.364870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.366853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.366859] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1239.368852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.368872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.370853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.370859] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.370863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1239.370879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1239.370902] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1239.371932] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1239.372847] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1239.372870] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1239.372892] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1239.372912] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1239.373900] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1239.373916] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1239.374993] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1239.374996] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1239.375077] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.375079] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.375084] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1239.375086] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1239.375090] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.375092] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.375099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1239.375102] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.375104] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.375107] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.375109] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.375111] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.375114] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.375116] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1239.375119] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.375121] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.375124] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.375126] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.375129] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.375131] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1239.375133] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.375136] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.375138] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1239.375141] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.375143] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.375146] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1239.375148] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1239.375150] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1239.375153] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1239.375155] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1239.375158] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1239.375160] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.375163] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.375165] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1239.375167] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.375170] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.375172] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1239.375202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1239.375220] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1239.376845] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.376864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.378854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.378859] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1239.380854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.380876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.382854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.382860] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.382863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1239.384118] [IGT] kms_flip: starting subtest 2x-vblank-vs-dpms-suspend-interruptible
>[ 1239.385410] [IGT] kms_flip: exiting, ret=77
>[ 1239.421119] Console: switching to colour frame buffer device 240x75
>[ 1239.551684] Console: switching to colour dummy device 80x25
>[ 1239.551779] [IGT] kms_flip: executing
>[ 1239.562311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1239.562339] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1239.563856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.563874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.565856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.565862] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1239.567865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.567885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.569873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.569879] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.569884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1239.569899] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1239.569922] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1239.570952] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1239.571867] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1239.571893] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1239.571915] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1239.571936] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1239.572937] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1239.572963] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1239.574018] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1239.574020] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1239.574102] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.574104] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.574108] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1239.574110] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1239.574114] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.574116] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.574123] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1239.574126] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.574129] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.574131] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.574134] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.574136] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.574139] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.574141] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1239.574144] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.574146] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.574149] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.574151] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.574153] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.574156] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1239.574158] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.574161] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.574163] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1239.574166] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.574168] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.574170] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1239.574173] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1239.574175] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1239.574178] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1239.574180] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1239.574183] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1239.574185] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.574187] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.574190] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1239.574192] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.574194] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.574197] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1239.574227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1239.574245] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1239.575872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.575892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.577865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.577871] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1239.579867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.579886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.581858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.581863] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.581867] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1239.582070] [IGT] kms_flip: starting subtest 2x-plain-flip-fb-recreate
>[ 1239.584422] [IGT] kms_flip: exiting, ret=77
>[ 1239.604592] Console: switching to colour frame buffer device 240x75
>[ 1239.733760] Console: switching to colour dummy device 80x25
>[ 1239.733909] [IGT] kms_flip: executing
>[ 1239.748309] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1239.748339] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1239.749812] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.749849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.751887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.751893] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1239.753962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.753981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.755455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.755461] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.755465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1239.755483] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1239.755507] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1239.756535] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1239.757420] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1239.757437] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1239.757452] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1239.757467] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1239.758450] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1239.758466] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1239.759516] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1239.759519] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1239.759602] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.759604] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.759609] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1239.759611] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1239.759614] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.759616] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.759624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1239.759627] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.759629] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.759631] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.759634] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.759637] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.759639] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.759642] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1239.759644] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.759647] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.759649] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.759651] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.759654] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.759656] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1239.759659] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.759661] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.759664] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1239.759666] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.759668] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.759671] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1239.759673] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1239.759676] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1239.759678] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1239.759680] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1239.759683] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1239.759685] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.759688] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.759690] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1239.759692] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.759695] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.759697] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1239.759729] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1239.759747] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1239.760941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.760959] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.762883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.762889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1239.764865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.764885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.766878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.766884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.766888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1239.768145] [IGT] kms_flip: starting subtest 2x-nonexisting-fb-interruptible
>[ 1239.769468] [IGT] kms_flip: exiting, ret=77
>[ 1239.804764] Console: switching to colour frame buffer device 240x75
>[ 1239.939597] Console: switching to colour dummy device 80x25
>[ 1239.939693] [IGT] kms_flip: executing
>[ 1239.950329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1239.950359] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1239.951891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.951912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.953891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1239.953897] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1239.955889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.955910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1239.957892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1239.957898] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.957902] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1239.957918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1239.957941] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1239.958967] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1239.959871] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1239.959888] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1239.959903] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1239.959916] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1239.960899] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1239.960915] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1239.961990] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1239.961993] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1239.962071] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.962074] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.962078] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1239.962080] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1239.962084] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1239.962086] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1239.962093] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1239.962096] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.962098] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.962101] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.962103] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.962106] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1239.962108] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.962111] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1239.962113] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.962116] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1239.962118] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1239.962120] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.962123] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1239.962125] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1239.962128] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.962130] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1239.962133] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1239.962135] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.962138] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1239.962140] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1239.962142] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1239.962145] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1239.962147] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1239.962150] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1239.962152] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1239.962155] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.962157] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1239.962159] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1239.962162] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.962164] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1239.962167] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1239.962196] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1239.962213] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1239.963873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.963889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.965899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1239.965904] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1239.967888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.967909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1239.969896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1239.969902] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1239.969906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1239.970109] [IGT] kms_flip: starting subtest 2x-absolute-wf_vblank
>[ 1239.972519] [IGT] kms_flip: exiting, ret=77
>[ 1240.004955] Console: switching to colour frame buffer device 240x75
>[ 1240.137940] Console: switching to colour dummy device 80x25
>[ 1240.138035] [IGT] kms_flip: executing
>[ 1240.152372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1240.152401] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1240.153910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.153931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.155901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.155907] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1240.157906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.157926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.159902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.159908] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.159912] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1240.159928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1240.159952] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1240.160986] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1240.161892] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1240.161919] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1240.161942] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1240.161957] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1240.162945] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1240.162961] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1240.164037] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1240.164040] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1240.164122] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.164124] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.164128] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1240.164130] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1240.164134] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.164136] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.164150] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1240.164153] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.164156] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.164158] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.164161] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.164163] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.164166] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.164168] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1240.164170] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.164173] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.164175] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.164178] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.164180] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.164183] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1240.164185] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.164187] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.164190] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1240.164192] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.164195] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.164197] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1240.164199] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1240.164202] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1240.164204] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1240.164207] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1240.164209] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1240.164211] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.164214] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.164216] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1240.164219] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.164221] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.164224] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1240.164257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1240.164278] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1240.165903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.165920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.167900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.167906] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1240.169908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.169927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.171994] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.171999] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.172003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1240.172200] [IGT] kms_flip: starting subtest 2x-blocking-wf_vblank
>[ 1240.174556] [IGT] kms_flip: exiting, ret=77
>[ 1240.205164] Console: switching to colour frame buffer device 240x75
>[ 1240.334058] Console: switching to colour dummy device 80x25
>[ 1240.334152] [IGT] kms_flip: executing
>[ 1240.345358] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1240.345389] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1240.346922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.346942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.348913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.348919] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1240.350904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.350924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.352913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.352919] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.352923] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1240.352940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1240.352963] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1240.353994] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1240.354899] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1240.354915] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1240.354931] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1240.354948] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1240.355937] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1240.355962] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1240.357020] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1240.357024] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1240.357106] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.357108] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.357112] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1240.357114] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1240.357118] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.357120] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.357128] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1240.357131] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.357133] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.357136] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.357138] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.357141] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.357143] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.357145] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1240.357148] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.357150] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.357153] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.357155] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.357158] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.357160] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1240.357162] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.357165] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.357167] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1240.357170] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.357172] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.357175] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1240.357177] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1240.357179] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1240.357182] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1240.357184] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1240.357187] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1240.357189] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.357191] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.357194] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1240.357196] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.357199] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.357201] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1240.357231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1240.357250] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1240.358916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.358934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.360917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.360922] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1240.362915] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.362935] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.364532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.364539] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.364545] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1240.364897] [IGT] kms_flip: starting subtest 2x-flip-vs-absolute-wf_vblank
>[ 1240.367323] [IGT] kms_flip: exiting, ret=77
>[ 1240.388656] Console: switching to colour frame buffer device 240x75
>[ 1240.517949] Console: switching to colour dummy device 80x25
>[ 1240.518045] [IGT] kms_flip: executing
>[ 1240.528387] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1240.528418] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1240.529931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.529951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.531924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.531930] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1240.533924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.533944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.535924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.535930] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.535934] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1240.535951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1240.535975] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1240.537011] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1240.537915] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1240.537932] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1240.537946] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1240.537960] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1240.538954] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1240.538981] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1240.540039] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1240.540042] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1240.540125] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.540127] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.540131] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1240.540133] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1240.540138] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.540140] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.540147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1240.540150] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.540153] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.540155] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.540158] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.540160] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.540163] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.540165] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1240.540167] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.540170] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.540172] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.540175] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.540177] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.540180] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1240.540182] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.540184] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.540187] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1240.540189] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.540192] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.540194] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1240.540197] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1240.540199] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1240.540201] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1240.540204] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1240.540206] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1240.540209] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.540211] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.540213] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1240.540216] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.540218] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.540221] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1240.540251] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1240.540269] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1240.541923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.541943] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.543917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.543922] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1240.545923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.545941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.547936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.547944] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.547949] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1240.548189] [IGT] kms_flip: starting subtest 2x-flip-vs-wf_vblank
>[ 1240.550535] [IGT] kms_flip: exiting, ret=77
>[ 1240.588810] Console: switching to colour frame buffer device 240x75
>[ 1240.722052] Console: switching to colour dummy device 80x25
>[ 1240.722151] [IGT] kms_flip: executing
>[ 1240.735363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1240.735389] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1240.736938] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.736958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.738942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1240.738948] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1240.740936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.740957] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1240.742937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1240.742942] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.742947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1240.742962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1240.742984] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1240.744017] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1240.744932] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1240.744958] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1240.744976] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1240.744991] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1240.745981] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1240.746003] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1240.747082] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1240.747085] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1240.747164] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.747167] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.747171] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1240.747173] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1240.747177] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1240.747179] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1240.747186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1240.747189] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.747191] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.747194] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.747196] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.747199] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1240.747201] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.747204] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1240.747206] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.747209] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1240.747211] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1240.747214] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.747216] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1240.747218] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1240.747221] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.747223] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1240.747226] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1240.747228] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.747231] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1240.747233] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1240.747235] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1240.747238] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1240.747240] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1240.747243] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1240.747245] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1240.747248] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.747250] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1240.747252] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1240.747255] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.747257] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1240.747260] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1240.747289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1240.747308] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1240.748935] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.748955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.750942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1240.750948] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1240.752936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.752956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1240.754937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1240.754942] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1240.754947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1240.756208] [IGT] kms_flip: starting subtest flip-vs-rmfb-interruptible
>[ 1240.756607] [drm:drm_mode_addfb2] [FB:75]
>[ 1240.756628] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.799232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1240.799286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.805568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1240.805593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.805634] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1240.824495] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1240.824519] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1240.824535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.824555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.824572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.824590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.824609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.824629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.824648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.824670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.824691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.824712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.824732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.824751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.824768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.824797] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.824819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.824845] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1240.824863] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.824979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1240.825102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.825213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1240.825228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.825298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.825325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.825361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.825389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.825411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.825436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.825460] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1240.825483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1240.825507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.825529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.825551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.825557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.825578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.825583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.825605] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.825627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.825649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.825670] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1240.825692] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.825713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.825734] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1240.825755] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1240.825774] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1240.825797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.825823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1240.828352] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.828369] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.828385] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.828414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.828434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.828453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.828471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.828490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.828509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.828529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.828549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.828568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.828587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.828603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.828622] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1240.828641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.830636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.830653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.830668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.830683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.832194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.832210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.832224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.833718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.833734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.835539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.838462] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1240.838497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.838513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1240.838535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.838588] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1240.838602] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1240.855242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.855267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1240.855303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.871930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1240.871940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.888685] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.888745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.921960] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1240.921987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.922026] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1240.940851] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1240.940873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1240.940889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.940958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.940988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.941017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.941042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.941067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.941092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.941122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.941149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.941175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.941201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.941224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.941247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.941291] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.941326] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.941357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1240.941385] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.941497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1240.941507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.941553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.941572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.941590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.941610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.941626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.941646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.941665] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1240.941685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1240.941704] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.941723] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.941742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.941746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.941765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.941768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.941788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.941807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.941826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.941845] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1240.941864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.941883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.941947] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1240.941972] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1240.941996] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1240.942022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.942049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1240.942127] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.942149] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.942172] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.942212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.942235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.942257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.942280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.942301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.942323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.942348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.942373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.942392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.942405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.942419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.942435] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1240.942450] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.944437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.944455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.944472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.944491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.946003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.946020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.946034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.947531] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.947549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.949358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.951691] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1240.951761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.951777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1240.951799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.951840] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1240.951858] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1240.968505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.968530] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1240.968565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.968675] [drm:drm_mode_addfb2] [FB:75]
>[ 1240.968740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.001858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.001884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.001975] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.020807] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.020829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.020846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.020865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.020882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.020946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.020974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.020999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.021026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.021055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.021082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.021107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.021133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.021156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.021179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.021222] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.021257] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.021289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.021317] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.021426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.021436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.021482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.021501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.021519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.021540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.021555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.021572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.021589] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.021605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.021620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.021634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.021648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.021652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.021666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.021669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.021684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.021698] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.021711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.021725] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.021741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.021756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.021777] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.021789] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.021802] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.021817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.021833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.021877] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.021891] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.021942] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.021980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.022001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.022021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.022041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.022061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.022083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.022105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.022127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.022149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.022169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.022189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.022212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.022234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.024444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.024461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.024475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.024490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.026001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.026016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.026029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.027527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.027543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.029355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.032306] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.032364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.032381] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.032403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.032443] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.032460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.049116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.049142] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.049176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.049288] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.049353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.082497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.082522] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.082560] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.101413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.101435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.101452] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.101471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.101488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.101509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.101529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.101549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.101568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.101590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.101611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.101631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.101652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.101671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.101690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.101718] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.101740] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.101765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.101783] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.101888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.101930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.102007] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.102035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.102063] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.102093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.102118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.102145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.102171] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.102196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.102221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.102244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.102267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.102273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.102295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.102301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.102325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.102348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.102371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.102393] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.102419] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.102442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.102465] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.102488] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.102510] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.102536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.102564] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.102622] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.102647] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.102671] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.102712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.102737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.102761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.102785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.102808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.102830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.102856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.102882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.102928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.102952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.102976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.103005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.103031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.105047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.105065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.105082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.105100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.106605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.106622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.106637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.108135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.108159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.109964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.112889] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.112973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.112990] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.113012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.113060] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.113086] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.129716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.129742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.129779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.129927] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.130031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.163073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.163099] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.163144] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.181958] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.181980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.181996] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.182016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.182033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.182050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.182066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.182085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.182104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.182126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.182147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.182168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.182188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.182207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.182226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.182255] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.182278] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.182302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.182321] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.182444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.182454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.182501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.182523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.182544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.182568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.182588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.182609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.182630] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.182650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.182671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.182691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.182711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.182715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.182734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.182738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.182759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.182779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.182799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.182819] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.182840] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.182860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.182880] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.182900] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.182962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.182993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.183023] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.183097] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.183122] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.183147] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.183188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.183520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.183545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.183569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.183591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.183615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.183642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.183668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.183694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.183715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.183737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.183765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.183787] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.185794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.185812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.185826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.185841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.187349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.187365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.187378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.188873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.188889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.190724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.193658] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.193734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.193750] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.193772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.193820] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.193846] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.210478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.210503] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.210537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.210645] [drm:drm_mode_addfb2] [FB:75]
>[ 1241.210727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.243833] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.243858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.243903] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.262778] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.262801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.262817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.262836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.262853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.262871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.262886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.262901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.262960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.262990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.263017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.263045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.263070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.263092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.263116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.263159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.263193] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.263225] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.263253] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.263386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.263402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.263472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.263491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.263510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.263531] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.263550] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.263570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.263589] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.263609] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.263628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.263647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.263666] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.263670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.263688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.263692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.263712] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.263731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.263750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.263769] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.263788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.263807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.263826] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.263845] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.263864] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.263884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.263905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.264010] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.264034] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.264058] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.264098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.264123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.264147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.264170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.264193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.264214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.264239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.264263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.264286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.264308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.264329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.264352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.264375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.266388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.266406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.266421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.266436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.267968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.267983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.267997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.269493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.269509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.271315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.274263] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.274324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.274341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.274363] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.274411] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.274437] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.291073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.291100] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.291137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.291262] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.291326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.324424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.324451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.324500] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.343347] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.343370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.343387] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.343407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.343423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.343441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.343456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.343471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.343487] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.343505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.343521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.343537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.343553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.343567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.343581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.343608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.343631] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.343652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.343669] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.343789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.343799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.343847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.343868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.343890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.343914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.343964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.343994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.344020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.344046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.344070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.344095] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.344116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.344124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.344146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.344153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.344177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.344199] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.344222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.344244] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.344270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.344291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.344315] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.344336] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.344360] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.344385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.344413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.344487] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.344512] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.344535] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.344575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.344597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.344621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.344643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.344665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.344690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.344722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.344745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.344767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.344789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.344808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.344832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.344853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.346874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.346890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.346907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.346949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.348464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.348481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.348499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.350003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.350020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.351827] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.353995] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.354026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.354043] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.354065] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.354106] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.354123] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.370769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.370793] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.370826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.370976] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.371076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.404127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.404150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.404185] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.423036] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.423058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.423074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.423094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.423110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.423131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.423151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.423171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.423190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.423212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.423233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.423253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.423273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.423292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.423311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.423339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.423362] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.423387] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.423405] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.423528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.423538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.423585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.423605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.423625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.423648] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.423669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.423690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.423710] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.423730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.423751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.423771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.423791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.423795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.423815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.423819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.423839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.423860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.423880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.423900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.423921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.423984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.424009] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.424036] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.424059] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.424087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.424116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.424176] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.424202] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.424226] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.424267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.424290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.424322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.424344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.424367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.424390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.424415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.424440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.424465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.424485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.424507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.424531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.424554] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.426569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.426587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.426601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.426616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.428123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.428141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.428159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.429652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.429669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.431475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.434400] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.434432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.434449] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.434471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.434521] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.434536] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.451178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.451203] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.451237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.451347] [drm:drm_mode_addfb2] [FB:75]
>[ 1241.451412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.484534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.484561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.484599] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.503449] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.503471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.503488] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.503507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.503524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.503542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.503557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.503572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.503588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.503606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.503622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.503638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.503654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.503668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.503682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.503708] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.503730] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.503751] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.503768] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.503874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.503884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.503984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.504011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.504045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.504071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.504092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.504116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.504140] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.504162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.504184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.504207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.504224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.504227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.504244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.504249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.504267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.504284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.504303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.504321] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.504339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.504357] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.504375] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.504393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.504411] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.504430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.504450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.504498] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.504513] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.504528] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.504556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.504574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.504593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.504611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.504629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.504647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.504667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.504686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.504705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.504723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.504741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.504760] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.504777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.506760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.506778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.506796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.506814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.508329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.508347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.508361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.509874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.509891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.511696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.514644] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.514705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.514722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.514744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.514783] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.514799] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.531448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.531473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.531508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.531619] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.531685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.564796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.564830] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.564880] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.583567] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.583589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.583606] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.583625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.583642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.583659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.583674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.583689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.583705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.583723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.583740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.583756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.583772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.583786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.583804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.583833] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.583856] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.583881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.583899] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.584038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.584049] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.584094] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.584113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.584131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.584153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.584173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.584193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.584212] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.584232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.584252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.584271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.584290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.584295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.584313] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.584318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.584338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.584357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.584377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.584396] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.584416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.584435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.584455] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.584475] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.584495] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.584514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.584536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.584581] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.584597] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.584613] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.584643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.584663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.584683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.584702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.584722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.584748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.584767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.584783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.584799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.584812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.584825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.584842] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.584857] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.586834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.586851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.586865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.586880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.588388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.588403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.588417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.589954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.589970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.591773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.594695] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.594732] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.594751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.594777] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.594818] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.594838] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.611476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.611501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.611535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.611643] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.611709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.644830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.644855] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.644891] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.663729] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.663751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.663767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.663787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.663804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.663822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.663837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.663852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.663869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.663886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.663903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.663918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.663978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.664000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.664022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.664067] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.664094] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.664116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.664134] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.664240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.664255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.664310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.664328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.664346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.664366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.664382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.664400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.664416] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.664433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.664448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.664464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.664478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.664482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.664496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.664499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.664514] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.664528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.664542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.664555] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.664574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.664594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.664614] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.664641] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.664656] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.664673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.664690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.664733] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.664747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.664760] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.664785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.664800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.664814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.664831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.664849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.664867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.664887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.664906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.664927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.664972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.664993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.665018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.665048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.667042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.667059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.667073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.667088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.668591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.668607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.668620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.670117] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.670132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.671941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.674887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.674994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.675020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.675054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.675103] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.675127] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.691706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.691732] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.691769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.691879] [drm:drm_mode_addfb2] [FB:75]
>[ 1241.691938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.725062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.725086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.725131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.743972] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.743994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.744010] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.744030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.744049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.744071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.744090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.744110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.744129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.744151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.744172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.744192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.744212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.744231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.744250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.744278] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.744300] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.744325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.744343] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.744466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.744475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.744519] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.744536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.744555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.744574] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.744589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.744605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.744622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.744638] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.744653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.744671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.744690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.744694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.744712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.744716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.744735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.744753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.744772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.744790] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.744809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.744827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.744846] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.744865] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.744883] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.744903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.744923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.745005] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.745029] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.745051] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.745090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.745113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.745137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.745158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.745180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.745202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.745227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.745252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.745277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.745297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.745319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.745346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.745367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.747363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.747379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.747393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.747408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.748927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.748960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.748975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.750479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.750495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.752317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.755259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.755327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.755344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.755365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.755413] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.755439] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.772060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.772083] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.772117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.772217] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.772275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.805425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.805449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.805494] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.824318] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.824342] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.824361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.824383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.824403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.824425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.824444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.824464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.824483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.824505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.824526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.824547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.824567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.824586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.824605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.824633] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.824656] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.824681] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.824699] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.824821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.824832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.824880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.824899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.824921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.824945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.825003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.825033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.825061] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.825087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.825114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.825139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.825163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.825170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.825193] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.825200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.825224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.825248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.825273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.825296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.825323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.825347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.825372] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.825395] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.825419] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.825447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.825475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.825549] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.825575] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.825599] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.825640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.825665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.825690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.825714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.825737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.825762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.825788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.825814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.825840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.825863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.825886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.825914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.825940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.827975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.827993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.828007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.828022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.829537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.829556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.829573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.833271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.833290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.835101] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.838045] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.838110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.838127] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.838148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.838186] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.838203] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.854845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.854870] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.854903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.855075] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.855161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.888208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.888233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.888279] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.906125] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.906147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.906163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.906183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.906199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.906217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.906232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.906247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.906263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.906281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.906298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.906314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.906330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.906348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.906367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.906396] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.906419] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.906444] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.906462] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.906584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.906595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.906642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.906662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.906682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.906703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.906720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.906738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.906756] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.906773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.906789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.906805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.906820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.906824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.906839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.906842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.906858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.906873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.906889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.906903] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.906921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.906940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.907003] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.907029] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.907054] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.907082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.907111] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.907184] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.907210] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.907236] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.907276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.907630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.907656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.907681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.907705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.907730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.907758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.907785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.907811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.907835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.907858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.907886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.907912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.909946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.909974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.909989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.910004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.911512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.911529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.911543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.913043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.913059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.914861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.916991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.917061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.917078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.917100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.917145] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.917160] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1241.933805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.933830] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.933866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.934017] [drm:drm_mode_addfb2] [FB:75]
>[ 1241.934132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.967160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1241.967185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.967231] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1241.985241] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1241.985263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1241.985280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.985299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.985316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.985334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.985350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.985365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.985380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.985398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.985414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.985434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.985455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.985474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.985493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.985522] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.985545] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.985569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1241.985587] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.985715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1241.985725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.985769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.985786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.985805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.985825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.985840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.985857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.985873] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1241.985889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1241.985905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.985919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.985933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.985937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.985951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.985990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.986013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.986036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.986060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.986082] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1241.986106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.986129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.986151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1241.986173] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1241.986195] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1241.986220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.986246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1241.986314] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.986337] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.986360] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.986397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.986420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.986443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.986465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.986486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.986509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.986533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.986557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.986581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.986601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.986622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.986647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1241.986670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.988671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.988688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.988703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.988718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.990227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.990242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.990256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.991748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.991765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.993572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.996494] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1241.996529] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.996546] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1241.996568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.996615] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1241.996641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.013275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.013300] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.013335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.013441] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.013508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.046631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.046655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.046701] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.065550] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.065574] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.065593] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.065615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.065635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.065657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.065676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.065696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.065715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.065737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.065757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.065778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.065798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.065817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.065836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.065864] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.065887] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.065912] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.065930] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.066073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.066082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.066128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.066147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.066166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.066186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.066203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.066220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.066238] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.066254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.066270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.066285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.066300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.066304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.066318] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.066321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.066336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.066351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.066365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.066379] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.066397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.066415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.066434] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.066458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.066475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.066494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.066513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.066556] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.066571] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.066584] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.066612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.066631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.066646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.066664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.066682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.066700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.066717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.066736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.066755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.066772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.066794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.066821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.066838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.068810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.068827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.068841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.068858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.070367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.070382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.070396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.071906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.071922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.073726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.076653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.076681] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.076696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.076717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.076762] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.076787] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.093427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.093453] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.093487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.093595] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.093662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.126784] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.126809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.126855] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.145697] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.145719] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.145736] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.145755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.145772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.145790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.145809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.145829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.145848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.145871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.145891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.145912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.145932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.145951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.146013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.146057] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.146094] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.146129] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.146158] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.146260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.146269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.146326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.146343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.146360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.146381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.146399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.146417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.146436] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.146454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.146472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.146490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.146507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.146511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.146528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.146532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.146550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.146568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.146586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.146603] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.146621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.146638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.146656] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.146674] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.146691] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.146710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.146730] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.146774] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.146789] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.146803] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.146831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.146849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.146867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.146885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.146904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.146921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.146941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.146965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.147012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.147033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.147055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.147080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.147101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.149095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.149112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.149126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.149141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.150643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.150658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.150672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.152166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.152182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.153992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.156941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.157038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.157131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.157157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.157199] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.157218] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.173745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.173770] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.173804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.173913] [drm:drm_mode_addfb2] [FB:75]
>[ 1242.174012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.207100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.207125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.207162] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.225870] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.225893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.225909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.225928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.225945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.225963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.226017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.226042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.226068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.226098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.226125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.226151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.226177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.226198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.226221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.226265] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.226299] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.226331] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.226359] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.226468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.226479] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.226529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.226547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.226566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.226586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.226602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.226619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.226636] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.226652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.226668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.226683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.226697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.226701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.226715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.226718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.226733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.226747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.226761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.226774] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.226790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.226804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.226818] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.226832] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.226845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.226869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.226885] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.226923] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.226936] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.226949] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.227014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.227038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.227061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.227084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.227107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.227130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.227155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.227180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.227205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.227227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.227249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.227276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.227299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.230400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.230419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.230435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.230451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.232022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.232041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.232058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.233563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.233582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.235405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.238364] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.238415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.238432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.238454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.238493] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.238510] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.255158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.255184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.255218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.255329] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.255395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.288515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.288543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.288588] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.307441] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.307463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.307479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.307499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.307515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.307533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.307549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.307564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.307580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.307598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.307614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.307630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.307646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.307661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.307675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.307702] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.307724] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.307745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.307762] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.307882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.307892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.307941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.307960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.308028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.308061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.308087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.308115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.308142] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.308169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.308195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.308220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.308244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.308251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.308274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.308281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.308305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.308329] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.308353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.308376] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.308403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.308427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.308451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.308474] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.308497] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.308523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.308551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.308617] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.308642] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.308665] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.308704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.308729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.308752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.308775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.308798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.308822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.308848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.308873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.308898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.308920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.308942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.308969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.309016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.311019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.311036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.311053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.311071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.312588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.312604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.312619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.314118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.314135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.315942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.318875] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.318952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.318968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.319029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.319190] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.319210] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.335686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.335710] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.335743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.335852] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.335916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.369052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.369078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.369117] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.387969] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.388007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.388024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.388043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.388060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.388078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.388093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.388108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.388124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.388142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.388158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.388174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.388190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.388204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.388218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.388245] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.388267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.388289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.388306] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.388427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.388437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.388485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.388504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.388525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.388546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.388563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.388581] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.388600] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.388617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.388637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.388658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.388678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.388682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.388702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.388705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.388726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.388747] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.388767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.388787] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.388807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.388827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.388848] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.388868] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.388888] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.388909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.388931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.389878] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.389902] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.389925] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.389964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.390012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.390035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.390060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.390083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.390107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.390132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.390156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.390180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.390202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.390223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.390248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.390271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.392272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.392290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.392304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.392320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.393823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.393839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.393853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.395348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.395364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.397167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.400098] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.400125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.400145] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.400171] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.400211] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.400231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.416869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.416894] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.416928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.417154] [drm:drm_mode_addfb2] [FB:75]
>[ 1242.417220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.450225] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.450252] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.450290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.469129] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.469153] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.469173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.469195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.469215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.469236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.469256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.469275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.469295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.469316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.469337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.469357] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.469378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.469397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.469416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.469444] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.469467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.469492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.469510] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.469634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.469645] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.469692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.469711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.469731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.469753] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.469770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.469788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.469807] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.469828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.469848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.469869] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.469889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.469893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.469913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.469916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.469937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.469958] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.469978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.470045] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.470074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.470102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.470128] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.470154] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.470178] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.470206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.470235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.470310] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.470335] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.470360] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.470400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.470425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.470449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.470473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.470496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.470521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.470548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.470574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.470600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.470625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.470649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.470674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.470700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.472715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.472732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.472747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.472762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.474268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.474284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.474298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.475790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.475806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.477611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.480542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.480570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.480586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.480608] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.480646] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.480663] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.497315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.497340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.497374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.497482] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.497548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.530670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.530697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.530735] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.549585] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.549609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.549629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.549651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.549671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.549693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.549712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.549731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.549751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.549772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.549793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.549814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.549834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.549853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.549872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.549900] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.549923] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.549948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.549966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.550121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.550136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.550207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.550232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.550260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.550290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.550312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.550339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.550363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.550386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.550409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.550432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.550452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.550458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.550480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.550485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.550508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.550529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.550551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.550572] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.550597] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.550618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.550640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.550661] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.550683] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.550707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.550733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.550801] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.550826] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.550850] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.550888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.550911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.550934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.550962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.550983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.551023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.551047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.551071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.551096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.551116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.551137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.551163] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.551184] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.554269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.554288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.554304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.554320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.555829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.555845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.555859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.557355] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.557371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.559176] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.562119] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.562185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.562203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.562227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.562264] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.562282] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.578929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.578954] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.578989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.579214] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.579272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.612286] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.612312] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.612350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.631197] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.631219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.631236] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.631255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.631272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.631291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.631310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.631329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.631348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.631370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.631391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.631411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.631431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.631450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.631469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.631497] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.631520] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.631545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.631564] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.631682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.631692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.631740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.631759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.631786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.631806] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.631821] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.631838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.631855] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.631878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.631901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.631916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.631930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.631933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.631947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.631950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.631964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.631977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.632029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.632050] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.632075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.632095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.632117] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.632138] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.632161] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.632184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.632210] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.632279] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.632302] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.632325] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.632363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.632384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.632406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.632426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.632448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.632469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.632493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.632517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.632540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.632560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.632581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.632607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.632628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.634632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.634650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.634667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.634685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.636192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.636208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.636223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.637714] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.637730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.639535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.642470] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.642544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.642561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.642583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.642621] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.642638] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.659288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.659313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.659348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.659455] [drm:drm_mode_addfb2] [FB:75]
>[ 1242.659520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.692654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.692680] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.692718] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.711508] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.711531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.711547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.711566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.711583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.711601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.711616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.711631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.711647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.711665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.711681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.711697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.711713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.711727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.711741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.711768] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.711790] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.711810] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.711828] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.711930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.711941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.711994] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.712047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.712078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.712109] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.712133] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.712161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.712186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.712211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.712235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.712260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.712281] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.712535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.712559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.712565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.712589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.712619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.712640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.712660] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.712684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.712703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.712724] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.712743] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.712764] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.712785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.712810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.712875] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.712897] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.712919] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.712955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.712976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.712997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.713038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.713058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.713082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.713107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.713131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.713156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.713176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.713197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.713223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.713244] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.715401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.715418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.715432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.715447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.716964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.716981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.716996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.718587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.718603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.720417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.723346] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.723374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.723390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.723411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.723449] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.723465] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.740121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.740146] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.740181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.740286] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.740351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.773476] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.773501] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.773537] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.791754] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.791776] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.791792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.791811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.791828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.791845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.791860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.791875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.791891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.791909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.791926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.791942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.791958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.791973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.791987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.792062] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.792099] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.792133] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.792162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.792279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.792289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.792332] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.792357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.792374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.792393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.792407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.792423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.792440] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.792458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.792477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.792494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.792513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.792517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.792534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.792538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.792556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.792574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.792592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.792609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.792628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.792645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.792663] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.792681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.792699] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.792718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.792737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.792779] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.792794] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.792808] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.792836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.792854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.792873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.792891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.792909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.792926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.792946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.792967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.792994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.793036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.793059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.793083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.793105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.795094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.795110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.795125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.795140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.796641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.796656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.796670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.798166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.798182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.800000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.802941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.803046] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.803074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.803182] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.803220] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.803237] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.819762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.819787] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.819822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.819928] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.819994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.853117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.853142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.853178] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.872049] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.872072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.872088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.872108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.872125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.872143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.872159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.872174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.872190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.872208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.872225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.872241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.872257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.872271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.872285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.872312] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.872333] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.872354] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.872371] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.872493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.872505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.872555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.872574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.872594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.872616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.872632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.872650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.872668] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.872685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.872702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.872718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.872733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.872737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.872752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.872756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.872776] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.872797] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.872817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.872837] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.872858] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.872877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.872898] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.872918] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.872938] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.872959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.872981] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.873082] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.873106] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.873127] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.873169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.873193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.873218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.873240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.873263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.873286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.873313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.873339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.873365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.873387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.873410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.873438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.873463] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.875490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.875507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.875522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.875537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.877074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.877090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.877103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.879670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.879688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.881512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.884467] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.884522] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.884542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.884568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.884608] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.884627] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.901266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.901291] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.901326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.901433] [drm:drm_mode_addfb2] [FB:75]
>[ 1242.901499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.934621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1242.934646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.934682] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1242.953535] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1242.953559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1242.953579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.953601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.953621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.953642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.953662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.953681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.953700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.953722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.953743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.953764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.953783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.953802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.953821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.953849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.953872] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.953897] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.953915] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.954055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1242.954072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.954147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.954174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.954200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.954229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.954251] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.954277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.954301] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1242.954325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1242.954348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.954372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.954393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.954399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.954420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.954426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.954449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.954470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.954493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.954513] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1242.954538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.954559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.954581] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1242.954602] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1242.954625] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1242.954648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.954674] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1242.954751] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.954773] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.954795] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.954831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.954851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.954873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.954892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.954913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.954933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.954957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.954980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.955003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.955051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.955071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.955096] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1242.955118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.957156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.957174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.957192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.957210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.958715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.958731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.958745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.960242] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.960257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.962062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.965309] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1242.965376] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.965395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1242.965421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.965462] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1242.965482] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1242.982119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.982145] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1242.982179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.982287] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.982357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.015475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.015499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.015535] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.033736] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.033758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.033774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.033794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.033811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.033829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.033844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.033859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.033875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.033893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.033910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.033926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.033942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.033957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.033971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.033998] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.034065] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.034102] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.034131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.034245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.034259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.034327] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.034352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.034380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.034409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.034433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.034460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.034491] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.034514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.034536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.034558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.034580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.034585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.034606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.034611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.034633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.034654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.034676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.034695] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.034719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.034740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.034760] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.034782] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.034803] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.034827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.034851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.034915] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.034938] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.034961] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.034999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.035041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.035065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.035086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.035109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.035133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.035158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.035183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.035207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.035229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.035251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.035277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.035300] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.037288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.037304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.037317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.037331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.038836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.038851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.038864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.040359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.040375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.042178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.045128] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.045187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.045205] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.045227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.045265] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.045282] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.061921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.061946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.061980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.062186] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.062242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.095288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.095314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.095352] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.114199] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.114231] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.114248] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.114267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.114284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.114303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.114318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.114332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.114348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.114366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.114382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.114397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.114413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.114427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.114441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.114468] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.114490] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.114515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.114534] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.114655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.114665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.114713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.114732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.114752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.114773] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.114793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.114814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.114835] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.114856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.114876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.114897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.114917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.114921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.114940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.114944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.114965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.114985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.115006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.115062] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.115092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.115117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.115143] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.115166] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.115190] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.115218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.115246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.115319] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.115344] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.115656] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.115697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.115721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.115746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.115768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.115791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.115813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.115840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.115865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.115891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.115912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.115934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.115959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.115983] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.117998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.118015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.118058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.118082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.119591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.119606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.119621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.121118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.121136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.122976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.125909] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.125985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.126002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.126068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.126230] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.126247] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.142730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.142755] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.142789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.142897] [drm:drm_mode_addfb2] [FB:75]
>[ 1243.142961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.176086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.176112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.176151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.195003] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.195025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.195089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.195123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.195149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.195178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.195203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.195227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.195253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.195282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.195309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.195335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.195360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.195384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.195407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.195451] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.195485] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.195517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.195546] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.195680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.195690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.195736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.195754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.195782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.195805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.195825] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.195844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.195864] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.195883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.195902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.195921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.195940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.195944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.195962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.195966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.195992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.196007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.196021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.196071] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.196095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.196115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.196136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.196157] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.196176] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.196199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.196223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.196290] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.196313] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.196336] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.196375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.196398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.196422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.196444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.196465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.196488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.196513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.196537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.196560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.196577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.196590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.196606] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.196621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.199806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.199823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.199837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.199852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.201359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.201374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.201387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.202880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.202895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.204700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.207632] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.207710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.207727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.207749] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.207788] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.207805] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.224453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.224479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.224514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.224621] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.224687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.257810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.257835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.257871] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.276717] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.276741] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.276761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.276783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.276803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.276825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.276845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.276864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.276883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.276905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.276926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.276946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.276967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.276986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.277005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.277079] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.277115] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.277151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.277180] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.277305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.277319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.277390] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.277416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.277444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.277474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.277500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.277526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.277552] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.277577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.277602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.277626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.277649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.277656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.277679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.277685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.277708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.277732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.277762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.277784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.277805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.277827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.277848] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.277870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.277889] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.277912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.277937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.278002] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.278026] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.278065] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.278105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.278130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.278153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.278176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.278198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.278222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.278247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.278272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.278296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.278318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.278340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.278366] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.278389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.280379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.280395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.280409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.280424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.281926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.281942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.281955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.283451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.283466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.285270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.288211] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.288279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.288296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.288319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.288357] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.288374] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.305022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.305066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.305103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.305214] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.305283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.338378] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.338402] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.338439] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.357295] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.357318] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.357338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.357360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.357380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.357402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.357421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.357441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.357460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.357482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.357502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.357522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.357543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.357562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.357580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.357609] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.357632] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.357656] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.357674] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.357800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.357810] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.357858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.357879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.357900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.357924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.357944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.357965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.357985] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.358005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.358026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.358091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.358116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.358123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.358146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.358152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.358175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.358197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.358219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.358241] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.358266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.358287] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.358309] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.358330] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.358352] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.358377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.358403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.358477] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.358499] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.358514] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.358541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.358557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.358572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.358587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.358601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.358616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.358633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.358649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.358665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.358679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.358693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.358711] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.358726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.360725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.360742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.360756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.360771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.362279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.362294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.362308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.363801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.363817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.365628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.368563] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.368636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.368652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.368672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.368708] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.368724] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.385381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.385406] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.385441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.385548] [drm:drm_mode_addfb2] [FB:75]
>[ 1243.385616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.418736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.418761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.418798] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.437642] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.437664] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.437683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.437705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.437725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.437747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.437766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.437786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.437805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.437827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.437848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.437868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.437888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.437907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.437926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.437955] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.437978] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.438003] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.438021] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.438170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.438185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.438249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.438274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.438300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.438327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.438350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.438374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.438399] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.438422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.438445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.438467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.438488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.438494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.438515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.438520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.438542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.438563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.438585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.438606] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.438630] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.438652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.438673] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.438693] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.438713] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.438737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.438762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.438827] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.438850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.438872] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.438908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.438931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.438953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.438975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.438995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.439017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.439042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.439083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.439109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.439131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.439153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.439180] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.439203] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.441194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.441210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.441224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.441239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.442742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.442758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.442771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.444267] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.444283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.446087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.449020] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.449128] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.449155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.449193] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.449310] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.449327] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.465851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.465877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.465912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.466020] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.466134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.499197] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.499223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.499261] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.518108] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.518130] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.518147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.518167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.518183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.518201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.518217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.518232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.518248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.518267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.518283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.518299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.518315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.518329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.518344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.518371] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.518392] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.518413] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.518430] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.518543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.518553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.518600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.518620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.518641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.518664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.518684] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.518705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.518726] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.518746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.518767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.518787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.518807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.518811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.518831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.518835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.518855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.518876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.518896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.518916] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.518937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.518957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.518977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.518998] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.519018] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.519039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.519107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.519179] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.519202] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.519224] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.519267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.519292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.519316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.519341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.519365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.519390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.519417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.519442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.519468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.519492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.519515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.519541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.519566] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.521586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.521602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.521616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.521631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.523157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.523175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.523193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.524693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.524711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.526518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.529464] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.529528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.529545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.529570] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.529612] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.529632] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.546272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.546297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.546332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.546441] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.546505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.579627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.579652] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.579689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.598528] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.598550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.598566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.598586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.598603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.598621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.598636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.598651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.598668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.598685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.598702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.598718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.598734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.598747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.598761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.598788] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.598810] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.598831] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.598848] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.598968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.598979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.599026] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.599047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.599107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.599138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.599161] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.599188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.599212] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.599236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.599259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.599281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.599302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.599310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.599331] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.599337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.599359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.599380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.599401] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.599424] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.599635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.599651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.599667] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.599681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.599695] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.599717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.599744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.599793] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.599809] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.599824] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.599854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.599874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.599893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.599913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.599932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.599951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.599972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.599993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.600013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.600032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.600051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.600096] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.600121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.602274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.602291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.602305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.602320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.603825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.603840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.603854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.605351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.605367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.607172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.610095] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.610130] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.610149] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.610175] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.610215] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.610234] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.626875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.626900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.626937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.627093] [drm:drm_mode_addfb2] [FB:75]
>[ 1243.627164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.660230] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.660255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.660292] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.679146] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.679168] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.679187] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.679209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.679229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.679250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.679270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.679290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.679309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.679331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.679352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.679372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.679392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.679411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.679430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.679458] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.679480] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.679505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.679523] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.679645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.679655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.679702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.679722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.679742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.679764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.679785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.679806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.679827] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.679847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.679868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.679888] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.679908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.679912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.679932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.679935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.679956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.679977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.679997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.680017] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.680037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.680057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.680123] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.680152] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.680178] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.680207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.680236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.680311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.680337] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.680362] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.680402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.680429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.680454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.680478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.680501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.680526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.680553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.680579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.680605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.680628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.680651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.680678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.680703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.682712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.682729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.682743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.682761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.684270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.684286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.684299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.685792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.685808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.687613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.690556] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.690623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.690640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.690662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.690706] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.690721] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.707367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.707393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.707427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.707546] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.707621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.740724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.740749] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.740786] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.759627] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.759649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.759666] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.759685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.759702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.759720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.759735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.759750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.759766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.759784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.759804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.759825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.759845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.759864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.759883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.759912] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.759934] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.759959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.759977] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.760118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.760136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.760221] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.760244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.760270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.760296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.760317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.760340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.760362] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.760385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.760405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.760426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.760446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.760451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.760471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.760476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.760497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.760517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.760537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.760556] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.760579] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.760598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.760618] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.760637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.760657] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.760679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.760703] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.760769] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.760800] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.760822] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.760858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.760879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.760901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.760920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.760941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.760961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.760985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.761009] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.761031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.761050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.761092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.761118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.761140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.763136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.763154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.763171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.763190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.764708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.764732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.764754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.766256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.766272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.768091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.771005] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.771048] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.771103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.771139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.771285] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.771302] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.787794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.787820] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.787854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.787971] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.788038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.821150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.821174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.821211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.840061] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.840099] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.840115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.840135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.840151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.840169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.840185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.840199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.840215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.840233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.840249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.840265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.840281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.840295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.840309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.840336] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.840358] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.840378] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.840395] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.840517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.840527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.840575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.840596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.840617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.840641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.840661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.840682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.840702] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.840722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.840743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.840763] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.840783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.840787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.840807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.840811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.840832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.840852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.840873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.840893] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.840913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.840933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.840953] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.840974] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.840994] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.841015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.841037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.841139] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.841163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.841185] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.841226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.841251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.841275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.841298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.841320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.841343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.841372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.841398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.841423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.841445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.841467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.841495] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.841513] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.844598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.844617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.844633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.844653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.846186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.846204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.846222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.847719] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.847736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.849562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.852500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.852571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.852587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.852609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.852647] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.852664] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.869317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.869342] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.869378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.869491] [drm:drm_mode_addfb2] [FB:75]
>[ 1243.869552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.902671] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.902696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.902733] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1243.921589] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1243.921611] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1243.921628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.921649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.921669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.921690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.921710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.921730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.921749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.921771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.921792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.921813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.921833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.921852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.921871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.921899] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.921922] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.921946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.921965] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.922052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1243.922098] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.922174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.922205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.922234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.922263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.922286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.922313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.922336] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1243.922361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1243.922383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.922406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.922427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.922433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.922455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.922460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.922483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.922504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.922527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.922547] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1243.922572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.922593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.922622] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1243.922641] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1243.922661] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1243.922682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.922706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1243.922773] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.922795] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.922817] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.922853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.922873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.922895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.922914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.922935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.922955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.922978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.923002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.923025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.923044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.923064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.923105] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1243.923127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.925122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.925139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.925154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.925168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.926688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.926704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.926717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.928212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.928228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.930038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.932959] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1243.932994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.933011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1243.933033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.933071] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1243.933128] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1243.949740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.949765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1243.949801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.949912] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.949980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.983111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1243.983136] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.983173] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.002019] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.002041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.002058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.002122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.002150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.002181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.002205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.002230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.002255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.002284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.002311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.002337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.002363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.002386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.002417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.002460] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.002493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.002524] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.002551] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.002653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.002663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.002708] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.002728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.002747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.002768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.002786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.002805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.002824] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.002843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.002861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.002880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.002898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.002902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.002920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.002924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.002942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.002961] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.002979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.002998] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.003016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.003035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.003053] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.003072] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.003131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.003157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.003183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.003255] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.003453] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.003468] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.003495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.003514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.003532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.003550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.003568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.003585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.003605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.003640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.003661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.003677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.003691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.003708] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.003723] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.005701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.005719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.005736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.005755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.007263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.007280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.007294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.008786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.008803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.010609] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.013544] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.013624] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.013639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.013659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.013695] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.013710] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.030362] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.030387] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.030422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.030531] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.030595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.063717] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.063741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.063777] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.082654] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.082676] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.082692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.082712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.082729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.082747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.082763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.082778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.082794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.082812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.082829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.082845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.082865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.082884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.082903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.082931] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.082954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.082979] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.082998] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.083131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.083149] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.083405] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.083429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.083455] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.083482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.083503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.083528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.083550] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.083573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.083594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.083616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.083635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.083641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.083662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.083667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.083688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.083708] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.083729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.083749] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.083773] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.083793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.083814] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.083834] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.083855] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.083877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.083901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.083969] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.083992] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.084014] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.084052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.084073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.084123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.084143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.084165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.084187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.084211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.084236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.084261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.084281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.084302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.084328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.084349] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.086578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.086595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.086609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.086627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.088157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.088175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.088193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.089692] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.089710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.091518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.093626] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.093667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.093684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.093706] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.093755] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.093781] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.110412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.110437] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.110471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.110579] [drm:drm_mode_addfb2] [FB:75]
>[ 1244.110645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.143768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.143793] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.143829] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.162676] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.162698] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.162715] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.162734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.162751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.162769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.162784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.162799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.162815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.162833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.162849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.162865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.162881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.162895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.162909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.162936] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.162958] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.162979] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.162996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.163129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.163148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.163224] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.163249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.163276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.163305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.163328] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.163353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.163377] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.163401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.163424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.163447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.163467] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.163473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.163494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.163500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.163523] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.163544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.163567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.163587] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.163612] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.163645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.163666] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.163688] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.163708] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.163734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.163760] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.163832] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.163857] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.163880] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.163926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.163946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.163968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.163988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.164009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.164029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.164053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.164076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.164118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.164138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.164161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.164185] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.164208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.166206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.166223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.166237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.166252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.167756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.167772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.167785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.169281] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.169297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.171118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.174059] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.174163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.174189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.174223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.174367] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.174383] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.190872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.190897] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.190932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.191039] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.191171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.224227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.224252] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.224288] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.243132] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.243154] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.243171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.243190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.243207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.243225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.243240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.243255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.243271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.243289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.243306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.243322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.243338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.243356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.243375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.243404] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.243427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.243451] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.243470] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.243577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.243588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.243636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.243655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.243675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.243697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.243713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.243731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.243749] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.243766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.243783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.243799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.243819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.243823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.243843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.243847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.243868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.243888] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.243909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.243929] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.243950] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.243970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.243990] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.244010] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.244030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.244051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.244073] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.244182] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.244209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.244234] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.244276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.244304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.244330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.244355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.244380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.244406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.244434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.244461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.244487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.244517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.244540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.244566] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.244589] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.246588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.246605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.246619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.246633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.248156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.248173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.248188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.249681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.249698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.251504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.254452] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.254514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.254531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.254553] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.254592] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.254609] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.271258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.271283] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.271317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.271427] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.271485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.304612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.304638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.304677] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.322575] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.322597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.322614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.322633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.322650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.322668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.322683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.322698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.322714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.322732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.322748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.322764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.322780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.322794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.322812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.322841] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.322863] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.322888] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.322906] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.323021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.323031] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.323078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.323144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.323176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.323207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.323232] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.323261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.323289] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.323321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.323345] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.323368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.323390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.323397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.323418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.323424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.323446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.323468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.323491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.323513] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.323537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.323559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.323805] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.323828] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.323850] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.323875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.323901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.323968] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.323991] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.324013] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.324050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.324073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.324095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.324134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.324156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.324177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.324203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.324227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.324251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.324272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.324294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.324478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.324501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.326502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.326519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.326534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.326549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.328056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.328071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.328085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.329621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.329638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.331478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.334414] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.334488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.334505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.334533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.334568] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.334583] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.351232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.351257] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.351292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.351401] [drm:drm_mode_addfb2] [FB:75]
>[ 1244.351459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.384587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.384611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.384648] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.403482] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.403504] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.403521] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.403541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.403558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.403576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.403591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.403605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.403621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.403640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.403656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.403672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.403688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.403702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.403716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.403743] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.403766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.403791] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.403809] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.403938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.403948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.403993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.404011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.404030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.404050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.404066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.404082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.404100] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.404150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.404173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.404197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.404220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.404228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.404249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.404256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.404279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.404302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.404325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.404347] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.404373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.404395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.404418] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.404440] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.404463] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.404489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.404515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.404829] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.404853] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.404876] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.404915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.404939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.404970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.404992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.405014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.405035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.405060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.405084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.405125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.405147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.405169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.405195] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.405219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.407343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.407360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.407374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.407389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.408892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.408908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.408922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.410417] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.410434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.412255] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.415025] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.415062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.415079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.415147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.415307] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.415325] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.431814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.431840] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.431878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.431990] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.432059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.465161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.465185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.465222] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.484071] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.484093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.484153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.484183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.484211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.484239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.484261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.484285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.484308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.484336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.484362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.484388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.484413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.484434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.484457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.484500] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.484534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.484566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.484593] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.484714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.484724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.484772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.484792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.484812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.484833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.484852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.484880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.484899] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.484916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.484932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.484951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.484970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.484975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.484994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.484998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.485018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.485038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.485057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.485077] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.485097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.485160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.485188] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.485213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.485238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.485265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.485293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.485366] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.485622] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.485646] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.485686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.485711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.485735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.485759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.485782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.485806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.485831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.485856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.485881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.485911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.485933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.485957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.485980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.487986] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.488003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.488020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.488038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.489547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.489563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.489577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.491072] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.491088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.492917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.495850] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.495926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.495943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.495965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.496003] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.496020] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.512670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.512696] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.512730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.512839] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.512905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.546026] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.546051] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.546087] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.564894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.564916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.564932] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.564952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.564968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.564986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.565001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.565016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.565032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.565050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.565066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.565083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.565099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.565161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.565183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.565227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.565263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.565296] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.565325] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.565455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.565472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.565549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.565577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.565605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.565642] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.565664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.565689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.565713] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.565736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.565769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.565791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.565814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.565819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.565840] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.565846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.565867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.565889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.565910] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.565929] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.565953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.565974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.565994] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.566015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.566036] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.566060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.566086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.566177] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.566202] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.566225] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.566263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.566286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.566308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.566330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.566352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.566375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.566400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.566424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.566447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.566468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.566490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.566515] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.566538] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.568534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.568551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.568565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.568582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.570090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.570106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.570151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.571649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.571666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.573493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.576433] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.576502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.576519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.576540] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.576578] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.576594] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.593248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.593274] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.593312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.593422] [drm:drm_mode_addfb2] [FB:75]
>[ 1244.593491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.626601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.626627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.626665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.645526] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.645549] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.645565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.645585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.645601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.645619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.645634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.645650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.645666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.645684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.645701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.645716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.645733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.645747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.645761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.645789] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.645812] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.645836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.645855] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.645979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.645989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.646036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.646056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.646076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.646097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.646114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.646168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.646193] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.646220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.646246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.646271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.646295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.646303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.646326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.646332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.646356] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.646380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.646405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.646428] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.646455] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.646479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.646503] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.646527] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.646551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.646578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.646606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.646943] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.646969] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.646993] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.647035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.647062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.647087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.647111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.647156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.647183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.647212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.647238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.647265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.647410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.647432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.647457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.647480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.649484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.649502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.649517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.649532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.651058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.651074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.651091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.652618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.652635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.654473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.657409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.657482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.657507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.657528] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.657563] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.657578] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.674227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.674254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.674290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.674401] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.674470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.707582] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.707608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.707646] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.726500] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.726522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.726539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.726558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.726575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.726593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.726613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.726632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.726652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.726674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.726695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.726715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.726735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.726754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.726773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.726801] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.726824] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.726849] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.726867] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.726982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.726992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.727039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.727059] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.727079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.727100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.727117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.727179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.727209] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.727235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.727262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.727287] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.727311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.727318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.727342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.727349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.727373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.727397] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.727422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.727445] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.727473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.727496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.727521] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.727545] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.727569] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.727596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.727889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.727962] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.727987] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.728011] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.728053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.728079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.728104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.728153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.728176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.728198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.728224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.728249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.728377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.728398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.728420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.728445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.728468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.730469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.730486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.730501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.730515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.732019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.732034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.732048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.733545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.733560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.735366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.738314] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.738373] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.738388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.738409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.738445] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.738460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.755118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.755160] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.755194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.755300] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.755358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.788475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.788499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.788535] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.807377] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.807398] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.807414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.807434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.807451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.807469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.807484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.807499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.807515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.807532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.807549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.807566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.807582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.807596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.807610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.807637] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.807659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.807680] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.807697] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.807810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.807821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.807869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.807888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.807915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.807936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.807955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.807976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.807996] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.808016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.808036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.808055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.808075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.808079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.808098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.808102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.808122] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.808183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.808210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.808236] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.808263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.808288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.808312] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.808337] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.808360] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.808387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.808414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.808485] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.808510] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.808534] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.808573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.808597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.808620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.808643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.808666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.808690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.808716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.808742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.808767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.808789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.808809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.808836] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.808860] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.810861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.810878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.810892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.810908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.812413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.812429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.812443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.813933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.813949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.815754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.818344] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.818409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.818426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.818448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.818485] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.818502] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.835153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.835178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.835212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.835322] [drm:drm_mode_addfb2] [FB:75]
>[ 1244.835387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.868507] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.868533] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.868572] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.887412] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.887434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.887450] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.887470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.887487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.887505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.887521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.887536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.887551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.887569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.887586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.887606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.887626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.887646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.887665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.887693] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.887716] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.887741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.887759] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.887880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.887891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.887938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.887957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.887977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.887998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.888015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.888033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.888051] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.888068] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.888084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.888100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.888115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.888158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.888182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.888189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.888214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.888236] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.888260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.888281] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.888308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.888330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.888353] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.888375] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.888398] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.888425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.888453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.888527] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.888552] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.888576] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.888616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.888638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.888662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.888693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.888714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.888738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.888771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.888794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.888817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.888836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.888856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.888878] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.888901] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.890899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.890916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.890932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.890951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.892468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.892486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.892504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.893999] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.894016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.895825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.898761] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.898835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.898852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.898875] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.898913] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.898930] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.915577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.915603] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.915637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.915744] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.915828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.948934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1244.948959] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.948995] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1244.967674] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1244.967696] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1244.967713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.967732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.967749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.967767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.967782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.967796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.967812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.967829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.967846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.967862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.967877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.967891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.967905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.967932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.967954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.967975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.967992] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.968097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1244.968108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.968215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.968241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.968270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.968301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.968323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.968351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.968375] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.968400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.968423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.968446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.968468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.968474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.968496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.968509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.968530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.968550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.968571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.968590] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.968613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.968632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.968653] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.968672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.968693] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.968714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.968738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.968807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.968829] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.968851] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.968887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.968909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.968930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.968950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.968971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.968991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.969014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.969037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.969060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.969079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.969099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.969124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.969167] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.971162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.971181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.971198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.971217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.972724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.972741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.972755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.974253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.974269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.976082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.979016] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.979092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.979108] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.979130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.979335] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.979353] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.995836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.995861] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.995895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.996004] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.996070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.029191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.029215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.029252] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.048096] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.048119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.048139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.048209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.048239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.048269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.048294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.048319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.048344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.048373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.048400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.048427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.048452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.048476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.048499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.048542] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.048577] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.048609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.048637] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.048760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.048770] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.048818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.048837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.048858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.048881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.048901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.048922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.048943] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.048963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.048984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.049004] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.049032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.049037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.049057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.049061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.049081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.049102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.049122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.049178] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.049204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.049229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.049253] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.049276] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.049297] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.049322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.049349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.049427] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.049450] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.049473] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.049512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.049536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.049559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.049581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.049603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.049626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.049650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.049674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.049698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.049718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.049732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.049750] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.049769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.051759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.051776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.051791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.051807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.053314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.053330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.053344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.054835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.054853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.056658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.059609] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.059666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.059681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.059702] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.059738] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.059754] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.076410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.076436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.076473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.076585] [drm:drm_mode_addfb2] [FB:75]
>[ 1245.076655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.109766] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.109791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.109828] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.128183] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.128205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.128222] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.128241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.128261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.128282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.128302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.128322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.128341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.128363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.128383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.128404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.128424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.128443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.128462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.128490] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.128513] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.128537] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.128561] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.128691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.128701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.128749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.128768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.128788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.128810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.128827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.128845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.128863] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.128880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.128897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.128912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.128932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.128936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.128956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.128959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.128980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.129000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.129021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.129041] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.129061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.129081] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.129101] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.129121] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.129141] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.129212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.129242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.129316] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.129342] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.129366] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.129407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.129431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.129455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.129478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.129501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.129524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.129550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.129575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.129601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.129622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.129645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.129670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.129695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.131702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.131719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.131733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.131750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.133261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.133277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.133292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.134786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.134802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.136608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.139557] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.139617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.139634] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.139656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.139695] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.139711] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.156361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.156386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.156421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.156529] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.156588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.189716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.189741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.189779] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.208623] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.208647] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.208667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.208689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.208709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.208730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.208750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.208769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.208789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.208810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.208831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.208852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.208872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.208891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.208910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.208938] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.208961] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.208986] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.209004] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.209102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.209114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.209201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.209228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.209257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.209287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.209311] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.209338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.209363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.209389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.209412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.209438] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.209460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.209467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.209489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.209496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.209520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.209800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.209830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.209852] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.209874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.209895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.209915] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.209936] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.209956] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.209979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.210004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.210069] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.210092] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.210113] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.210150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.210256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.210277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.210298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.210318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.210339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.210364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.210387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.210410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.210429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.210450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.210474] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.210495] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.212488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.212504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.212518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.212532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.214039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.214054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.214067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.215563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.215579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.217385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.220329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.220394] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.220411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.220433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.220472] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.220488] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.237147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.237190] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.237224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.237343] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.237409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.270527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.270552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.270589] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.289444] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.289466] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.289483] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.289502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.289519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.289537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.289553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.289568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.289584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.289605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.289626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.289647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.289667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.289686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.289705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.289733] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.289756] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.289781] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.289799] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.289920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.289931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.289978] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.289998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.290018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.290040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.290057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.290075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.290094] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.290111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.290128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.290144] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.290202] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.290209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.290234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.290240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.290265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.290287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.290311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.290333] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.290359] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.290381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.290404] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.290426] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.290449] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.290476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.290504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.290564] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.290589] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.290614] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.290653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.290676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.290699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.290721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.290743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.290765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.290791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.290817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.290842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.290862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.290885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.290909] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.290933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.292940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.292956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.292970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.292985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.294492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.294508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.294522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.296014] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.296030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.297836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.300778] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.300845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.300861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.300882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.300919] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.300935] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.317587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.317611] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.317644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.317764] [drm:drm_mode_addfb2] [FB:75]
>[ 1245.317837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.350943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.350966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.351002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.369828] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.369851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.369867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.369887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.369904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.369925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.369945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.369965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.369984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.370006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.370027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.370048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.370068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.370087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.370106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.370134] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.370201] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.370237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.370266] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.370388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.370403] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.370467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.370486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.370505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.370525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.370541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.370559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.370576] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.370593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.370609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.370624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.370638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.370643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.370657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.370660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.370680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.370700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.370720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.370740] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.370760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.370779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.370799] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.370818] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.370839] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.370859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.370880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.370926] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.370943] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.370958] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.370989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.371008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.371028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.371047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.371067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.371086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.371108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.371136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.371153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.371195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.371216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.371241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.371264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.373258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.373275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.373290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.373305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.374808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.374823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.374836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.376335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.376350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.378160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.381105] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.381221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.381249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.381285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.381344] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.381368] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.397922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.397946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.397979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.398099] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.398220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.431280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.431304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.431350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.450199] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.450221] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.450238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.450257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.450274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.450292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.450308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.450322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.450339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.450356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.450373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.450389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.450405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.450419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.450433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.450460] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.450483] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.450507] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.450526] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.450651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.450661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.450711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.450732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.450755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.450778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.450799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.450820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.450840] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.450860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.450881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.450901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.450921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.450925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.450944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.450948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.450969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.450989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.451010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.451030] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.451050] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.451070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.451090] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.451110] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.451131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.451152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.451222] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.451282] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.451306] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.451328] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.451371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.451398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.451422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.451444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.451469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.451490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.451508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.451525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.451541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.451556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.451570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.451589] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.451605] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.453585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.453602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.453619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.453638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.455146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.455174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.455188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.456700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.456718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.458537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.461481] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.461546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.461563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.461585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.461624] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.461643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.478298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.478325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.478362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.478478] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.478548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.511677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.511704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.511742] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.530576] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.530598] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.530614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.530634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.530651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.530668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.530684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.530699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.530715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.530733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.530749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.530766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.530782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.530796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.530810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.530837] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.530859] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.530880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.530897] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.531020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.531030] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.531078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.531098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.531118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.531139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.531156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.531218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.531244] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.531270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.531293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.531318] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.531339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.531347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.531370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.531377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.531401] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.531423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.531447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.531468] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.531494] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.531516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.531539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.531561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.531584] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.531611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.531638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.531711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.531736] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.531759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.531799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.531822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.531845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.531865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.531888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.531910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.531936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.531961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.531986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.532006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.532028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.532053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.532077] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.534079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.534096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.534110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.534125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.535630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.535645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.535658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.537154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.537183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.538988] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.541913] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.541945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.541962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.541984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.542031] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.542056] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.558688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.558715] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.558751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.558854] [drm:drm_mode_addfb2] [FB:75]
>[ 1245.558917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.592047] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.592072] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.592108] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.610967] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.610991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.611011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.611032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.611052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.611074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.611093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.611113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.611132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.611153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.611174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.611238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.611267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.611291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.611315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.611358] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.611392] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.611424] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.611452] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.611567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.611585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.611660] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.611687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.611716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.611755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.611780] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.611807] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.611834] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.611859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.611885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.611909] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.611932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.611938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.611961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.611968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.611991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.612014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.612037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.612058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.612084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.612107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.612128] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.612151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.612171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.612219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.612246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.612321] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.612354] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.612377] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.612414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.612436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.612459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.612479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.612500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.612521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.612546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.612570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.612593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.612615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.612636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.612660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.612683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.614708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.614726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.614740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.614755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.616258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.616274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.616287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.617778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.617794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.619598] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.622542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.622606] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.622621] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.622642] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.622678] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.622693] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.639351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.639377] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.639414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.639517] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.639581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.672705] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.672730] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.672767] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.691643] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.691665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.691681] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.691701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.691718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.691735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.691750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.691765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.691781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.691799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.691815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.691832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.691847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.691862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.691876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.691903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.691925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.691946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.691963] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.692081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.692091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.692135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.692154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.692173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.692231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.692256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.692283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.692309] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.692335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.692359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.692383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.692406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.692413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.692435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.692442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.692466] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.692488] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.692512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.692534] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.692560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.692582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.692606] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.692628] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.692651] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.692677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.692702] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.692771] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.692795] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.692818] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.692856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.692880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.692902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.692925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.692947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.692971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.692996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.693020] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.693045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.693074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.693095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.693120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.693144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.695155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.695172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.695219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.695246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.696758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.696773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.696786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.698298] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.698315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.700127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.703049] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.703085] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.703105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.703131] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.703171] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.703221] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.719829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.719854] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.719889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.719988] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.720055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.753186] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.753226] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.753263] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.771231] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.771253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.771269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.771289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.771306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.771323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.771338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.771353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.771369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.771387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.771404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.771420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.771436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.771450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.771464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.771491] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.771514] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.771534] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.771551] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.771668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.771678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.771725] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.771749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.771767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.771786] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.771801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.771817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.771834] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.771853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.771871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.771889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.771907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.771911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.771928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.771931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.771950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.771968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.771986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.772003] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.772022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.772039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.772057] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.772075] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.772093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.772112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.772131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.772177] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.772239] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.772265] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.772306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.772331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.772356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.772380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.772403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.772427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.772454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.772479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.772504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.772527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.772550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.772577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.772601] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.774614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.774631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.774648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.774666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.776173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.776203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.776221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.777713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.777730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.779538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.782502] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.782548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.782567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.782593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.782638] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.782658] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.799292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.799318] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.799352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.799459] [drm:drm_mode_addfb2] [FB:75]
>[ 1245.799530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.832670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.832697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.832735] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.851573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.851598] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.851618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.851640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.851659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.851681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.851701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.851720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.851739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.851761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.851782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.851802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.851821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.851840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.851859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.851888] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.851911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.851936] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.851954] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.852070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.852080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.852126] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.852144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.852162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.852185] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.852236] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.852263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.852287] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.852311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.852333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.852355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.852376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.852382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.852403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.852409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.852431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.852452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.852473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.852494] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.852518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.852539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.852560] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.852581] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.852602] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.852628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.852655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.852726] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.852742] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.852756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.852783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.852799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.852814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.852829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.852842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.852858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.852875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.852891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.852907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.852921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.852934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.852952] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.852968] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.854949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.854967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.854985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.855003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.856509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.856525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.856539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.858029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.858045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.859858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.862773] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.862814] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.862831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.862853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.862891] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.862907] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.879568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.879590] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.879623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.879725] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.879789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.912914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.912949] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.913002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.930891] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.930914] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.930934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.930956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.930975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.930997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.931017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.931036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.931056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.931076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.931097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.931117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.931137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.931156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.931175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.931248] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.931283] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.931316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.931334] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.931420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.931430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.931475] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.931492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.931511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.931530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.931546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.931563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.931579] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.931595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.931611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.931625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.931640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.931644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.931657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.931661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.931680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.931700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.931719] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.931738] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.931758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.931776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.931796] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.931815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.931834] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.931854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.931875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.931915] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.931931] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.931946] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.931976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.931996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.932016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.932035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.932055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.932074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.932095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.932115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.932142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.932158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.932172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.932195] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.932248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.934247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.934264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.934279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.934294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.935800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.935816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.935829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.937327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.937343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.939150] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.942177] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.942261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.942279] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.942307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.942352] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.942375] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.958997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.959024] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.959062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.959206] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.959313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.992361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.992388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.992437] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.011275] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.011299] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.011315] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.011335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.011352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.011370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.011385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.011400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.011415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.011433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.011450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.011466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.011482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.011497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.011511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.011538] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.011560] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.011581] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.011598] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.011723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.011734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.011780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.011799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.011818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.011839] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.011855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.011872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.011892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.011912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.011932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.011952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.011971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.011975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.011995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.011998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.012019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.012038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.012058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.012077] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.012097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.012117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.012136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.012156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.012176] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.012197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.012253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.012328] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.012353] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.012377] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.012419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.012445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.012469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.012524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.012548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.012572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.012599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.012624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.012649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.012672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.012694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.012729] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.012752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.014753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.014770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.014785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.014800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.016308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.016324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.016338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.017830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.017848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.019654] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.022587] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.022663] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.022680] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.022702] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.022751] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.022777] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.039407] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.039433] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.039467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.039580] [drm:drm_mode_addfb2] [FB:75]
>[ 1246.039638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.072763] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.072787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.072833] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.091688] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.091712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.091731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.091753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.091773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.091795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.091814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.091834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.091853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.091875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.091896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.091916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.091937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.091956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.091975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.092003] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.092026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.092050] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.092069] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.092172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.092183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.092286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.092483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.092512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.092550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.092572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.092597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.092622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.092645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.092669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.092691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.092712] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.092718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.092738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.092743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.092765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.092787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.092808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.092828] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.092852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.092873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.092895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.092916] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.092937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.092961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.092987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.093054] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.093077] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.093099] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.093137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.093160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.093182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.093203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.093243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.093266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.093292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.093317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.093341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.093363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.093385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.093411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.093435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.095666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.095683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.095697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.095713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.097238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.097254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.097267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.098764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.098780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.100620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.103567] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.103629] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.103646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.103668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.103724] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.103748] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.120373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.120399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.120434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.120541] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.120606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.153728] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.153753] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.153798] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.172645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.172667] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.172684] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.172703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.172720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.172738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.172753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.172768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.172784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.172802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.172819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.172835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.172851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.172865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.172879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.172906] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.172928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.172950] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.172967] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.173090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.173100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.173148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.173168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.173188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.173253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.173281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.173310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.173338] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.173365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.173390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.173415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.173439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.173446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.173469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.173476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.173500] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.173524] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.173548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.173571] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.173598] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.173622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.173646] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.173670] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.173694] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.173721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.173750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.174120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.174146] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.174171] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.174214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.174260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.174287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.174311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.174337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.174369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.174467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.174491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.174515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.174536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.174557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.174582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.174605] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.176602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.176619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.176636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.176654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.178167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.178183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.178199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.179730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.179746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.181563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.184523] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.184571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.184588] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.184610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.184654] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.184669] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.201324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.201349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.201384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.201498] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.201564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.234703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.234728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.234766] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.252967] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.252990] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.253010] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.253032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.253052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.253074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.253093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.253113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.253132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.253152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.253173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.253194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.253259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.253289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.253317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.253359] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.253394] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.253427] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.253456] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.253585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.253603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.253678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.253703] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.253731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.253760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.253783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.253809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.253834] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.253858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.253881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.253904] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.253926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.253932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.253954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.253959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.253983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.254004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.254026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.254047] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.254072] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.254093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.254115] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.254136] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.254157] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.254182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.254215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.254307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.254330] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.254353] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.254389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.254411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.254433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.254453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.254474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.254495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.254519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.254542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.254565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.254584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.254605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.254629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.254650] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.256640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.256656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.256670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.256685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.258193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.258211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.258258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.259758] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.259775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.261584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.264515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.264541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.264558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.264579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.264627] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.264653] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.281279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.281303] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.281337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.281444] [drm:drm_mode_addfb2] [FB:75]
>[ 1246.281509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.314642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.314667] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.314713] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.333560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.333582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.333598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.333618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.333634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.333652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.333667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.333682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.333698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.333715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.333732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.333748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.333764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.333778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.333792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.333819] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.333840] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.333861] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.333878] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.334000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.334010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.334064] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.334083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.334103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.334126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.334146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.334166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.334186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.334205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.334274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.334302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.334327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.334334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.334358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.334364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.334388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.334412] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.334437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.334460] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.334486] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.334510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.334534] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.334557] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.334580] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.334607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.334634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.334708] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.334733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.334756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.334795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.334819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.334843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.334866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.334889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.334914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.334939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.334965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.334990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.335013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.335035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.335069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.335092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.338184] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.338201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.338249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.338275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.339785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.339801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.339815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.341322] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.341341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.343241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.346184] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.346284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.346309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.346386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.346431] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.346455] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.362994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.363020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.363057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.363170] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.363287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.396350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.396374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.396420] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.415269] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.415291] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.415308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.415327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.415347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.415369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.415389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.415408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.415427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.415449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.415470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.415491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.415511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.415529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.415548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.415577] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.415600] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.415624] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.415649] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.415769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.415779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.415825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.415844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.415863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.415884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.415901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.415918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.415935] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.415952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.415968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.415987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.416007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.416011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.416030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.416034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.416054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.416074] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.416093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.416113] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.416133] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.416152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.416172] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.416192] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.416212] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.416280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.416311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.416384] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.416409] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.416433] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.416473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.416500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.416525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.416549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.416572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.416598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.416624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.416649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.416681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.416702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.416723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.416749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.416771] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.418782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.418800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.418814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.418829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.420339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.420355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.420371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.421866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.421882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.423689] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.426627] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.426699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.426716] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.426737] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.426776] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.426792] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.443440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.443464] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.443497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.443610] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.443682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.476798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.476821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.476857] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.495716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.495738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.495754] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.495774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.495790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.495808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.495823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.495838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.495855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.495872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.495889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.495905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.495921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.495936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.495950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.495977] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.495999] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.496020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.496037] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.496150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.496161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.496208] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.496229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.496283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.496315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.496340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.496375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.496398] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.496422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.496445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.496468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.496488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.496495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.496518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.496524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.496547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.496567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.496590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.496610] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.496635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.496656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.496678] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.496699] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.496720] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.496743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.496768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.496827] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.496850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.496872] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.496911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.496931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.496953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.496973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.496995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.497015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.497040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.497064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.497088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.497107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.497128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.497154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.497175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.499200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.499219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.499274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.499300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.500812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.500828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.500842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.502345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.502363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.504171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.507106] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.507181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.507197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.507220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.507436] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.507454] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.523923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.523948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.523982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.524090] [drm:drm_mode_addfb2] [FB:75]
>[ 1246.524154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.557279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.557305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.557344] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.574979] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.575001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.575017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.575037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.575054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.575072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.575088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.575103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.575118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.575137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.575153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.575169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.575185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.575204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.575223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.575303] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.575338] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.575368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.575395] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.575500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.575515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.575571] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.575589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.575608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.575628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.575644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.575660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.575680] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.575699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.575719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.575738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.575758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.575762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.575782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.575786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.575806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.575825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.575844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.575864] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.575883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.575902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.575922] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.575941] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.575960] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.575982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.576003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.576042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.576058] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.576080] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.576107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.576123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.576137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.576151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.576165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.576180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.576196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.576211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.576233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.576277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.576297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.576322] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.576343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.578339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.578355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.578370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.578384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.579887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.579903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.579917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.581410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.581428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.583236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.586175] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.586279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.586304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.586377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.586423] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.586447] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.602995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.603021] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.603058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.603169] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.603236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.636351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.636376] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.636421] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.655273] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.655295] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.655312] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.655331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.655348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.655366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.655381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.655396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.655412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.655430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.655447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.655463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.655479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.655493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.655507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.655534] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.655556] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.655576] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.655594] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.655713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.655723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.655770] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.655790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.655810] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.655831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.655849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.655867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.655885] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.655902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.655920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.655935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.655951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.655954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.655969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.655973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.655989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.656004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.656019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.656037] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.656058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.656078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.656098] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.656119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.656139] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.656160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.656182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.656232] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.656296] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.656320] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.656363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.656388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.656412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.656435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.656457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.656480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.656507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.656532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.656557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.656578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.656600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.656626] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.656649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.658660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.658677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.658692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.658707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.661321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.661337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.661351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.662844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.662860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.664667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.667617] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.667676] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.667693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.667715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.667763] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.667789] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.684420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.684446] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.684483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.684596] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.684662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.717774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.717798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.717843] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.736712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.736735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.736751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.736771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.736791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.736813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.736833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.736852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.736871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.736893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.736914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.736935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.736954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.736973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.736992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.737020] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.737043] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.737068] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.737086] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.737192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.737203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.737297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.737322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.737349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.737378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.737401] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.737427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.737452] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.737475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.737501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.737678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.737692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.737696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.737709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.737712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.737727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.737740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.737753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.737765] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.737781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.737794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.737807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.737820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.737833] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.737850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.737870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.737915] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.737930] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.737944] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.737973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.737991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.738010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.738027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.738046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.738064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.738084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.738103] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.738123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.738140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.738158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.738177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.738195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.740198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.740215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.740230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.740287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.741797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.741812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.741826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.743419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.743436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.745269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.748203] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.748311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.748337] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.748375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.748508] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.748534] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.765012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.765038] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.765073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.765196] [drm:drm_mode_addfb2] [FB:75]
>[ 1246.765328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.798378] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.798403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.798449] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.817287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.817309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.817325] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.817345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.817365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.817387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.817407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.817426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.817445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.817467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.817488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.817508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.817528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.817547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.817566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.817594] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.817617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.817642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.817660] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.817782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.817793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.817840] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.817860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.817880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.817901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.817918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.817939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.817965] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.817986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.818002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.818017] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.818031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.818034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.818048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.818052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.818066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.818080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.818093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.818107] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.818123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.818137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.818151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.818165] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.818179] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.818195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.818213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.818301] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.818324] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.818346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.818386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.818410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.818433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.818454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.818476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.818499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.818524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.818549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.818573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.818604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.818873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.818892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.818908] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.820901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.820918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.820932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.820947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.822458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.822474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.822488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.823982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.823998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.825805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.828748] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.828813] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.828829] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.828850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.828897] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.828921] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.845558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.845585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.845622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.845733] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.845794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.878913] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.878937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.878983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.897849] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.897873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.897893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.897915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.897935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.897957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.897976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.897996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.898015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.898037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.898058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.898078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.898098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.898117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.898136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.898164] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.898187] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.898212] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.898230] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.898373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.898389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.898461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.898486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.898512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.898539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.898562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.898586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.898610] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.898634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.898657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.898679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.898700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.898706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.898727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.898732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.898754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.898775] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.898797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.898817] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.898841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.898862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.898884] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.898903] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.898924] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.898948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.898974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.899037] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.899060] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.899082] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.899119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.899142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.899164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.899186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.899206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.899228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.899253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.899295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.899319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.899340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.899362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.899388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.899412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.901404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.901420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.901433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.901448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.902950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.902968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.902985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.904484] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.904500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.906305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.909239] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.909315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.909332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.909354] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.909402] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.909428] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1246.926059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.926086] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.926122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.926231] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.926349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.959414] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1246.959439] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1246.959484] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1246.978339] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1246.978361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1246.978377] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1246.978397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.978413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.978432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.978447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.978462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.978478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1246.978496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.978513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.978529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.978544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.978559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.978572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.978599] [drm:intel_power_well_disable [i915]] disabling display
>[ 1246.978621] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1246.978642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1246.978660] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1246.978780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1246.978790] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1246.978838] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1246.978858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1246.978879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1246.978903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1246.978923] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1246.978944] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1246.978965] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1246.978985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1246.979005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1246.979026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1246.979045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1246.979049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.979069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1246.979073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1246.979094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1246.979114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1246.979141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1246.979166] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1246.979185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1246.979202] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1246.979217] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1246.979232] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1246.979246] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1246.979308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1246.979336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1246.979410] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1246.979436] [drm:intel_power_well_enable [i915]] enabling display
>[ 1246.979461] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1246.979502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1246.979525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1246.979549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1246.979571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1246.979595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1246.979619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1246.979645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1246.979670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1246.979696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1246.979717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1246.979740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1246.979767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1246.979790] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1246.981800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1246.981818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1246.981833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.981847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1246.984440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1246.984460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1246.984479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1246.985978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1246.985995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1246.987802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1246.990737] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1246.990812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1246.990832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1246.990858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1246.990907] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1246.990934] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.007556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.007581] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.007615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.007723] [drm:drm_mode_addfb2] [FB:75]
>[ 1247.007787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.040910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.040934] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.040980] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.058860] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.058884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.058904] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.058925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.058945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.058967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.058986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.059006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.059025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.059047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.059068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.059088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.059108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.059127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.059146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.059175] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.059197] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.059222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.059240] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.059394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.059408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.059478] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.059505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.059534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.059563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.059588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.059615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.059641] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.059666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.059692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.059716] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.059740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.059746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.059769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.059775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.059798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.059822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.059852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.059874] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.059898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.059919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.059941] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.059963] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.059985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.060009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.060034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.060099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.060122] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.060144] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.060181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.060204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.060226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.060249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.060287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.060312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.060335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.060361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.060385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.060407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.060429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.060455] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.060478] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.062469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.062485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.062499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.062514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.064017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.064033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.064046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.065541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.065557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.067361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.069901] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.069967] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.069987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.070013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.070069] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.070093] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.086709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.086735] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.086772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.086882] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.086950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.120063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.120087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.120132] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.138227] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.138248] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.138307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.138339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.138367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.138395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.138420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.138444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.138470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.138500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.138527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.138553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.138579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.138602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.138625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.138669] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.138704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.138735] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.138764] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.138862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.138872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.138918] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.138936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.138955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.138974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.138990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.139007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.139024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.139040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.139055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.139070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.139084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.139088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.139101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.139105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.139119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.139137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.139157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.139176] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.139195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.139214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.139233] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.139252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.139314] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.139341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.139368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.139428] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.139451] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.139475] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.139518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.139543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.139568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.139592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.139621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.139643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.139668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.139692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.139716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.139737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.139759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.139785] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.139808] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.141813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.141831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.141849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.141867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.143388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.143405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.143419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.144913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.144929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.146736] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.149683] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.149745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.149761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.149783] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.149837] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.149860] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.166489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.166514] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.166548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.166657] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.166723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.199845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.199872] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.199918] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.218773] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.218796] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.218812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.218831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.218848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.218866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.218882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.218897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.218913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.218931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.218948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.218964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.218979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.218994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.219008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.219035] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.219057] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.219078] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.219095] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.219193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.219205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.219255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.219311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.219347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.219373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.219394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.219419] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.219442] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.219463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.219485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.219505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.219525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.219531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.219550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.219555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.219575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.219595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.219614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.219635] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.219659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.219678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.219698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.219717] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.219768] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.219791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.219816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.219872] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.219896] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.219918] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.219956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.219979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.219994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.220008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.220022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.220037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.220053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.220068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.220083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.220096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.220110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.220126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.220141] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.222116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.222131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.222145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.222160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.223668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.223683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.223697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.225215] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.225231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.227041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.229981] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.230051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.230068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.230090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.230130] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.230155] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.246824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.246852] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.246897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.247006] [drm:drm_mode_addfb2] [FB:75]
>[ 1247.247071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.280182] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.280207] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.280244] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.299116] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.299140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.299160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.299182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.299202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.299223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.299249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.299275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.299337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.299371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.299399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.299427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.299453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.299477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.299502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.299546] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.299581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.299613] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.299641] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.299757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.299774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.299842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.299861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.299880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.299900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.299915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.299933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.299950] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.299966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.299982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.300000] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.300019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.300023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.300042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.300046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.300065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.300084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.300103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.300122] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.300142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.300160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.300179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.300198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.300217] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.300237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.300257] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.300361] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.300388] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.300413] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.300455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.300479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.300505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.300528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.300551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.300574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.300601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.300627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.300652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.300673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.300696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.300721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.300746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.302745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.302761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.302775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.302790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.306436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.306455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.306472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.309049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.309069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.311985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.314684] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.314743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.314760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.314782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.314821] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.314837] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.331486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.331511] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.331549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.331658] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.331719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.364829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.364854] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.364900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.382978] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.383001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.383017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.383037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.383054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.383071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.383087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.383106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.383126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.383148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.383168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.383189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.383209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.383228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.383247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.383275] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.383347] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.383383] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.383412] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.383507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.383522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.383594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.383612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.383631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.383651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.383666] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.383684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.383701] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.383718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.383734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.383749] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.383764] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.383768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.383782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.383786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.383801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.383815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.383829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.383843] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.383859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.383873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.383895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.383908] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.383920] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.383935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.383952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.383988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.384001] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.384014] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.384038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.384053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.384066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.384080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.384093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.384110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.384130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.384149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.384169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.384186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.384204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.384223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.384241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.386245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.386262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.386277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.386325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.387835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.387850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.387864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.389363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.389379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.391190] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.394133] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.394198] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.394215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.394236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.394283] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.394334] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.410943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.410969] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.411006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.411119] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.411186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.444288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.444331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.444377] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.463215] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.463237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.463253] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.463272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.463331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.463360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.463384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.463409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.463433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.463461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.463488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.463514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.463539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.463560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.463583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.463625] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.463659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.463691] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.463718] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.463841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.463851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.463895] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.463913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.463932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.463953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.463972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.463991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.464010] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.464028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.464047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.464066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.464084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.464087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.464106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.464109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.464129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.464147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.464166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.464184] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.464203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.464221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.464240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.464258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.464277] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.464339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.464364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.464418] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.464442] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.464464] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.464535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.464559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.464582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.464605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.464628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.464650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.464676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.464700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.464716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.464730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.464743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.464761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.464779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.466767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.466784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.466799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.466814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.468346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.468361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.468375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.469880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.469902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.471716] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.474655] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.474725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.474741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.474763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.474801] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.474818] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.491461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.491485] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.491519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.491624] [drm:drm_mode_addfb2] [FB:75]
>[ 1247.491686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.524825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.524850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.524894] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.543763] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.543785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.543801] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.543821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.543838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.543855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.543871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.543886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.543901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.543919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.543936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.543952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.543968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.543982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.543995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.544022] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.544044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.544065] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.544082] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.544202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.544213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.544260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.544280] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.544348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.544378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.544402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.544428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.544461] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.544484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.544507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.544528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.544549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.544555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.544576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.544582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.544605] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.544628] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.544648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.544669] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.544693] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.544715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.544734] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.544748] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.544762] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.544778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.544796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.544843] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.544858] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.544872] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.544898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.544914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.544928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.544943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.544956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.544971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.544987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.545002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.545018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.545032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.545045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.545062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.545078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.547058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.547075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.547088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.547103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.548620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.548638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.548652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.550147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.550164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.551971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.554905] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.554981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.554997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.555020] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.555068] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.555093] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.571724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.571750] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.571784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.571892] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.571958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.605080] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.605105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.605150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.623998] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.624022] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.624042] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.624064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.624083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.624105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.624125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.624144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.624163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.624185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.624206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.624227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.624247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.624265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.624285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.624363] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.624399] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.624434] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.624463] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.624588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.624602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.624673] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.624699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.624727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.624757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.624782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.624809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.624835] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.624860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.624885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.624909] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.624932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.624938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.624961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.624967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.624991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.625014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.625038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.625061] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.625087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.625111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.625140] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.625160] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.625181] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.625204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.625229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.625293] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.625338] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.625361] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.625400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.625424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.625447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.625470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.625492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.625516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.625541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.625566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.625591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.625613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.625634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.625661] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.625683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.627669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.627685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.627704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.627725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.629239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.629255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.629268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.630763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.630779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.632583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.634669] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.634732] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.634748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.634770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.634818] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.634843] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.651477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.651502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.651539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.651649] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.651718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.684831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.684857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.684903] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.703764] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.703786] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.703803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.703824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.703844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.703866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.703886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.703905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.703925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.703946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.703967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.703987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.704008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.704027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.704046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.704074] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.704097] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.704122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.704140] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.704248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.704259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.704352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.704378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.704406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.704435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.704458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.704484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.704509] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.704532] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.704557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.704752] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.704772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.704776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.704795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.704799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.704819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.704838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.704858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.704877] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.704898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.704917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.704936] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.704956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.704976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.705002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.705022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.705066] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.705080] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.705093] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.705119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.705136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.705158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.705177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.705196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.705214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.705234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.705253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.705272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.705290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.705326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.705351] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.705373] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.707378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.707395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.707409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.707424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.708936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.708953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.708968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.710469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.710485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.712308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.714372] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.714419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.714436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.714458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.714506] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.714532] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.731162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.731187] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.731222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.731385] [drm:drm_mode_addfb2] [FB:75]
>[ 1247.731463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.764520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.764544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.764590] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.782657] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.782680] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.782696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.782715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.782732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.782749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.782765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.782779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.782795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.782813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.782830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.782846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.782866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.782885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.782905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.782933] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.782956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.782981] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.782999] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.783115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.783125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.783173] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.783192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.783212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.783234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.783255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.783275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.783296] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.783360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.783389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.783416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.783440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.783448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.783472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.783479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.783504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.783528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.783553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.783577] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.783605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.783629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.783654] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.783678] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.783702] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.783730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.783758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.783832] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.783857] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.783881] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.783921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.783946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.783970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.783992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.784016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.784038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.784066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.784092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.784118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.784141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.784165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.784190] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.784215] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.786234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.786251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.786266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.786281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.787822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.787838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.787852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.789425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.789443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.791339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.794272] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.794378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.794405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.794490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.794539] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.794565] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.811084] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.811108] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.811141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.811250] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.811355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.844448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.844473] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.844519] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.863371] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.863393] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.863409] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.863429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.863446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.863463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.863479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.863494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.863509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.863527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.863544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.863560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.863576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.863590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.863604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.863631] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.863653] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.863673] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.863691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.863813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.863824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.863871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.863890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.863910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.863931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.863948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.863966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.863984] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.864004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.864025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.864046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.864066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.864070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.864090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.864094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.864114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.864135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.864155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.864175] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.864195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.864215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.864236] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.864256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.864277] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.864298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.864388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.864460] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.864485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.864510] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.864551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.864577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.864602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.864626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.864650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.864675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.864702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.864729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.864755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.864778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.864802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.864829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.864854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.866860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.866877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.866894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.866913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.868434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.868452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.868469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.869964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.869981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.871807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.874760] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.874815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.874833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.874859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.874907] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.874932] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.891559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.891584] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.891618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.891729] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.891793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.924892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1247.924916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1247.924962] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1247.942971] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1247.942993] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1247.943012] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1247.943034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.943054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.943076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.943096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.943115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.943135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.943157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.943177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.943197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.943218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.943237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.943256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.943284] [drm:intel_power_well_disable [i915]] disabling display
>[ 1247.943307] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1247.943382] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.943410] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1247.943529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1247.943544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1247.943610] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1247.943627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1247.943646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1247.943671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1247.943695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1247.943713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1247.943730] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1247.943746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1247.943761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1247.943776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1247.943791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1247.943795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.943809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1247.943812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1247.943827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1247.943840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1247.943854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1247.943867] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1247.943883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1247.943897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1247.943911] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1247.943924] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1247.943938] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1247.943953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1247.943971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1247.944016] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1247.944032] [drm:intel_power_well_enable [i915]] enabling display
>[ 1247.944047] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1247.944076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1247.944095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1247.944115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1247.944134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1247.944153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1247.944171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1247.944192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1247.944213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1247.944233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.944252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1247.944271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1247.944291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1247.944310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1247.946341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.946357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.946372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.946387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.947896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1247.947912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1247.947928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.949430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.949447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1247.951254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.954210] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1247.954263] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1247.954280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1247.954302] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1247.954516] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.954534] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.971006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1247.971032] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1247.971069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1247.971180] [drm:drm_mode_addfb2] [FB:75]
>[ 1247.971248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.004363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.004393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.004436] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.023294] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.023316] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.023374] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.023397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.023418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.023440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.023460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.023480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.023500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.023522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.023543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.023564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.023586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.023605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.023625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.023653] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.023676] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.023702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.023720] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.023825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.023839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.023886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.023904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.023923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.023945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.023964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.023983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.024002] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.024022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.024041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.024060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.024079] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.024082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.024109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.024112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.024129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.024144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.024159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.024172] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.024188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.024201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.024215] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.024228] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.024240] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.024255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.024272] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.024309] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.024359] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.024380] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.024417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.024437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.024458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.024479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.024498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.024519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.024542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.024564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.024586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.024605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.024626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.024649] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.024670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.026664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.026680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.026695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.026710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.028215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.028230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.028244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.029737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.029753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.031556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.034507] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.034567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.034586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.034612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.034653] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.034672] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.051309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.051351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.051386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.051495] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.051563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.084665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.084689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.084726] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.103065] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.103089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.103109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.103131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.103151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.103172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.103192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.103211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.103231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.103253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.103274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.103294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.103315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.103373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.103400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.103446] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.103480] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.103514] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.103541] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.103666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.103681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.103750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.103774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.103808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.103834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.103855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.103879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.103900] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.103922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.103943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.103964] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.103983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.103988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.104008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.104013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.104034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.104053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.104074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.104092] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.104115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.104134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.104155] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.104174] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.104194] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.104215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.104240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.104304] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.104344] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.104367] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.104404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.104425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.104448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.104468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.104490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.104512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.104537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.104560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.104585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.104604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.104625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.104651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.104673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.106661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.106677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.106691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.106705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.108210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.108226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.108240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.109736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.109752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.111557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.114487] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.114513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.114530] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.114552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.114589] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.114606] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.131259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.131285] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.131319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.131543] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.131600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.164615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.164640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.164687] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.183542] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.183565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.183581] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.183600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.183617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.183635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.183651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.183665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.183681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.183699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.183716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.183732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.183749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.183763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.183782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.183810] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.183833] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.183858] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.183877] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.183993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.184004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.184051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.184072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.184093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.184117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.184137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.184158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.184178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.184198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.184219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.184239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.184259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.184263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.184288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.184294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.184320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.184386] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.184413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.184439] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.184467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.184492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.184517] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.184541] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.184566] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.184593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.184622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.184697] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.184722] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.184747] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.184787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.184812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.184837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.184860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.184883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.184906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.184932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.184957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.184983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.185005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.185028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.185054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.185079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.187095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.187113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.187131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.187149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.188658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.188674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.188689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.190181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.190197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.192003] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.194938] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.195012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.195028] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.195050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.195099] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.195125] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.211755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.211781] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.211815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.211923] [drm:drm_mode_addfb2] [FB:75]
>[ 1248.211981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.245111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.245137] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.245183] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.264051] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.264073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.264090] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.264109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.264126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.264144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.264159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.264174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.264190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.264209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.264225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.264241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.264258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.264272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.264287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.264314] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.264382] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.264416] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.264443] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.264564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.264579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.264639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.264656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.264675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.264695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.264711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.264728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.264745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.264761] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.264776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.264791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.264805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.264810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.264824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.264827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.264843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.264857] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.264871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.264884] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.264904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.264923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.264942] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.264962] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.264982] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.265002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.265024] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.265070] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.265087] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.265102] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.265131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.265151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.265172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.265191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.265212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.265231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.265253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.265274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.265296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.265314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.265336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.265385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.265416] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.267406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.267423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.267437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.267452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.268966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.268982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.268995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.270492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.270508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.272334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.275276] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.275385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.275464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.275487] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.275536] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.275567] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.292096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.292121] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.292156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.292263] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.292327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.325452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.325476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.325521] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.344375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.344396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.344412] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.344432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.344449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.344467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.344483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.344498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.344514] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.344532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.344549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.344565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.344581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.344595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.344609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.344636] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.344659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.344683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.344702] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.344823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.344833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.344880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.344899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.344919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.344943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.344963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.344984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.345005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.345025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.345046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.345066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.345086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.345090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.345110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.345114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.345135] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.345155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.345176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.345196] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.345216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.345237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.345257] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.345277] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.345298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.345319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.345387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.345465] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.345491] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.345516] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.345558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.345585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.345611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.345635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.345660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.345686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.345714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.345740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.345767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.345790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.345813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.345840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.345865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.347877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.347894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.347908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.347923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.349445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.349463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.349479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.350974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.350991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.352799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.355757] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.355809] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.355826] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.355848] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.355896] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.355922] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.372553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.372577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.372611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.372720] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.372784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.405908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.405933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.405978] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.424822] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.424845] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.424861] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.424880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.424897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.424915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.424930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.424945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.424960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.424978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.424994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.425010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.425027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.425041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.425055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.425082] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.425104] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.425125] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.425143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.425263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.425273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.425320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.425340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.425390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.425421] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.425447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.425476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.425503] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.425529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.425555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.425580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.425604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.425612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.425635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.425642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.425666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.425690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.425714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.425738] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.425765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.425789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.425813] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.425844] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.426100] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.426126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.426152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.426221] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.426245] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.426268] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.426307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.426331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.426374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.426399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.426421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.426444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.426469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.426495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.426662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.426685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.426707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.426733] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.426757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.428756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.428773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.428788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.428803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.430307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.430322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.430336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.431869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.431886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.433698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.436092] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.436150] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.436167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.436189] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.436237] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.436263] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.452894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.452920] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.452954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.453063] [drm:drm_mode_addfb2] [FB:75]
>[ 1248.453130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.486247] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.486273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.486319] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.504412] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.504434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.504450] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.504470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.504487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.504505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.504521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.504536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.504552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.504570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.504586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.504606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.504627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.504646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.504665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.504693] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.504716] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.504741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.504759] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.504883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.504894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.504941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.504961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.504983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.505006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.505026] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.505048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.505068] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.505088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.505109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.505129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.505149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.505153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.505173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.505177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.505197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.505218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.505238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.505258] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.505279] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.505298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.505319] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.505339] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.505408] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.505439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.505469] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.505543] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.505570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.505594] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.505635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.505660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.505685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.505710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.505734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.505758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.505786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.505811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.505837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.505860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.505883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.505910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.505935] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.507953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.507972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.507989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.508008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.509518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.509534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.509548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.511041] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.511056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.512863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.515799] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.515874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.515890] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.515912] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.515960] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.515986] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.532617] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.532643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.532678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.532785] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.532852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.565972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.565997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.566042] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.584899] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.584922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.584938] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.584958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.584975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.584992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.585007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.585022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.585038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.585056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.585073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.585089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.585105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.585119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.585133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.585160] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.585182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.585203] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.585220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.585317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.585328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.585434] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.585462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.585491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.585521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.585545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.585572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.585598] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.585624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.585649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.585673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.585696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.585702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.585724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.585730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.585754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.585777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.585800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.585823] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.585849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.585872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.585895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.585918] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.585940] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.585966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.585994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.586070] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.586096] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.586120] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.586160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.586185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.586210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.586234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.586257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.586283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.586317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.586341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.586379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.586402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.586423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.586449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.586473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.588468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.588484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.588498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.588512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.590028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.590045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.590059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.592636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.592656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.596607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.599550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.599614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.599630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.599650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.599695] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.599719] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.616374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.616399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.616434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.616541] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.616599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.649716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.649741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.649787] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.668644] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.668666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.668682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.668702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.668719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.668737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.668753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.668768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.668784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.668802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.668818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.668834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.668850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.668864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.668878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.668905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.668927] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.668948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.668965] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.669087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.669096] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.669142] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.669160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.669179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.669198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.669215] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.669235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.669254] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.669273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.669293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.669312] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.669331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.669334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.669353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.669393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.669421] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.669448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.669474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.669497] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.669524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.669548] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.669572] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.669595] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.669618] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.669644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.669671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.669742] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.669766] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.669789] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.669827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.669851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.669874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.669897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.669920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.669943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.669969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.669993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.670018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.670040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.670063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.670095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.670118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.672124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.672141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.672161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.672183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.673691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.673706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.673720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.675212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.675231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.677037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.679985] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.680047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.680063] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.680085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.680132] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.680158] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.696789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.696816] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.696853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.696965] [drm:drm_mode_addfb2] [FB:75]
>[ 1248.697033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.730144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.730167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.730212] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.749051] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.749073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.749090] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.749109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.749126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.749144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.749158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.749173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.749189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.749207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.749223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.749239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.749259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.749278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.749297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.749326] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.749348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.749417] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.749445] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.749565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.749579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.749650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.749676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.749696] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.749719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.749738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.749758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.749778] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.749798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.749818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.749838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.749857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.749862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.749888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.749892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.749909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.749925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.749939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.749953] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.749968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.749982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.749996] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.750009] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.750021] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.750037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.750053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.750096] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.750110] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.750123] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.750148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.750162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.750176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.750190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.750203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.750217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.750232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.750246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.750260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.750273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.750286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.750302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.750319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.752315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.752332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.752346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.752393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.753910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.753925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.753939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.755500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.755518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.757359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.760300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.760406] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.760433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.760516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.760565] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.760592] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.777120] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.777147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.777184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.777295] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.777363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.810475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.810500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.810545] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.829400] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.829423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.829442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.829464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.829484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.829506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.829525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.829545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.829564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.829586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.829607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.829628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.829647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.829666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.829686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.829714] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.829736] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.829761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.829779] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.829900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.829910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.829957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.829977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.829997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.830020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.830040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.830061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.830081] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.830102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.830122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.830143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.830163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.830167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.830186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.830190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.830211] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.830231] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.830252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.830272] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.830292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.830312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.830332] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.830353] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.830426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.830459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.830489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.830563] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.830590] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.830615] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.830656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.830682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.830709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.830734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.830758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.830783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.830810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.830836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.830862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.830886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.830909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.830936] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.830961] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.832972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.832990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.833005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.833020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.834533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.834553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.834567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.836061] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.836077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.837883] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.840832] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.840900] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.840915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.840935] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.840979] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.841003] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.857636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.857662] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.857696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.857804] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.857870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.891002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.891026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.891071] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.909918] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.909940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.909956] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.909976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.909993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.910011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.910026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.910041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.910057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.910075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.910092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.910108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.910124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.910139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.910153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.910180] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.910202] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.910226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.910244] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.910352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.910397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.910644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.910670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.910696] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.910724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.910746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.910770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.910795] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.910818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.910841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.910863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.910884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.910890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.910910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.910916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.910938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.910960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.910981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.911000] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.911024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.911045] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.911067] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.911088] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.911109] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.911133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.911159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.911228] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.911252] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.911274] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.911312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.911336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.911358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.911401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.911425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.911448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.911474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.911499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.911523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.911545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.911568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.911594] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.911617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.913852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.913869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.913884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.913899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.915433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.915448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.915461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.916958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.916975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.918785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1248.921071] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1248.921137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1248.921154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1248.921176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1248.921216] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1248.921233] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1248.937890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.937915] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.937950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.938063] [drm:drm_mode_addfb2] [FB:75]
>[ 1248.938143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.971268] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1248.971293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1248.971330] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1248.990175] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1248.990197] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1248.990213] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1248.990232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.990249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.990266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.990282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.990297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.990313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1248.990331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.990347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.990363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.990426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.990448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.990471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.990514] [drm:intel_power_well_disable [i915]] disabling display
>[ 1248.990551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1248.990585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1248.990614] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1248.990715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1248.990725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1248.990768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1248.990785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1248.990804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1248.990824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1248.990840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1248.990857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1248.990874] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1248.990889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1248.990905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1248.990919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1248.990933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1248.990937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.990951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1248.990955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1248.990970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1248.990984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1248.990998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1248.991012] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1248.991029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1248.991043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1248.991057] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1248.991071] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1248.991085] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1248.991102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1248.991126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1248.991171] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1248.991186] [drm:intel_power_well_enable [i915]] enabling display
>[ 1248.991199] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1248.991223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1248.991238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1248.991251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1248.991265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1248.991278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1248.991292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1248.991307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1248.991327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1248.991349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1248.991364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1248.991407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1248.991432] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1248.991453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1248.993459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1248.993477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1248.993491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.993506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1248.995017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1248.995033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1248.995047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1248.996544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1248.996560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1248.998364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.001303] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.001332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.001350] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.001375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.001538] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.001556] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.018079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.018104] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.018139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.018247] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.018305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.051434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.051458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.051497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.070339] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.070361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.070377] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.070441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.070468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.070496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.070521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.070539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.070555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.070574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.070592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.070608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.070625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.070639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.070653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.070681] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.070704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.070730] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.070756] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.070840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.070852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.070894] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.070911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.070929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.070948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.070962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.070978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.070994] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.071009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.071027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.071045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.071063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.071068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.071084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.071087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.071107] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.071125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.071144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.071162] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.071181] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.071199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.071215] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.071234] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.071252] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.071271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.071291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.071328] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.071343] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.071357] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.071419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.071443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.071466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.071487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.071509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.071531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.071555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.071579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.071602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.071622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.071642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.071667] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.071689] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.073689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.073705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.073719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.073737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.075240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.075256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.075270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.076765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.076783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.078590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.081542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.081600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.081617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.081640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.081678] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.081695] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.098342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.098368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.098454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.098583] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.098646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.131698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.131724] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.131762] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.150624] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.150646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.150662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.150682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.150699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.150717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.150732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.150747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.150763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.150781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.150797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.150817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.150838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.150858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.150877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.150905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.150928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.150953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.150971] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.151093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.151103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.151150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.151170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.151190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.151211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.151228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.151246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.151264] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.151281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.151297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.151313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.151329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.151332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.151347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.151351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.151367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.151382] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.151442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.151465] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.151492] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.151514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.151538] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.151559] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.151582] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.151610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.151638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.151713] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.151738] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.151763] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.151802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.151825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.151848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.151870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.151892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.151914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.151940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.151966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.151991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.152012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.152034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.152061] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.152084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.154090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.154107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.154122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.154137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.155642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.155657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.155671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.157162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.157177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.158982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.161676] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.161739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.161764] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.161784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.161821] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.161839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.178492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.178518] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.178555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.178671] [drm:drm_mode_addfb2] [FB:75]
>[ 1249.178740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.211870] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.211895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.211932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.230215] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.230237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.230253] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.230273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.230290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.230308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.230323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.230338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.230354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.230372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.230431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.230457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.230484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.230506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.230529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.230572] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.230610] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.230643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.230672] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.230766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.230776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.230820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.230836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.230855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.230875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.230891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.230908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.230925] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.230940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.230956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.230970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.230985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.230988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.231003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.231006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.231021] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.231036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.231049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.231063] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.231080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.231094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.231108] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.231122] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.231137] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.231153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.231172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.231218] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.231232] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.231245] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.231269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.231287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.231306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.231323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.231341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.231359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.231380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.231428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.231453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.231473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.231494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.231519] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.231541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.233537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.233553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.233567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.233582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.235089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.235104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.235118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.236618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.236635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.238447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.241397] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.241455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.241472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.241494] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.241540] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.241565] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.258195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.258220] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.258256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.258379] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.258482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.291555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.291580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.291625] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.310468] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.310490] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.310507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.310526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.310543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.310564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.310584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.310604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.310623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.310645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.310666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.310686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.310707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.310726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.310745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.310773] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.310796] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.310820] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.310839] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.310961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.310971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.311018] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.311038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.311058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.311079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.311096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.311114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.311132] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.311149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.311165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.311181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.311197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.311200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.311215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.311219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.311239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.311260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.311280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.311301] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.311321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.311341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.311361] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.311382] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.311449] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.311480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.311510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.311613] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.311639] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.311664] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.311705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.311731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.311756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.311780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.311804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.311830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.311856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.311882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.311908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.311932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.311955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.311982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.312007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.314011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.314028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.314042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.314057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.315563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.315579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.315592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.317084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.317101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.318908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.321850] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.321918] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.321938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.321964] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.322013] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.322040] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.338662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.338689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.338725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.338838] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.338907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.372017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.372041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.372086] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.390955] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.390977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.390993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.391013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.391030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.391048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.391064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.391079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.391095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.391113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.391129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.391145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.391161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.391175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.391193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.391222] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.391245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.391269] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.391288] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.391421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.391438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.391698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.391726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.391762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.391790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.391813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.391838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.391862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.391885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.391908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.391929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.391951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.391957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.391977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.391983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.392005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.392026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.392048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.392070] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.392093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.392115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.392136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.392156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.392176] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.392200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.392225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.392292] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.392316] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.392338] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.392374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.392397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.392445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.392469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.392492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.392516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.392543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.392567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.392592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.392614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.392636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.392662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.392686] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.394928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.394945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.394963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.394981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.396497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.396513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.396528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.398024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.398042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.399853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.402325] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.402356] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.402373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.402395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.402487] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.402511] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.419095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.419120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.419156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.419267] [drm:drm_mode_addfb2] [FB:75]
>[ 1249.419325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.452467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.452490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.452526] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.471370] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.471392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.471457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.471487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.471514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.471543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.471567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.471592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.471613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.471636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.471657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.471678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.471700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.471719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.471738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.471767] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.471791] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.471816] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.471834] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.471919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.471929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.471976] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.471996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.472016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.472039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.472058] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.472078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.472098] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.472117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.472137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.472156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.472175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.472179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.472198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.472202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.472223] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.472242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.472262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.472281] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.472301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.472321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.472340] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.472359] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.472379] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.472405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.472458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.472534] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.472555] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.472575] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.472614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.472637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.472659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.472682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.472703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.472726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.472751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.472775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.472800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.472821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.472843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.472868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.472891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.474880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.474898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.474916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.474934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.476469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.476485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.476500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.478000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.478016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.479827] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.482774] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.482836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.482853] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.482875] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.482914] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.482931] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.499581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.499607] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.499644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.499754] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.499815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.532936] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.532960] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.532997] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.551843] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.551865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.551882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.551903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.551923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.551945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.551964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.551984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.552003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.552025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.552046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.552067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.552087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.552106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.552125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.552153] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.552176] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.552201] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.552219] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.552346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.552355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.552401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.552888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.552915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.552944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.552967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.552990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.553015] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.553039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.553063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.553086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.553108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.553114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.553135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.553141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.553163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.553185] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.553207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.553227] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.553251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.553280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.553299] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.553320] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.553339] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.553362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.553387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.553476] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.553500] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.553523] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.553561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.553584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.553607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.553630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.553652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.553674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.553699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.553723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.553747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.553768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.553789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.553814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.553836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.555837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.555855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.555869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.555885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.557391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.557406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.557445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.558954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.558972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.560796] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.563731] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.563806] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.563825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.563851] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.563892] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.563911] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.580551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.580577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.580611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.580721] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.580786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.613906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.613932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.613970] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.632816] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.632839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.632855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.632874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.632891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.632909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.632925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.632940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.632956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.632974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.632991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.633007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.633023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.633037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.633051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.633078] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.633100] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.633121] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.633138] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.633262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.633272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.633320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.633341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.633363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.633387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.633407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.633471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.633501] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.633529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.633555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.633580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.633604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.633612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.633635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.633641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.633666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.633690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.633715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.633738] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.633766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.633790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.633814] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.633837] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.633862] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.633889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.633918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.634290] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.634316] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.634341] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.634383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.634409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.634455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.634481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.634504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.634529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.634558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.634691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.634718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.634741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.634765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.634792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.634817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.636825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.636842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.636856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.636871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.638379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.638395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.638408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.639944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.639960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.641773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.644715] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.644782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.644799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.644821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.644861] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.644878] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.661527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.661553] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.661587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.661711] [drm:drm_mode_addfb2] [FB:75]
>[ 1249.661785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.694878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.694901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.694936] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.713174] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.713196] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.713213] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.713232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.713249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.713271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.713290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.713310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.713330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.713352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.713373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.713394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.713413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.713472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.713499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.713545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.713588] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.713620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.713646] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.713769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.713785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.713854] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.713880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.713906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.713934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.713956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.713981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.714005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.714029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.714052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.714074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.714094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.714099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.714121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.714126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.714148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.714171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.714193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.714214] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.714238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.714260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.714282] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.714304] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.714323] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.714347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.714373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.714458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.714483] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.714509] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.714548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.714572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.714604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.714627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.714651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.714674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.714700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.714725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.714749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.714771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.714792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.714817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.714841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.716846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.716865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.716882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.716901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.718411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.718440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.718455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.719952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.719968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.721780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.724737] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.724790] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.724809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.724835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.724876] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.724896] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.741533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.741558] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.741593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.741714] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.741790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.774861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.774884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.774919] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.793179] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.793201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.793218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.793238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.793254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.793272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.793288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.793303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.793319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.793337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.793353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.793369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.793385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.793399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.793413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.793491] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.793528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.793562] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.793591] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.793706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.793715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.793759] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.793776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.793795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.793814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.793832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.793852] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.793872] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.793891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.793911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.793931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.793951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.793955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.793974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.793978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.793998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.794017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.794037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.794056] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.794075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.794095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.794114] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.794133] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.794153] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.794173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.794194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.794240] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.794256] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.794271] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.794307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.794324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.794339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.794353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.794367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.794383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.794399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.794415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.794454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.794475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.794495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.794519] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.794541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.796532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.796548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.796562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.796577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.798080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.798095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.798109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.799603] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.799619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.801426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.804372] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.804471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.804506] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.804577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.804622] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.804646] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.821186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.821212] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.821249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.821372] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.821499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.854542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.854567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.854612] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.873472] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.873495] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.873511] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.873530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.873547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.873564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.873579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.873594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.873609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.873627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.873643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.873663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.873684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.873703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.873722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.873750] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.873773] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.873798] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.873816] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.873909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.873919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.873971] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.873990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.874010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.874031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.874050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.874069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.874088] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.874106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.874125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.874143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.874161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.874165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.874183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.874187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.874205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.874224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.874242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.874261] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.874280] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.874298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.874316] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.874335] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.874353] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.874373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.874393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.874476] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.874502] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.874526] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.874565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.874589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.874614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.874637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.874661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.874685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.874711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.874736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.874760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.874782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.874805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.874831] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.874855] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.876854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.876870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.876885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.876899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.878417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.878449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.878464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.879974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.879990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.881811] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.884769] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.884821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.884837] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.884860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.884908] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.884934] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.901565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.901590] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.901625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.901745] [drm:drm_mode_addfb2] [FB:75]
>[ 1249.901811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.934920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1249.934945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1249.934990] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1249.953832] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1249.953856] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1249.953876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1249.953898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.953918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.953940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.953959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.953979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.953998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.954020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.954041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.954061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.954081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.954100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.954119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.954147] [drm:intel_power_well_disable [i915]] disabling display
>[ 1249.954170] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1249.954195] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.954213] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1249.954329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1249.954339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1249.954386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1249.954405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1249.954426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1249.954500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1249.954527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1249.954557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1249.954584] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1249.954611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1249.954636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1249.954661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1249.954685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1249.954693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.954716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1249.954722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1249.954746] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1249.954777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1249.954801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1249.954823] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1249.954850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1249.954872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1249.954896] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1249.954919] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1249.954943] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1249.954969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1249.954996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1249.955069] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1249.955094] [drm:intel_power_well_enable [i915]] enabling display
>[ 1249.955117] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1249.955156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1249.955180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1249.955203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1249.955226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1249.955249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1249.955271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1249.955296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1249.955321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1249.955346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.955369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1249.955391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1249.955418] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1249.955463] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1249.957466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1249.957484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1249.957498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.957513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1249.959026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1249.959042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1249.959056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1249.960573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1249.960591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1249.962479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1249.965402] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1249.965436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1249.965483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1249.965518] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1249.965575] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1249.965598] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1249.982182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1249.982207] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1249.982241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1249.982350] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.982416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.015537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.015563] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.015610] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.033470] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.033492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.033509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.033528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.033545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.033563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.033579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.033594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.033610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.033628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.033644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.033660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.033676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.033690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.033704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.033731] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.033752] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.033773] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.033791] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.033909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.033919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.033967] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.033987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.034008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.034032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.034052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.034073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.034093] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.034114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.034134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.034154] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.034174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.034178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.034198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.034201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.034222] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.034242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.034263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.034283] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.034303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.034323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.034343] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.034363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.034384] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.034405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.034427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.034541] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.034567] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.034592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.034635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.034662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.034689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.034715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.034740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.034766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.034794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.034821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.034847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.034871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.034896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.034924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.034950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.036980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.036997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.037011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.037027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.038555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.038571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.038585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.040078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.040094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.041900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.044846] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.044909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.044927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.044949] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.044997] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.045023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.061654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.061679] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.061714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.061823] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.061889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.095008] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.095034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.095081] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.112950] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.112972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.112989] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.113009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.113026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.113043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.113059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.113073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.113089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.113107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.113124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.113140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.113156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.113170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.113184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.113211] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.113233] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.113253] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.113271] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.113374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.113386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.113440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.113492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.113524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.113554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.113580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.113609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.113638] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.113664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.113690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.113715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.113739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.113746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.113769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.113775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.113799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.113824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.113848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.114101] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.114128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.114153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.114178] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.114202] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.114232] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.114256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.114281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.114348] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.114372] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.114394] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.114432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.114472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.114495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.114518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.114540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.114563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.114589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.114613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.114637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.114659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.114846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.114871] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.114901] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.116913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.116930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.116945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.116960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.118493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.118508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.118522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.120025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.120041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.121868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.124818] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.124877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.124894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.124915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.124963] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.124989] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.141622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.141648] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.141686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.141795] [drm:drm_mode_addfb2] [FB:75]
>[ 1250.141863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.174977] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.175004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.175051] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.193928] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.193952] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.193972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.193994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.194014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.194036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.194055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.194074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.194094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.194115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.194136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.194157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.194177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.194196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.194215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.194244] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.194266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.194291] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.194309] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.194417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.194429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.194536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.194564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.194593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.194623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.194648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.194675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.194701] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.194726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.194751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.194775] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.194798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.194804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.194827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.194833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.194856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.194887] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.194909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.194930] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.194954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.194975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.194996] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.195017] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.195038] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.195062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.195087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.195155] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.195179] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.195201] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.195238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.195261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.195284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.195306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.195327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.195351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.195375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.195399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.195423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.195444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.195482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.195508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.195532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.197530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.197547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.197564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.197583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.199097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.199114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.199129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.200628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.200644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.202484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.205411] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.205442] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.205499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.205523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.205571] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.205597] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.222187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.222213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.222250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.222360] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.222430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.255542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.255566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.255612] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.274437] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.274477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.274493] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.274513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.274529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.274547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.274562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.274577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.274593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.274611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.274628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.274644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.274664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.274683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.274702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.274731] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.274754] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.274778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.274797] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.274922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.274932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.274979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.275001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.275022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.275046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.275066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.275087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.275108] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.275128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.275149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.275169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.275189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.275193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.275213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.275217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.275238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.275258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.275279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.275299] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.275319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.275339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.275359] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.275380] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.275400] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.275422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.275444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.275550] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.275577] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.275599] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.275642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.275669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.275693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.275716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.275740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.275765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.275792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.275818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.275844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.275865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.275888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.275915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.275938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.277951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.277968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.277983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.277998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.279538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.279556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.279574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.281073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.281091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.282901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.285224] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.285252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.285268] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.285290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.285329] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.285346] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.301997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.302022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.302056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.302166] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.302224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.335351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.335375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.335420] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.354219] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.354241] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.354257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.354277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.354293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.354311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.354327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.354342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.354358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.354376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.354393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.354409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.354426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.354440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.354454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.354527] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.354562] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.354595] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.354623] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.354735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.354750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.354819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.354842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.354868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.354897] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.354920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.354946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.354969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.354994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.355016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.355039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.355060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.355066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.355088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.355093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.355116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.355138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.355160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.355180] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.355205] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.355226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.355249] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.355269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.355297] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.355318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.355343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.355406] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.355429] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.355450] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.355509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.355531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.355554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.355574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.355596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.355617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.355642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.355666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.355691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.355711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.355732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.355758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.355780] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.357769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.357784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.357801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.357819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.359325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.359341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.359359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.360858] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.360875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.362679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.365618] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.365688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.365707] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.365733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.365783] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.365809] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.382433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.382460] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.382546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.382678] [drm:drm_mode_addfb2] [FB:75]
>[ 1250.382742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.415789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.415813] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.415859] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.434716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.434738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.434754] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.434774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.434791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.434809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.434824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.434839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.434855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.434873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.434890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.434906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.434922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.434936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.434958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.434991] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.435013] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.435034] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.435051] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.435171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.435181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.435228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.435250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.435271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.435295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.435315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.435336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.435356] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.435377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.435397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.435417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.435437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.435441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.435461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.435504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.435531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.435556] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.435580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.435602] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.435627] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.435649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.435671] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.435692] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.435714] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.435739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.435765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.435841] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.435864] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.435888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.435929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.435954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.435978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.436002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.436034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.436056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.436081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.436106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.436129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.436148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.436161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.436178] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.436193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.438181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.438198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.438213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.438228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.439737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.439753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.439767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.441262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.441279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.443084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.446020] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.446093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.446110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.446133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.446188] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.446212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.462836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.462863] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.462900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.463011] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.463079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.496192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.496216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.496261] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.515113] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.515135] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.515151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.515171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.515187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.515205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.515221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.515236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.515255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.515277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.515298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.515318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.515339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.515358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.515377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.515405] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.515427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.515452] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.515519] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.515644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.515660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.515735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.515759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.515785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.515813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.515835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.515860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.515884] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.515907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.515930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.515952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.515973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.515979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.515999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.516004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.516026] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.516048] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.516069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.516088] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.516112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.516133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.516154] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.516176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.516198] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.516221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.516246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.516311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.516334] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.516356] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.516393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.516415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.516438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.516460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.516500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.516523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.516546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.516571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.516595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.516617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.516639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.516665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.516688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.518677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.518695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.518712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.518730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.520235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.520252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.520268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.521764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.521780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.523585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.526501] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.526542] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.526559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.526581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.526628] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.526654] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.543289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.543314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.543348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.543488] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.543645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.576644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.576670] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.576717] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.595574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.595596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.595613] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.595632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.595649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.595667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.595682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.595697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.595713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.595731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.595748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.595768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.595789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.595808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.595827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.595855] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.595878] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.595903] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.595922] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.596051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.596063] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.596110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.596128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.596146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.596166] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.596182] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.596199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.596216] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.596232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.596247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.596262] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.596276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.596280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.596298] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.596302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.596322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.596341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.596360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.596379] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.596398] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.596417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.596436] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.596456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.596519] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.596545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.596574] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.596645] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.596671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.596695] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.596737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.596756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.596772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.596787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.596802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.596819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.596837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.596853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.596869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.596884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.596898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.596917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.596933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.598942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.598959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.598974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.598989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.600527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.600542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.600556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.602057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.602075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.603888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.606831] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.606898] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.606917] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.606943] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.606984] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.607003] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.623668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.623694] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.623729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.623833] [drm:drm_mode_addfb2] [FB:75]
>[ 1250.623906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.657029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.657053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.657090] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.675022] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.675047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.675066] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.675088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.675108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.675130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.675149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.675169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.675188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.675210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.675230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.675251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.675270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.675289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.675308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.675337] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.675359] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.675384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.675403] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.675767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.675783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.675856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.675883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.675912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.675942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.675967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.675994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.676020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.676045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.676070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.676093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.676116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.676122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.676145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.676151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.676175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.676197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.676220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.676243] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.676269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.676293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.676316] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.676339] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.676360] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.676385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.676412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.676508] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.676533] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.676558] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.676600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.676626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.676652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.676676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.676701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.676726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.676754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.676781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.676807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.676831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.677068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.677096] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.677128] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.679115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.679131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.679146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.679161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.680666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.680682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.680695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.682187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.682202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.684009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.686943] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.687018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.687038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.687064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.687114] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.687140] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.703762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.703788] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.703822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.703929] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.703988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.737118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.737142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.737188] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.756039] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.756061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.756078] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.756098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.756117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.756139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.756159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.756178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.756197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.756219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.756240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.756261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.756281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.756300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.756319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.756347] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.756370] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.756395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.756413] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.756542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.756560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.756624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.756643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.756662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.756684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.756703] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.756724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.756744] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.756770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.756788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.756802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.756816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.756820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.756837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.756841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.756859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.756878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.756896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.756913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.756931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.756948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.756966] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.756984] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.757001] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.757020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.757040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.757086] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.757101] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.757115] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.757158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.757178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.757195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.757213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.757231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.757250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.757270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.757290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.757309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.757327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.757342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.757361] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.757379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.759357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.759374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.759389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.759404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.760921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.760939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.760957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.762455] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.762472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.764297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.767226] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.767254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.767270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.767292] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.767340] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.767365] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.784001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.784027] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.784062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.784178] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.784237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.817356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.817380] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.817425] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.836249] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.836271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.836287] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.836307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.836323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.836341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.836356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.836371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.836387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.836405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.836421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.836437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.836453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.836468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.836481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.836565] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.836599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.836631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.836659] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.836785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.836803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.836880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.836907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.836935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.836965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.836990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.837017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.837044] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1250.837069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1250.837095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.837119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.837142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.837149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.837172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.837178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.837202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.837225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.837246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.837268] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1250.837294] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.837317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.837337] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1250.837360] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1250.837382] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1250.837408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.837436] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1250.837545] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.837578] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.837601] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.837639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.837663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.837685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.837707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.837729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.837751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.837775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.837799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.837822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.837843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.837864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.837888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1250.837911] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.839914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.839931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.839946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.839961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.841467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.841482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.841526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.843022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.843037] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.844843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.847778] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1250.847850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.847865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1250.847888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.847933] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1250.847956] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1250.864588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.864612] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.864645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.864751] [drm:drm_mode_addfb2] [FB:75]
>[ 1250.864814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.897952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1250.897978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1250.898025] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1250.916867] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1250.916891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1250.916910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1250.916932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.916952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.916974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.916994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.917013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.917032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.917054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.917075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.917095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.917115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.917134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.917153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.917181] [drm:intel_power_well_disable [i915]] disabling display
>[ 1250.917204] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1250.917228] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1250.917246] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1250.917465] [drm:drm_mode_addfb2] [FB:75]
>[ 1250.917536] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.940717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1250.940803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1250.940861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1250.940916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1250.940931] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1250.940992] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1250.941009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1250.941026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1250.941047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1250.941064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1250.941083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1250.941100] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1250.941118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1250.941136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1250.941153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1250.941170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1250.941174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.941191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1250.941194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1250.941212] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1250.941229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1250.941247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1250.941264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1250.941281] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1250.941299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1250.941316] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1250.941334] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1250.941351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1250.941369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1250.941389] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1250.943915] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1250.943931] [drm:intel_power_well_enable [i915]] enabling display
>[ 1250.943946] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1250.943976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1250.943993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1250.944009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1250.944024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1250.944039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1250.944055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1250.944072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1250.944088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1250.944104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.944118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1250.944132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1250.944152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1250.944171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1250.946166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1250.946182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1250.946196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.946211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1250.947725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1250.947743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1250.947757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1250.949252] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1250.949269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1250.951075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1250.953997] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1250.954039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1250.954054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1250.954075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1250.970778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1250.970804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1250.970839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1250.987470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1250.987481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.004224] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.004286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.020843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.020868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.020915] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.039758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.039777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.039798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.039815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.039832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.039848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.039863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.039880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.039898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.039914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.039930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.039946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.039961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.039974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.040002] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.040024] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.040045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.040060] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.040175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.040185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.040232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.040252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.040272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.040296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.040316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.040337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.040358] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.040378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.040398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.040419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.040438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.040442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.040462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.040466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.040487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.040555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.040584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.040611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.040638] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.040664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.040689] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.040715] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.040739] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.040768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.040796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.040870] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.040894] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.040919] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.040961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.040986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.041018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.041040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.041062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.041086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.041111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.041135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.041160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.041181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.041203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.041229] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.041252] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.044331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.044350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.044366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.044383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.045890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.045905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.045919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.047411] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.047427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.049231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.052173] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.052248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.052264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.052285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.068976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.069000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.069034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.069141] [drm:drm_mode_addfb2] [FB:75]
>[ 1251.069197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.085683] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.085708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.085753] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.104618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.104637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.104658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.104675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.104695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.104715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.104735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.104754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.104776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.104797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.104818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.104837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.104856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.104875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.104903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.104926] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.104951] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.104967] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.105087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.105097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.105144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.105164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.105184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.105205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.105221] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.105239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.105257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.105274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.105291] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.105307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.105322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.105326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.105346] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.105350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.105370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.105391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.105411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.105431] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.105452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.105472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.105492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.105556] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.105581] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.105611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.105641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.105714] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.105740] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.105764] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.105806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.106101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.106127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.106152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.106176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.106202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.106229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.106256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.106291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.106315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.106336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.106363] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.106389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.108390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.108406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.108420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.108435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.109951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.109968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.109986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.112562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.112581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.114389] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.117311] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.117347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.117363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.117385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.134089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.134115] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.134150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.134259] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.134327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.150769] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.150795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.150841] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.169104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.169123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.169143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.169160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.169177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.169192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.169207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.169223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.169240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.169257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.169273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.169288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.169302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.169316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.169343] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.169365] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.169386] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.169402] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.169538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.169555] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.169635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.169663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.169692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.169722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.169747] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.169774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.169801] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.169826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.169851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.169875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.169899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.169905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.169928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.169934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.169964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.169986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.170007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.170028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.170052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.170074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.170096] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.170117] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.170136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.170160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.170185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.170254] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.170277] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.170299] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.170337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.170360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.170383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.170407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.170428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.170452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.170477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.170502] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.170547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.170567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.170589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.170615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.170639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.173711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.173729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.173743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.173759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.175263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.175278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.175295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.176792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.176808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.178611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.181547] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.181620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.181636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.181658] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.198362] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.198389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.198426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.198634] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.198700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.215069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.215094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.215139] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.233984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.234003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.234024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.234041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.234059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.234075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.234090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.234106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.234124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.234141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.234157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.234173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.234187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.234201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.234228] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.234250] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.234271] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.234287] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.234407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.234417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.234465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.234486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.234507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.234570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.234598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.234628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.234655] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.234682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.234708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.234733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.234757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.234764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.234787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.234794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.234818] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.234842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.234867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.234890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.234917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.234941] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.234966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.234989] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.235014] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.235040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.235348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.235421] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.235452] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.235474] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.235513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.235553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.235577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.235600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.235623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.235646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.235672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.235796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.235820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.235842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.235864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.235889] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.235920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.237922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.237940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.237954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.237969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.239476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.239494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.239541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.241040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.241056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.242888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.245831] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.245897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.245914] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.245936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.262630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.262654] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.262689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.262798] [drm:drm_mode_addfb2] [FB:75]
>[ 1251.262865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.279320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.279345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.279390] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.298231] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.298250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.298270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.298287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.298305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.298321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.298336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.298352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.298370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.298386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.298402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.298418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.298432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.298446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.298473] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.298494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.298556] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.298586] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.298709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.298723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.298791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.298820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.298845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.298871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.298892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.298915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.298936] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.298958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.298978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.298999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.299018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.299023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.299043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.299048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.299069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.299088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.299109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.299127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.299150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.299169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.299189] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.299208] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.299228] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.299250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.299274] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.299336] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.299359] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.299380] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.299417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.299437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.299459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.299479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.299500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.299540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.299565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.299590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.299615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.299635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.299656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.299682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.299704] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.301693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.301709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.301723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.301737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.303241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.303258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.303275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.304772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.304790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.306597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.309537] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.309608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.309624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.309646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.326348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.326375] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.326412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.326557] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.326664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.343024] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.343046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.343091] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.361934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.361953] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.361975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.361995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.362017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.362037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.362056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.362075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.362097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.362118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.362139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.362158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.362177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.362196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.362224] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.362247] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.362271] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.362288] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.362402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.362412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.362460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.362480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.362500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.362568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.362595] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.362624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.362651] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.362677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.362703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.362728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.362752] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.362759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.362782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.362789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.362813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.362838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.362862] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.362886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.362913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.362937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.362961] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.362985] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.363009] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.363036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.363064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.363140] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.363165] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.363189] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.363230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.363255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.363280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.363304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.363325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.363349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.363375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.363401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.363427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.363451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.363474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.363501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.363545] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.365549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.365565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.365579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.365594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.368172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.368189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.368204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.369703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.369720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.371542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.374478] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.374593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.374618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.374655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.391302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.391327] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.391364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.391480] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.391591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.407978] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.408004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.408052] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.426924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.426943] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.426964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.426981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.426999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.427015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.427030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.427046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.427064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.427080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.427096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.427112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.427126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.427140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.427169] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.427191] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.427213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.427228] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.427357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.427368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.427419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.427440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.427461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.427485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.427505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.427526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.427585] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.427611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.427635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.427660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.427682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.427689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.427711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.427718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.427742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.427764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.427788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.427810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.427836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.427858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.427881] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.427902] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.427926] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.427952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.427981] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.428046] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.428070] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.428094] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.428135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.428159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.428180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.428203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.428224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.428248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.428274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.428300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.428325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.428346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.428368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.428395] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.428418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.430429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.430446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.430460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.430478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.431986] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.432002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.432016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.433508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.433537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.435343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.438280] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.438352] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.438369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.438391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.455087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.455111] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.455145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.455263] [drm:drm_mode_addfb2] [FB:75]
>[ 1251.455327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.471775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.471798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.471834] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.490004] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.490023] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.490043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.490060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.490078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.490093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.490109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.490125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.490143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.490159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.490175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.490190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.490204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.490218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.490245] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.490267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.490291] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.490308] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.490432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.490442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.490489] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.490509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.490529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.490586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.490611] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.490639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.490664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.490690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.490714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.490739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.490761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.490768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.490799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.490805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.490829] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.490850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.490873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.490894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.490918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.490939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.490963] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.490984] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.491006] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.491032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.491058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.491116] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.491138] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.491194] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.491233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.491256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.491279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.491299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.491321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.491343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.491368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.491393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.491417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.491438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.491459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.491483] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.491506] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.493551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.493569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.493584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.493599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.495106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.495122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.495136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.496634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.496652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.498474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.501405] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.501431] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.501447] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.501469] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.518176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.518203] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.518240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.518359] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.518429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.534856] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.534880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.534916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.553766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.553785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.553805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.553822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.553839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.553854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.553869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.553885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.553903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.553920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.553936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.553952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.553966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.553985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.554014] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.554037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.554061] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.554078] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.554201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.554211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.554259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.554285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.554305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.554326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.554343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.554360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.554378] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.554395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.554411] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.554426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.554441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.554445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.554460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.554463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.554478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.554493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.554508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.554522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.554583] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.554605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.554629] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.554651] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.554674] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.554700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.554728] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.554786] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.554811] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.554834] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.554873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.554898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.554920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.554942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.554963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.554986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.555011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.555036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.555060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.555080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.555101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.555125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.555148] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.557153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.557170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.557185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.557199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.558706] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.558721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.558735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.560228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.560244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.562049] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.565095] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.565169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.565194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.565228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.581903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.581928] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.581964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.582074] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.582144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.598582] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.598607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.598643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.617487] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.617508] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.617530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.617592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.617623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.617647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.617672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.617695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.617724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.617751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.617776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.617801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.617822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.617845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.617886] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.617921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.617952] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.617978] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.618100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.618110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.618157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.618177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.618197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.618218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.618235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.618255] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.618276] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.618297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.618318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.618338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.618358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.618363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.618383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.618386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.618407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.618428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.618448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.618468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.618489] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.618509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.618529] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.618598] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.618622] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.618646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.618671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.618724] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.618747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.618801] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.618843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.618867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.618890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.618912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.618934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.618957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.618983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.619007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.619028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.619046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.619064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.619083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.619101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.621096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.621113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.621127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.621145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.623737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.623755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.623771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.625267] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.625283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.627090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.630033] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.630099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.630116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.630138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.646842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.646868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.646902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.647009] [drm:drm_mode_addfb2] [FB:75]
>[ 1251.647076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.663511] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.663533] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.663623] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.682468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.682487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.682507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.682524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.682588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.682613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.682638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.682664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.682694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.682721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.682747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.682773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.682796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.682819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.682863] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.682906] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.682936] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.682960] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.683069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.683079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.683121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.683137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.683154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.683172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.683186] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.683202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.683217] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.683231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.683245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.683259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.683271] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.683275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.683288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.683291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.683304] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.683317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.683329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.683341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.683356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.683369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.683382] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.683395] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.683407] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.683422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.683441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.683477] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.683491] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.683505] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.683533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.683616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.683639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.683660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.683681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.683702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.683726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.683748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.683770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.683789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.683809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.683833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.683854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.685857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.685874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.685889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.685904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.688486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.688505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.688520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.690056] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.690072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.691897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.694845] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.694907] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.694924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.694946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.711649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.711675] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.711710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.711817] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.711875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.728328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.728352] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.728389] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.747247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.747266] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.747287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.747303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.747321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.747335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.747350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.747366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.747384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.747401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.747417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.747433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.747447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.747461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.747489] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.747510] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.747531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.747595] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.747709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.747723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.747792] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.747817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.747845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.747875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.747899] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.747926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.747952] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.747977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.748002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.748025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.748048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.748054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.748077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.748082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.748106] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.748130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.748153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.748174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.748200] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.748223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.748247] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.748270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.748294] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.748326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.748352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.748416] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.748439] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.748461] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.748499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.748522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.748544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.748583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.748606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.748629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.748655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.748680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.748704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.748726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.748748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.748774] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.748798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.750788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.750804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.750818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.750832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.752335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.752350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.752364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.753860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.753875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.755679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.758619] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.758688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.758705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.758727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.775420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.775445] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.775485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.775656] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.775722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.792110] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.792135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.792172] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.811017] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.811037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.811057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.811074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.811091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.811111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.811134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.811153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.811175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.811196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.811216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.811236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.811255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.811275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.811303] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.811326] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.811351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.811367] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.811488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.811498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.811546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.811607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.811637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.811666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.811689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.811715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.811739] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.811763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.811785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.811808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.811829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.811836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.811857] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.811863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.811886] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.811907] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.811930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.811951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.811976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.811996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.812018] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.812037] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.812059] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.812085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.812110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.812166] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.812188] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.812210] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.812248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.812271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.812291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.812313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.812333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.812356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.812380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.812404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.812427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.812447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.812468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.812493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.812515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.814542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.814574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.814588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.814603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.817194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.817213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.817229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.820874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.820893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.822716] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.825676] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.825724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.825741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.825763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.842475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.842499] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.842533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.842704] [drm:drm_mode_addfb2] [FB:75]
>[ 1251.842770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.859149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.859172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.859207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.878041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.878060] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.878080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.878097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.878115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.878130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.878144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.878160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.878178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.878194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.878214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.878235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.878254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.878273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.878301] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.878324] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.878349] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.878366] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.878488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.878499] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.878546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.878605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.878633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.878661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.878685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.878711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.878735] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.878759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.878782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.878803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.878825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.878832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.878853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.878859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.878882] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.878905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.878928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.878949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.878975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.878993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.879007] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.879021] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.879035] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.879052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.879077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.879123] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.879138] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.879151] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.879179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.879199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.879217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.879236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.879254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.879273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.879293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.879312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.879333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.879351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.879369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.879388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.879407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.881398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.881416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.881430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.881445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.882956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.882972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.882985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.884499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.884515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.886322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.889261] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.889330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.889346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.889367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.906074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.906099] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.906134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.906233] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.906301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.922753] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.922779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.922816] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1251.941668] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1251.941687] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1251.941707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.941724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.941742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.941758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.941773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.941789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.941806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.941827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.941848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.941868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.941887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.941906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.941935] [drm:intel_power_well_disable [i915]] disabling display
>[ 1251.941958] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1251.941982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.941999] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1251.942121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1251.942131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1251.942178] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1251.942200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1251.942221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1251.942244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1251.942264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1251.942285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1251.942305] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1251.942326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1251.942346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1251.942366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1251.942386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1251.942390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.942410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1251.942414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1251.942435] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1251.942455] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1251.942475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1251.942495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1251.942516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1251.942535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1251.942556] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1251.942615] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1251.942640] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1251.942666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.942693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1251.942767] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1251.942791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1251.942816] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1251.943093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1251.943111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1251.943128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1251.943143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1251.943158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1251.943174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1251.943192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1251.943213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1251.943234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.943253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1251.943273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1251.943295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1251.943315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1251.945305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1251.945324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1251.945341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.945360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1251.946870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1251.946887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1251.946901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1251.948394] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1251.948411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1251.950217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1251.953140] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1251.953174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1251.953191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1251.953213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1251.969918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1251.969944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1251.969978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1251.970086] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.970152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1251.986598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1251.986622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1251.986659] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.005507] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.005526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.005546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.005608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.005641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.005666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.005691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.005717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.005746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.005772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.005798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.005824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.005847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.005870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.005913] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.005948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.005979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.006005] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.006109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.006119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.006165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.006183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.006202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.006222] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.006237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.006254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.006273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.006293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.006312] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.006331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.006350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.006354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.006373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.006376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.006396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.006415] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.006434] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.006453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.006472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.006491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.006510] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.006529] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.006548] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.006610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.006639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.006712] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.006738] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.006766] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.006806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.006830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.006853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.006875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.006898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.006921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.006947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.006971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.006995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.007010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.007023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.007039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.007057] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.009044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.009063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.009080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.009099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.011757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.011777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.011796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.013293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.013312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.015120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.018045] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.018078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.018095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.018117] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.034831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.034857] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.034891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.034997] [drm:drm_mode_addfb2] [FB:75]
>[ 1252.035055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.051497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.051526] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.051562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.070429] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.070448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.070468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.070485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.070503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.070518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.070533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.070549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.070615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.070644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.070671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.070698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.070722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.070746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.070791] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.070825] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.070857] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.070883] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.070999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.071015] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.071085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.071104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.071130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.071148] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.071163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.071179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.071195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.071209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.071223] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.071237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.071250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.071253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.071266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.071269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.071281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.071294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.071311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.071328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.071346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.071363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.071380] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.071398] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.071415] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.071433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.071452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.071497] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.071511] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.071525] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.071552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.071610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.071634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.071656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.071677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.071698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.071723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.071746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.071769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.071789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.071809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.071832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.071854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.073861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.073878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.073893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.073908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.077598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.077615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.077631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.080201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.080220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.082028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.084953] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.084985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.085002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.085024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.101729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.101755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.101789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.101896] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.101954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.118418] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.118443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.118478] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.137350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.137369] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.137389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.137406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.137424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.137438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.137453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.137469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.137487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.137504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.137520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.137536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.137555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.137616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.137658] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.137693] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.137726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.137752] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.137874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.137889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.137958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.137984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.138012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.138041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.138066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.138092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.138118] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.138143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.138168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.138191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.138214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.138221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.138242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.138247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.138271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.138294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.138318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.138340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.138366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.138389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.138410] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.138433] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.138456] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.138482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.138509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.138595] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.138621] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.138646] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.138693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.138717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.138740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.138762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.138785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.138808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.138835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.138859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.138884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.138905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.138927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.138952] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.138975] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.140963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.140978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.140992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.141010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.142519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.142535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.142549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.144090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.144106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.145993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.148928] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.149003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.149020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.149042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.165736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.165771] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.165822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.165935] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.165998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.182424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.182450] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.182488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.200326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.200345] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.200365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.200382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.200400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.200416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.200431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.200447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.200465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.200481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.200498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.200514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.200528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.200542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.200615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.200654] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.200687] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.200713] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.200836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.200852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.200920] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.200953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.200978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.201006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.201028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.201052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.201076] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.201099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.201122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.201143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.201164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.201170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.201190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.201196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.201218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.201239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.201261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.201282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.201305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.201327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.201349] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.201370] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.201389] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.201412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.201437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.201500] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.201522] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.201544] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.201601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.201625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.201647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.201669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.201691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.201715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.201741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.201765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.201790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.201812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.201834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.201860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.201883] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.203871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.203887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.203901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.203915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.207539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.207557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.207614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.209127] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.209145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.211032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.213977] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.214041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.214058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.214080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.230810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.230836] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.230871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.230981] [drm:drm_mode_addfb2] [FB:75]
>[ 1252.231047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.247472] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.247494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.247529] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.266379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.266398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.266418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.266435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.266453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.266469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.266484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.266500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.266518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.266534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.266550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.266566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.266629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.266656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.266702] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.266737] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.266770] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.266796] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.266921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.266936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.267005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.267031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.267058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.267088] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.267112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.267138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.267164] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.267189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.267220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.267241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.267263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.267269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.267289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.267295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.267316] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.267337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.267358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.267377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.267400] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.267421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.267442] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.267462] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.267482] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.267506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.267531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.267614] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.267639] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.267661] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.267700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.267724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.267747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.267771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.267792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.267816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.267842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.267866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.267890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.267912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.267934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.267960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.267984] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.269978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.269993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.270008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.270022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.272624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.272643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.272659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.275231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.275250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.277073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.279996] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.280030] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.280047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.280068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.296773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.296799] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.296834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.296953] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.297028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.313463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.313488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.313535] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.331714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.331734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.331754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.331771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.331789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.331804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.331819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.331835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.331853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.331869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.331885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.331900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.331914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.331928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.331955] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.331977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.331998] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.332013] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.332133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.332143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.332191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.332210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.332230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.332251] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.332269] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.332286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.332305] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.332322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.332338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.332354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.332374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.332378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.332398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.332402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.332423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.332443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.332463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.332483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.332503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.332523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.332544] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.332564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.332631] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.332662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.332692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.332766] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.332791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.332816] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.332858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.332883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.332910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.332935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.332958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.332983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.333010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.333036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.333062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.333085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.333108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.333135] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.333160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.337453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.337473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.337492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.337512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.339031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.339048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.339062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.340618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.340634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.342440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.345375] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.345450] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.345467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.345489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.362190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.362216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.362251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.362370] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.362445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.378883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.378907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.378956] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.396844] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.396863] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.396884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.396900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.396918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.396933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.396948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.396964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.396982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.396998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.397014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.397030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.397044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.397058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.397086] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.397107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.397129] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.397144] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.397258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.397268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.397315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.397335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.397355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.397378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.397398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.397419] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.397440] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.397460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.397481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.397501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.397521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.397525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.397545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.397549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.397569] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.397638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.397667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.397693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.397721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.397747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.397772] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.397796] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.397821] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.397849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.397877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.397952] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.397976] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.398001] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.398043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.398068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.398092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.398116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.398139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.398164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.398191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.398217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.398243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.398266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.398289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.398316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.398341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.400348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.400364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.400379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.400393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.402963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.402981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.402998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.405608] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.405627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.407438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.410369] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.410448] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.410464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.410486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.427216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.427242] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.427277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.427386] [drm:drm_mode_addfb2] [FB:75]
>[ 1252.427444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.443888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.443914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.443954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.462813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.462832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.462852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.462869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.462887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.462902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.462917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.462933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.462951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.462968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.462984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.462999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.463013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.463027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.463055] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.463077] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.463098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.463113] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.463224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.463234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.463295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.463315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.463341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.463360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.463375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.463391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.463408] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.463423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.463439] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.463453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.463467] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.463470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.463484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.463487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.463501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.463514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.463528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.463541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.463557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.463570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.463627] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.463648] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.463668] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.463693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.463719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.463776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.463798] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.463822] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.463863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.463886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.463910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.463934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.463956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.463980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.464006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.464030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.464055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.464078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.464100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.464127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.464151] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.466149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.466166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.466182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.466201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.468774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.468793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.468809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.472438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.472456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.474260] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.476649] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.476712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.476729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.476751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.493463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.493488] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.493523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.493692] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.493763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.510151] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.510175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.510213] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.528328] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.528347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.528367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.528384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.528402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.528418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.528432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.528448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.528466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.528486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.528507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.528528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.528546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.528565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.528642] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.528679] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.528715] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.528741] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.528871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.528887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.528957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.528980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.529005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.529032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.529053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.529077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.529099] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.529121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.529142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.529164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.529183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.529189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.529209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.529214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.529235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.529255] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.529284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.529303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.529326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.529345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.529365] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.529384] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.529404] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.529425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.529449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.529503] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.529525] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.529546] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.529583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.529625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.529648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.529669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.529691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.529712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.529737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.529761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.529786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.529805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.529827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.529853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.529874] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.531863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.531880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.531894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.531908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.533411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.533426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.533442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.534940] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.534957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.536761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.539342] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.539417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.539434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.539456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.556167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.556193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.556231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.556335] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.556404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.572855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.572880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.572918] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.591770] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.591789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.591810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.591826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.591844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.591859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.591878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.591898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.591920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.591941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.591961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.591981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.592000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.592019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.592048] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.592071] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.592095] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.592112] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.592240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.592250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.592296] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.592315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.592335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.592357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.592377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.592397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.592417] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.592437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.592457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.592476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.592496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.592500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.592519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.592523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.592543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.592562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.592582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.592644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.592672] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.592698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.592721] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.592745] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.592767] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.592794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.592822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.592880] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.592905] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.592928] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.592969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.592991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.593015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.593037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.593060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.593082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.593107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.593132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.593156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.593176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.593205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.593227] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.593250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.595249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.595266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.595280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.595295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.597883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.597902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.597918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.600528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.600547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.602356] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.605293] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.605366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.605383] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.605411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.622136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.622162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.622198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.622311] [drm:drm_mode_addfb2] [FB:75]
>[ 1252.622379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.638798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.638822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.638860] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.657717] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.657737] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.657757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.657774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.657792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.657807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.657822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.657838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.657856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.657872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.657887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.657902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.657917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.657930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.657957] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.657979] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.658000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.658016] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.658138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.658148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.658195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.658214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.658235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.658258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.658279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.658300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.658320] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.658349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.658370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.658391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.658411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.658415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.658434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.658438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.658459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.658479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.658499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.658519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.658540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.658560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.658580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.658637] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.658665] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.658692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.658721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.658781] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.658806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.658831] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.658872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.658896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.658920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.658942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.658966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.658990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.659017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.659042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.659068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.659089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.659112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.659139] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.659162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.661171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.661187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.661202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.661217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.663808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.663825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.663839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.666405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.666423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.668233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.671193] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.671244] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.671264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.671290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.687993] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.688018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.688053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.688153] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.688222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.704681] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.704706] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.704745] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.723588] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.723634] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.723656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.723676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.723698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.723717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.723737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.723756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.723778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.723799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.723818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.723838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.723858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.723877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.723905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.723928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.723953] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.723969] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.724092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.724103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.724151] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.724170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.724190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.724211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.724228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.724246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.724264] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.724284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.724305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.724326] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.724346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.724350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.724370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.724374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.724394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.724415] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.724435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.724455] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.724476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.724495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.724516] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.724536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.724556] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.724578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.724600] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.724711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.724734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.724759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.724802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.724827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.724853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.724876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.724901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.724924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.724952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.724978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.725004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.725026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.725050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.725078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.725101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.728174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.728191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.728206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.728222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.730863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.730881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.730895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.732392] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.732408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.734219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.737156] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.737230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.737249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.737275] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.753979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.754004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.754039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.754141] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.754203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.770667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.770692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.770731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.789583] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.789602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.789668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.789696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.789725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.789751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.789772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.789791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.789815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.789836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.789857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.789879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.789898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.789918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.789947] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.789970] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.789995] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.790012] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.790097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.790112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.790158] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.790176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.790194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.790214] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.790230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.790246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.790264] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.790280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.790295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.790310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.790324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.790328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.790342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.790345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.790360] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.790374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.790388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.790401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.790418] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.790432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.790451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.790470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.790489] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.790510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.790530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.790575] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.790588] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.790639] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.790678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.790700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.790721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.790742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.790762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.790783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.790807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.790829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.790852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.790872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.790891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.790915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.790936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.792930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.792946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.792961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.792976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.794481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.794496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.794510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.796008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.796023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.797831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.800787] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.800841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.800860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.800886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.817577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.817601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.817686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.817815] [drm:drm_mode_addfb2] [FB:75]
>[ 1252.817878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.834254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.834277] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.834323] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.853188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.853207] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.853227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.853244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.853262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.853277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.853291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.853307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.853325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.853342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.853358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.853373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.853388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.853402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.853429] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.853450] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.853471] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.853487] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.853589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.853637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.853714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.853733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.853753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.853775] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.853795] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.853815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.853835] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.853855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.853875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.853895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.853921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.853925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.853941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.853944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.853960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.853974] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.853988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.854001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.854017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.854031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.854045] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.854058] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.854071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.854089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.854109] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.854144] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.854159] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.854173] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.854201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.854220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.854236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.854254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.854271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.854288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.854307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.854326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.854346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.854364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.854381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.854400] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.854418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.856399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.856416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.856430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.856445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.857961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.857980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.857997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.859493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.859511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.861317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.864251] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.864326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.864343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.864365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.881069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.881096] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.881133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.881244] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.881312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.897749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.897775] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.897821] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.916662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.916681] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.916701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.916718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.916735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.916750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.916765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.916781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.916799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.916815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.916831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.916846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.916861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.916874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.916902] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.916923] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.916944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.916960] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.917079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.917088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.917136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.917156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.917176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.917197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.917214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.917232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.917250] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.917267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.917284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.917300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.917315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.917319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.917334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.917337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.917353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.917368] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.917383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.917398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.917415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.917431] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.917446] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.917461] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.917476] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.917493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.917512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.917562] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.917579] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.917595] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.917670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.917694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.917719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.917742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.917764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.917788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.917813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.917838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.917863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.917884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.917906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.917932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.917955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.919964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.919981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.919995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.920010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.921516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.921531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.921545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.923041] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.923057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.924860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.927789] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.927817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.927833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.927855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1252.944561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.944588] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.944668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.944804] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.944870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.961241] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1252.961267] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.961313] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.980145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1252.980163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1252.980183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.980200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.980218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.980233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.980248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.980264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1252.980282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.980298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.980313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.980329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.980343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.980357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.980384] [drm:intel_power_well_disable [i915]] disabling display
>[ 1252.980405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1252.980426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1252.980442] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1252.980534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1252.980544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1252.980587] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1252.980605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1252.980665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1252.980695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1252.980718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1252.980751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1252.980773] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1252.980794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1252.980815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1252.980835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1252.980854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1252.980861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.980879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1252.980885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1252.980905] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1252.980924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1252.980944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1252.980963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1252.980985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1252.981005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1252.981026] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1252.981046] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1252.981066] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1252.981090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1252.981115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1252.981171] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1252.981194] [drm:intel_power_well_enable [i915]] enabling display
>[ 1252.981218] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1252.981257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1252.981280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1252.981302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1252.981324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1252.981339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1252.981353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1252.981369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1252.981384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1252.981403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1252.981421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1252.981439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1252.981458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1252.981475] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1252.983451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1252.983469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.983486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.983504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.985011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1252.985027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1252.985042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.987644] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.987664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.989469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.992405] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.992478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1252.992495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1252.992517] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.009216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.009240] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.009274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.009379] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.009444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.025901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.025925] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.025970] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.044814] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.044833] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.044853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.044870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.044887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.044903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.044917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.044933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.044951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.044967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.044983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.044999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.045013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.045027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.045054] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.045076] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.045097] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.045112] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.045228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.045238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.045283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.045301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.045320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.045350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.045369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.045389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.045408] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.045427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.045447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.045466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.045484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.045488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.045507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.045511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.045530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.045550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.045569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.045588] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.045607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.045674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.045703] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.045729] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.045755] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.045783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.045813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.045873] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.045898] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.045922] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.045963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.045988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.046012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.046036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.046059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.046084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.046117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.046140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.046164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.046184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.046206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.046231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.046254] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.048255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.048271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.048286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.048300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.049805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.049820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.049836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.052425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.052442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.054247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.056609] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.056700] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.056717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.056739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.073443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.073467] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.073501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.073641] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.073731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.090163] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.090188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.090224] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.109094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.109113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.109133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.109150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.109168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.109184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.109199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.109218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.109240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.109261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.109281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.109302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.109321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.109340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.109368] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.109391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.109415] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.109432] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.109531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.109542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.109595] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.109615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.109671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.109700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.109724] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.109749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.109773] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.109797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.109820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.109843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.109864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.109871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.109892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.109898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.109920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.109943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.109965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.109986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.110011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.110032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.110056] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.110074] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.110089] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.110106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.110126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.110191] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.110207] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.110221] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.110249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.110265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.110280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.110295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.110309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.110324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.110341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.110357] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.110380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.110393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.110406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.110422] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.110440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.112417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.112433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.112447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.112462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.113966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.113982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.113995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.115487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.115502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.117310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.120243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.120318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.120335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.120357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.137061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.137087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.137121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.137250] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.137307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.153741] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.153766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.153811] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.172666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.172685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.172705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.172722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.172740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.172755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.172774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.172794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.172821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.172844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.172861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.172878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.172896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.172915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.172943] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.172966] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.172991] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.173007] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.173128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.173138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.173185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.173204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.173225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.173246] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.173263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.173281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.173299] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.173316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.173333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.173348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.173363] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.173367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.173382] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.173385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.173406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.173426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.173447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.173467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.173488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.173508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.173528] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.173548] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.173569] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.173590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.173612] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.173711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.173733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.173755] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.173798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.173823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.173848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.173872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.173895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.173920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.173947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.173968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.173989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.174008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.174028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.174049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.174068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.176049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.176066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.176080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.176095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.177614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.177647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.177662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.179170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.179186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.181005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.183941] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.184013] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.184029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.184049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.200787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.200812] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.200849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.200963] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.201030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.217452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.217477] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.217514] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.235111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.235130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.235151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.235168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.235185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.235200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.235215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.235231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.235253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.235274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.235294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.235315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.235334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.235353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.235381] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.235404] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.235429] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.235445] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.235569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.235579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.235627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.235689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.235717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.235746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.235770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.235795] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.235820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.235844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.235867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.235889] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.235911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.235918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.235940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.235947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.235970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.235992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.236014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.236037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.236064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.236086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.236109] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.236132] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.236155] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.236189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.236215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.236272] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.236289] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.236302] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.236327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.236342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.236355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.236369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.236382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.236396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.236412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.236427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.236441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.236454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.236467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.236483] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.236498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.238473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.238489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.238503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.238517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.240025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.240044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.240061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.241581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.241598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.243408] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.246351] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.246416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.246432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.246453] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.263158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.263184] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.263218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.263339] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.263412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.279852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.279875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.279920] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.298780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.298799] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.298820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.298836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.298854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.298869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.298884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.298900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.298918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.298935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.298950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.298966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.298980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.298994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.299021] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.299043] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.299064] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.299080] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.299193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.299204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.299249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.299267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.299286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.299306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.299325] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.299345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.299364] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.299383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.299403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.299422] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.299441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.299445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.299464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.299467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.299487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.299506] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.299525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.299544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.299563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.299582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.299601] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.299620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.299683] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.299713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.299744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.299818] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.299843] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.299868] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.299910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.299938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.299963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.299988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.300011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.300036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.300063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.300088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.300114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.300137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.300160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.300188] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.300212] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.302215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.302231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.302245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.302260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.304854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.304874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.304893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.306393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.306410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.308218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.311147] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.311176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.311192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.311214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.327916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.327940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.327974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.328073] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.328141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.344597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.344620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.344710] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.363388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.363408] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.363428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.363448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.363470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.363490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.363509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.363528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.363550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.363571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.363591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.363611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.363630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.363692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.363737] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.363773] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.363808] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.363834] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.363941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.363951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.363993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.364011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.364031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.364052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.364069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.364088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.364106] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.364124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.364142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.364161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.364178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.364182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.364199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.364203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.364221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.364239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.364257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.364274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.364292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.364309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.364327] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.364345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.364362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.364381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.364401] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.364437] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.364451] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.364465] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.364493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.364511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.364529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.364547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.364566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.364583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.364603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.364622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.364673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.364696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.364718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.364743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.364764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.366761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.366777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.366792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.366808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.368312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.368328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.368342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.369838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.369855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.371669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.374602] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.374708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.374738] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.374774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.391421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.391448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.391482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.391591] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.391700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.408103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.408129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.408167] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.426384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.426403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.426424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.426441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.426458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.426474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.426489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.426505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.426523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.426539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.426555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.426571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.426585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.426599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.426627] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.426693] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.426727] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.426754] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.426866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.426880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.426948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.426973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.426998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.427027] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.427049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.427074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.427098] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.427122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.427145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.427168] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.427196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.427201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.427221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.427226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.427247] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.427266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.427287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.427306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.427328] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.427348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.427368] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.427387] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.427407] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.427429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.427452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.427515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.427536] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.427558] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.427595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.427615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.427637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.427680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.427700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.427723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.427749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.427772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.427797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.427817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.427839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.427864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.427886] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.429873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.429889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.429903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.429917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.431421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.431436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.431452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.432947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.432963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.434765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.437198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.437269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.437286] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.437308] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.454018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.454045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.454082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.454201] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.454275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.470729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.470754] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.470791] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.489641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.489678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.489699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.489716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.489734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.489749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.489764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.489780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.489797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.489818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.489839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.489859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.489878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.489897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.489925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.489948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.489973] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.489989] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.490105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.490115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.490163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.490182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.490203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.490227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.490248] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.490269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.490289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.490310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.490330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.490350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.490370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.490374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.490394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.490398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.490419] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.490439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.490459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.490480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.490500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.490520] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.490540] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.490561] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.490581] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.490602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.490624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.490711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.490737] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.490759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.490803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.490828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.490853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.490876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.490900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.490924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.490952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.490978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.491005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.491027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.491051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.491079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.491103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.493122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.493139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.493153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.493168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.494701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.494716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.494730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.496233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.496250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.500218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.502499] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.502570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.502587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.502609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.519314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.519339] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.519374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.519483] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.519547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.535994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.536018] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.536054] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.554897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.554916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.554937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.554954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.554971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.554987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.555002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.555018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.555036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.555057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.555077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.555098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.555117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.555136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.555164] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.555187] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.555212] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.555228] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.555350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.555360] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.555408] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.555428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.555448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.555469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.555486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.555504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.555522] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.555541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.555562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.555582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.555602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.555606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.555626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.555630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.555655] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.555701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.555717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.555733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.555750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.555765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.555781] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.555795] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.555810] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.555826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.555846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.555885] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.555900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.555914] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.555944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.555964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.555984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.556004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.556024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.556044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.556082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.556105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.556123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.556138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.556154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.556172] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.556189] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.558193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.558209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.558223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.558238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.559756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.559775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.559792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.561287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.561304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.563113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.565915] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.565971] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.565988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.566010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.582705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.582729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.582763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.582871] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.582935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.599394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.599419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.599455] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.618300] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.618319] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.618339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.618356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.618374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.618389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.618404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.618420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.618438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.618455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.618471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.618487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.618506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.618525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.618553] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.618576] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.618601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.618617] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.618762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.618777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.618848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.618876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.618901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.618921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.618937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.618954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.618971] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.618991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.619010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.619030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.619050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.619055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.619073] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.619077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.619096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.619116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.619143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.619160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.619178] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.619193] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.619211] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.619229] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.619246] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.619265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.619284] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.619326] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.619340] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.619354] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.619382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.619400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.619418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.619436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.619454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.619472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.619491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.619511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.619530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.619548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.619566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.619584] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.619602] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.621573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.621589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.621604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.621618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.623124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.623140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.623153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.624668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.624684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.626486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.629405] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.629443] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.629460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.629481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.646187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.646213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.646251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.646359] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.646426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.662866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.662890] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.662927] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.681776] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.681795] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.681815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.681832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.681850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.681865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.681880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.681897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.681915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.681931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.681947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.681963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.681981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.682001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.682029] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.682051] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.682076] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.682093] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.682215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.682226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.682273] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.682293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.682312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.682334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.682353] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.682375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.682395] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.682415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.682436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.682457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.682477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.682481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.682501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.682505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.682525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.682546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.682566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.682586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.682607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.682627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.682647] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.682712] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.682738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.682764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.682790] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.682864] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.682888] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.682911] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.682952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.682969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.682985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.683000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.683015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.683031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.683048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.683064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.683080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.683094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.683112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.683133] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.683153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.685143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.685160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.685174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.685189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.686719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.686737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.686755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.689333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.689353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.691162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.694110] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.694172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.694189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.694211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.710914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.710941] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.710978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.711087] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.711156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.727594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.727620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.727658] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.746540] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.746560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.746580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.746597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.746614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.746629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.746644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.746660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.746725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.746753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.746781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.746808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.746832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.746857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.746901] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.746935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.746968] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.746993] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.747122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.747137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.747186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.747204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.747224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.747246] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.747265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.747284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.747303] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.747322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.747342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.747369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.747387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.747392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.747411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.747415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.747434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.747453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.747472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.747491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.747510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.747529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.747548] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.747567] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.747586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.747606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.747627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.747707] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.747734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.747758] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.747802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.747828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.747854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.747878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.747902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.747926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.747959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.747985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.748010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.748030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.748051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.748077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.748098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.750098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.750116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.750130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.750145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.751710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.751726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.751740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.753244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.753260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.756160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.759109] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.759169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.759184] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.759205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.775913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.775938] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.775973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.776082] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.776140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.792592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.792617] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.792653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.811533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.811552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.811572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.811589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.811607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.811622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.811637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.811653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.811718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.811748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.811775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.811803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.811827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.811852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.811896] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.811931] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.811963] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.811988] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.812102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.812115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.812165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.812183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.812219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.812242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.812264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.812280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.812295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.812310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.812324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.812337] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.812350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.812354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.812371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.812374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.812392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.812409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.812427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.812444] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.812462] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.812479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.812497] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.812514] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.812532] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.812550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.812569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.812614] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.812629] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.812643] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.812708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.812732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.812753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.812774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.812795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.812816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.812840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.812863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.812886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.812905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.812925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.812949] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.812970] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.814973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.814991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.815005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.815020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.816525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.816540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.816554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.818049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.818065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.819868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.822799] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.822827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.822846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.822872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.839568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.839593] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.839628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.839888] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.839951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.856248] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.856274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.856312] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.874430] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.874449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.874469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.874486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.874504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.874519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.874533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.874550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.874568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.874588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.874609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.874629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.874648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.874667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.874748] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.874785] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.874819] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.874845] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.874978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.874992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.875062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.875088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.875116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.875146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.875171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.875197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.875223] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.875248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.875273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.875297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.875320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.875326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.875349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.875355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.875379] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.875402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.875425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.875448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.875474] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.875497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.875520] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.875543] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.875564] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.875589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.875617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.875702] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.875734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.875756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.875794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.875818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.875841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.875864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.875886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.875910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.875935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.875959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.875984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.876006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.876027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.876052] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.876075] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.878065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.878080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.878094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.878109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.879614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.879629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.879642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.881137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.881155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.882961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.885904] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.885968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.885983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.886003] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.902713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.902738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.902773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.902880] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.902944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.919391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.919415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.919452] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1253.937429] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1253.937448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1253.937468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.937488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.937510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.937530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.937549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.937568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.937589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.937610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.937630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.937650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.937669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.937734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.937782] [drm:intel_power_well_disable [i915]] disabling display
>[ 1253.937817] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1253.937851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.937877] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1253.938003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1253.938020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1253.938095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1253.938128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1253.938153] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1253.938179] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1253.938200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1253.938224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1253.938246] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1253.938268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1253.938289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1253.938310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1253.938329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1253.938335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.938356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1253.938361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1253.938382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1253.938401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1253.938422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1253.938440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1253.938463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1253.938482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1253.938503] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1253.938522] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1253.938541] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1253.938563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.938587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1253.938640] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1253.938662] [drm:intel_power_well_enable [i915]] enabling display
>[ 1253.938706] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1253.938745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1253.938766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1253.938790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1253.938810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1253.938833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1253.938854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1253.938879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1253.938904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1253.938929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.938949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1253.938970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1253.938996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1253.939018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1253.941014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1253.941030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.941045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.941059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.942562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1253.942577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1253.942591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.944086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.944102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.945912] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.948857] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1253.948921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1253.948938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1253.948960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1253.965650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1253.965676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1253.965761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1253.965905] [drm:drm_mode_addfb2] [FB:75]
>[ 1253.965982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1253.982373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1253.982398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1253.982445] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.001301] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.001320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.001341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.001360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.001382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.001402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.001422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.001441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.001461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.001482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.001503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.001522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.001541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.001560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.001588] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.001611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.001636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.001653] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.001805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.001819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.001891] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.001917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.001937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.001957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.001973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.001991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.002008] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.002025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.002041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.002056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.002070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.002074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.002092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.002096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.002116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.002135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.002155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.002174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.002195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.002214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.002234] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.002253] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.002273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.002293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.002314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.002353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.002368] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.002383] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.002413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.002433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.002459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.002475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.002491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.002506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.002523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.002538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.002561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.002582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.002596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.002612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.002627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.004602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.004622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.004644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.004660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.006191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.006206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.006219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.008799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.008817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.010645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.012851] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.012903] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.012926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.012958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.029644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.029670] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.029761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.029917] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.029984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.046321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.046346] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.046386] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.064437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.064456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.064477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.064494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.064512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.064528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.064543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.064559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.064577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.064593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.064610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.064626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.064640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.064654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.064722] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.064760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.064794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.064818] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.064924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.064939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.065002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.065019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.065037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.065056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.065072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.065088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.065105] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.065121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.065136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.065150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.065164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.065168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.065181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.065185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.065199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.065213] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.065227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.065256] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.065275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.065289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.065303] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.065316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.065330] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.065346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.065364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.065403] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.065417] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.065430] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.065457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.065472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.065487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.065502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.065515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.065530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.065546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.065562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.065577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.065591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.065609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.065629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.065648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.067661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.067677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.067726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.067744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.069262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.069280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.069295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.070796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.070814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.072629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.075551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.075587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.075604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.075626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.092331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.092357] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.092395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.092504] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.092580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.109011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.109035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.109071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.127921] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.127940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.127960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.127978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.127995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.128010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.128025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.128041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.128058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.128075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.128091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.128107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.128125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.128144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.128184] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.128208] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.128231] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.128246] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.128359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.128369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.128416] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.128436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.128456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.128476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.128493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.128511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.128529] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.128546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.128563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.128578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.128593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.128597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.128612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.128615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.128631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.128646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.128661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.128675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.128733] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.128756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.128781] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.128803] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.128825] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.128852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.128880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.128941] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.128967] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.128991] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.129033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.129059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.129082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.129107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.129128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.129152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.129178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.129210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.129233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.129253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.129274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.129298] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.129320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.131322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.131340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.131358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.131376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.132885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.132902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.132919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.134415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.134433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.136240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.139177] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.139249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.139266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.139288] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.155991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.156017] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.156053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.156162] [drm:drm_mode_addfb2] [FB:75]
>[ 1254.156222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.172662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.172685] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.172770] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.191625] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.191644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.191664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.191680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.191746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.191774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.191799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.191825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.191855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.191881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.191909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.191935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.191959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.191982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.192024] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.192059] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.192092] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.192118] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.192239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.192251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.192304] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.192325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.192346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.192370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.192390] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.192411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.192432] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.192452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.192473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.192493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.192514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.192518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.192538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.192541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.192562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.192582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.192610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.192628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.192646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.192663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.192678] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.192729] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.192750] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.192773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.192797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.192853] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.192876] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.192896] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.192935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.192959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.192977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.192992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.193005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.193020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.193036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.193051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.193066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.193079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.193092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.193109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.193124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.195099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.195115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.195129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.195143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.196650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.196665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.196678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.198217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.198232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.200050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.202999] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.203060] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.203077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.203099] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.219828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.219853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.219888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.219995] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.220068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.236499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.236524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.236561] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.254439] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.254457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.254478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.254494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.254512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.254527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.254542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.254559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.254576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.254593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.254608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.254624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.254638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.254652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.254679] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.254749] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.254781] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.254808] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.254912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.254927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.254995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.255013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.255031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.255051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.255067] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.255091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.255107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.255122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.255136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.255150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.255163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.255168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.255181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.255184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.255198] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.255211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.255223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.255236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.255251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.255268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.255286] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.255304] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.255321] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.255340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.255360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.255405] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.255420] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.255434] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.255462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.255480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.255498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.255516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.255534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.255552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.255572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.255591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.255610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.255628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.255660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.255682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.255727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.257729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.257746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.257761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.257775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.259296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.259313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.259327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.260830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.260847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.262655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.265589] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.265664] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.265681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.265742] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.282399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.282425] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.282462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.282582] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.282646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.299107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.299132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.299177] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.318076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.318095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.318116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.318132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.318150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.318166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.318181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.318197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.318215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.318231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.318247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.318263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.318277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.318291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.318317] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.318339] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.318360] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.318376] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.318496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.318506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.318553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.318573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.318593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.318614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.318630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.318648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.318666] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.318686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.318750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.318775] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.318796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.318803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.318825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.318831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.318853] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.318875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.318896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.318917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.318942] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.318963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.318985] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.319006] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.319028] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.319053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.319079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.319153] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.319171] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.319187] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.319214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.319231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.319246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.319260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.319274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.319290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.319307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.319323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.319339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.319353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.319367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.319384] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.319400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.321385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.321402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.321416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.321431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.322949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.322967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.322985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.324480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.324497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.326304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.329237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.329313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.329330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.329352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.346055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.346082] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.346119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.346229] [drm:drm_mode_addfb2] [FB:75]
>[ 1254.346297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.362755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.362780] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.362825] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.381646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.381666] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.381686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.381749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.381782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.381807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.381832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.381857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.381886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.381913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.381939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.381965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.381989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.382012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.382056] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.382090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.382122] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.382148] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.382290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.382300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.382347] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.382366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.382386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.382407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.382424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.382444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.382465] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.382486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.382506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.382526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.382546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.382551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.382571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.382574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.382595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.382615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.382636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.382656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.382676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.382697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.382749] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.382773] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.382797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.382823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.382850] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.382929] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.382951] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.382975] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.383015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.383038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.383061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.383083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.383105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.383128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.383153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.383177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.383201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.383217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.383230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.383261] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.383280] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.385262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.385278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.385292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.385307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.386836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.386853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.386867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.388362] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.388379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.390202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.393156] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.393213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.393232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.393258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.409954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.409981] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.410018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.410127] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.410197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.426634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.426659] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.426703] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.445578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.445598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.445618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.445635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.445653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.445669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.445688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.445747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.445776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.445804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.445829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.445856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.445877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.445899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.445943] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.445976] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.446008] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.446032] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.446144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.446154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.446200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.446225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.446243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.446262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.446279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.446297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.446315] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.446332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.446350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.446368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.446385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.446388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.446406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.446409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.446427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.446444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.446462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.446479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.446496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.446514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.446531] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.446549] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.446566] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.446584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.446603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.446646] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.446660] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.446674] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.446701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.446762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.446788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.446813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.446836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.446861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.446888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.446913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.446938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.446960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.446983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.447009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.447032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.449304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.449322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.449336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.449351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.450857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.450873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.450886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.452378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.452394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.454215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.457155] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.457224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.457240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.457262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.473963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.473987] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.474021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.474127] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.474183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.490646] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.490671] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.490752] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.509561] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.509580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.509601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.509618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.509636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.509651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.509666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.509683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.509701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.509763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.509790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.509818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.509840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.509864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.509908] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.509941] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.509973] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.509998] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.510113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.510130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.510205] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.510233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.510261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.510291] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.510315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.510342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.510368] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.510393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.510418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.510441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.510464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.510470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.510493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.510499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.510522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.510552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.510575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.510595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.510619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.510641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.510661] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.510683] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.510703] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.510761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.510789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.510860] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.511070] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.511084] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.511112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.511129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.511144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.511158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.511172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.511187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.511204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.511219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.511235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.511248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.511262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.511279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.511294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.513278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.513295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.513310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.513325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.514832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.514849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.514867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.516360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.516377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.518206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.521160] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.521216] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.521236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.521262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.537957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.537982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.538017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.538130] [drm:drm_mode_addfb2] [FB:75]
>[ 1254.538195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.554638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.554663] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.554708] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.573570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.573589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.573609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.573626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.573645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.573664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.573683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.573703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.573770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.573797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.573823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.573850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.573871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.573894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.573937] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.573971] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.574003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.574027] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.574148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.574160] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.574207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.574225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.574243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.574263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.574279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.574296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.574313] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.574329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.574344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.574359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.574373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.574377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.574390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.574394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.574413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.574433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.574452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.574471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.574490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.574509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.574528] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.574547] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.574566] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.574586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.574607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.574654] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.574669] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.574684] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.574720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.574775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.574803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.574829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.574854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.574887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.574914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.574939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.574964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.574985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.575008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.575034] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.575058] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.577293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.577310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.577324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.577339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.578856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.578873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.578888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.580380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.580396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.582223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.585139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.585180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.585198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.585223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.601920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.601945] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.601980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.602082] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.602152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.618640] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.618665] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.618701] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.637604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.637623] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.637643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.637660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.637681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.637701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.637766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.637795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.637826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.637853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.637879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.637905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.637928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.637951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.637992] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.638026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.638059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.638085] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.638195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.638205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.638258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.638275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.638292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.638310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.638324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.638340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.638355] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.638370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.638384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.638398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.638411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.638414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.638427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.638430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.638443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.638460] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.638478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.638496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.638521] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.638538] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.638556] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.638574] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.638591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.638609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.638628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.638672] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.638686] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.638700] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.638771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.638794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.638816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.638836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.638857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.638878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.638903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.638926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.638948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.638968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.638988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.639012] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.639033] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.641039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.641056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.641070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.641085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.642590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.642606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.642620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.644115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.644132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.645935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.648868] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.648945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.648962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.648983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.665696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.665759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.665816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.665937] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.666002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.682368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.682403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.682438] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.700475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.700494] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.700514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.700531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.700549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.700565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.700580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.700597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.700615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.700632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.700648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.700664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.700678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.700692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.700759] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.700796] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.700828] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.700855] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.700960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.700974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.701044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.701067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.701086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.701106] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.701123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.701144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.701163] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.701183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.701203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.701237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.701255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.701259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.701274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.701278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.701294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.701308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.701323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.701337] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.701355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.701369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.701384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.701398] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.701412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.701429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.701448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.701486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.701500] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.701514] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.701541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.701557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.701572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.701586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.701601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.701625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.701640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.701655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.701669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.701682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.701694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.701714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.701758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.703755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.703772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.703785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.703800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.705309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.705324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.705338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.706844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.706862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.708669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.711601] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.711679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.711696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.711718] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.728430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.728456] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.728490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.728593] [drm:drm_mode_addfb2] [FB:75]
>[ 1254.728659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.745100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.745125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.745161] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.764013] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.764032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.764054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.764074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.764095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.764115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.764134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.764154] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.764176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.764197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.764217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.764238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.764257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.764276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.764304] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.764326] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.764351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.764368] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.764492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.764502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.764550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.764569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.764589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.764611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.764628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.764648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.764669] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.764689] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.764711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.764776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.764800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.764807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.764829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.764836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.764859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.764881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.764903] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.764924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.764948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.764970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.764992] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.765013] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.765034] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.765058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.765084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.765158] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.765176] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.765190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.765218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.765234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.765250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.765265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.765279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.765295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.765312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.765328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.765343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.765357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.765371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.765389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.765405] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.767390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.767406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.767420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.767435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.768940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.768958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.768976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.770481] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.770499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.772308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.775220] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.775264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.775280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.775300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.792009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.792036] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.792074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.792185] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.792246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.808679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.808702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.808780] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.827637] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.827656] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.827676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.827693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.827711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.827774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.827799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.827824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.827853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.827881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.827898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.827915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.827934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.827954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.827982] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.828005] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.828030] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.828047] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.828127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.828136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.828182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.828200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.828219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.828240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.828255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.828282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.828298] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.828314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.828329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.828342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.828356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.828359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.828373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.828376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.828390] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.828403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.828417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.828429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.828445] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.828458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.828472] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.828484] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.828497] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.828513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.828530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.828566] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.828579] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.828592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.828617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.828632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.828646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.828659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.828672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.828686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.828701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.828718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.828767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.828787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.828807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.828830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.828852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.830845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.830862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.830879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.830897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.832406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.832423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.832437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.833934] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.833950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.835755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.838180] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.838207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.838224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.838246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.854959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.854985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.855023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.855138] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.855205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.871638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.871661] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.871707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.890582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.890601] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.890622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.890639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.890657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.890672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.890687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.890703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.890721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.890780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.890807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.890835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.890858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.890881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.890925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.890959] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.890991] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.891016] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.891142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.891158] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.891229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.891257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.891284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.891314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.891339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.891365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.891392] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.891417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.891442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.891466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.891489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.891495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.891518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.891524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.891547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.891571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.891594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.891614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.891640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.891662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.891683] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.891713] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.891733] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.891812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.891837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.892063] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.892077] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.892090] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.892117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.892135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.892153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.892171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.892188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.892206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.892225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.892244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.892262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.892279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.892294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.892313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.892331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.894318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.894335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.894350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.894365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.895876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.895891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.895905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.897401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.897417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.899244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.902191] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.902254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.902273] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.902299] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.919009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.919035] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.919071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.919173] [drm:drm_mode_addfb2] [FB:75]
>[ 1254.919243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.935701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.935725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.935817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1254.954494] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1254.954522] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1254.954546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.954564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.954582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.954597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.954613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.954629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.954650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.954672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.954692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.954713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.954732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.954790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.954835] [drm:intel_power_well_disable [i915]] disabling display
>[ 1254.954871] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1254.954906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.954932] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1254.955025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1254.955035] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1254.955086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1254.955102] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1254.955119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1254.955139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1254.955157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1254.955176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1254.955194] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1254.955212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1254.955230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1254.955248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1254.955266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1254.955270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.955288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1254.955291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1254.955309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1254.955327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1254.955345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1254.955362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1254.955380] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1254.955396] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1254.955415] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1254.955432] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1254.955451] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1254.955469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.955488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1254.955523] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1254.955537] [drm:intel_power_well_enable [i915]] enabling display
>[ 1254.955552] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1254.955580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1254.955599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1254.955617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1254.955635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1254.955653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1254.955672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1254.955691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1254.955710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1254.955733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.955779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1254.955800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1254.955825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1254.955847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1254.957850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1254.957867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1254.957882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.957897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1254.959400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1254.959416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1254.959432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1254.960929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1254.960945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1254.962770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1254.966011] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1254.966083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1254.966099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1254.966121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1254.982826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1254.982852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1254.982886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1254.982994] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.983060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1254.999506] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1254.999530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1254.999566] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.018419] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.018438] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.018458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.018475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.018493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.018508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.018522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.018538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.018556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.018572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.018587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.018603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.018617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.018631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.018658] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.018679] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.018700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.018715] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.018866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.018881] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.018951] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.018975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.019002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.019030] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.019052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.019078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.019101] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.019125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.019147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.019170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.019191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.019197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.019218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.019223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.019246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.019267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.019289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.019309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.019334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.019354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.019377] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.019398] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.019425] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.019447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.019470] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.019532] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.019553] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.019574] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.019611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.019633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.019652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.019673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.019692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.019714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.019738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.019779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.019804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.019824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.019845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.019871] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.019893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.021883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.021900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.021914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.021929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.023432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.023447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.023461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.024956] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.024972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.026777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.029711] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.029813] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.029843] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.029878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.046530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.046556] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.046591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.046697] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.046815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.063209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.063234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.063270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.082121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.082140] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.082160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.082177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.082195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.082210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.082225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.082241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.082259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.082275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.082291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.082307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.082321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.082340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.082368] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.082391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.082416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.082432] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.082555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.082565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.082613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.082634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.082656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.082679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.082699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.082720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.082740] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.082797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.082823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.082849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.082874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.082881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.082904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.082911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.082936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.082960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.082984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.083008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.083036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.083060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.083085] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.083108] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.083133] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.083160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.083188] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.083248] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.083272] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.083297] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.083338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.083363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.083387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.083411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.083432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.083457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.083484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.083510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.083536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.083559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.083582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.083610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.083635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.085646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.085663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.085677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.085692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.087199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.087214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.087227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.088724] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.088740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.090565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.093499] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.093575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.093591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.093613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.110317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.110344] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.110381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.110490] [drm:drm_mode_addfb2] [FB:75]
>[ 1255.110550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.126997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.127023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.127061] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.145910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.145929] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.145949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.145966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.145983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.145999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.146014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.146030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.146047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.146064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.146080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.146096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.146110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.146124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.146151] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.146172] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.146193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.146209] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.146326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.146338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.146385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.146404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.146425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.146448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.146468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.146489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.146510] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.146530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.146551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.146571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.146591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.146595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.146615] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.146619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.146640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.146660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.146680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.146701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.146721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.146741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.146801] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.146827] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.146854] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.146882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.146912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.147006] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.147031] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.147055] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.147097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.147123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.147147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.147171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.147195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.147220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.147247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.147273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.147298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.147321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.147345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.147372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.147397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.149403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.149419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.149433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.149447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.150957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.150972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.150985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.152482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.152498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.154307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.157243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.157317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.157334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.157356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.174071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.174096] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.174132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.174244] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.174303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.190782] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.190806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.190852] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.209672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.209691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.209712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.209729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.209747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.209800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.209825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.209853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.209883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.209910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.209936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.209963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.209986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.210009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.210052] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.210088] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.210120] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.210146] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.210258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.210268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.210321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.210338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.210355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.210373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.210387] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.210402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.210418] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.210433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.210447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.210460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.210472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.210476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.210488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.210491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.210504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.210517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.210530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.210546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.210564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.210582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.210599] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.210617] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.210634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.210652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.210671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.210708] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.210722] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.210736] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.210809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.210831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.210853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.210874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.210894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.210915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.210939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.210961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.210985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.211004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.211025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.211049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.211070] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.213066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.213082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.213096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.213111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.214615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.214630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.214647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.216145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.216163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.217972] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.220792] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.220830] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.220847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.220869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.237562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.237588] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.237624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.237733] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.237866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.254263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.254287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.254321] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.272271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.272289] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.272310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.272327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.272344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.272360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.272374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.272390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.272408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.272425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.272441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.272456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.272471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.272485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.272512] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.272533] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.272554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.272569] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.272671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.272682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.272735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.272759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.272817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.272847] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.272874] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.272902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.272931] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.272957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.272984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.273008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.273031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.273039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.273061] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.273067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.273090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.273114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.273136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.273159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.273185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.273208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.273231] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.273255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.273277] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.273303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.273330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.273390] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.273415] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.273440] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.273481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.273506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.273530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.273554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.273577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.273599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.273626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.273652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.273684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.273705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.273726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.273751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.273794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.275791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.275809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.275827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.275845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.277351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.277368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.277382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.278878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.278895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.280701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.283634] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.283711] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.283730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.283794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.300452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.300479] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.300516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.300638] [drm:drm_mode_addfb2] [FB:75]
>[ 1255.300712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.317152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.317178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.317215] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.336071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.336090] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.336110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.336127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.336145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.336159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.336174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.336190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.336208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.336224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.336239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.336255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.336269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.336283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.336310] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.336331] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.336352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.336368] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.336489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.336499] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.336546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.336565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.336585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.336606] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.336623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.336641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.336658] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.336675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.336692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.336707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.336722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.336726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.336741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.336781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.336806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.336832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.336858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.336881] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.336909] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.336933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.336958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.336982] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.337038] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.337066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.337094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.337167] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.337191] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.337215] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.337257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.337281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.337305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.337329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.337352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.337377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.337404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.337429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.337456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.337479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.337503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.337530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.337555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.339557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.339574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.339589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.339604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.341111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.341126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.341140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.342632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.342647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.344454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.347378] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.347411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.347428] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.347449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.364148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.364174] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.364209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.364308] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.364377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.380836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.380862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.380900] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.399764] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.399800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.399821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.399838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.399856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.399872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.399887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.399906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.399928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.399949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.399970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.399990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.400009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.400028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.400056] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.400079] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.400104] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.400120] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.400243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.400253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.400300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.400329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.400348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.400371] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.400390] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.400409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.400428] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.400447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.400467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.400486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.400504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.400508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.400527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.400530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.400549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.400568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.400587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.400606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.400625] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.400644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.400663] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.400682] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.400701] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.400721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.400742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.400840] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.400865] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.400888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.400929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.400956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.400980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.401004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.401027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.401052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.401078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.401104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.401129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.401477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.401500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.401526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.401549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.403547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.403565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.403580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.403595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.405103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.405118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.405132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.406625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.406641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.408448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.411383] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.411465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.411480] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.411501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.428199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.428226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.428263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.428372] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.428441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.444880] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.444906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.444944] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.463800] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.463819] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.463839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.463856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.463874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.463893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.463913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.463933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.463954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.463976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.463996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.464016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.464035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.464054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.464082] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.464105] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.464130] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.464147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.464259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.464269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.464317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.464336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.464356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.464378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.464394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.464412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.464431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.464448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.464465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.464481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.464496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.464500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.464515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.464518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.464534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.464558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.464574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.464589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.464607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.464626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.464647] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.464667] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.464687] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.464709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.464731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.464829] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.464855] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.464880] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.464923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.464951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.464977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.465003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.465028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.465055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.465083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.465110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.465137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.465161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.465185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.465212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.465238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.467239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.467255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.467270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.467284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.468823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.468838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.468852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.470348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.470364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.472174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.475139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.475182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.475200] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.475222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.491954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.491979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.492014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.492125] [drm:drm_mode_addfb2] [FB:75]
>[ 1255.492183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.508623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.508649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.508696] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.527468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.527487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.527507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.527525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.527543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.527558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.527577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.527597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.527619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.527639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.527660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.527680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.527699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.527718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.527746] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.527812] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.527849] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.527876] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.527992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.528006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.528069] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.528091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.528116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.528142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.528163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.528186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.528208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.528230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.528250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.528271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.528290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.528296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.528315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.528320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.528341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.528361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.528381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.528400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.528422] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.528442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.528463] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.528482] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.528502] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.528523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.528547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.528609] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.528631] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.528652] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.528688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.528710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.528730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.528750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.528771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.528812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.528838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.528863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.528887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.528907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.528928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.528954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.528975] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.530968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.530984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.530998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.531012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.532518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.532533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.532547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.534044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.534060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.535866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.538799] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.538874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.538891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.538913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.555618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.555644] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.555678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.555838] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.555935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.572320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.572344] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.572381] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.591248] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.591267] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.591288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.591305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.591323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.591338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.591353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.591369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.591387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.591404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.591420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.591436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.591450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.591464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.591491] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.591512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.591533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.591548] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.591670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.591680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.591728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.591747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.591767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.591836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.591861] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.591889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.591914] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.591939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.591963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.591986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.592008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.592015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.592039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.592045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.592070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.592092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.592116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.592137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.592163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.592184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.592207] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.592227] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.592249] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.592276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.592311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.592381] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.592403] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.592425] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.592464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.592488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.592509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.592530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.592551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.592574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.592599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.592623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.592647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.592668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.592689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.592715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.592737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.594758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.594782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.594797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.594812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.596327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.596345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.596362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.597864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.597881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.599684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.602603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.602640] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.602657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.602679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.619385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.619410] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.619445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.619553] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.619618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.636086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.636110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.636147] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.654987] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.655006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.655026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.655043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.655061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.655076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.655091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.655107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.655125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.655144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.655164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.655185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.655205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.655223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.655252] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.655275] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.655300] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.655316] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.655439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.655449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.655496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.655516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.655536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.655559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.655580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.655600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.655621] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.655641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.655662] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.655682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.655702] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.655706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.655726] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.655730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.655751] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.655771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.655836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.655861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.655887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.655911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.655933] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.655956] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.655977] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.656003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.656029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.656134] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.656159] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.656182] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.656225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.656251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.656276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.656300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.656324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.656349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.656372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.656390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.656406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.656421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.656439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.656461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.656481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.658466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.658485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.658502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.658521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.660040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.660058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.660072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.661567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.661583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.663390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.666312] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.666346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.666363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.666384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.683091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.683117] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.683155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.683277] [drm:drm_mode_addfb2] [FB:75]
>[ 1255.683345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.699762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.699808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.699843] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.718697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.718716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.718736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.718753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.718771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.718829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.718852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.718878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.718908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.718934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.718960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.718986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.719009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.719032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.719075] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.719110] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.719141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.719167] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.719294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.719306] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.719348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.719365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.719382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.719400] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.719415] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.719430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.719446] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.719460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.719474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.719487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.719500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.719504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.719516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.719520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.719533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.719546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.719559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.719571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.719586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.719599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.719612] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.719625] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.719637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.719652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.719670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.719706] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.719720] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.719734] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.719762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.719780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.719834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.719859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.719882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.719904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.719930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.719955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.719980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.720000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.720023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.720047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.720070] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.722070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.722087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.722103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.722121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.723630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.723648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.723665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.725165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.725183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.727008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.729959] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.730018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.730035] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.730057] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.746754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.746779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.746869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.746985] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.747053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.763440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.763464] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.763500] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.781535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.781555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.781575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.781592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.781610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.781624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.781639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.781655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.781673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.781689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.781705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.781720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.781734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.781748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.781776] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.781848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.781882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.781908] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.782041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.782059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.782135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.782160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.782187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.782216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.782239] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.782265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.782289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.782314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.782337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.782360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.782381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.782387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.782409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.782415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.782438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.782466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.782487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.782506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.782528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.782547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.782567] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.782586] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.782606] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.782628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.782652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.782718] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.782739] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.782761] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.782828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.782851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.782873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.782894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.782916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.782937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.782962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.782986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.783011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.783031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.783052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.783078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.783099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.785097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.785113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.785128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.785142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.786645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.786660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.786674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.788167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.788182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.789984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.792885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.792941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.792957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.792979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.809683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.809709] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.809744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.809913] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.809977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.826364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.826388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.826424] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.845251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.845270] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.845291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.845307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.845325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.845340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.845355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.845371] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.845389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.845406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.845422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.845438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.845452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.845466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.845493] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.845514] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.845536] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.845552] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.845646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.845657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.845709] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.845729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.845749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.845769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.845787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.845838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.845862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.845886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.845909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.845931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.845952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.845959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.845980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.845986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.846008] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.846029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.846051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.846072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.846096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.846117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.846139] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.846160] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.846183] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.846209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.846236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.846284] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.846300] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.846315] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.846347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.846367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.846386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.846406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.846426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.846446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.846467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.846488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.846509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.846529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.846548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.846568] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.846588] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.848578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.848596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.848610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.848625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.850133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.850149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.850163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.851655] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.851673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.853481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.856403] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.856438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.856454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.856476] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.873171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.873194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.873227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.873331] [drm:drm_mode_addfb2] [FB:75]
>[ 1255.873392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.889871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.889893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.889927] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.908760] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.908779] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.908847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.908876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.908905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.908930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.908954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.908979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.909008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.909035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.909060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.909086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.909109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.909133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.909183] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.909216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.909247] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.909272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.909384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.909395] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.909443] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.909461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.909479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.909498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.909514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.909530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.909555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.909571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.909586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.909601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.909614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.909618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.909631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.909635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.909649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.909662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.909676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.909689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.909705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.909718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.909732] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.909745] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.909758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.909774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.909828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.909897] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.909918] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.909940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.909981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.910006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.910029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.910051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.910072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.910095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.910117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.910133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.910148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.910171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.910187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.910207] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.910225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.912206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.912222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.912236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.912251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.913757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.913774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.913791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.915320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.915338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.917153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.920085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.920162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.920178] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.920200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.936905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.936931] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.936965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.937076] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.937141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.953608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1255.953634] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.953671] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1255.971553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1255.971572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.971592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.971609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.971626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.971645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.971665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.971684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.971706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.971727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.971747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.971768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.971787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.971849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.971898] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.971933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.971967] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.971993] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.972123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.972140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.972215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.972240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.972268] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.972298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.972321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.972347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.972371] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.972396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.972418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.972441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.972462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.972468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.972489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.972495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.972518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.972539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.972561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.972581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.972606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.972627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.972656] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.972675] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.972695] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.972716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.972740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.972831] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.972855] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.972877] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.972916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.972939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.972960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.972982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.973003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.973025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.973050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.973075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.973098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.973118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.973138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.973164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.973185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.975181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.975198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.975212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.975227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.976742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.976757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.976771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.978296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.978312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.980114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.983048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.983124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.983143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.983169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.999865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.999891] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.999925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.000033] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.000100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.016545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.016570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.016606] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.034560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.034578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.034598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.034615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.034633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.034648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.034662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.034678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.034696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.034713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.034728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.034744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.034757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.034771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.034844] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.034879] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.034912] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.034938] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.035065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.035078] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.035141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.035165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.035190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.035217] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.035239] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.035263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.035287] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.035310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.035333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.035355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.035376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.035382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.035403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.035408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.035430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.035452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.035473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.035494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.035518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.035539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.035560] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.035582] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.035601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.035624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.035648] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.035712] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.035734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.035756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.035793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.035834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.035858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.035879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.035902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.035925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.035951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.035976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.036000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.036022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.036045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.036071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.036094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.038085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.038101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.038115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.038129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.039632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.039647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.039661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.041156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.041172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.042976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.045910] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.045983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.046000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.046022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.062726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.062752] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.062787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.062964] [drm:drm_mode_addfb2] [FB:75]
>[ 1256.063031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.079407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.079431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.079468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.098314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.098333] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.098353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.098370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.098387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.098402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.098421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.098441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.098463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.098484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.098504] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.098524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.098543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.098562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.098590] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.098613] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.098637] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.098654] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.098759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.098770] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.098866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.098892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.098921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.098951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.098974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.099002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.099027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.099052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.099075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.099097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.099120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.099127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.099148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.099155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.099179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.099200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.099222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.099243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.099268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.099289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.099312] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.099332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.099355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.099385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.099409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.099465] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.099487] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.099508] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.099546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.099567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.099587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.099608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.099627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.099648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.099672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.099695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.099718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.099737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.099757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.099779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.099802] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.101846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.101863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.101877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.101892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.103398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.103415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.103432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.104930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.104948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.106755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.109690] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.109765] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.109782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.109846] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.126507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.126533] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.126568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.126672] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.126730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.143209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.143233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.143270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.162126] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.162146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.162166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.162185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.162207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.162227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.162247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.162266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.162288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.162309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.162329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.162349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.162368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.162387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.162415] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.162438] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.162463] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.162479] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.162597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.162608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.162655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.162673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.162699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.162717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.162731] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.162747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.162762] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.162777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.162791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.162844] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.162865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.162872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.162893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.162899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.162921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.162941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.162963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.162982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.163006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.163026] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.163047] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.163067] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.163089] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.163112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.163137] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.163193] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.163215] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.163237] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.163274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.163296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.163316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.163337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.163357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.163378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.163402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.163425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.163449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.163468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.163488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.163511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.163533] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.165544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.165569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.165591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.165613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.167126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.167142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.167158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.168653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.168669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.170475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.173416] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.173485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.173502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.173524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.190225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.190251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.190286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.190386] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.190447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.206905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.206929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.206965] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.225409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.225428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.225448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.225466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.225484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.225499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.225514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.225530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.225548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.225568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.225589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.225610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.225629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.225648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.225676] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.225699] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.225723] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.225740] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.225882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.225898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.225974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.226002] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.226030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.226060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.226092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.226117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.226141] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.226164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.226187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.226210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.226231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.226237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.226258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.226263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.226285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.226306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.226327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.226348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.226373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.226394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.226414] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.226435] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.226457] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.226481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.226506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.226574] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.226596] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.226618] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.226656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.226679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.226702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.226722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.226744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.226767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.226792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.226836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.226858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.226881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.226903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.226929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.226952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.228949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.228966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.228982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.229000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.230504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.230520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.230534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.232030] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.232046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.233850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.236771] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.236807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.236859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.236895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.253551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.253577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.253611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.253719] [drm:drm_mode_addfb2] [FB:75]
>[ 1256.253784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.270252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.270277] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.270313] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.288567] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.288586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.288606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.288623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.288645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.288665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.288684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.288703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.288725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.288746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.288766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.288786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.288805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.288867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.288911] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.288945] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.288979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.289004] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.289127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.289142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.289212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.289235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.289262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.289291] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.289314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.289339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.289362] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.289386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.289409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.289431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.289458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.289464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.289483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.289488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.289509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.289528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.289549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.289567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.289590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.289609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.289630] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.289649] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.289669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.289690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.289713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.289776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.289797] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.289837] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.289874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.289895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.289918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.289938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.289960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.289981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.290005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.290030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.290055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.290074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.290095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.290120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.290144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.292133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.292149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.292163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.292178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.293682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.293697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.293711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.295208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.295224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.297031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.299967] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.300041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.300058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.300080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.316782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.316808] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.316967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.317073] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.317137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.333463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.333487] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.333523] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.351576] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.351595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.351615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.351632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.351650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.351665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.351680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.351697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.351715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.351731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.351747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.351763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.351778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.351792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.351862] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.351897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.351930] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.351955] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.352078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.352093] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.352162] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.352186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.352212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.352240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.352263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.352288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.352311] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.352335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.352357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.352380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.352400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.352406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.352428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.352434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.352457] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.352478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.352501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.352521] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.352545] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.352566] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.352588] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.352609] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.352631] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.352654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.352680] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.352748] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.352779] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.352800] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.352856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.352881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.352902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.352924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.352944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.352967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.352992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.353016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.353040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.353060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.353081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.353106] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.353127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.355116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.355134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.355151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.355169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.356675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.356691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.356705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.358201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.358217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.360021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.362964] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.363029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.363044] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.363064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.379774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.379800] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.379875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.380058] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.380123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.396454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.396478] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.396514] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.414579] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.414597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.414618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.414635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.414653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.414668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.414682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.414698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.414716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.414733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.414749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.414765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.414779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.414792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.414820] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.414888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.414922] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.414948] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.415070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.415084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.415154] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.415184] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.415208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.415234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.415255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.415278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.415299] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.415321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.415341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.415362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.415381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.415386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.415406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.415411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.415432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.415451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.415471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.415489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.415512] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.415531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.415552] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.415570] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.415591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.415614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.415638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.415701] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.415722] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.415744] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.415780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.415802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.415822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.415861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.415881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.415904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.415929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.415952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.415976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.415996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.416017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.416043] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.416064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.418055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.418070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.418084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.418098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.419602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.419617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.419633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.421130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.421146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.422951] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.425880] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.425909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.425925] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.425953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.442652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.442678] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.442713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.442849] [drm:drm_mode_addfb2] [FB:75]
>[ 1256.443043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.459333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.459358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.459394] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.478242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.478261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.478283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.478303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.478325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.478344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.478364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.478383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.478404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.478424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.478444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.478464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.478484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.478503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.478531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.478554] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.478579] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.478595] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.478710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.478720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.478767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.478787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.478807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.478873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.478897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.478926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.478954] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.478980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.479006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.479031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.479055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.479063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.479086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.479093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.479117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.479141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.479165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.479189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.479216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.479240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.479265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.479289] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.479312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.479338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.479366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.479429] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.479454] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.479477] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.479519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.479544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.479574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.479597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.479620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.479642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.479668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.479692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.479716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.479738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.479760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.479786] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.479810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.481849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.481866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.481881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.481896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.483404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.483421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.483434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.484930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.484946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.486774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.489669] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.489733] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.489752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.489784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.506475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.506501] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.506536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.506641] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.506698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.523155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.523181] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.523219] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.542070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.542089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.542109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.542126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.542143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.542159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.542173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.542189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.542210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.542231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.542252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.542273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.542292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.542310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.542339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.542361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.542386] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.542402] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.542518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.542528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.542575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.542594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.542614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.542635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.542651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.542672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.542693] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.542713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.542734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.542754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.542774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.542778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.542798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.542802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.542823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.542889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.542915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.542938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.542963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.542986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.543008] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.543030] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.543052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.543077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.543103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.543164] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.543189] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.543211] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.543254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.543279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.543303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.543327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.543350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.543375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.543402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.543428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.543454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.543478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.543499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.543518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.543535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.545530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.545546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.545560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.545575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.547092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.547110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.547125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.548619] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.548635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.550446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.553380] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.553455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.553472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.553494] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.570198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.570224] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.570262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.570387] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.570461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.586890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.586914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.586948] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.605802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.605821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.605886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.605913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.605943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.605967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.605992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.606018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.606047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.606074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.606100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.606126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.606149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.606172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.606216] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.606250] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.606282] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.606315] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.606441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.606450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.606494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.606512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.606530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.606550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.606565] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.606582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.606599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.606614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.606630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.606644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.606659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.606662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.606680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.606683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.606702] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.606721] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.606740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.606758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.606777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.606795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.606814] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.606833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.606888] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.606913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.606938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.607006] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.607029] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.607049] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.607090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.607113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.607136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.607158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.607180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.607202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.607227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.607252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.607276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.607298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.607316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.607335] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.607353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.609342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.609359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.609377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.609395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.610916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.610934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.610951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.612446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.612463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.614268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.617225] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.617277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.617294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.617316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.634019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.634045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.634079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.634199] [drm:drm_mode_addfb2] [FB:75]
>[ 1256.634273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.650712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.650736] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.650771] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.669634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.669655] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.669677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.669697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.669719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.669739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.669758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.669777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.669799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.669820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.669887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.669919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.669945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.669971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.670016] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.670050] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.670083] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.670109] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.670238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.670255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.670326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.670345] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.670364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.670384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.670400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.670417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.670434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.670450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.670466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.670481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.670495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.670499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.670513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.670516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.670530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.670544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.670559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.670572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.670589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.670603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.670617] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.670630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.670651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.670674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.670697] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.670744] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.670757] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.670770] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.670795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.670809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.670823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.670874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.670895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.670916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.670939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.670962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.670984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.671003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.671023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.671047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.671068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.673073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.673090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.673104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.673121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.674626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.674644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.674662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.676160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.676177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.677985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.680928] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.680994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.681011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.681032] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.697736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.697762] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.697797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.697976] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.698047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.714436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.714460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.714497] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.731598] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.731617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.731637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.731654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.731671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.731687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.731702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.731718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.731737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.731753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.731769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.731785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.731800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.731814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.731884] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.731920] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.731954] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.731981] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.732111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.732127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.732196] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.732219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.732244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.732271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.732291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.732314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.732337] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.732359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.732379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.732401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.732420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.732426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.732446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.732451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.732473] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.732492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.732513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.732532] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.732555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.732574] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.732594] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.732613] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.732633] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.732655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.732679] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.732734] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.732756] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.732778] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.732815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.732838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.732881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.732902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.732924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.732946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.732970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.732995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.733019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.733039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.733061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.733086] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.733108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.735102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.735119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.735133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.735148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.736652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.736669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.736687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.738185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.738202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.740008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.742952] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.743017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.743034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.743056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.759758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.759784] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.759818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.760004] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.760076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.776461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.776485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.776522] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.794600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.794619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.794641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.794661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.794683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.794703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.794722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.794741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.794762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.794782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.794803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.794824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.794842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.794906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.794949] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.794984] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.795018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.795044] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.795173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.795190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.795265] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.795291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.795317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.795346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.795369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.795400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.795422] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.795444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.795465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.795486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.795505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.795511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.795531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.795536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.795557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.795576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.795597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.795616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.795639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.795657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.795677] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.795696] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.795716] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.795737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.795763] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.795818] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.795840] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.795882] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.795921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.795942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.795965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.795985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.796007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.796028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.796053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.796077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.796101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.796121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.796142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.796169] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.796191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.798185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.798203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.798217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.798232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.799735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.799750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.799764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.801259] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.801275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.803079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.806022] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.806088] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.806107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.806133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.822829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.822878] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.822913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.823020] [drm:drm_mode_addfb2] [FB:75]
>[ 1256.823077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.839532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.839557] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.839593] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.857608] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.857627] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.857647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.857664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.857686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.857705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.857725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.857744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.857766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.857787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.857807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.857827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.857845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.857919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.857961] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.857996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.858030] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.858056] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.858172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.858189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.858264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.858289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.858316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.858345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.858368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.858394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.858418] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.858442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.858465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.858488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.858509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.858515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.858537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.858542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.858565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.858586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.858608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.858628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.858653] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.858673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.858696] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.858717] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.858738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.858769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.858795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.858851] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.858895] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.858917] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.858955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.858979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.859001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.859023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.859043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.859066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.859091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.859115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.859138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.859157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.859178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.859203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.859224] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.861219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.861236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.861250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.861265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.862795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.862810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.862824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.864319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.864336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.866142] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.869063] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.869099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.869115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.869137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.885843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.885887] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.885925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.886035] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.886101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.902545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.902570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.902606] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.920533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.920552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.920573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.920593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.920615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.920635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.920654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.920673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.920695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.920716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.920737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.920756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.920775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.920794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.920822] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.920845] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.920917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.920945] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.921085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.921101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.921171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.921194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.921219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.921245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.921266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.921290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.921312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.921334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.921355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.921376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.921395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.921401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.921421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.921426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.921448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.921467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.921488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.921506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.921538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.921558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.921579] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.921597] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.921617] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.921639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.921663] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.921718] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.921740] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.921762] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.921799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.921821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.921841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.921883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.921904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.921927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.921952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.921976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.922000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.922020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.922041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.922067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.922089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.924095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.924112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.924126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.924141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.925643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.925658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.925677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.927172] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.927188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.928992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.931920] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.931950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.931966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.931987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1256.948691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.948718] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.948755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.948901] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.948998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.965400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1256.965433] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1256.965485] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1256.983614] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1256.983633] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1256.983653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.983670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.983688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.983703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.983718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.983734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1256.983751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.983767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.983783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.983799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.983817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.983836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.983908] [drm:intel_power_well_disable [i915]] disabling display
>[ 1256.983944] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1256.983979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1256.984005] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1256.984129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1256.984146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1256.984220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1256.984248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1256.984291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1256.984319] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1256.984341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1256.984366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1256.984390] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1256.984413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1256.984436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1256.984458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1256.984480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1256.984486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.984507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1256.984512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1256.984534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1256.984555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1256.984576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1256.984595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1256.984619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1256.984641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1256.984662] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1256.984683] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1256.984702] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1256.984725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1256.984750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1256.984805] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1256.984828] [drm:intel_power_well_enable [i915]] enabling display
>[ 1256.984850] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1256.984910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1256.984934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1256.984957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1256.984980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1256.985003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1256.985027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1256.985052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1256.985077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1256.985102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1256.985124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1256.985146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1256.985172] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1256.985196] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1256.987191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1256.987208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1256.987222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.987237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1256.988743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1256.988759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1256.988772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1256.991332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1256.991350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1256.993156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1256.995542] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1256.995608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1256.995625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1256.995647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.012349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.012374] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.012411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.012521] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.012589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.029029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.029054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.029091] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.047087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.047106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.047127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.047144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.047162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.047181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.047201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.047220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.047242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.047263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.047283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.047303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.047322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.047341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.047369] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.047392] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.047416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.047433] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.047562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.047571] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.047616] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.047635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.047653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.047673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.047689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.047706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.047723] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.047739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.047755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.047770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.047784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.047787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.047802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.047805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.047820] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.047834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.047848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.047908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.047932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.047955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.047978] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.048000] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.048023] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.048049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.048075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.048131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.048155] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.048178] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.048216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.048240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.048262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.048285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.048307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.048330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.048355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.048379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.048403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.048424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.048446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.048472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.048496] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.050501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.050518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.050532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.050550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.052061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.052077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.052091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.053583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.053599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.055404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.058338] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.058413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.058433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.058459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.075156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.075181] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.075216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.075323] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.075389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.091826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.091849] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.091935] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.110622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.110641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.110661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.110678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.110696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.110711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.110726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.110742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.110760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.110776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.110792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.110807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.110822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.110836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.110901] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.110940] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.110972] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.110999] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.111125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.111139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.111194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.111211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.111230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.111250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.111266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.111283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.111300] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.111316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.111332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.111347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.111361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.111366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.111379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.111383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.111403] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.111423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.111443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.111462] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.111482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.111501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.111520] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.111540] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.111559] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.111578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.111599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.111646] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.111661] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.111676] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.111707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.111726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.111746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.111766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.111792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.111818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.111838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.111861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.111900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.111920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.111941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.111965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.111987] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.116163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.116182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.116198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.116215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.117722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.117737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.117751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.119247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.119263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.121067] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.124010] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.124075] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.124090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.124110] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.140818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.140844] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.140992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.141095] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.141152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.157499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.157525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.157562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.175622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.175641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.175661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.175678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.175695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.175710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.175725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.175741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.175758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.175775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.175791] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.175806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.175820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.175834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.175862] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.175932] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.175965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.175992] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.176084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.176099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.176160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.176185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.176203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.176221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.176235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.176252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.176267] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.176283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.176297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.176311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.176324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.176328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.176341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.176344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.176358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.176371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.176384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.176397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.176412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.176425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.176438] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.176451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.176468] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.176487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.176507] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.176550] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.176569] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.176582] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.176609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.176625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.176640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.176654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.176667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.176682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.176698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.176712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.176727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.176740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.176753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.176770] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.176785] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.178765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.178782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.178800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.178818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.180326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.180342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.180356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.181875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.181899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.183704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.186626] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.186661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.186678] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.186700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.203405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.203431] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.203466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.203576] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.203652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.220086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.220110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.220146] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.238987] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.239005] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.239026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.239043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.239061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.239076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.239091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.239107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.239125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.239141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.239157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.239172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.239187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.239210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.239240] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.239262] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.239283] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.239299] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.239416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.239434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.239480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.239499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.239519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.239539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.239555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.239573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.239590] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.239610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.239630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.239649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.239669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.239673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.239692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.239696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.239716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.239736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.239756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.239775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.239795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.239814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.239834] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.239853] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.239873] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.239935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.239966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.240038] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.240063] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.240088] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.240405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.240431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.240462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.240485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.240507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.240530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.240555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.240580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.240604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.240625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.240647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.240672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.240695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.242693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.242711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.242726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.242741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.244248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.244264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.244277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.245770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.245786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.247592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.250498] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.250550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.250567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.250588] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.267293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.267319] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.267357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.267465] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.267532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.283973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.283999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.284037] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.302906] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.302925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.302946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.302963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.302981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.302996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.303012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.303030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.303052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.303073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.303094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.303114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.303133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.303152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.303180] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.303203] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.303228] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.303245] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.303365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.303375] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.303422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.303442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.303462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.303483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.303500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.303518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.303537] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.303554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.303570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.303586] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.303601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.303605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.303620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.303624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.303644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.303665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.303685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.303706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.303726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.303747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.303767] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.303787] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.303808] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.303829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.303851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.303940] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.303966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.303991] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.304035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.304063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.304089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.304114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.304139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.304166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.304194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.304222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.304249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.304273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.304298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.304326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.304675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.306676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.306695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.306712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.306731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.308241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.308257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.308272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.309764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.309780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.311586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.314535] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.314595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.314614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.314640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.331335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.331361] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.331396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.331501] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.331567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.348024] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.348047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.348082] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.366491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.366508] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.366526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.366542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.366558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.366572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.366586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.366601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.366617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.366632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.366647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.366662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.366675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.366688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.366712] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.366733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.366752] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.366772] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.366903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.366915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.366974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.366999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.367025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.367053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.367076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.367099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.367115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.367133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.367151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.367169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.367186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.367190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.367207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.367210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.367228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.367246] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.367263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.367280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.367298] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.367315] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.367333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.367350] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.367368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.367386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.367405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.367452] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.367466] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.367480] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.367508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.367526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.367544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.367562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.367579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.367597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.367616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.367635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.367653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.367670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.367685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.367704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.367721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.369696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.369713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.369727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.369742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.371247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.371262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.371276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.372767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.372783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.374588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.377511] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.377545] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.377561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.377583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.394287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.394313] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.394348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.394455] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.394520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.410989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.411013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.411049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.429875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.429913] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.429933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.429950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.429968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.429987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.430007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.430026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.430048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.430069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.430089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.430109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.430128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.430147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.430175] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.430198] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.430223] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.430239] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.430361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.430371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.430419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.430440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.430461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.430485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.430505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.430526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.430546] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.430567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.430587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.430607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.430627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.430631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.430651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.430655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.430676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.430696] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.430716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.430736] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.430757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.430777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.430797] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.430817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.430837] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.430859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.430881] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.430990] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.431016] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.431041] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.431084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.431110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.431133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.431157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.431180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.431205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.431232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.431258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.431283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.431304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.431327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.431352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.431376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.433389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.433406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.433421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.433435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.435051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.435068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.435083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.437658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.437677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.440591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.443526] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.443601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.443618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.443640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.460344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.460370] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.460404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.460516] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.460584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.477022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.477047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.477083] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.495925] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.495945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.495965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.495982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.496000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.496016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.496030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.496046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.496064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.496081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.496097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.496113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.496127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.496141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.496168] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.496190] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.496213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.496230] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.496345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.496356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.496407] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.496427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.496447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.496469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.496485] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.496503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.496522] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.496539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.496559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.496580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.496600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.496604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.496624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.496628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.496648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.496669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.496689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.496710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.496730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.496750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.496770] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.496791] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.496811] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.496832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.496854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.496944] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.496969] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.496994] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.497037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.497064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.497088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.497112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.497135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.497167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.497195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.497222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.497248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.497269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.497292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.497319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.497342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.499677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.499693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.499707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.499722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.502322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.502340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.502355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.503854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.503870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.505706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.508644] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.508715] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.508732] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.508754] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.525465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.525491] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.525525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.525656] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.525713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.542155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.542179] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.542217] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.561050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.561069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.561089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.561106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.561124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.561139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.561154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.561170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.561188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.561214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.561235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.561251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.561265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.561279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.561306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.561328] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.561352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.561369] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.561483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.561493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.561541] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.561560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.561580] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.561609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.561625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.561643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.561660] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.561679] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.561700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.561720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.561739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.561743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.561762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.561766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.561786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.561806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.561826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.561845] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.561865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.561885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.561951] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.561979] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.562005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.562033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.562061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.562119] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.562143] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.562167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.562207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.562232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.562258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.562282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.562305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.562329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.562356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.562381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.562406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.562428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.562451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.562477] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.562502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.564507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.564524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.564538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.564553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.566062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.566077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.566091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.567585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.567603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.569415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.572352] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.572424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.572441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.572463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.589174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.589200] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.589235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.589339] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.589405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.605857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.605882] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.605973] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.624651] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.624670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.624690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.624707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.624725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.624740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.624755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.624771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.624789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.624806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.624821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.624837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.624851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.624865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.624892] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.624963] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.624996] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.625023] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.625145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.625159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.625216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.625234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.625253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.625272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.625288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.625306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.625323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.625340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.625355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.625371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.625389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.625394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.625413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.625417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.625437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.625456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.625476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.625495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.625516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.625535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.625555] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.625574] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.625594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.625614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.625635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.625674] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.625689] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.625704] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.625734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.625754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.625775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.625794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.625814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.625834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.625855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.625877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.625921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.625954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.625975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.626000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.626022] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.628016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.628033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.628047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.628062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.629568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.629584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.629598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.631097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.631113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.632926] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.636377] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.636441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.636457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.636479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.653183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.653209] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.653243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.653351] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.653417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.669863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.669887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.669975] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.688834] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.688853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.688873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.688890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.688951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.688977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.689002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.689028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.689057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.689085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.689104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.689121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.689140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.689159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.689188] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.689211] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.689236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.689253] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.689346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.689355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.689397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.689413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.689430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.689448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.689462] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.689478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.689494] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.689509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.689523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.689537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.689550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.689553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.689566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.689570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.689584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.689601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.689620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.689637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.689656] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.689673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.689691] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.689709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.689727] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.689746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.689765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.689802] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.689817] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.689831] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.689859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.689878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.689901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.689946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.689968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.689991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.690015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.690038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.690061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.690081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.690101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.690125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.690146] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.692141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.692157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.692172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.692188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.693692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.693708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.693722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.695216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.695232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.697037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.699974] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.700047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.700066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.700092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.716784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.716808] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.716842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.717010] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.717090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.733466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.733490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.733525] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.751658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.751677] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.751699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.751719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.751741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.751760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.751780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.751799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.751821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.751842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.751862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.751882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.751901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.751963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.752007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.752036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.752062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.752079] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.752185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.752200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.752266] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.752286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.752307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.752330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.752347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.752367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.752386] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.752406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.752426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.752446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.752464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.752469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.752488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.752492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.752511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.752531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.752551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.752569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.752589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.752608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.752627] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.752647] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.752666] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.752694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.752714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.752757] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.752770] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.752783] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.752810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.752828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.752846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.752864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.752883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.752905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.752951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.752976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.752999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.753019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.753040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.753064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.753085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.756156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.756174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.756190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.756210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.757716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.757732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.757746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.759241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.759257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.761060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.764002] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.764069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.764084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.764105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.780821] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.780848] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.780885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.781066] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.781133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.797493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.797517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.797553] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.816424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.816443] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.816463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.816479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.816497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.816512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.816527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.816543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.816560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.816576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.816596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.816617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.816636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.816655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.816684] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.816706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.816731] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.816748] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.816853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.816864] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.816958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.816984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.817011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.817039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.817062] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.817088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.817112] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.817136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.817160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.817182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.817205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.817212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.817234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.817242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.817271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.817292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.817314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.817335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.817358] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.817379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.817401] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.817422] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.817442] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.817466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.817492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.817535] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.817548] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.817562] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.817588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.817606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.817625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.817644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.817662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.817679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.817699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.817718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.817737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.817755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.817773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.817791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.817810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.819785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.819802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.819816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.819831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.821342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.821358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.821371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.822871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.822887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.824721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.827639] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.827679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.827699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.827725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.844420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.844447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.844481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.844588] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.844646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.861123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.861148] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.861185] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.880027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.880046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.880066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.880083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.880101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.880117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.880132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.880148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.880166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.880185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.880205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.880226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.880245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.880264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.880292] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.880315] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.880340] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.880356] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.880471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.880481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.880528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.880548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.880568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.880589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.880605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.880623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.880641] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.880658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.880674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.880690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.880705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.880709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.880724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.880728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.880743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.880758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.880773] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.880787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.880805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.880820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.880835] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.880849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.880864] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.880882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.880901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.881024] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.881048] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.881072] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.881115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.881141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.881165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.881189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.881212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.881237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.881265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.881291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.881317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.881340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.881363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.881382] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.881398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.883387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.883405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.883419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.883434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.884975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.884991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.885005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.886505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.886523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.888335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.890660] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.890737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.890754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.890776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.907480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.907505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.907540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.907647] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.907711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.924161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.924185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.924221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1257.943069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1257.943088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1257.943108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.943125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.943143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.943158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.943173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.943189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.943207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.943227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.943248] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.943268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.943288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.943307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.943335] [drm:intel_power_well_disable [i915]] disabling display
>[ 1257.943357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1257.943382] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.943399] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1257.943519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1257.943529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1257.943576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1257.943595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1257.943616] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1257.943637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1257.943654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1257.943674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1257.943695] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1257.943716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1257.943737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1257.943757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1257.943777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1257.943781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.943801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1257.943805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1257.943826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1257.943846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1257.943866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1257.943887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1257.943907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1257.943972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1257.943998] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1257.944021] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1257.944044] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1257.944070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.944096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1257.944169] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1257.944227] [drm:intel_power_well_enable [i915]] enabling display
>[ 1257.944243] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1257.944272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1257.944288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1257.944304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1257.944319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1257.944333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1257.944349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1257.944366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1257.944386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1257.944408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.944427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1257.944447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1257.944468] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1257.944487] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1257.946482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1257.946500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1257.946514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.946529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1257.948056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1257.948073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1257.948088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1257.950662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1257.950681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1257.952492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1257.955417] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1257.955449] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1257.955466] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1257.955488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1257.972193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1257.972219] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1257.972253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1257.972360] [drm:drm_mode_addfb2] [FB:75]
>[ 1257.972423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1257.988862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1257.988885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1257.988961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.007815] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.007834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.007854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.007871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.007889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.007904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.007965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.007991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.008021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.008049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.008075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.008102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.008125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.008149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.008190] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.008224] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.008256] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.008282] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.008407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.008417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.008459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.008476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.008493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.008511] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.008525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.008541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.008557] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.008571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.008589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.008606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.008624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.008627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.008645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.008648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.008666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.008684] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.008701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.008718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.008736] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.008753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.008770] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.008788] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.008805] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.008823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.008842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.008885] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.008899] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.008912] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.008986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.009009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.009031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.009083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.009105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.009126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.009152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.009176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.009200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.009221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.009242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.009268] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.009292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.011294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.011311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.011325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.011340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.012870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.012885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.012899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.014424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.014440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.018428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.021366] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.021438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.021455] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.021477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.038180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.038206] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.038241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.038348] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.038413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.054882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.054908] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.054996] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.073679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.073698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.073718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.073735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.073753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.073768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.073783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.073799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.073816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.073833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.073848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.073864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.073878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.073892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.073919] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.073991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.074025] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.074052] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.074176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.074190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.074260] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.074285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.074313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.074342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.074367] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.074393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.074419] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.074444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.074468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.074492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.074515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.074522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.074544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.074550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.074574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.074597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.074621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.074644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.074676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.074697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.074719] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.074738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.074759] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.074783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.074808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.074872] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.074895] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.074918] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.074980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.075005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.075028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.075050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.075073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.075096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.075122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.075146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.075171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.075193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.075215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.075241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.075264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.077253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.077269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.077283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.077298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.078800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.078815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.078829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.080325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.080341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.082151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.085092] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.085161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.085178] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.085200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.101901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.101927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.102017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.102142] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.102207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.118583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.118608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.118643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.137494] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.137513] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.137534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.137550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.137568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.137583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.137597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.137616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.137638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.137659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.137679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.137699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.137718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.137737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.137765] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.137788] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.137813] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.137830] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.137972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.137989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.138061] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.138085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.138111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.138138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.138160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.138184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.138207] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.138230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.138252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.138273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.138293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.138299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.138319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.138325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.138347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.138367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.138388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.138408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.138431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.138451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.138472] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.138492] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.138513] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.138535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.138560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.138617] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.138639] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.138661] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.138699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.138720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.138743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.138763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.138784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.138805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.138829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.138853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.138876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.138896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.138925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.138968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.138989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.140986] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.141002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.141016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.141034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.144696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.144715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.144733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.146233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.146249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.148056] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.150989] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.151064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.151081] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.151110] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.167837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.167865] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.167911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.168095] [drm:drm_mode_addfb2] [FB:75]
>[ 1258.168153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.184505] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.184531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.184570] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.203424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.203443] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.203464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.203488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.203512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.203531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.203551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.203570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.203592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.203613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.203633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.203653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.203672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.203692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.203720] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.203743] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.203768] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.203784] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.203881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.203892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.203989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.204015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.204045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.204076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.204099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.204127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.204152] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.204178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.204201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.204225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.204247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.204253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.204274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.204288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.204310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.204330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.204350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.204369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.204391] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.204410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.204431] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.204449] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.204469] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.204491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.204515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.204570] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.204592] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.204613] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.204650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.204672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.204692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.204713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.204732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.204754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.204778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.204801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.204824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.204843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.204863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.204888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.204909] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.206923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.206953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.206967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.206982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.208493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.208509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.208523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.212201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.212219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.214026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.216962] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.217036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.217052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.217074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.233777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.233803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.233838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.233991] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.234078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.250479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.250504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.250548] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.269414] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.269433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.269453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.269470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.269488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.269503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.269518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.269534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.269552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.269568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.269584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.269600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.269614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.269627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.269654] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.269676] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.269697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.269713] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.269833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.269843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.269891] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.269910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.269931] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.269999] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.270025] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.270054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.270081] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.270107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.270133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.270158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.270182] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.270190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.270212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.270219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.270243] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.270267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.270290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.270315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.270341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.270365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.270389] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.270421] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.270445] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.270471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.270498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.270564] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.270588] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.270612] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.270652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.270677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.270700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.270723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.270746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.270768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.270794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.270819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.270844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.270867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.270889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.270916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.270957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.272962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.272978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.272993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.273008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.274514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.274529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.274546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.276051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.276068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.277875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.280830] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.280885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.280901] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.280923] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.297634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.297660] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.297697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.297808] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.297876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.314340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.314363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.314408] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.333236] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.333255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.333275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.333292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.333310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.333325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.333340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.333357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.333374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.333391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.333407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.333422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.333436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.333450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.333477] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.333499] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.333519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.333535] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.333653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.333663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.333711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.333730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.333750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.333771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.333788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.333806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.333824] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.333841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.333857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.333873] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.333888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.333892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.333907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.333910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.333930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.334000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.334026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.334051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.334078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.334103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.334128] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.334151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.334176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.334203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.334231] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.334290] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.334315] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.334339] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.334381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.334406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.334431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.334455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.334479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.334503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.334530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.334556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.334582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.334605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.334626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.334652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.334677] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.336690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.336709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.336726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.336744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.338255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.338272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.338286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.339779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.339795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.341602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.344537] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.344611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.344628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.344650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.361354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.361380] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.361415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.361524] [drm:drm_mode_addfb2] [FB:75]
>[ 1258.361589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.378033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.378058] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.378102] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.396710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.396731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.396753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.396773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.396795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.396814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.396833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.396852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.396874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.396895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.396915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.396934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.396996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.397020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.397063] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.397100] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.397135] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.397161] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.397255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.397265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.397309] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.397327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.397345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.397365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.397382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.397399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.397417] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.397432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.397452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.397471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.397491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.397496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.397515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.397519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.397538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.397558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.397577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.397596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.397616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.397635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.397654] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.397674] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.397693] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.397713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.397735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.397774] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.397789] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.397805] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.397835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.397855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.397876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.397911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.397934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.397988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.398013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.398036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.398059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.398079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.398099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.398123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.398145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.401235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.401254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.401272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.401293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.403909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.403927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.403980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.405480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.405496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.407302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.410252] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.410309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.410325] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.410346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.427052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.427078] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.427112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.427219] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.427285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.443755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.443779] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.443823] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.462665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.462684] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.462704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.462721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.462739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.462754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.462769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.462785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.462803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.462820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.462836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.462851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.462865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.462879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.462906] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.462928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.462991] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.463019] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.463164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.463180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.463255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.463282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.463311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.463348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.463371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.463395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.463419] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.463442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.463465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.463487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.463508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.463514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.463535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.463540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.463562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.463584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.463606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.463627] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.463651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.463672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.463693] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.463713] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.463733] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.463757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.463782] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.463837] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.463859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.463882] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.463920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.463942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.463984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.464007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.464028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.464052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.464077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.464102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.464126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.464148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.464169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.464196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.464220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.466215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.466232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.466248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.466266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.467772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.467789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.467806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.469303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.469320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.471124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.474069] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.474133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.474150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.474172] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.490874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.490900] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.490935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.491179] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.491245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.507556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.507582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.507628] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.526468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.526489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.526511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.526531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.526553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.526572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.526592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.526611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.526632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.526653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.526673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.526694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.526713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.526732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.526759] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.526782] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.526807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.526823] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.526920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.526932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.527035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.527063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.527091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.527121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.527146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.527173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.527199] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.527225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.527250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.527274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.527297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.527303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.527325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.527331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.527355] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.527379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.527402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.527425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.527451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.527474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.527497] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.527520] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.527543] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.527569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.527596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.527668] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.527692] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.527717] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.527758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.527783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.527814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.527836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.527858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.527881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.527907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.527931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.527972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.527993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.528015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.528041] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.528065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.530060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.530077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.530095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.530113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.531620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.531637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.531651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.533149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.533165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.534977] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.537902] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.537935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.537983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.538021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.554707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.554733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.554768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.554876] [drm:drm_mode_addfb2] [FB:75]
>[ 1258.554934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.571376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.571401] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.571439] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.589710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.589729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.589749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.589766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.589783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.589799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.589814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.589832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.589854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.589875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.589896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.589917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.589936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.589955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.590033] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.590069] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.590104] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.590130] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.590248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.590261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.590325] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.590349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.590375] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.590403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.590426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.590450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.590474] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.590497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.590520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.590542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.590563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.590569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.590590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.590596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.590618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.590639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.590661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.590682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.590706] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.590727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.590747] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.590768] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.590789] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.590813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.590838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.590900] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.590922] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.590945] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.591002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.591025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.591049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.591072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.591095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.591119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.591145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.591169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.591194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.591216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.591238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.591264] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.591288] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.595478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.595497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.595513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.595529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.597143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.597160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.597175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.599748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.599768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.601580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.604515] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.604589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.604606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.604628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.621332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.621358] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.621393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.621500] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.621564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.638011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.638036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.638079] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.656932] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.656951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.657017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.657044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.657073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.657098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.657118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.657135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.657155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.657171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.657188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.657204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.657227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.657247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.657275] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.657297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.657318] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.657334] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.657417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.657427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.657471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.657495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.657511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.657529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.657543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.657562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.657579] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.657598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.657616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.657634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.657652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.657656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.657673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.657677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.657696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.657714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.657732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.657750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.657768] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.657785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.657804] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.657822] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.657840] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.657859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.657879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.657914] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.657929] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.657943] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.658008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.658032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.658054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.658075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.658095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.658117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.658141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.658164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.658186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.658206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.658225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.658249] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.658270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.660264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.660281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.660295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.660310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.663954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.663982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.664001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.665566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.665583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.667387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.670322] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.670395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.670412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.670433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.687139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.687165] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.687200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.687305] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.687370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.703818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.703843] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.703889] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.722675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.722694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.722714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.722731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.722749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.722764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.722778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.722795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.722812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.722828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.722844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.722860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.722874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.722888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.722914] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.722936] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.722957] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.723015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.723138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.723153] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.723221] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.723245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.723272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.723301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.723323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.723349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.723372] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.723396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.723419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.723441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.723462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.723468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.723489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.723494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.723517] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.723538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.723560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.723580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.723605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.723626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.723649] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.723669] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.723691] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.723714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.723740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.723808] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.723832] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.723855] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.723895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.723925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.723945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.723983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.724005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.724027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.724052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.724075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.724100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.724120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.724141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.724165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.724188] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.727252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.727268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.727282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.727296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.728799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.728815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.728829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.730326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.730344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.732151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.735096] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.735161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.735177] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.735200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.751901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.751927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.751963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.752183] [drm:drm_mode_addfb2] [FB:75]
>[ 1258.752247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.768602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.768628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.768675] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.787538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.787557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.787578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.787594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.787612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.787627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.787642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.787658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.787676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.787692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.787708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.787724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.787738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.787752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.787779] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.787800] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.787821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.787837] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.787941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.787990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.788068] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.788087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.788106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.788127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.788142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.788160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.788177] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.788194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.788210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.788226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.788240] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.788245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.788259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.788263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.788283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.788302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.788323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.788342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.788362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.788382] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.788401] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.788420] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.788448] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.788467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.788486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.788532] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.788547] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.788561] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.788590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.788608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.788626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.788644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.788661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.788679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.788698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.788717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.788737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.788754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.788772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.788791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.788808] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.790790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.790808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.790826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.790844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.792356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.792372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.792387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.793920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.793938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.795780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.798716] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.798789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.798808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.798834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.815531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.815557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.815591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.815698] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.815764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.832234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.832261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.832310] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.851171] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.851191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.851211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.851228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.851245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.851261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.851275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.851292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.851309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.851326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.851342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.851357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.851372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.851386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.851415] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.851437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.851459] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.851475] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.851617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.851630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.851681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.851700] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.851720] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.851742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.851759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.851777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.851795] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.851812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.851829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.851845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.851860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.851864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.851883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.851887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.851908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.851929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.851957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.852046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.852072] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.852099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.852122] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.852147] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.852169] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.852196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.852225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.852298] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.852321] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.852346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.852388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.852411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.852434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.852456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.852479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.852503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.852529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.852554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.852579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.852599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.852621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.852646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.852670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.855761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.855779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.855794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.855809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.857317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.857333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.857347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.858838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.858856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.860662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.863596] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.863672] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.863689] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.863711] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.880414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.880440] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.880475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.880588] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.880648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.897094] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.897119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.897165] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.916027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.916046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.916066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.916083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.916101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.916117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.916132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.916148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.916166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.916183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.916199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.916214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.916228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.916242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.916269] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.916291] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.916312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.916328] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.916441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.916451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.916498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.916518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.916537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.916558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.916575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.916593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.916611] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.916628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.916644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.916660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.916675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.916679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.916694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.916697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.916713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.916728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.916747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.916769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.916789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.916809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.916830] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.916850] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.916870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.916892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.916913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.916963] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.917021] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.917048] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.917091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.917119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.917143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.917168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.917190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.917215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.917243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.917270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.917297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.917319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.917342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.917371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.917395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.919734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.919751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.919765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.919780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.921288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.921305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.921323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.923917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.923935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.925741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.928674] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.928751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.928770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.928796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1258.945492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.945518] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.945552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.945658] [drm:drm_mode_addfb2] [FB:75]
>[ 1258.945722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.962174] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1258.962198] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1258.962242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1258.981100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1258.981119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1258.981139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.981156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.981174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.981190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.981209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.981229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1258.981251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.981271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.981292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.981312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.981332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.981351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.981379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1258.981402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1258.981426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1258.981443] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1258.981573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1258.981583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1258.981630] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1258.981650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1258.981670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1258.981691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1258.981708] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1258.981726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1258.981744] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1258.981760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1258.981777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1258.981792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1258.981807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1258.981811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.981826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1258.981830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1258.981850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1258.981871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1258.981891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1258.981912] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1258.981932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1258.981952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1258.981973] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1258.982033] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1258.982058] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1258.982087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1258.982115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1258.982189] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1258.982214] [drm:intel_power_well_enable [i915]] enabling display
>[ 1258.982238] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1258.982280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1258.982589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1258.982611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1258.982632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1258.982652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1258.982675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1258.982699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1258.982723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1258.982746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1258.982766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1258.982786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1258.982809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1258.982831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1258.984829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1258.984847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1258.984862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.984877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1258.986385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1258.986400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1258.986414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1258.987926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1258.987942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1258.989747] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1258.992684] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1258.992758] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1258.992777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1258.992803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.009498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.009524] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.009559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.009666] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.009731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.026179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.026205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.026252] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.045105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.045124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.045144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.045161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.045179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.045195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.045210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.045226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.045244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.045260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.045276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.045296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.045315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.045334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.045363] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.045385] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.045410] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.045427] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.045546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.045556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.045603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.045623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.045643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.045664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.045681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.045699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.045717] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.045734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.045751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.045767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.045782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.045786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.045805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.045809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.045830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.045851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.045871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.045891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.045912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.045931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.045952] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.045972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.046037] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.046065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.046092] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.046164] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.046186] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.046210] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.046253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.046278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.046302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.046320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.046335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.046352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.046369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.046385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.046401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.046416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.046430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.046448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.046464] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.048472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.048490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.048508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.048526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.050125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.050142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.050157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.051652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.051669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.053494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.056429] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.056503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.056520] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.056542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.073246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.073272] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.073307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.073413] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.073478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.089946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.089971] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.090052] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.108743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.108762] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.108782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.108799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.108817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.108833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.108848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.108864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.108885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.108906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.108927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.108948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.108967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.108986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.109062] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.109098] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.109133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.109160] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.109289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.109306] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.109382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.109407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.109434] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.109463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.109486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.109512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.109548] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.109574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.109596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.109619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.109640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.109646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.109668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.109673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.109696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.109717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.109739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.109760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.109785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.109805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.109828] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.109849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.109871] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.109894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.109920] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.110017] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.110041] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.110063] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.110101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.110125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.110146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.110168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.110188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.110211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.110236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.110260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.110284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.110304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.110324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.110348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.110370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.112365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.112383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.112400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.112418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.113933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.113950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.113967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.115493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.115510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.117346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.120295] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.120357] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.120376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.120402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.137097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.137122] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.137157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.137262] [drm:drm_mode_addfb2] [FB:75]
>[ 1259.137327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.153798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.153823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.153862] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.172698] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.172719] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.172741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.172761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.172783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.172802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.172822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.172841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.172862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.172883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.172904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.172923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.172942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.172961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.173036] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.173075] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.173111] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.173137] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.173268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.173282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.173345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.173369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.173395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.173422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.173445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.173469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.173493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.173516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.173539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.173561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.173582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.173588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.173609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.173615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.173637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.173659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.173680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.173701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.173725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.173746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.173766] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.173787] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.173807] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.173831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.173856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.173919] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.173942] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.173964] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.174023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.174049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.174070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.174093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.174115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.174139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.174165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.174189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.174213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.174235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.174257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.174283] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.174306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.177397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.177416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.177432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.177448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.178959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.178975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.179024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.182683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.182702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.184514] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.187451] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.187530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.187545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.187565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.204265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.204290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.204325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.204432] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.204490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.220967] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.220991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.221079] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.239754] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.239774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.239796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.239816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.239838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.239858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.239877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.239896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.239918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.239939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.239959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.239978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.240041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.240066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.240109] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.240145] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.240180] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.240207] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.240321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.240338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.240413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.240438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.240466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.240495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.240518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.240543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.240568] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.240592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.240615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.240645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.240664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.240669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.240689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.240694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.240716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.240736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.240756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.240775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.240798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.240817] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.240838] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.240857] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.240877] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.240898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.240922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.240978] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.241026] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.241049] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.241088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.241112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.241133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.241156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.241177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.241200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.241225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.241250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.241275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.241327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.241346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.241371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.241393] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.243389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.243405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.243420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.243435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.247099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.247118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.247134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.248632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.248649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.250455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.253385] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.253411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.253428] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.253450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.270157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.270182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.270217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.270323] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.270381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.286836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.286861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.286906] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.305725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.305744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.305764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.305781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.305798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.305814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.305829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.305845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.305862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.305879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.305895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.305911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.305925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.305939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.305966] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.305987] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.306056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.306084] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.306376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.306391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.306458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.306483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.306510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.306539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.306562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.306588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.306613] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.306637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.306661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.306684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.306706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.306712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.306734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.306740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.306762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.306785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.306807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.306826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.306851] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.306873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.306893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.306915] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.306935] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.306959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.306986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.307074] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.307099] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.307130] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.307169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.307363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.307380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.307398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.307416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.307433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.307453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.307471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.307490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.307507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.307525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.307543] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.307561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.311742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.311760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.311777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.311794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.313303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.313318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.313332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.314825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.314841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.316646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.319570] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.319603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.319619] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.319641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.336347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.336373] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.336411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.336519] [drm:drm_mode_addfb2] [FB:75]
>[ 1259.336586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.353028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.353052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.353096] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.371958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.371977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.371998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.372058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.372089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.372115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.372141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.372166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.372196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.372223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.372249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.372274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.372297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.372320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.372364] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.372399] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.372430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.372456] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.372560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.372570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.372620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.372637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.372654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.372672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.372686] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.372702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.372718] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.372732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.372746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.372759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.372772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.372776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.372789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.372792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.372805] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.372818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.372831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.372843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.372858] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.372871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.372884] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.372897] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.372909] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.372924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.372940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.372976] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.373035] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.373061] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.373100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.373124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.373147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.373169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.373189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.373213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.373240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.373264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.373289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.373311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.373333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.373360] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.373383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.376476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.376495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.376510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.376526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.378077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.378093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.378108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.379611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.379627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.381443] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.384386] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.384452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.384469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.384491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.401194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.401221] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.401258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.401369] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.401436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.417897] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.417922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.417967] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.436773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.436791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.436812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.436829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.436847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.436862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.436877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.436893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.436911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.436928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.436944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.436960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.436974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.436988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.437060] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.437094] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.437126] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.437152] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.437276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.437291] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.437359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.437382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.437408] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.437437] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.437459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.437484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.437507] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.437531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.437553] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.437576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.437597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.437603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.437624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.437630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.437652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.437673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.437695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.437716] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.437742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.437763] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.437786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.437806] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.437828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.437852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.437877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.437950] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.437972] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.437993] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.438048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.438070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.438093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.438114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.438136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.438157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.438181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.438205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.438230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.438250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.438271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.438296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.438318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.440306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.440322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.440338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.440356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.441862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.441880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.441897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.443395] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.443413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.445220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.448150] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.448176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.448193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.448215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.464930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.464956] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.464990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.465212] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.465277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.481597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.481622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.481668] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.500520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.500539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.500560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.500577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.500594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.500610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.500624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.500641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.500658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.500675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.500695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.500716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.500735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.500754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.500782] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.500805] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.500830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.500846] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.500952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.500963] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.501019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.501076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.501104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.501135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.501161] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.501188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.501215] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.501242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.501267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.501290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.501321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.501327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.501347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.501352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.501374] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.501395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.501416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.501437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.501461] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.501482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.501503] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.501524] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.501545] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.501569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.501594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.501649] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.501671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.501694] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.501731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.501754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.501776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.501798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.501817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.501840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.501864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.501888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.501912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.501933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.501952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.501977] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.502000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.504011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.504038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.504053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.504068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.505574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.505590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.505604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.507106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.507122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.508957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.511891] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.511966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.511983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.512005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.528705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.528729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.528762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.528871] [drm:drm_mode_addfb2] [FB:75]
>[ 1259.528937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.545387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.545410] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.545457] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.564313] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.564332] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.564352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.564370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.564388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.564403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.564418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.564435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.564452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.564469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.564485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.564500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.564515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.564529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.564557] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.564578] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.564599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.564615] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.564723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.564733] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.564779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.564797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.564816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.564836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.564852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.564871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.564890] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.564910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.564929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.564948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.564967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.564971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.564989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.564993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.565013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.565074] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.565098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.565121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.565146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.565169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.565192] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.565213] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.565235] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.565261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.565287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.565358] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.565384] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.565408] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.565452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.565477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.565500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.565524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.565546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.565570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.565596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.565621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.565652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.565673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.565694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.565718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.565740] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.567739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.567756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.567770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.567784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.570366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.570382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.570397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.571894] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.571910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.573719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.576636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.576676] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.576692] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.576713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.593446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.593472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.593506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.593628] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.593694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.610095] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.610121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.610162] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.630073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.630091] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.630110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.630125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.630141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.630159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.630177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.630195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.630215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.630234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.630253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.630271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.630288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.630306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.630333] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.630355] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.630378] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.630393] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.630514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.630525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.630570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.630588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.630606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.630626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.630641] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.630657] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.630674] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.630692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.630712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.630730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.630748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.630752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.630770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.630774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.630793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.630811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.630830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.630848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.630867] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.630886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.630905] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.630923] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.630950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.630971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.630991] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.631094] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.631117] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.631138] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.631181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.631206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.631228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.631251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.631275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.631299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.631326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.631352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.631377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.631400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.631422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.631450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.631467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.633444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.633460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.633474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.633489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.634990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.635006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.635051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.636546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.636561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.638375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.641311] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.641384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.641401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.641423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.658127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.658154] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.658191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.658311] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.658380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.674828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.674852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.674890] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.692758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.692777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.692797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.692814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.692832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.692847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.692863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.692888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.692909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.692925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.692942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.692957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.692971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.692985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.693013] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.693083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.693114] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.693142] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.693248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.693270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.693330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.693347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.693364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.693382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.693397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.693413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.693428] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.693443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.693457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.693471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.693484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.693488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.693500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.693504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.693517] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.693530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.693544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.693556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.693572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.693585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.693598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.693611] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.693624] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.693639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.693656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.693700] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.693713] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.693727] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.693751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.693766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.693780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.693793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.693806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.693820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.693836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.693850] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.693869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.693887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.693904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.693923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.693942] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.695918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.695935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.695949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.695964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.697469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.697484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.697498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.698992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.699009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.700841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.703771] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.703799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.703816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.703838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.720539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.720564] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.720600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.720722] [drm:drm_mode_addfb2] [FB:75]
>[ 1259.720795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.737231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.737255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.737291] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.756107] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.756126] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.756146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.756163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.756181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.756196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.756211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.756228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.756246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.756262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.756278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.756294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.756308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.756322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.756349] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.756371] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.756391] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.756407] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.756527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.756537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.756584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.756604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.756624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.756647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.756668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.756689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.756710] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.756730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.756751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.756771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.756791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.756795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.756815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.756819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.756839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.756860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.756880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.756900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.756921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.756941] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.756961] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.756981] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.757001] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.757023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.757089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.757150] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.757175] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.757200] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.757244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.757270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.757297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.757322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.757346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.757372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.757399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.757425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.757451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.757475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.757498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.757526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.757549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.759562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.759577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.759591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.759606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.761119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.761134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.761148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.762643] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.762658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.764470] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.768482] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.768541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.768558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.768580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.785291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.785316] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.785351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.785460] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.785526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.801979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.802003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.802089] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.820975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.820994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.821014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.821074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.821104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.821128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.821152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.821176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.821206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.821232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.821258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.821283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.821305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.821327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.821370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.821404] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.821435] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.821460] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.821584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.821595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.821642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.821662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.821682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.821703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.821720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.821738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.821756] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.821773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.821790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.821806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.821822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.821826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.821841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.821845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.821865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.821886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.821906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.821926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.821947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.821967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.821987] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.822008] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.822071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.822096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.822121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.822188] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.822212] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.822235] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.822265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.822283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.822301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.822319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.822337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.822355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.822374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.822394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.822413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.822431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.822446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.822466] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.822483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.824456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.824473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.824487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.824502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.826004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.826019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.826065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.827560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.827576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.829388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.832330] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.832398] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.832418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.832444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.849138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.849163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.849198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.849304] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.849371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.865820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.865846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.865884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.883755] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.883774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.883795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.883812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.883833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.883853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.883872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.883892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.883912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.883933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.883954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.883974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.883993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.884012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.884085] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.884121] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.884151] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.884168] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.884274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.884289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.884356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.884382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.884399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.884417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.884432] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.884448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.884464] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.884479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.884493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.884508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.884521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.884525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.884538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.884542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.884555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.884571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.884590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.884607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.884626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.884643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.884662] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.884679] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.884698] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.884717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.884737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.884782] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.884796] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.884810] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.884838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.884856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.884874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.884892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.884910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.884928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.884948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.884967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.884987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.885004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.885025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.885071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.885095] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.887086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.887103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.887117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.887132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.888638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.888654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.888669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.890170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.890186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.892028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.894943] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.894999] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.895015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.895075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.911739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.911763] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.911797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.911905] [drm:drm_mode_addfb2] [FB:75]
>[ 1259.911962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.928432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.928457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.928493] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1259.947275] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1259.947294] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1259.947316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.947336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.947358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.947378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.947397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.947416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.947438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.947459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.947479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.947499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.947518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.947537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.947565] [drm:intel_power_well_disable [i915]] disabling display
>[ 1259.947587] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1259.947612] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.947629] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1259.947750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1259.947759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1259.947802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1259.947821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1259.947841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1259.947862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1259.947880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1259.947900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1259.947918] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1259.947937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1259.947956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1259.947975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1259.947993] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1259.947997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.948015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1259.948018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1259.948077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1259.948100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1259.948125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1259.948149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1259.948175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1259.948198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1259.948221] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1259.948244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1259.948267] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1259.948293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.948319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1259.948387] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1259.948410] [drm:intel_power_well_enable [i915]] enabling display
>[ 1259.948433] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1259.948471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1259.948495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1259.948517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1259.948540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1259.948561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1259.948584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1259.948608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1259.948632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1259.948655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.948674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1259.948695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1259.948721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1259.948744] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1259.950743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1259.950761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1259.950776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.950791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1259.952296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1259.952311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1259.952325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1259.953815] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1259.953831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1259.956702] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1259.959624] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1259.959659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1259.959676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1259.959697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1259.976403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1259.976429] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1259.976463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1259.976571] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.976634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1259.993085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1259.993111] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1259.993149] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.011992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.012011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.012031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.012093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.012122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.012147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.012171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.012197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.012217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.012235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.012250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.012267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.012281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.012296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.012323] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.012345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.012367] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.012382] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.012466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.012476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.012520] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.012536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.012554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.012576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.012596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.012616] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.012636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.012655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.012675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.012694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.012713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.012717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.012736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.012740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.012760] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.012779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.012799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.012819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.012838] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.012857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.012877] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.012895] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.012916] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.012936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.012958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.013006] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.013021] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.013076] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.013117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.013140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.013161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.013182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.013203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.013224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.013248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.013271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.013294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.013314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.013334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.013358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.013379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.015372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.015388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.015402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.015417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.016920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.016935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.016948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.018444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.018460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.020266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.023213] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.023276] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.023293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.023316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.040018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.040087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.040126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.040234] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.040300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.056698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.056722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.056758] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.074803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.074822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.074842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.074860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.074877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.074893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.074908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.074924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.074941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.074958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.074974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.074994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.075014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.075033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.075111] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.075146] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.075170] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.075186] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.075287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.075302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.075369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.075387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.075406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.075433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.075448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.075464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.075481] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.075500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.075518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.075536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.075553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.075558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.075575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.075578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.075596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.075614] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.075631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.075649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.075666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.075683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.075701] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.075718] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.075736] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.075755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.075775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.075820] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.075834] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.075848] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.075876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.075894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.075913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.075945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.075963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.075980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.075997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.076013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.076029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.076075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.076095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.076119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.076141] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.078137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.078153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.078167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.078181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.079684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.079699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.079713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.082275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.082293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.084112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.088127] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.088183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.088199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.088222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.104925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.104951] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.104986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.105161] [drm:drm_mode_addfb2] [FB:75]
>[ 1260.105246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.121606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.121631] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.121666] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.139724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.139743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.139764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.139781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.139798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.139813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.139827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.139843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.139861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.139877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.139893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.139909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.139923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.139937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.139964] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.139985] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.140006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.140022] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.140188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.140203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.140257] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.140274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.140293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.140313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.140329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.140346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.140363] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.140379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.140395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.140410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.140424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.140429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.140447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.140451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.140471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.140491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.140511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.140530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.140551] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.140570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.140590] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.140609] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.140629] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.140649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.140671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.140718] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.140750] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.140775] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.140818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.140850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.140872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.140893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.140913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.140935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.140958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.140981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.141003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.141023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.141043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.141087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.141108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.143111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.143128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.143142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.143157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.144676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.144694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.144709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.148367] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.148385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.150194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.153129] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.153207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.153222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.153243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.169956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.169980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.170014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.170221] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.170286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.186647] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.186676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.186722] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.204802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.204821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.204841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.204858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.204876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.204891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.204906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.204922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.204943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.204964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.204984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.205005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.205024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.205043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.205121] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.205156] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.205180] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.205196] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.205301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.205316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.205388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.205404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.205422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.205440] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.205455] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.205471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.205487] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.205502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.205532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.205547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.205561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.205564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.205577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.205581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.205599] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.205617] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.205635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.205653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.205671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.205688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.205706] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.205724] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.205741] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.205760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.205780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.205823] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.205837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.205852] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.205880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.205899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.205917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.205935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.205953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.205972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.205991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.206010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.206029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.206051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.206096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.206121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.206144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.209232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.209251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.209267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.209284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.210794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.210810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.210824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.212319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.212335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.214140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.216785] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.216846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.216863] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.216886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.233614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.233640] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.233674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.233774] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.233835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.250274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.250296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.250331] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.269186] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.269204] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.269225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.269242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.269260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.269276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.269291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.269307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.269324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.269341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.269356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.269372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.269386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.269400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.269427] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.269448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.269469] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.269485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.269598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.269607] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.269661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.269680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.269700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.269720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.269736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.269754] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.269771] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.269788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.269804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.269823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.269843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.269847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.269866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.269870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.269890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.269910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.269930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.269949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.269969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.269988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.270009] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.270028] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.270048] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.270114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.270144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.270214] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.270238] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.270261] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.270303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.270326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.270350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.270372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.270395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.270417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.270443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.270468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.270493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.270513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.270535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.270561] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.270583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.273677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.273694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.273709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.273731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.275257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.275273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.275287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.276779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.276795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.279705] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.282641] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.282714] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.282731] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.282753] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.299457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.299483] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.299518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.299625] [drm:drm_mode_addfb2] [FB:75]
>[ 1260.299683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.316158] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.316183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.316228] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.335088] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.335107] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.335127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.335143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.335161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.335176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.335195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.335215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.335236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.335258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.335278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.335298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.335317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.335336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.335364] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.335387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.335412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.335429] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.335548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.335558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.335604] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.335624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.335644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.335666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.335682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.335704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.335725] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.335745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.335766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.335786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.335806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.335810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.335830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.335834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.335854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.335875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.335895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.335915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.335935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.335955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.335976] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.335996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.336016] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.336038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.336060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.336145] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.336168] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.336189] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.336233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.336258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.336281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.336304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.336326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.336350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.336377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.336403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.336428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.336449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.336471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.336499] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.336519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.338523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.338541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.338555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.338571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.340096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.340111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.340125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.341627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.341643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.343461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.346424] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.346469] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.346486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.346508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.363212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.363238] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.363273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.363381] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.363445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.379914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.379938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.379983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.398775] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.398794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.398815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.398832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.398849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.398865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.398879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.398896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.398913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.398930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.398947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.398963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.398977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.398991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.399018] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.399040] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.399064] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.399125] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.399271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.399288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.399363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.399390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.399424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.399452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.399475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.399499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.399524] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.399547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.399570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.399592] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.399613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.399619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.399639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.399645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.399667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.399688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.399708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.399729] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.399754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.399776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.399798] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.399819] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.399841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.399865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.399890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.399946] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.399968] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.399990] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.400029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.400051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.400096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.400116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.400137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.400160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.400184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.400208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.400231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.400253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.400274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.400298] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.400321] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.402316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.402333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.402348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.402363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.403867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.403882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.403896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.405393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.405410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.407214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.410156] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.410224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.410241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.410263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.426958] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.426983] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.427016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.427233] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.427298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.443672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.443697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.443744] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.462598] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.462619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.462641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.462661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.462682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.462702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.462722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.462741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.462763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.462783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.462804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.462823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.462843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.462862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.462890] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.462912] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.462937] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.462954] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.463089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.463106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.463182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.463210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.463238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.463267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.463291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.463318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.463345] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.463370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.463395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.463419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.463442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.463448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.463470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.463476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.463500] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.463523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.463546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.463569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.463595] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.463618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.463641] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.463665] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.463688] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.463715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.463743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.463811] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.463834] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.463855] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.463893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.463916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.463938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.463960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.463982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.464002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.464026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.464050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.464093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.464114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.464136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.464162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.464185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.466188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.466205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.466220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.466235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.467739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.467755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.467769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.469264] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.469281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.471099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.474028] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.474055] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.474105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.474202] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.490799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.490825] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.490860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.490967] [drm:drm_mode_addfb2] [FB:75]
>[ 1260.491032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.507499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.507524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.507569] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.526390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.526409] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.526429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.526446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.526464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.526479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.526494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.526510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.526528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.526544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.526560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.526576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.526590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.526604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.526630] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.526652] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.526673] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.526688] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.526808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.526818] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.526865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.526885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.526905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.526926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.526943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.526960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.526979] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.526995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.527012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.527028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.527044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.527048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.527067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.527110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.527136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.527162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.527187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.527211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.527238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.527263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.527287] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.527311] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.527336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.527363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.527391] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.527451] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.527475] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.527500] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.527541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.527565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.527589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.527613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.527636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.527661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.527688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.527714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.527740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.527763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.527787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.527814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.527839] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.529853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.529870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.529887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.529906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.531413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.531431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.531449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.532942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.532959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.534765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.537685] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.537723] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.537739] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.537761] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.554466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.554491] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.554528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.554639] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.554708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.571168] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.571194] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.571239] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.590113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.590132] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.590152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.590169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.590187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.590201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.590216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.590232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.590250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.590266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.590281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.590297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.590311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.590325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.590352] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.590374] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.590395] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.590411] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.590525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.590535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.590583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.590603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.590623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.590647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.590667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.590689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.590709] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.590730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.590750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.590770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.590790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.590794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.590815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.590818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.590839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.590859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.590879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.590899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.590920] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.590940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.590960] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.590981] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.591001] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.591022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.591044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.591148] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.591173] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.591199] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.591244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.591272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.591298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.591324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.591349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.591375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.591403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.591431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.591457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.591481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.591505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.591534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.591559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.593563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.593580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.593594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.593608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.595208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.595223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.595236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.596731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.596746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.598567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.601526] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.601575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.601593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.601617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.618349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.618375] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.618413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.618524] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.618584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.635016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.635040] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.635077] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.653962] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.653983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.654005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.654025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.654047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.654066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.654131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.654162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.654193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.654221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.654248] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.654275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.654298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.654322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.654365] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.654400] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.654432] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.654458] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.654561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.654580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.654625] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.654642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.654660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.654678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.654693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.654708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.654724] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.654741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.654759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.654777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.654794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.654798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.654815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.654818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.654836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.654853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.654871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.654888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.654906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.654922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.654940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.654957] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.654975] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.654993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.655012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.655058] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.655072] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.655120] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.655160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.655183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.655206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.655227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.655250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.655272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.655297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.655322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.655348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.655368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.655390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.655415] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.655438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.657432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.657448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.657462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.657477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.658980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.658996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.659010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.660505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.660521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.662326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.664715] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.664779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.664796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.664818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.681515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.681538] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.681571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.681678] [drm:drm_mode_addfb2] [FB:75]
>[ 1260.681740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.698218] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.698242] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.698280] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.717124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.717143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.717163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.717180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.717197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.717213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.717227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.717243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.717264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.717286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.717306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.717327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.717346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.717365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.717393] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.717416] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.717442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.717458] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.717580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.717590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.717637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.717657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.717678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.717698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.717715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.717733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.717751] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.717768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.717785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.717801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.717816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.717820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.717839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.717843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.717864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.717885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.717905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.717925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.717946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.717966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.717986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.718006] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.718027] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.718048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.718070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.718178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.718203] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.718227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.718271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.718296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.718322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.718345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.718370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.718394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.718420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.718446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.718473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.718494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.718516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.718541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.718565] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.720565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.720582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.720596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.720611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.722225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.722240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.722254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.723746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.723762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.725585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.728179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.728241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.728258] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.728280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.745010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.745035] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.745072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.745239] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.745317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.761679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.761704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.761742] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.780558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.780577] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.780598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.780615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.780632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.780647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.780662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.780678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.780696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.780712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.780728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.780743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.780757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.780771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.780798] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.780820] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.780841] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.780856] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.780978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.780988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.781036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.781055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.781076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.781142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.781166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.781192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.781217] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.781240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.781264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.781286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.781308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.781314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.781336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.781342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.781364] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.781385] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.781407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.781428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.781454] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.781476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.781505] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.781526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.781547] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.781573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.781599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.781673] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.781698] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.781721] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.781763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.781788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.781812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.781836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.781854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.781870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.781888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.781903] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.781920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.781933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.781948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.781965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.781981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.783958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.783974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.783989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.784003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.785506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.785521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.785534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.787027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.787042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.788846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.791760] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.791802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.791821] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.791847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.808536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.808561] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.808595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.808700] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.808765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.825227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.825253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.825299] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.844119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.844138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.844158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.844174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.844192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.844211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.844231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.844251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.844278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.844302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.844319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.844335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.844349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.844363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.844391] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.844413] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.844434] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.844450] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.844570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.844580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.844628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.844648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.844668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.844689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.844706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.844724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.844742] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.844759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.844776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.844796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.844816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.844820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.844840] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.844843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.844864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.844884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.844905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.844925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.844945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.844965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.844986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.845006] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.845026] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.845048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.845069] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.845160] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.845183] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.845204] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.845248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.845273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.845296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.845318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.845340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.845364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.845389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.845415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.845441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.845462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.845484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.845512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.845531] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.847508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.847524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.847538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.847553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.849059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.849073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.849112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.850614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.850630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.852442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.855388] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.855451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.855467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.855489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.872218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.872244] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.872279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.872385] [drm:drm_mode_addfb2] [FB:75]
>[ 1260.872451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.888885] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.888909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.888947] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.907818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.907836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.907857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.907874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.907892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.907907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.907922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.907938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.907956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.907972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.907988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.908003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.908018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.908032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.908058] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.908081] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.908151] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.908176] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.908300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.908315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.908383] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.908406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.908433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.908462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.908484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.908509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.908533] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.908557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.908579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.908602] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.908623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.908629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.908650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.908656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.908679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.908700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.908722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.908742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.908767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.908787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.908810] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.908831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.908853] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.908876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.908902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.908978] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.908999] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.909021] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.909058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.909079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.909118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.909141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.909162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.909184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.909209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.909233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.909257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.909277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.909298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.909324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.909345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.911343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.911361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.911379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.911397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.912902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.912919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.912933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.914426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.914442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.916239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.918627] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.918692] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.918709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.918731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.935423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.935447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.935480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.935584] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.935639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.952122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1260.952147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1260.952193] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1260.971021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1260.971040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1260.971060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.971077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.971095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.971152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.971176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.971204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.971234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.971262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.971289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.971315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.971338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.971361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.971404] [drm:intel_power_well_disable [i915]] disabling display
>[ 1260.971439] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1260.971471] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.971497] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1260.971601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1260.971612] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1260.971663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1260.971681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1260.971700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1260.971720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1260.971736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1260.971753] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1260.971770] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1260.971786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1260.971801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1260.971816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1260.971830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1260.971834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.971847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1260.971851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1260.971865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1260.971879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1260.971893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1260.971906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1260.971923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1260.971937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1260.971951] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1260.971965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1260.971978] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1260.971994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1260.972012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1260.972072] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1260.972087] [drm:intel_power_well_enable [i915]] enabling display
>[ 1260.972137] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1260.972178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1260.972202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1260.972231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1260.972251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1260.972271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1260.972292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1260.972316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1260.972338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1260.972360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.972379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1260.972399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1260.972423] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1260.972444] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1260.974446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1260.974463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1260.974480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.974499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1260.976007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1260.976024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1260.976039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1260.977536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1260.977553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1260.979358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1260.982002] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1260.982064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1260.982083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1260.982144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1260.998799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1260.998826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1260.998863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1260.998975] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.999043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.015485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1261.015509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.015554] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1261.034412] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1261.034431] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.034452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.034469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.034486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.034501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.034516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.034532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.034550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.034567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.034583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.034599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.034613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.034627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.034654] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.034683] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.034704] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1261.034720] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.034951] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.034975] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.058044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1261.058181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1261.058274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.058333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.058344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.058391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.058408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.058425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.058443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.058458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.058473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.058489] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.058506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.058524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.058542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.058559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.058562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.058580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.058583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.058601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.058618] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.058636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.058653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.058671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.058688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.058705] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.058723] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.058741] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.058759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.058779] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.061293] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.061308] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.061321] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.061350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.061366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.061381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.061395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.061408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.061422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.061438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.061452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.061466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.061479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.061492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.061510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.061528] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.063505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.063522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.063540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.063558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.065065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.065083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.065100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.066628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.066645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.068468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.071418] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.071477] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.071493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.071514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.088220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.088247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.088285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.104914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.104924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.121678] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.121749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.138282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.138306] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.138346] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.157187] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.157205] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.157226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.157243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.157260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.157280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.157299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.157319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.157341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.157361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.157382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.157402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.157421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.157440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.157468] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.157491] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.157516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.157533] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.157655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.157665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.157713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.157733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.157753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.157777] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.157797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.157818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.157839] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.157859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.157880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.157900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.157920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.157924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.157943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.157947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.157968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.157988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.158009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.158028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.158049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.158069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.158089] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.158109] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.158206] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.158236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.158265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.158336] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.158361] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.158385] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.158426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.158451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.158473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.158496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.158517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.158541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.158567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.158592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.158618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.158639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.158661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.158686] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.158710] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.160718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.160734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.160748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.160763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.162273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.162291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.162315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.163812] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.163829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.165637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.168595] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.168644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.168659] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.168680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.185365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.185390] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.185424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.185532] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.185589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.202074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.202103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.202188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.220873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.220900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.220925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.220942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.220960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.220975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.220990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.221006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.221024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.221040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.221056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.221072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.221087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.221101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.221176] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.221210] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.221242] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.221268] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.221384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.221400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.221476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.221504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.221532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.221563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.221587] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.221621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.221645] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.221669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.221692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.221714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.221736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.221741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.221762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.221768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.221789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.221811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.221833] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.221853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.221875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.221897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.221918] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.221939] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.221959] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.221982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.222007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.222063] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.222086] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.222108] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.222170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.222194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.222218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.222241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.222264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.222288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.222313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.222338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.222362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.222384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.222407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.222433] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.222457] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.224454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.224473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.224490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.224509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.226015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.226031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.226045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.227541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.227557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.229359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.232305] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.232370] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.232389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.232415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.249109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.249153] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.249191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.249299] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.249365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.265791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.265817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.265855] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.284708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.284727] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.284747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.284764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.284782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.284797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.284812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.284828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.284846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.284862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.284878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.284894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.284908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.284922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.284949] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.284972] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.284997] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.285014] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.285143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.285160] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.285237] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.285263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.285292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.285321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.285343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.285369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.285393] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.285417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.285440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.285464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.285485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.285491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.285513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.285518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.285541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.285563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.285585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.285606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.285631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.285652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.285674] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.285695] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.285717] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.285743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.285770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.285843] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.285867] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.285891] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.285931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.285963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.285982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.286003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.286022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.286044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.286068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.286091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.286114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.286156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.286176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.286201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.286223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.288218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.288235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.288250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.288264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.289766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.289782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.289795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.291290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.291306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.293106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.296030] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.296079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.296098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.296156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.312807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.312832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.312866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.312972] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.313034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.329494] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.329519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.329565] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.348400] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.348419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.348440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.348457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.348475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.348491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.348510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.348529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.348551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.348572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.348593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.348613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.348632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.348651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.348679] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.348701] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.348726] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.348743] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.348864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.348874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.348921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.348942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.348964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.348988] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.349008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.349029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.349049] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.349070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.349090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.349111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.349172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.349180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.349206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.349212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.349238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.349262] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.349286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.349309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.349336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.349358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.349382] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.349404] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.349427] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.349455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.349483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.349556] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.349580] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.349604] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.349644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.349668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.349690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.349713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.349734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.349759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.349785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.349810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.349835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.349856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.349878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.349903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.349927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.351931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.351948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.351962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.351977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.353492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.353511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.353528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.355024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.355042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.356848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.359785] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.359857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.359874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.359896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.376601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.376627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.376662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.376769] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.376835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.393275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.393299] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.393344] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.412191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.412210] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.412231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.412248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.412266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.412281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.412300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.412320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.412342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.412363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.412383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.412403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.412422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.412441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.412469] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.412492] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.412516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.412533] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.412659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.412668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.412713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.412731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.412751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.412771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.412787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.412804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.412821] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.412837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.412856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.412875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.412893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.412897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.412916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.412920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.412939] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.412958] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.412977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.412996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.413015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.413034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.413053] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.413072] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.413091] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.413111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.413172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.413241] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.413264] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.413286] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.413326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.413350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.413371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.413393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.413413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.413436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.413461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.413486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.413511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.413531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.413552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.413575] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.413598] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.415605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.415623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.415641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.415659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.417194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.417212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.417226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.418722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.418739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.420549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.423494] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.423558] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.423575] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.423597] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.440307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.440332] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.440366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.440475] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.440540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.456990] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.457014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.457062] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.475896] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.475915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.475935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.475952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.475970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.475986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.476005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.476024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.476046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.476067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.476088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.476107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.476126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.476188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.476232] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.476266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.476301] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.476326] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.476458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.476475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.476550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.476578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.476606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.476636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.476661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.476688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.476715] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.476741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.476766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.476791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.476812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.476826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.476847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.476852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.476874] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.476895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.476916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.476935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.476959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.476980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.477002] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.477021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.477042] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.477065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.477092] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.477184] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.477208] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.477231] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.477269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.477294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.477316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.477339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.477361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.477384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.477409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.477432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.477455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.477476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.477498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.477523] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.477546] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.479544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.479562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.479579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.479598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.481104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.481120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.481168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.482671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.482687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.484492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.487424] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.487500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.487516] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.487541] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.504244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.504270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.504305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.504415] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.504473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.520924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.520948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.520984] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.538878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.538897] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.538918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.538937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.538959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.538979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.538998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.539017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.539039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.539060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.539081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.539100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.539119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.539181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.539226] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.539256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.539280] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.539296] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.539388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.539402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.539462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.539480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.539498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.539518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.539535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.539552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.539569] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.539585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.539601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.539615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.539630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.539634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.539648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.539652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.539666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.539681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.539695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.539709] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.539726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.539740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.539754] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.539769] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.539788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.539809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.539830] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.539871] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.539886] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.539902] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.539932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.539952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.539969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.539989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.540009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.540029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.540050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.540071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.540092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.540111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.540138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.540191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.540221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.542213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.542230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.542244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.542259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.543773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.543790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.543805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.545302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.545320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.547137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.550085] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.550187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.550215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.550300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.566906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.566933] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.566971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.567086] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.567188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.583597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.583623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.583663] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.601890] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.601909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.601929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.601946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.601964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.601979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.601998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.602018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.602040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.602061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.602082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.602102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.602121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.602182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.602227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.602264] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.602299] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.602326] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.602428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.602438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.602483] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.602500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.602519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.602539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.602555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.602572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.602589] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.602605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.602620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.602639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.602658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.602663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.602682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.602693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.602709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.602724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.602738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.602751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.602766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.602780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.602793] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.602806] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.602818] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.602834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.602851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.602886] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.602900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.602913] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.602937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.602952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.602966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.602979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.602991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.603006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.603021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.603035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.603054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.603071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.603089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.603109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.603129] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.605160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.605177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.605192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.605207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.606717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.606733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.606746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.608248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.608264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.610082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.612619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.612686] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.612703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.612724] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.629425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.629450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.629483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.629582] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.629648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.646121] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.646163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.646199] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.664992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.665013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.665035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.665055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.665077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.665096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.665116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.665135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.665206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.665235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.665263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.665291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.665316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.665335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.665364] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.665387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.665409] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.665425] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.665510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.665519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.665562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.665579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.665597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.665617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.665633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.665650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.665667] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.665682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.665698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.665712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.665726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.665730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.665743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.665747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.665762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.665776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.665791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.665804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.665820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.665834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.665849] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.665862] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.665882] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.665902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.665924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.665971] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.665988] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.666003] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.666034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.666054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.666082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.666099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.666115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.666134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.666180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.666204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.666227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.666247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.666267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.666291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.666312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.668305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.668323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.668340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.668358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.669863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.669879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.669894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.671391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.671407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.673212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.676158] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.676221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.676238] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.676260] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.692962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.692989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.693027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.693190] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.693290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.709644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.709669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.709705] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.727892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.727911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.727931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.727948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.727966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.727981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.727997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.728013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.728030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.728047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.728063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.728079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.728093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.728107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.728134] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.728207] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.728239] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.728266] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.728370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.728385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.728441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.728458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.728477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.728497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.728513] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.728533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.728557] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.728572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.728586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.728600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.728612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.728616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.728629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.728632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.728646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.728659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.728672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.728684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.728700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.728713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.728726] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.728739] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.728752] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.728767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.728783] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.728819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.728832] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.728845] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.728870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.728884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.728898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.728911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.728924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.728938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.728953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.728968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.728982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.728995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.729007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.729023] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.729038] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.731015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.731032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.731046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.731061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.732566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.732581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.732595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.734088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.734104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.735910] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.738371] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.738412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.738429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.738451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.755195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.755222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.755260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.755373] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.755452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.771853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.771877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.771915] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.789824] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.789843] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.789863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.789880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.789898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.789913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.789928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.789944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.789962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.789978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.789994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.790010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.790024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.790038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.790066] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.790089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.790114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.790131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.790290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.790304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.790374] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.790396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.790416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.790438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.790457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.790478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.790497] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.790517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.790537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.790557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.790577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.790581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.790600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.790605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.790624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.790644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.790663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.790682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.790702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.790721] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.790747] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.790764] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.790779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.790796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.790813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.790848] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.790861] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.790874] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.790899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.790914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.790929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.790942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.790956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.790970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.790986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.791001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.791015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.791029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.791042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.791058] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.791073] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.793049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.793066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.793079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.793094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.794601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.794616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.794630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.796130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.796159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.797967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.800892] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.800925] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.800948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.800968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.817675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.817701] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.817736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.817844] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.817911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.834365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.834390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.834428] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.853274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.853294] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.853314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.853331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.853348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.853364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.853379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.853395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.853413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.853429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.853445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.853461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.853475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.853489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.853516] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.853537] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.853558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.853574] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.853687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.853697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.853744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.853763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.853783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.853807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.853827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.853848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.853869] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.853889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.853910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.853930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.853950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.853954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.853974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.853978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.853999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.854019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.854039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.854060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.854080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.854100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.854121] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.854141] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.854205] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.854234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.854261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.854332] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.854354] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.854378] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.854421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.854446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.854471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.854490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.854505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.854536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.854560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.854577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.854597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.854617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.854637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.854658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.854678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.856688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.856706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.856723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.856742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.858253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.858270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.858284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.859777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.859793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.861601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.863729] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.863801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.863817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.863839] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.880544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.880570] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.880605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.880714] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.880772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.897245] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.897272] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.897310] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.916154] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.916189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.916209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.916226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.916243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.916258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.916273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.916289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.916307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.916323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.916339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.916355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.916369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.916383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.916409] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.916431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.916452] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.916468] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.916581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.916591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.916639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.916659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.916679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.916703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.916723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.916744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.916764] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.916785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.916806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.916826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.916846] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.916850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.916870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.916874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.916895] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.916915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.916936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.916956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.916977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.916997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.917017] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.917038] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.917058] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.917079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.917101] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.917143] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.917204] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.917226] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.917270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.917295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.917318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.917341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.917363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.917387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.917413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.917438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.917463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.917484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.917506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.917532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.917555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.919566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.919584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.919598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.919613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.921122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.921138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.921186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.922684] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.922700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.924579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.927524] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.927588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.927611] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.927632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1261.944330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.944357] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.944394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.944507] [drm:drm_mode_addfb2] [FB:75]
>[ 1261.944574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.961012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1261.961036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1261.961073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1261.979922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1261.979941] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1261.979961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.979978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.979996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.980011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.980025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.980041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1261.980059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.980075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.980091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.980107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.980121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.980135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.980207] [drm:intel_power_well_disable [i915]] disabling display
>[ 1261.980245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1261.980278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1261.980305] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1261.980431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1261.980448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1261.980524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1261.980549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1261.980577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1261.980613] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1261.980634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1261.980658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1261.980680] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1261.980703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1261.980724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1261.980745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1261.980764] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1261.980770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.980790] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1261.980795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1261.980816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1261.980835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1261.980856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1261.980875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1261.980898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1261.980917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1261.980938] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1261.980957] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1261.980977] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1261.980999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1261.981023] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1261.981088] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1261.981111] [drm:intel_power_well_enable [i915]] enabling display
>[ 1261.981133] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1261.981194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1261.981218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1261.981239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1261.981262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1261.981282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1261.981305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1261.981330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1261.981355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1261.981379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1261.981399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1261.981421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1261.981446] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1261.981468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1261.983463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1261.983480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1261.983494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.983509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1261.985012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1261.985028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1261.985042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1261.986537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1261.986553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1261.988358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1261.991289] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1261.991366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1261.991382] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1261.991404] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.008108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.008134] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.008213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.008396] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.008459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.024788] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.024812] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.024849] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.042915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.042934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.042954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.042971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.042989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.043004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.043023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.043043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.043065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.043086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.043106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.043126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.043145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.043208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.043251] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.043286] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.043320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.043346] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.043469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.043484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.043553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.043579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.043607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.043636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.043661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.043687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.043713] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.043738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.043763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.043787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.043811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.043817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.043839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.043845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.043869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.043892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.043915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.043938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.043970] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.043992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.044013] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.044034] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.044054] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.044077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.044102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.044181] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.044206] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.044227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.044265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.044288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.044311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.044334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.044356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.044379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.044404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.044427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.044452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.044472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.044493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.044517] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.044540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.046532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.046548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.046562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.046577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.048106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.048121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.048134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.049630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.049645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.051449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.054396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.054458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.054475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.054497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.071201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.071227] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.071262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.071368] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.071433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.087881] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.087906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.087941] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.105919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.105938] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.105958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.105975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.105993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.106008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.106023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.106039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.106056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.106073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.106089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.106104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.106118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.106132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.106159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.106231] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.106266] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.106292] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.106416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.106430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.106499] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.106525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.106553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.106582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.106607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.106633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.106659] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.106684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.106708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.106732] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.106755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.106762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.106784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.106790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.106814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.106837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.106861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.106884] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.106909] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.106932] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.106953] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.106976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.106999] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.107024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.107052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.107121] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.107145] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.107189] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.107233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.107259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.107293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.107316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.107339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.107362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.107387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.107412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.107437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.107459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.107481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.107506] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.107530] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.109520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.109535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.109550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.109564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.111069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.111084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.111098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.112593] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.112608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.114411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.117362] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.117419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.117436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.117458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.134163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.134206] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.134241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.134346] [drm:drm_mode_addfb2] [FB:75]
>[ 1262.134412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.150843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.150869] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.150906] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.169769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.169788] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.169808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.169825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.169843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.169858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.169872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.169888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.169906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.169922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.169937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.169953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.169967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.169981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.170008] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.170030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.170054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.170071] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.170206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.170223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.170299] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.170325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.170352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.170381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.170404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.170430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.170454] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.170479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.170501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.170524] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.170545] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.170551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.170572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.170578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.170601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.170630] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.170650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.170669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.170691] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.170710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.170731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.170749] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.170770] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.170792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.170817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.170874] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.170896] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.170918] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.170955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.170976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.170998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.171018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.171038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.171059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.171082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.171105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.171128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.171147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.171168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.171210] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.171234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.173228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.173245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.173259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.173274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.174779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.174794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.174808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.176302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.176318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.178123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.181059] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.181132] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.181152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.181223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.197875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.197901] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.197937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.198044] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.198102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.214554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.214579] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.214615] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.233477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.233496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.233517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.233537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.233558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.233578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.233597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.233617] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.233639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.233659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.233680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.233700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.233719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.233738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.233766] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.233788] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.233813] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.233830] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.233945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.233955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.234008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.234026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.234044] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.234063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.234078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.234095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.234111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.234127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.234142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.234157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.234208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.234215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.234238] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.234244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.234267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.234287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.234309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.234329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.234353] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.234373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.234394] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.234414] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.234436] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.234461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.234487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.234542] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.234563] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.234585] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.234622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.234645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.234665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.234687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.234706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.234728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.234752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.234775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.234798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.234818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.234838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.234861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.234884] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.236893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.236910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.236924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.236939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.238449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.238465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.238479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.239973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.239991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.241799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.244714] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.244757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.244774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.244796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.261499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.261526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.261563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.261672] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.261739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.278215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.278241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.278279] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.297119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.297138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.297159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.297223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.297256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.297282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.297308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.297334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.297364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.297391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.297417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.297443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.297467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.297490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.297533] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.297568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.297600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.297626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.297766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.297776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.297823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.297843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.297863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.297884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.297901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.297919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.297938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.297955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.297972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.297987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.298003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.298006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.298022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.298025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.298041] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.298056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.298071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.298085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.298103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.298123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.298143] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.298164] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.298223] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.298257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.298282] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.298336] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.298357] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.298377] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.298415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.298438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.298459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.298482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.298504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.298526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.298551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.298576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.298601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.298623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.298645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.298670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.298693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.300715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.300733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.300747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.300765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.302286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.302303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.302318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.303822] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.303840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.305646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.308423] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.308502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.308517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.308538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.325246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.325273] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.325310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.325413] [drm:drm_mode_addfb2] [FB:75]
>[ 1262.325483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.341925] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.341951] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.341989] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.359058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.359077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.359099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.359119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.359140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.359160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.359179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.359243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.359275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.359304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.359331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.359358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.359382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.359407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.359451] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.359485] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.359518] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.359543] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.359672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.359687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.359748] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.359765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.359782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.359802] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.359827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.359845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.359864] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.359881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.359899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.359917] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.359934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.359937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.359954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.359958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.359975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.359993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.360010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.360027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.360045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.360062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.360079] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.360097] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.360114] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.360132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.360151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.360228] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.360248] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.360268] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.360308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.360331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.360352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.360374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.360396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.360417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.360443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.360466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.360490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.360511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.360532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.360557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.360580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.362583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.362600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.362614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.362630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.364138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.364156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.364173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.365711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.365728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.367601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.370561] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.370611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.370627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.370653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.387352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.387378] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.387415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.387525] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.387594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.404052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.404076] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.404113] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.422960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.422979] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.423001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.423021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.423043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.423062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.423082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.423101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.423123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.423144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.423164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.423184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.423249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.423279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.423324] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.423359] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.423392] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.423418] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.423546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.423563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.423638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.423663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.423690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.423719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.423741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.423767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.423791] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.423816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.423838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.423861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.423882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.423888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.423910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.423915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.423938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.423959] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.423981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.424001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.424027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.424048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.424070] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.424090] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.424112] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.424137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.424164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.424254] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.424279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.424304] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.424345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.424369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.424395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.424417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.424441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.424464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.424489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.424516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.424542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.424563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.424586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.424613] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.424637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.426660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.426679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.426696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.426721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.428259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.428275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.428289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.429792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.429810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.431624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.433853] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.433926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.433943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.433966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.450668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.450694] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.450729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.450829] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.450898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.467369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.467394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.467431] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.486284] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.486302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.486322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.486339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.486357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.486372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.486386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.486402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.486420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.486437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.486453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.486469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.486483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.486497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.486524] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.486546] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.486571] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.486588] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.486712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.486722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.486769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.486788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.486808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.486829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.486846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.486864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.486883] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.486900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.486916] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.486932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.486950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.486954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.486974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.486978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.486998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.487019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.487039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.487059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.487080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.487100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.487120] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.487140] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.487160] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.487182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.487247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.487306] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.487331] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.487355] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.487398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.487424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.487447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.487472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.487495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.487521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.487548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.487574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.487600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.487622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.487645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.487672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.487695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.489733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.489750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.489765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.489780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.491290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.491306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.491320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.492814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.492830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.494638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.496808] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.496838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.496857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.496883] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.513580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.513606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.513642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.513740] [drm:drm_mode_addfb2] [FB:75]
>[ 1262.513800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.530261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.530287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.530324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.549172] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.549191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.549255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.549281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.549310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.549332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.549357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.549380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.549407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.549434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.549459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.549485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.549506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.549528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.549571] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.549605] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.549637] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.549662] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.549775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.549785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.549833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.549853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.549873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.549894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.549910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.549928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.549947] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.549967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.549988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.550008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.550028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.550032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.550052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.550056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.550077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.550097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.550118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.550138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.550158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.550178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.550240] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.550266] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.550289] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.550315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.550342] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.550415] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.550439] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.550464] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.550509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.550534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.550566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.550588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.550609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.550632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.550657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.550681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.550700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.550714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.550728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.550744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.550759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.552738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.552754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.552768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.552783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.554297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.554312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.554325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.555821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.555837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.557646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.560596] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.560655] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.560672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.560694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.577397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.577421] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.577456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.577565] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.577635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.594095] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.594121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.594169] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.613007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.613026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.613046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.613063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.613080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.613095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.613109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.613125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.613143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.613160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.613175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.613191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.613248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.613271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.613315] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.613349] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.613381] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.613406] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.613527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.613541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.613609] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.613633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.613660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.613689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.613712] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.613737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.613761] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.613792] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.613812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.613833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.613852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.613858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.613877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.613882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.613904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.613923] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.613943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.613962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.613985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.614004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.614024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.614047] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.614066] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.614089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.614114] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.614164] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.614186] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.614229] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.614267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.614291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.614311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.614334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.614355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.614377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.614402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.614427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.614452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.614472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.614493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.614519] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.614540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.616534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.616550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.616564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.616578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.618084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.618099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.618112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.619611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.619627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.621436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.624371] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.624445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.624461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.624486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.641188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.641228] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.641262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.641367] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.641430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.657884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.657910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.657958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.676798] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.676817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.676837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.676856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.676878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.676898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.676918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.676937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.676959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.676980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.677000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.677020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.677039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.677058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.677086] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.677109] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.677134] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.677150] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.677277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.677295] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.677370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.677398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.677426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.677456] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.677481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.677507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.677534] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.677559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.677584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.677608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.677631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.677637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.677660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.677666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.677689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.677713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.677736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.677759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.677785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.677808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.677832] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.677856] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.677878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.677903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.677930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.677990] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.678015] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.678039] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.678080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.678112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.678135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.678158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.678179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.678202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.678263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.678289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.678314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.678336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.678358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.678384] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.678408] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.680398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.680414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.680428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.680443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.681945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.681960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.681974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.683470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.683485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.685288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.687984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.688045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.688062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.688084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.704795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.704821] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.704856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.704957] [drm:drm_mode_addfb2] [FB:75]
>[ 1262.705025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.721484] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.721509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.721549] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.740403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.740422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.740442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.740460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.740477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.740492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.740507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.740523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.740544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.740565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.740586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.740606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.740625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.740644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.740672] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.740695] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.740720] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.740736] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.740858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.740868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.740915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.740934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.740955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.740979] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.740999] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.741020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.741040] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.741061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.741081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.741101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.741121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.741125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.741145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.741149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.741170] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.741190] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.741255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.741280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.741305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.741329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.741351] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.741374] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.741396] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.741421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.741447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.741715] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.741731] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.741745] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.741774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.741792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.741808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.741823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.741838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.741857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.741879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.741900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.741921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.741941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.741958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.741979] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.741997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.743980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.743996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.744010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.744025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.745531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.745547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.745565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.747058] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.747075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.748884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.751822] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.751894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.751913] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.751947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.768632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.768657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.768705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.768826] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.768899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.785327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.785350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.785387] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.804245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.804268] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.804298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.804316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.804334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.804354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.804373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.804392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.804414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.804435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.804456] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.804475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.804494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.804513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.804542] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.804565] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.804589] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.804606] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.804729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.804739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.804787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.804806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.804826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.804848] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.804865] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.804883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.804901] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.804921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.804942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.804963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.804983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.804987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.805007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.805011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.805032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.805052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.805073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.805093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.805113] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.805133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.805153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.805174] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.805194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.805260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.805288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.805347] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.805370] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.805391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.805435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.805461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.805484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.805506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.805528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.805554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.805576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.805594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.805611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.805626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.805641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.805659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.805676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.807675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.807692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.807707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.807722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.809264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.809279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.809292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.810796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.810812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.812625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.815562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.815634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.815650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.815672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.832384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.832411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.832449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.832553] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.832626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.849072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.849096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.849143] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.867975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.867994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.868015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.868032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.868049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.868065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.868080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.868099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.868121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.868142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.868163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.868183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.868202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.868268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.868311] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.868345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.868378] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.868404] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.868520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.868537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.868611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.868639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.868667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.868698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.868723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.868750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.868777] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.868802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.868828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.868852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.868876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.868882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.868905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.868911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.868935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.868958] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.868981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.869002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.869028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.869051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.869074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.869095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.869117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.869143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.869171] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.869291] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.869314] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.869337] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.869375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.869399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.869422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.869445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.869465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.869488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.869513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.869537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.869560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.869582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.869603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.869628] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.869651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.871648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.871664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.871678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.871693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.873198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.873226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.873239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.874742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.874758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.876570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.879516] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.879581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.879600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.879626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.896321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.896347] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.896383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.896491] [drm:drm_mode_addfb2] [FB:75]
>[ 1262.896549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.913023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.913048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.913087] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.930941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.930960] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.930980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.930997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.931015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.931031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.931046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.931065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.931087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.931108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.931128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.931149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.931168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.931187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.931260] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.931298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.931333] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.931360] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.931476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.931493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.931569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.931601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.931626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.931652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.931673] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.931697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.931719] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.931742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.931762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.931784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.931804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.931809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.931829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.931834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.931855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.931875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.931895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.931914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.931937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.931956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.931977] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.931996] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.932016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.932038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.932062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.932115] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.932137] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.932158] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.932196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.932218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.932255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.932276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.932298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.932320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.932345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.932369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.932393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.932414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.932435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.932461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.932483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.934479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.934497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.934515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.934533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.936038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.936054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.936069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.937565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1262.937581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1262.939386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1262.942331] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1262.942395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1262.942412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1262.942434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1262.959136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.959162] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.959199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.959377] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.959441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.975839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1262.975863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1262.975900] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1262.993972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1262.993991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1262.994011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.994028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.994046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.994060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.994075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.994091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1262.994109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.994125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.994141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.994156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.994170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.994184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.994211] [drm:intel_power_well_disable [i915]] disabling display
>[ 1262.994282] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1262.994316] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1262.994343] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1262.994467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1262.994482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1262.994550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1262.994577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1262.994604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1262.994634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1262.994659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1262.994685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1262.994711] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1262.994736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1262.994761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1262.994785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1262.994808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1262.994814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.994837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1262.994843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1262.994867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1262.994890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1262.994914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1262.994937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1262.994970] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1262.994991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1262.995012] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1262.995032] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1262.995053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1262.995076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1262.995101] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1262.995166] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1262.995189] [drm:intel_power_well_enable [i915]] enabling display
>[ 1262.995212] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1262.995269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1262.995293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1262.995318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1262.995338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1262.995361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1262.995384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1262.995410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1262.995435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1262.995459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1262.995481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1262.995503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1262.995529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1262.995552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1262.997540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1262.997557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1262.997571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1262.997586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1262.999089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1262.999104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1262.999118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.000615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.000631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.002437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.005368] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.005394] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.005410] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.005432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.022138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.022164] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.022199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.022384] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.022470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.038839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.038864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.038902] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.057739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.057758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.057778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.057795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.057813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.057832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.057852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.057871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.057893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.057914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.057935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.057954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.057974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.057992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.058030] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.058056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.058080] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.058096] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.058205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.058242] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.058316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.058342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.058369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.058397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.058420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.058445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.058470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.058494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.058518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.058540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.058562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.058568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.058590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.058595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.058617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.058640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.058661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.058683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.058707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.058729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.058751] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.058773] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.058794] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.058817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.058843] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.058900] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.058924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.058946] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.058985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.059008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.059029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.059051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.059073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.059097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.059123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.059147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.059172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.059195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.059224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.059267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.059291] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.061278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.061296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.061310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.061325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.062834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.062850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.062864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.064354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.064371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.066172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.068123] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.068169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.068185] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.068207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.084913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.084939] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.084975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.085085] [drm:drm_mode_addfb2] [FB:75]
>[ 1263.085171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.101614] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.101640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.101679] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.119979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.119999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.120019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.120036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.120054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.120069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.120083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.120099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.120117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.120134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.120154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.120175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.120194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.120213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.120286] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.120320] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.120355] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.120381] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.120510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.120527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.120601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.120629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.120658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.120688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.120713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.120746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.120770] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.120794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.120817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.120839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.120861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.120867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.120888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.120893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.120915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.120936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.120957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.120976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.120999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.121021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.121042] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.121061] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.121082] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.121106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.121131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.121186] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.121208] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.121255] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.121296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.121320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.121344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.121367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.121390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.121414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.121439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.121464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.121489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.121511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.121533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.121558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.121582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.123579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.123597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.123615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.123633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.125140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.125156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.125171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.126666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.126682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.128487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.131437] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.131496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.131512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.131534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.148251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.148277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.148313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.148418] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.148484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.164937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.164961] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.164999] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.183838] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.183857] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.183877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.183894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.183912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.183927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.183941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.183957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.183975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.183991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.184007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.184023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.184037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.184051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.184078] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.184099] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.184120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.184136] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.184273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.184290] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.184368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.184397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.184426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.184456] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.184481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.184508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.184534] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.184559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.184585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.184609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.184632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.184639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.184661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.184667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.184691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.184714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.184738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.184761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.184786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.184810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.184834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.184857] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.184878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.184903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.184930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.184989] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.185014] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.185038] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.185079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.185104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.185135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.185157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.185179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.185199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.185223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.185273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.185295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.185317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.185340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.185366] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.185389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.187387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.187405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.187419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.187434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.188937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.188953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.188967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.190463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.190479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.192283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.195201] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.195268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.195295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.195342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.211984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.212010] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.212045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.212154] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.212212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.228665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.228689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.228726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.246986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.247004] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.247024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.247041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.247059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.247074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.247089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.247105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.247123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.247140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.247156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.247172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.247186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.247200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.247227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.247297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.247330] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.247356] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.247464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.247473] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.247518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.247538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.247559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.247582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.247599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.247619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.247638] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.247658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.247678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.247698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.247717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.247721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.247740] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.247744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.247764] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.247783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.247802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.247822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.247841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.247860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.247880] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.247899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.247919] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.247940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.247961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.248007] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.248022] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.248037] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.248067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.248087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.248108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.248128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.248147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.248166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.248188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.248209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.248235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.248280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.248304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.248331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.248361] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.250353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.250369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.250383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.250398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.251899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.251915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.251929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.253424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.253440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.255263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.258199] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.258302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.258329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.258413] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.275015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.275042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.275079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.275188] [drm:drm_mode_addfb2] [FB:75]
>[ 1263.275297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.291695] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.291720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.291756] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.309989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.310008] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.310028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.310046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.310064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.310083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.310102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.310121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.310144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.310164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.310185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.310205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.310224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.310285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.310330] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.310366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.310401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.310428] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.310530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.310540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.310584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.310602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.310627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.310646] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.310661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.310676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.310692] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.310707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.310721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.310735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.310748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.310752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.310764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.310768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.310781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.310799] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.310817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.310835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.310852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.310870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.310888] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.310905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.310923] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.310942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.310961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.311012] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.311025] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.311038] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.311065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.311081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.311099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.311117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.311135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.311153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.311173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.311192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.311211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.311232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.311276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.311302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.311324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.313319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.313335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.313349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.313363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.314865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.314880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.314893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.317451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.317471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.319284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.322222] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.322294] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.322311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.322333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.339036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.339062] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.339097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.339203] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.339318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.355715] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.355740] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.355776] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.374612] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.374631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.374651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.374668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.374686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.374701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.374716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.374732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.374750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.374767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.374783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.374799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.374813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.374827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.374854] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.374876] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.374900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.374917] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.375038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.375048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.375095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.375115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.375135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.375156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.375173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.375191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.375209] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.375225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.375286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.375309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.375334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.375341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.375365] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.375372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.375396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.375420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.375445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.375468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.375495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.375519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.375544] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.375567] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.375591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.375618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.375646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.375720] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.375745] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.375769] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.375844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.375868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.375893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.375915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.375939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.375961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.375988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.376014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.376040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.376063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.376086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.376112] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.376136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.378143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.378159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.378177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.378195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.379706] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.379722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.379736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.381251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.381283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.383088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.386014] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.386044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.386063] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.386089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.402789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.402816] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.402850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.402984] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.403049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.419490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.419515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.419553] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.438391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.438410] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.438430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.438447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.438465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.438484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.438504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.438523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.438546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.438575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.438594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.438610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.438625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.438639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.438666] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.438688] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.438709] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.438725] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.438845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.438855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.438903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.438922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.438942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.438963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.438980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.438998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.439016] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.439033] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.439049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.439069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.439089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.439093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.439114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.439117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.439138] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.439159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.439179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.439199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.439220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.439240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.439303] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.439332] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.439358] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.439386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.439415] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.439490] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.439514] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.439539] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.439580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.439607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.439631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.439655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.439679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.439704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.439731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.439757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.439782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.439805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.439829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.439857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.439882] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.441889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.441906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.441923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.441941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.443452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.443469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.443483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.444975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.444991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.446797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.449722] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.449754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.449770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.449792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.466498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.466524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.466559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.466667] [drm:drm_mode_addfb2] [FB:75]
>[ 1263.466733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.483199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.483223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.483300] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.502155] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.502174] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.502194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.502211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.502228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.502243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.502305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.502329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.502348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.502365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.502381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.502401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.502421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.502440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.502469] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.502492] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.502517] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.502534] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.502622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.502632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.502676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.502694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.502714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.502737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.502763] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.502782] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.502799] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.502814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.502828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.502842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.502855] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.502859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.502871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.502875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.502888] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.502901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.502919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.502936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.502954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.502972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.502990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.503007] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.503025] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.503043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.503063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.503098] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.503112] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.503127] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.503154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.503172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.503191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.503209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.503227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.503250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.503297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.503322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.503345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.503365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.503385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.503409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.503431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.505421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.505437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.505451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.505466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.506969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.506984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.506997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.508493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.508509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.510313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.513249] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.513323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.513340] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.513362] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.530065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.530092] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.530130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.530238] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.530355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.546745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.546769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.546806] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.565127] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.565146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.565167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.565187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.565209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.565229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.565248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.565313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.565344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.565372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.565399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.565426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.565451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.565468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.565496] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.565518] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.565540] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.565556] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.565655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.565669] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.565736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.565761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.565788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.565817] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.565841] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.565866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.565891] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.565915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.565938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.565961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.565983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.565989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.566011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.566016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.566039] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.566061] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.566083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.566104] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.566130] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.566152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.566174] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.566195] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.566223] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.566245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.566288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.566349] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.566370] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.566391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.566428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.566450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.566470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.566490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.566510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.566532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.566556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.566578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.566601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.566620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.566640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.566664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.566685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.568675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.568693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.568711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.568729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.570285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.570301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.570316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.571808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.571824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.573678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.576617] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.576688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.576708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.576734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.593439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.593465] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.593500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.593603] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.593664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.610130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.610155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.610195] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.629058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.629077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.629097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.629114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.629132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.629147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.629161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.629178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.629195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.629212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.629228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.629244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.629305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.629331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.629376] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.629411] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.629444] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.629470] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.629593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.629609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.629691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.629715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.629739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.629765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.629786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.629810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.629832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.629854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.629875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.629896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.629916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.629921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.629941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.629946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.629967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.629987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.630008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.630027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.630049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.630069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.630089] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.630108] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.630128] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.630150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.630174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.630240] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.630289] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.630312] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.630350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.630374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.630396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.630418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.630438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.630462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.630487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.630511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.630536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.630556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.630577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.630603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.630625] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.632879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.632895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.632910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.632924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.634435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.634451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.634464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.635956] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.635972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.637778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.640717] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.640788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.640808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.640834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.657521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.657546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.657579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.657683] [drm:drm_mode_addfb2] [FB:75]
>[ 1263.657745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.674210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.674235] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.674317] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.693172] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.693190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.693210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.693228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.693245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.693299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.693325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.693349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.693379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.693406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.693433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.693458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.693479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.693502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.693544] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.693579] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.693610] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.693636] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.693753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.693764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.693810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.693829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.693847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.693867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.693882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.693898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.693915] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.693931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.693947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.693961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.693975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.693979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.693993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.693996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.694011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.694025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.694038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.694066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.694082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.694095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.694108] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.694121] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.694138] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.694157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.694176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.694211] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.694225] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.694239] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.694307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.694334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.694358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.694382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.694405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.694430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.694456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.694481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.694505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.694527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.694549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.694576] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.694600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.696598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.696614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.696631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.696649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.698155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.698171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.698185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.699683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.699698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.701505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.704452] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.704513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.704530] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.704552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.721253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.721297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.721332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.721442] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.721507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.737955] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.737982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.738021] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.756876] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.756895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.756916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.756933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.756951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.756966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.756980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.756996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.757014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.757031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.757047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.757067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.757086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.757105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.757133] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.757156] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.757181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.757197] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.757338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.757355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.757432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.757460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.757494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.757517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.757535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.757554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.757572] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.757591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.757609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.757627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.757645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.757649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.757666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.757671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.757689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.757707] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.757725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.757743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.757761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.757778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.757796] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.757814] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.757831] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.757850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.757870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.757907] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.757921] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.757936] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.757964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.757982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.758000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.758018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.758036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.758055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.758074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.758093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.758113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.758130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.758149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.758167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.758186] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.760160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.760177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.760191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.760206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.761713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.761729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.761742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.763235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.763250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.765079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.767145] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.767176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.767191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.767211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.783930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.783956] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.783991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.784094] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.784163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.800616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.800640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.800678] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.819542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.819561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.819581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.819598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.819615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.819631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.819645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.819662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.819679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.819696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.819711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.819727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.819741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.819755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.819782] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.819804] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.819825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.819841] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.819962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.819973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.820020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.820039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.820060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.820081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.820098] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.820116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.820134] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.820152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.820168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.820184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.820200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.820204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.820219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.820222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.820238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.820253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.820313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.820335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.820361] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.820383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.820407] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.820428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.820451] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.820479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.820507] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.820579] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.820603] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.820628] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.820669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.820691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.820715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.820736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.820759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.820781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.820806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.820831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.820856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.820877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.820900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.820924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.820955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.822958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.822975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.822989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.823004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.824511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.824526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.824540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.826033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.826049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.827858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.830783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.830816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.830833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.830855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.847567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.847593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.847629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.847739] [drm:drm_mode_addfb2] [FB:75]
>[ 1263.847807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.864245] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.864269] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.864361] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.883030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.883049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.883069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.883086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.883105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.883120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.883135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.883151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.883169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.883186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.883202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.883218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.883232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.883247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.883317] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.883354] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.883388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.883414] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.883528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.883545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.883620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.883645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.883672] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.883701] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.883724] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.883750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.883774] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.883798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.883821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.883845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.883866] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.883872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.883894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.883900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.883923] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.883944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.883966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.883987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.884012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.884032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.884055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.884076] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.884098] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.884123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.884150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.884209] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.884239] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.884260] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.884322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.884344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.884368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.884388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.884410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.884432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.884456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.884481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.884506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.884526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.884547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.884573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.884594] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.886589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.886605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.886619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.886633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.888137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.888152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.888166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.889662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.889679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.891488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.894429] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.894499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.894526] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.894549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.911239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.911266] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.911411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.911517] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.911574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.927939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.927966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.928004] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1263.945811] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1263.945830] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1263.945850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.945867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.945885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.945904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.945924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.945943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.945965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.945986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.946006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.946026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.946045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.946064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.946092] [drm:intel_power_well_disable [i915]] disabling display
>[ 1263.946115] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1263.946140] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.946156] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1263.946255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1263.946305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1263.946383] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1263.946410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1263.946438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1263.946467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1263.946493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1263.946519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1263.946546] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1263.946571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1263.946596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1263.946620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1263.946651] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1263.946657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.946677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1263.946683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1263.946704] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1263.946725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1263.946747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1263.946767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1263.946791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1263.946812] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1263.946833] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1263.946855] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1263.946876] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1263.946900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.946926] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1263.946992] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1263.947015] [drm:intel_power_well_enable [i915]] enabling display
>[ 1263.947038] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1263.947076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1263.947099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1263.947122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1263.947144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1263.947166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1263.947187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1263.947211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1263.947235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1263.947259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.947295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1263.947317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1263.947343] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1263.947367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1263.949362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1263.949379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1263.949393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.949408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1263.950910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1263.950926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1263.950940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1263.952444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1263.952460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1263.954271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1263.957215] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1263.957317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1263.957344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1263.957426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1263.974030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1263.974058] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1263.974096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1263.974208] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.974275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1263.990732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1263.990756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1263.990794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.009033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.009053] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.009073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.009091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.009109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.009125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.009140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.009156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.009177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.009199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.009219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.009240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.009259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.009278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.009357] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.009393] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.009418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.009434] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.009538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.009552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.009621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.009639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.009658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.009678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.009694] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.009711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.009728] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.009748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.009768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.009788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.009807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.009812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.009830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.009834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.009854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.009874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.009893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.009912] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.009939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.009956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.009972] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.009986] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.010000] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.010015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.010032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.010068] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.010081] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.010095] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.010123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.010141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.010159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.010177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.010196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.010213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.010233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.010253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.010274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.010319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.010341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.010366] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.010388] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.012382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.012401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.012418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.012436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.013941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.013957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.013972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.015468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.015484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.017310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.020245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.020346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.020373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.020409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.037061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.037088] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.037126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.037235] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.037345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.053764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.053788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.053824] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.072044] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.072063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.072083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.072100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.072118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.072133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.072147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.072163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.072181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.072197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.072213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.072229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.072243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.072257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.072326] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.072361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.072394] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.072420] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.072543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.072558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.072626] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.072650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.072677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.072705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.072728] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.072753] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.072777] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.072801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.072823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.072846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.072867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.072873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.072894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.072900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.072924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.072944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.072967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.072987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.073012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.073033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.073055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.073076] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.073098] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.073125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.073151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.073219] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.073249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.073271] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.073327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.073350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.073373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.073394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.073416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.073437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.073462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.073487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.073512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.073532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.073553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.073579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.073600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.075588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.075603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.075617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.075632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.077137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.077152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.077168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.078664] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.078680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.080484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.083415] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.083449] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.083464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.083484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.100185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.100211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.100246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.100492] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.100557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.116887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.116911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.116948] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.135041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.135060] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.135080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.135097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.135114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.135130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.135144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.135160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.135178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.135194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.135210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.135225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.135239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.135253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.135279] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.135346] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.135380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.135408] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.135531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.135546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.135614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.135644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.135667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.135694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.135715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.135739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.135760] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.135782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.135803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.135824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.135846] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.135851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.135871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.135876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.135897] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.135916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.135937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.135956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.135979] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.135998] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.136019] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.136038] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.136058] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.136079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.136103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.136166] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.136188] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.136209] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.136246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.136267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.136289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.136328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.136349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.136372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.136397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.136421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.136446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.136466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.136487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.136513] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.136535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.138523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.138539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.138553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.138570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.140075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.140090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.140104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.141599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.141614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.143418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.146367] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.146427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.146447] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.146473] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.163168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.163194] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.163229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.163429] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.163494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.179869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.179893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.179929] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.198774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.198793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.198813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.198833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.198855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.198874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.198894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.198913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.198935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.198956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.198976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.198996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.199015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.199034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.199062] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.199085] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.199110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.199126] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.199233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.199244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.199300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.199352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.199383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.199414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.199439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.199468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.199496] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.199523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.199549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.199574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.199598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.199606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.199628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.199634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.199658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.199681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.199704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.199727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.199752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.199775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.199798] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.199821] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.199844] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.199870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.199898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.199958] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.199982] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.200006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.200055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.200077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.200100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.200121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.200141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.200163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.200187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.200211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.200235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.200256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.200275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.200320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.200343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.202341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.202358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.202373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.202388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.203893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.203909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.203922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.205419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.205435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.207240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.210164] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.210197] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.210214] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.210235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.226942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.226968] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.227002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.227109] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.227167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.243622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.243647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.243683] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.262534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.262553] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.262573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.262590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.262607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.262622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.262637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.262653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.262671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.262687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.262702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.262718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.262732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.262746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.262773] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.262795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.262816] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.262832] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.262946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.262956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.263003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.263022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.263043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.263063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.263080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.263098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.263116] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.263133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.263150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.263165] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.263180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.263184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.263199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.263203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.263218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.263233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.263257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.263272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.263291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.263341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.263363] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.263388] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.263412] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.263439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.263468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.263527] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.263552] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.263577] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.263618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.263644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.263669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.263693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.263717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.263741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.263768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.263794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.263819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.263842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.263865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.263892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.263916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.265925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.265942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.265957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.265972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.267477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.267493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.267510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.269002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.269020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.270828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.273779] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.273837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.273854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.273876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.290579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.290605] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.290640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.290739] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.290806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.307256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.307279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.307361] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.326062] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.326081] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.326101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.326118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.326136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.326152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.326167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.326186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.326208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.326229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.326249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.326269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.326288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.326350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.326393] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.326428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.326462] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.326488] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.326608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.326623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.326696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.326719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.326743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.326770] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.326790] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.326813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.326835] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.326857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.326877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.326898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.326917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.326922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.326942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.326947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.326968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.326987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.327007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.327026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.327049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.327068] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.327089] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.327108] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.327128] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.327151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.327176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.327228] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.327249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.327271] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.327327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.327349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.327372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.327393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.327415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.327436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.327461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.327485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.327510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.327530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.327551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.327578] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.327599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.329588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.329604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.329618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.329633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.331135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.331150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.331164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.332659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.332675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.334478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.337414] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.337487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.337504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.337525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.354228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.354255] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.354290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.354458] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.354522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.370930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.370956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.370995] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.388869] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.388888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.388909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.388926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.388944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.388959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.388974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.388990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.389008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.389024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.389040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.389056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.389070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.389089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.389117] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.389140] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.389165] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.389181] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.389280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.389323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.389402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.389429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.389458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.389488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.389512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.389539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.389566] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.389591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.389616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.389640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.389664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.389670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.389692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.389698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.389721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.389745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.389768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.389791] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.389816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.389840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.389870] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.389892] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.389913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.389937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.389962] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.390017] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.390039] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.390061] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.390099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.390122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.390145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.390167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.390189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.390212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.390237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.390261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.390285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.390326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.390347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.390373] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.390397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.392394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.392411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.392427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.392445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.393950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.393966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.393981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.395478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.395494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.397295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.400243] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.400353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.400378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.400414] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.417057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.417084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.417119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.417217] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.417284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.433739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.433765] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.433811] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.452668] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.452687] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.452707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.452725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.452743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.452758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.452773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.452790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.452808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.452824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.452840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.452856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.452871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.452885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.452912] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.452933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.452954] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.452970] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.453091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.453101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.453155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.453175] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.453196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.453218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.453238] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.453258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.453278] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.453298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.453361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.453389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.453415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.453422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.453445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.453452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.453476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.453530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.453554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.453578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.453605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.453628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.453651] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.453674] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.453697] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.453724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.453751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.453819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.453843] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.453867] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.453906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.453930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.453952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.453976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.453999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.454024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.454051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.454076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.454101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.454124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.454151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.454176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.454199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.456209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.456226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.456240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.456254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.457771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.457788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.457803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.459300] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.459330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.461132] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.464071] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.464142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.464158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.464181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.480884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.480910] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.480945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.481046] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.481115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.497563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.497588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.497632] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.516500] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.516519] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.516539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.516556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.516574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.516589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.516604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.516621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.516639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.516655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.516672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.516688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.516702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.516717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.516743] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.516765] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.516786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.516802] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.516924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.516934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.516981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.517001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.517022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.517046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.517066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.517087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.517107] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.517128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.517148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.517169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.517189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.517193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.517213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.517216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.517237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.517258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.517278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.517298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.517356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.517385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.517412] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.517438] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.517463] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.517491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.517519] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.517593] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.517618] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.517643] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.517684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.517710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.517734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.517759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.517782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.517806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.517832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.517858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.517883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.517906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.517929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.517956] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.517982] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.519989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.520005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.520019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.520033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.521541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.521556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.521570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.523065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.523083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.524894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.527542] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.527601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.527618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.527640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.544349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.544374] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.544408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.544507] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.544566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.561034] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.561059] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.561096] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.579313] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.579350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.579371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.579388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.579406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.579422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.579437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.579452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.579470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.579487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.579503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.579519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.579533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.579547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.579574] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.579597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.579622] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.579639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.579754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.579764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.579812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.579833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.579854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.579878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.579898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.579919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.579940] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.579960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.579981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.580001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.580021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.580025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.580045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.580048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.580069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.580090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.580110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.580130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.580150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.580170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.580191] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.580211] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.580231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.580252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.580274] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.580349] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.580376] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.580401] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.580444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.580469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.580495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.580517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.580542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.580565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.580593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.580619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.580646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.580668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.580691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.580720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.580744] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.582744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.582760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.582776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.582794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.584302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.584327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.584344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.585850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.585869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.587690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.590617] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.590648] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.590667] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.590693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.607391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.607417] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.607452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.607552] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.607613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.624071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.624098] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.624135] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.643002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.643021] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.643041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.643057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.643075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.643090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.643104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.643121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.643138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.643155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.643171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.643186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.643200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.643214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.643241] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.643263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.643284] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.643300] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.643455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.643469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.643536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.643555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.643573] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.643593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.643609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.643627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.643644] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.643659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.643675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.643689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.643703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.643707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.643721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.643725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.643739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.643753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.643768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.643781] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.643800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.643820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.643839] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.643863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.643886] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.643905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.643924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.643962] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.643977] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.643990] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.644018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.644034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.644050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.644065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.644079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.644094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.644111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.644127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.644143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.644158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.644172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.644192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.644212] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.646186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.646202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.646217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.646231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.647737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.647753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.647767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.649266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.649282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.651088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.654027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.654098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.654114] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.654136] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.670840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.670867] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.670905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.671027] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.671091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.687520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.687545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.687581] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.706427] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.706446] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.706466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.706483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.706501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.706516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.706531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.706556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.706579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.706596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.706612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.706627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.706641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.706655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.706683] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.706704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.706726] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.706742] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.706860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.706870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.706918] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.706939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.706960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.706984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.707004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.707025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.707046] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.707066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.707087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.707107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.707127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.707131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.707151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.707154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.707175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.707195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.707216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.707236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.707257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.707276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.707297] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.707317] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.707381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.707410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.707440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.707515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.707540] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.707564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.707606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.707630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.707655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.707678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.707702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.707724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.707750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.707776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.707802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.707823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.707845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.707870] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.707895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.709904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.709921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.709938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.709956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.711466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.711482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.711497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.712989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.713004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.714820] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.717757] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.717827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.717842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.717862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.734572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.734599] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.734634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.734740] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.734806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.751272] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.751296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.751377] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.770237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.770256] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.770276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.770293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.770310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.770369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.770395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.770421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.770452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.770479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.770505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.770531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.770554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.770577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.770618] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.770653] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.770685] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.770711] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.770827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.770838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.770884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.770903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.770922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.770942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.770957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.770982] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.770997] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.771012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.771026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.771040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.771052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.771056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.771069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.771072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.771085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.771098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.771110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.771123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.771138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.771150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.771163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.771176] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.771188] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.771203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.771220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.771263] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.771276] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.771289] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.771314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.771393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.771415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.771436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.771456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.771477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.771500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.771522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.771544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.771563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.771583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.771607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.771628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.773622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.773638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.773652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.773666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.775172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.775187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.775201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.776700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.776716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.778525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.781463] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.781534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.781551] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.781572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.798284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.798310] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.798397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.798535] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.798601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.814975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.814999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.815046] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.833944] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.833963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.833983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.834003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.834024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.834044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.834063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.834082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.834104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.834125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.834146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.834165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.834184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.834203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.834231] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.834254] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.834279] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.834296] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.834444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.834458] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.834530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.834556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.834576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.834595] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.834610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.834628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.834644] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.834660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.834676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.834690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.834705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.834709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.834723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.834727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.834742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.834757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.834772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.834785] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.834803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.834817] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.834832] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.834845] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.834859] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.834876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.834893] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.834939] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.834954] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.834970] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.835000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.835020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.835040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.835059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.835079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.835098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.835119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.835142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.835163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.835182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.835201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.835222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.835241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.837236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.837252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.837267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.837281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.838790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.838805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.838818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.840332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.840364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.842170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.845094] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.845127] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.845143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.845165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.861870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.861898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.861936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.862045] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.862114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.878551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.878575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.878611] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.897458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.897478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.897500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.897520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.897542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.897562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.897581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.897600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.897622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.897643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.897664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.897683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.897702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.897722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.897749] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.897772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.897797] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.897814] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.897929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.897940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.897987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.898006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.898026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.898047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.898064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.898082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.898100] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.898117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.898133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.898148] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.898163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.898167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.898182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.898185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.898200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.898215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.898230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.898245] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.898262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.898277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.898292] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.898306] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.898321] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.898407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.898436] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.898505] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.898530] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.898554] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.898595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.898621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.898644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.898667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.898688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.898712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.898746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.898771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.898796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.898816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.898837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.898861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.898885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.900900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.900917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.900931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.900946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.902457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.902473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.902486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.903979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.903995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.905800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.908737] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.908809] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.908826] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.908847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.925551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.925577] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.925612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.925718] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.925776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.942232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1264.942257] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1264.942294] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1264.961135] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1264.961154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1264.961175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.961191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.961209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.961225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.961239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.961255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.961273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.961290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.961305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.961321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.961385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.961410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.961455] [drm:intel_power_well_disable [i915]] disabling display
>[ 1264.961490] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1264.961523] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.961548] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1264.961700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1264.961717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1264.961792] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1264.961818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.961846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.961875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.961898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.961924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.961948] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1264.961973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.961996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.962019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1264.962040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.962046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.962075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.962080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1264.962101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1264.962120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.962141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.962159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.962182] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1264.962201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.962221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1264.962240] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1264.962260] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1264.962282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1264.962306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1264.962399] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1264.962422] [drm:intel_power_well_enable [i915]] enabling display
>[ 1264.962445] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1264.962483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1264.962506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1264.962529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1264.962550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1264.962571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1264.962591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1264.962615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1264.962638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1264.962661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.962680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1264.962700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1264.962725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1264.962746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1264.964750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1264.964767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1264.964782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.964796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1264.966311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1264.966334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1264.966384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1264.967882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1264.967898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1264.969712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1264.972663] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1264.972721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1264.972738] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1264.972760] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1264.989463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1264.989491] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1264.989529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1264.989639] [drm:drm_mode_addfb2] [FB:75]
>[ 1264.989706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.006163] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.006187] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.006225] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.025094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.025113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.025134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.025151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.025172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.025191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.025211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.025230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.025252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.025273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.025294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.025313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.025332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.025396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.025440] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.025470] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.025495] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.025512] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.025600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.025610] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.025654] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.025673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.025691] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.025711] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.025727] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.025745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.025762] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.025781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.025801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.025821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.025840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.025844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.025863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.025867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.025887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.025906] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.025926] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.025945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.025965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.025984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.026003] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.026023] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.026042] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.026063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.026084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.026125] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.026141] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.026157] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.026187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.026207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.026227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.026247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.026267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.026287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.026309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.026341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.026387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.026410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.026430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.026455] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.026476] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.028470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.028487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.028505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.028523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.030027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.030044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.030058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.031555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.031572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.033378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.036313] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.036416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.036444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.036528] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.053130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.053156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.053191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.053299] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.053414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.069831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.069856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.069894] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.088101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.088120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.088140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.088156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.088174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.088189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.088203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.088220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.088237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.088254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.088269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.088285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.088299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.088313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.088340] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.088410] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.088443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.088470] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.088576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.088590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.088658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.088676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.088702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.088720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.088735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.088754] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.088772] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.088790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.088809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.088827] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.088844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.088848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.088866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.088869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.088887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.088905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.088923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.088940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.088958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.088975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.088993] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.089011] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.089029] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.089047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.089070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.089113] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.089128] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.089140] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.089167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.089183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.089198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.089216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.089235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.089252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.089272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.089291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.089311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.089328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.089377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.089404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.089426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.091421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.091437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.091452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.091466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.092967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.092982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.092995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.094509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.094527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.096374] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.099310] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.099412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.099440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.099540] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.116127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.116153] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.116188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.116317] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.116441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.132806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.132831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.132867] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.151104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.151123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.151144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.151161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.151178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.151194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.151208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.151224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.151242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.151259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.151275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.151290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.151304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.151318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.151388] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.151424] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.151458] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.151485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.151615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.151632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.151707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.151731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.151759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.151788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.151811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.151836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.151860] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.151884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.151907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.151937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.151956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.151962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.151981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.151987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.152009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.152028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.152049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.152068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.152091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.152110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.152131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.152150] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.152170] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.152191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.152215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.152270] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.152292] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.152314] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.152350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.152395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.152416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.152438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.152458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.152482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.152507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.152532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.152556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.152576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.152598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.152623] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.152645] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.154643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.154659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.154674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.154688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.156192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.156210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.156228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.157724] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.157741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.159545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.162499] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.162554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.162571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.162593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.179294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.179320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.179400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.179534] [drm:drm_mode_addfb2] [FB:75]
>[ 1265.179600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.195976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.196002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.196039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.214887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.214906] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.214926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.214943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.214960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.214975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.214990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.215009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.215031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.215052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.215073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.215093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.215112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.215131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.215159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.215182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.215207] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.215224] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.215336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.215370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.215442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.215467] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.215495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.215523] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.215544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.215568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.215591] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.215614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.215635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.215656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.215676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.215682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.215702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.215707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.215729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.215748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.215769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.215788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.215812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.215831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.215853] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.215872] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.215892] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.215914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.215939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.215994] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.216017] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.216039] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.216077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.216100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.216121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.216142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.216162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.216185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.216210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.216233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.216257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.216276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.216297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.216320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.216351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.218382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.218399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.218413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.218428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.219945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.219962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.219977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.221476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.221493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.223299] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.225905] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.225953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.225970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.225992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.242696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.242722] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.242757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.242863] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.242921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.259397] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.259421] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.259458] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.277447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.277467] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.277489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.277509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.277531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.277550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.277570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.277589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.277611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.277631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.277652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.277672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.277691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.277710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.277738] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.277761] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.277786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.277802] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.277918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.277928] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.277975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.277996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.278017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.278041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.278061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.278082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.278103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.278123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.278144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.278164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.278184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.278188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.278208] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.278212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.278232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.278253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.278273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.278293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.278314] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.278334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.278354] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.278412] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.278438] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.278467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.278496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.278556] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.278582] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.278606] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.278648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.278672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.278697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.278719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.278743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.278767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.278793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.278819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.278844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.278865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.278887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.278914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.278937] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.280986] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.281003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.281018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.281033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.282542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.282558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.282571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.284065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.284081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.285887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.288825] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.288904] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.288920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.288941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.305638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.305664] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.305699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.305800] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.305866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.322330] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.322353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.322444] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.341117] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.341137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.341157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.341174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.341192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.341207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.341227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.341246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.341268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.341289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.341309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.341329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.341348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.341410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.341453] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.341488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.341521] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.341548] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.341673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.341690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.341765] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.341792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.341820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.341850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.341875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.341902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.341928] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.341953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.341978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.342002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.342026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.342032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.342055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.342061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.342084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.342108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.342130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.342151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.342177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.342201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.342224] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.342245] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.342267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.342292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.342319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.342425] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.342451] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.342476] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.342518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.342544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.342570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.342594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.342617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.342642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.342670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.342695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.342721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.342744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.342767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.342794] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.342819] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.344838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.344857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.344874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.344893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.346429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.346446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.346460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.347954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.347970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.349778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.352721] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.352788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.352804] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.352826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.369530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.369556] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.369593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.369703] [drm:drm_mode_addfb2] [FB:75]
>[ 1265.369770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.386209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.386234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.386270] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.405090] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.405109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.405130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.405147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.405165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.405180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.405195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.405211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.405229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.405246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.405265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.405286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.405305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.405324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.405353] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.405422] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.405459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.405485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.405608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.405623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.405691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.405715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.405743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.405772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.405795] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.405821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.405844] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.405868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.405891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.405914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.405935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.405941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.405963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.405968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.405992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.406013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.406035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.406056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.406081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.406102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.406124] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.406145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.406167] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.406191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.406217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.406285] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.406309] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.406332] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.406398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.406422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.406444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.406466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.406486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.406509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.406534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.406558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.406582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.406603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.406624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.406650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.406671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.408660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.408676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.408689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.408703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.410206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.410221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.410235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.411730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.411746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.413549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.416493] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.416559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.416578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.416609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.433300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.433328] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.433365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.433547] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.433613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.450001] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.450026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.450061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.468915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.468934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.468955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.468972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.468990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.469009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.469028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.469048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.469069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.469090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.469111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.469131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.469150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.469169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.469197] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.469219] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.469244] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.469261] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.469396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.469416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.469494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.469519] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.469547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.469576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.469599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.469625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.469649] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.469680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.469701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.469722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.469742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.469748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.469768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.469775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.469795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.469816] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.469835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.469855] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.469877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.469897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.469916] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.469937] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.469956] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.469978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.470003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.470061] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.470083] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.470104] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.470141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.470162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.470184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.470203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.470224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.470244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.470267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.470290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.470313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.470332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.470352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.470395] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.470419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.472414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.472432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.472446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.472462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.473967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.473982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.473996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.475492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.475508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.477320] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.480245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.480278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.480298] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.480324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.497021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.497048] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.497086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.497199] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.497266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.513692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.513716] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.513752] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.532597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.532616] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.532636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.532653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.532671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.532686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.532700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.532716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.532734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.532750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.532766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.532782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.532796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.532814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.532843] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.532865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.532890] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.532907] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.533030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.533040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.533087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.533106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.533126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.533147] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.533164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.533182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.533200] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.533217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.533233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.533251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.533271] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.533275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.533295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.533299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.533320] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.533340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.533360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.533420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.533446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.533471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.533494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.533516] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.533538] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.533564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.533590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.533648] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.533673] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.533696] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.533738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.533763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.533787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.533810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.533833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.533858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.533885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.533911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.533937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.533960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.533983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.534010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.534027] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.536022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.536040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.536054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.536069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.537577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.537594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.537612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.539106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.539123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.540929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.543855] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.543886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.543902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.543924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.560630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.560656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.560691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.560795] [drm:drm_mode_addfb2] [FB:75]
>[ 1265.560852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.577331] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.577355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.577443] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.596133] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.596153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.596175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.596195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.596217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.596236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.596256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.596275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.596297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.596318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.596338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.596358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.596419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.596446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.596489] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.596524] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.596558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.596583] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.596701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.596718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.596793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.596818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.596845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.596875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.596897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.596923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.596947] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.596972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.596994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.597018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.597039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.597045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.597067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.597072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.597095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.597117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.597139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.597160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.597185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.597206] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.597229] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.597249] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.597281] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.597305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.597332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.597416] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.597441] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.597473] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.597510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.597534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.597556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.597578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.597599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.597622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.597647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.597670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.597694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.597714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.597734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.597760] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.597781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.599774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.599790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.599807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.599826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.601336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.601353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.601371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.602899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.602916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.604732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.607686] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.607740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.607755] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.607776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.624499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.624525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.624560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.624661] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.624722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.641177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.641202] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.641239] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.659713] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.659732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.659752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.659769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.659787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.659802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.659817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.659835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.659857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.659878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.659899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.659919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.659938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.659957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.659985] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.660008] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.660032] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.660049] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.660169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.660179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.660227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.660246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.660266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.660287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.660304] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.660322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.660340] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.660357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.660373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.660426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.660448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.660456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.660477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.660483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.660505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.660527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.660549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.660570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.660594] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.660616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.660638] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.660659] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.660680] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.660705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.660731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.660791] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.660815] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.660839] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.660873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.660893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.660911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.660938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.660956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.660973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.660991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.661010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.661031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.661050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.661069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.661089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.661108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.663090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.663107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.663121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.663135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.664644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.664660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.664673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.666166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.666187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.667996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.670921] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.670953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.670970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.670991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.687697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.687722] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.687760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.687870] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.687937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.704368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.704413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.704448] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.723295] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.723314] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.723334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.723351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.723368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.723427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.723452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.723476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.723505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.723533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.723559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.723584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.723605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.723627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.723671] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.723704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.723736] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.723761] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.723872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.723883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.723929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.723947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.723966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.723986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.724002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.724019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.724036] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.724052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.724067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.724082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.724096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.724100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.724114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.724117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.724131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.724145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.724159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.724172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.724188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.724209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.724222] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.724234] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.724246] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.724261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.724277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.724311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.724324] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.724337] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.724361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.724376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.724432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.724456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.724478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.724502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.724528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.724553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.724577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.724599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.724622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.724648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.724671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.726667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.726683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.726697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.726712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.728217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.728233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.728246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.729746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.729761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.731569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.733956] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.734023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.734042] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.734068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.750762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.750788] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.750825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.750928] [drm:drm_mode_addfb2] [FB:75]
>[ 1265.750997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.767445] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.767468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.767503] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.786360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.786379] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.786448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.786475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.786504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.786528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.786552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.786577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.786605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.786632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.786652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.786669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.786683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.786698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.786726] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.786748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.786769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.786786] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.786874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.786884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.786927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.786943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.786962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.786981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.786996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.787014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.787031] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.787047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.787063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.787078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.787092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.787097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.787111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.787114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.787130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.787144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.787159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.787172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.787190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.787204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.787218] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.787232] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.787246] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.787262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.787281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.787318] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.787333] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.787349] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.787382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.787435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.787456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.787476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.787495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.787517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.787540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.787563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.787585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.787604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.787624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.787648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.787669] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.789658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.789674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.789688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.789703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.791203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.791217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.791231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.792724] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.792739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.794541] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.796942] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.796994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.797010] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.797032] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.813741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.813767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.813802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.813919] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.813986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.830424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.830448] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.830487] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.849334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.849353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.849373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.849436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.849465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.849490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.849514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.849539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.849568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.849595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.849621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.849647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.849670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.849693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.849737] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.849771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.849803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.849829] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.849928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.849938] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.849983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.850001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.850020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.850039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.850055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.850072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.850089] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.850105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.850122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.850145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.850165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.850169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.850183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.850186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.850200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.850214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.850228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.850241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.850258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.850272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.850286] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.850300] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.850313] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.850330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.850347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.850384] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.850442] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.850465] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.850506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.850529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.850553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.850575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.850597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.850619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.850651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.850675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.850697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.850717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.850738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.850762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.850784] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.852777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.852793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.852807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.852821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.854333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.854348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.854362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.855854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.855870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.857674] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.860598] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.860631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.860648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.860670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.877339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.877362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.877427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.877546] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.877616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.894058] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.894080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.894115] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.912043] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.912060] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.912080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.912096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.912113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.912128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.912142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.912158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.912176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.912192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.912208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.912224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.912238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.912251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.912277] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.912298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.912319] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.912334] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.912445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.912462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.912528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.912546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.912565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.912585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.912601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.912618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.912635] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.912651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.912667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.912682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.912697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.912701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.912715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.912719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.912734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.912748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.912770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.912782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.912798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.912811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.912825] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.912837] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.912850] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.912865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.912883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.912919] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.912933] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.912947] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.912975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.912993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.913017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.913040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.913056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.913070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.913087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.913101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.913116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.913129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.913142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.913158] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.913173] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.915158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.915174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.915188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.915203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.916711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.916726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.916740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.918232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.918248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.920055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.922978] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.923011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.923026] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.923047] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.939736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.939759] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.939793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.939900] [drm:drm_mode_addfb2] [FB:75]
>[ 1265.939955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.956460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1265.956486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.956525] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1265.975361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1265.975381] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.975438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.975465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.975493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.975518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.975541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.975567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.975590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.975608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.975624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.975641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.975655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.975670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.975698] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.975720] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.975742] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.975758] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.975841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.975853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.975908] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.975924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.975942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.975970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.975984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.976000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.976015] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.976029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.976044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.976058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.976071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.976074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.976087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.976090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.976104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.976116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.976129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.976142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.976157] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.976169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.976183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.976195] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.976209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.976224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.976241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.976277] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.976290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.976303] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.976328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.976342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.976356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.976369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.976383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.976431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.976454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.976477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.976498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.976518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.976538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.976561] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.976582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.978581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.978597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.978611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.978626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.980128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.980146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.980163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.981660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.981676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.983480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.986318] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.986388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.986436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.986474] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.003130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.003156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.003191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.003305] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.003370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.019834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.019859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.019896] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.038753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.038772] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.038793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.038810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.038827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.038843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.038857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.038873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.038891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.038912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.038933] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.038953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.038972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.038991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.039019] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.039042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.039067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.039084] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.039207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.039218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.039266] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.039285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.039305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.039327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.039344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.039361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.039380] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.039397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.039456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.039478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.039500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.039507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.039528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.039535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.039557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.039578] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.039600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.039621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.039645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.039667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.039689] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.039710] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.039731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.039756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.039781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.039857] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.039877] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.039892] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.039919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.039935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.039950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.039965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.039979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.039994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.040012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.040028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.040043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.040058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.040072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.040089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.040108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.042105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.042122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.042137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.042152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.043661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.043677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.043691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.045185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.045200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.047008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.049944] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.050018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.050035] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.050057] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.066760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.066787] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.066825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.066936] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.067004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.083440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.083465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.083501] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.102346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.102367] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.102389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.102454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.102487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.102513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.102538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.102564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.102594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.102621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.102647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.102673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.102696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.102720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.102763] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.102798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.102830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.102856] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.102989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.103000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.103045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.103064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.103082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.103105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.103124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.103143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.103163] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.103182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.103201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.103220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.103238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.103242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.103261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.103265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.103284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.103303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.103322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.103341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.103360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.103379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.103407] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.103467] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.103495] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.103525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.103554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.103628] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.103653] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.103678] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.103725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.103748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.103771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.103793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.103815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.103835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.103860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.103884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.103908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.103929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.103949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.103974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.103997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.105998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.106015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.106029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.106044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.107554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.107575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.107590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.109082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.109098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.110920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.113881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.113927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.113942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.113962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.130671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.130697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.130732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.130838] [drm:drm_mode_addfb2] [FB:75]
>[ 1266.130904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.147362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.147384] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.147460] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.166285] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.166313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.166342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.166368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.166395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.166458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.166482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.166507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.166536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.166561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.166586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.166611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.166633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.166654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.166697] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.166720] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.166741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.166758] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.166844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.166854] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.166897] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.166914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.166932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.166952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.166967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.166984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.167001] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.167017] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.167039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.167052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.167065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.167069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.167082] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.167085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.167098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.167111] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.167124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.167136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.167151] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.167164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.167177] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.167190] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.167203] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.167218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.167235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.167278] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.167292] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.167305] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.167330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.167344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.167358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.167371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.167384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.167400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.167443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.167466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.167488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.167508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.167528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.167551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.167572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.169567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.169584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.169601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.169620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.171125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.171141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.171155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.172653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.172669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.174475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.177399] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.177486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.177503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.177525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.194213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.194239] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.194274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.194382] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.194512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.210926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.210951] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.210988] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.228142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.228161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.228182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.228202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.228224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.228243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.228263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.228282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.228304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.228325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.228346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.228365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.228384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.228403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.228482] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.228519] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.228555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.228582] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.228687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.228697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.228741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.228759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.228777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.228798] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.228821] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.228847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.228866] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.228882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.228898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.228912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.228926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.228930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.228944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.228948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.228962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.228982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.229002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.229021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.229040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.229059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.229078] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.229098] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.229117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.229138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.229159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.229204] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.229220] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.229235] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.229265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.229293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.229310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.229325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.229340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.229355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.229372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.229387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.229403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.229447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.229468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.229493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.229514] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.231504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.231521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.231535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.231550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.233053] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.233068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.233081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.234578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.234594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.236396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.239331] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.239361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.239378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.239399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.256104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.256130] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.256166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.256272] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.256329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.272800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.272824] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.272860] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.291170] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.291190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.291213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.291233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.291254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.291274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.291293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.291313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.291335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.291356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.291376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.291396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.291415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.291476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.291520] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.291549] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.291585] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.291610] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.291697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.291711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.291777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.291794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.291812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.291831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.291846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.291862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.291879] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.291894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.291908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.291922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.291936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.291940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.291953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.291956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.291970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.291984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.291997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.292010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.292026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.292040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.292053] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.292067] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.292080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.292095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.292112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.292157] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.292172] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.292186] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.292215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.292234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.292253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.292271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.292290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.292309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.292329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.292348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.292369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.292386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.292405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.292457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.292479] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.294479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.294496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.294510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.294525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.296032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.296047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.296061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.297556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.297572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.299376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.302326] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.302385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.302402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.302460] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.319127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.319154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.319189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.319295] [drm:drm_mode_addfb2] [FB:75]
>[ 1266.319359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.335807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.335833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.335870] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.354172] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.354190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.354211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.354227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.354245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.354260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.354275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.354291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.354309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.354325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.354347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.354371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.354397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.354416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.354493] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.354528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.354552] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.354568] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.354670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.354685] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.354740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.354758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.354777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.354797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.354813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.354838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.354854] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.354868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.354883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.354897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.354910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.354914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.354927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.354931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.354948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.354966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.354984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.355002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.355019] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.355037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.355055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.355073] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.355091] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.355109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.355129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.355172] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.355186] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.355200] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.355228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.355246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.355262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.355280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.355299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.355317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.355336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.355353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.355372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.355390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.355409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.355458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.355481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.357475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.357493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.357510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.357528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.359045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.359062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.359077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.360577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.360594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.362405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.365356] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.365459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.365485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.365523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.382176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.382203] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.382238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.382341] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.382409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.398866] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.398892] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.398930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.417180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.417201] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.417223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.417243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.417265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.417284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.417304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.417323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.417345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.417365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.417386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.417405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.417424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.417489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.417537] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.417572] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.417606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.417632] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.417757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.417774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.417848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.417873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.417900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.417929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.417953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.417978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.418003] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.418027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.418049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.418072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.418093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.418099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.418121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.418126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.418150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.418170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.418193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.418221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.418244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.418263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.418283] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.418302] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.418323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.418344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.418368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.418455] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.418478] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.418501] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.418539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.418560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.418583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.418604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.418625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.418647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.418673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.418697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.418722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.418742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.418763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.418788] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.418809] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.420799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.420815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.420829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.420844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.422369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.422385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.422399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.423929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.423945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.425779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.428251] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.428282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.428299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.428324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.445023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.445049] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.445084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.445190] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.445255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.461725] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.461749] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.461785] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.479780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.479799] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.479819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.479836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.479854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.479869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.479883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.479899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.479917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.479933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.479949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.479964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.479979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.479993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.480020] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.480041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.480062] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.480077] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.480199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.480209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.480257] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.480276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.480296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.480318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.480334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.480352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.480371] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.480388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.480405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.480421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.480482] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.480489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.480514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.480521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.480545] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.480570] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.480595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.480618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.480645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.480669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.480694] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.480717] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.480741] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.480768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.480797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.480856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.480881] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.480905] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.480946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.480970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.480995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.481018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.481042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.481064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.481091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.481117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.481142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.481166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.481189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.481217] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.481242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.483243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.483261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.483278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.483297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.484813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.484830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.484845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.486342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.486360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.488168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.491104] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.491177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.491194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.491216] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.507919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.507945] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.507980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.508089] [drm:drm_mode_addfb2] [FB:75]
>[ 1266.508156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.524623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.524647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.524684] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.543532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.543551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.543571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.543588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.543607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.543622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.543637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.543654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.543672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.543688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.543704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.543720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.543734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.543748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.543775] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.543797] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.543818] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.543833] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.543954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.543964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.544011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.544030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.544050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.544071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.544088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.544106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.544124] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.544141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.544158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.544174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.544189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.544193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.544208] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.544211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.544227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.544243] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.544258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.544272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.544290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.544305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.544321] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.544336] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.544350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.544368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.544387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.544474] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.544497] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.544524] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.544566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.544592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.544618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.544642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.544667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.544693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.544721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.544748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.544775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.544799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.544823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.544852] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.544878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.546901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.546918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.546932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.546947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.548498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.548515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.548530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.550023] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.550041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.551848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.554798] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.554856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.554874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.554909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.571599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.571627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.571674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.571780] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.571837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.588301] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.588325] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.588363] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.607240] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.607259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.607279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.607296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.607313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.607329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.607343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.607359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.607377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.607393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.607409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.607425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.607483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.607505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.607548] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.607585] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.607617] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.607644] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.607746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.607756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.607800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.607817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.607835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.607855] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.607871] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.607888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.607905] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.607922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.607937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.607957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.607976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.607981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.608000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.608004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.608024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.608043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.608063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.608082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.608102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.608121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.608141] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.608167] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.608184] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.608200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.608219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.608260] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.608273] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.608286] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.608311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.608327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.608341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.608354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.608368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.608383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.608398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.608413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.608427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.608468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.608488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.608512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.608533] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.610524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.610540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.610555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.610570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.612072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.612087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.612101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.613596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.613611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.615438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.618374] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.618402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.618419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.618477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.635146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.635172] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.635207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.635314] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.635371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.651847] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.651871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.651916] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.670770] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.670789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.670810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.670831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.670852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.670872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.670891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.670911] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.670932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.670953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.670974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.670993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.671012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.671031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.671059] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.671082] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.671107] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.671123] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.671245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.671255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.671303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.671324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.671353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.671376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.671394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.671412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.671430] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.671494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.671521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.671545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.671569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.671575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.671598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.671605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.671629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.671652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.671676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.671698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.671725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.671748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.671771] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.671794] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.671818] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.671844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.671871] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.671943] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.671966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.671989] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.672029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.672055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.672079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.672102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.672125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.672149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.672176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.672201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.672226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.672249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.672272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.672298] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.672322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.674347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.674363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.674377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.674392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.675900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.675915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.675928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.677477] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.677492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.679298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.682224] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.682255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.682274] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.682300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.699008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.699035] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.699073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.699205] [drm:drm_mode_addfb2] [FB:75]
>[ 1266.699271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.715696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.715721] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.715759] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.734618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.734637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.734658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.734677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.734699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.734719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.734739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.734758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.734790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.734813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.734834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.734854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.734873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.734892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.734920] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.734943] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.734968] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.734984] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.735105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.735115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.735163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.735182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.735202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.735223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.735240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.735260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.735281] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.735302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.735322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.735343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.735362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.735366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.735386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.735390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.735411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.735431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.735500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.735528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.735557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.735584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.735610] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.735635] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.735659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.735688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.735716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.735776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.735800] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.735824] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.735866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.735891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.735915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.735939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.735962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.735986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.736013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.736039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.736066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.736089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.736111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.736138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.736163] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.738175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.738192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.738209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.738228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.739739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.739756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.739773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.741269] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.741285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.743095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.746020] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.746053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.746070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.746092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.762825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.762852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.762890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.762993] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.763064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.779493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.779518] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.779555] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.797592] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.797611] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.797632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.797649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.797666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.797682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.797696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.797713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.797733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.797754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.797775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.797795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.797814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.797833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.797861] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.797884] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.797909] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.797925] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.798049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.798059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.798106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.798126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.798146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.798168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.798185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.798203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.798221] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.798238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.798255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.798275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.798295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.798299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.798319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.798323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.798344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.798364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.798385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.798405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.798426] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.798446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.798508] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.798534] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.798559] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.798588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.798617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.798689] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.798714] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.798738] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.798780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.798803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.798828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.798850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.798873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.798895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.798922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.798954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.798977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.798996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.799017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.799041] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.799062] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.801065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.801082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.801096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.801111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.802621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.802636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.802650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.804142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.804158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.805970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.808908] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.808980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.808997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.809019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.825731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.825757] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.825792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.825900] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.825966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.842410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.842432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.842523] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.860956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.860977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.860999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.861019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.861041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.861060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.861080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.861099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.861122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.861142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.861163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.861183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.861202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.861221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.861248] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.861271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.861296] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.861312] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.861417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.861429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.861569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.861597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.861625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.861656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.861681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.861708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.861734] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.861759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.861784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.861808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.861831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.861837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.861860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.861866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.861889] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.861912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.861936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.861958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.861984] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.862008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.862031] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.862054] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.862077] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.862101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.862128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.862198] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.862223] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.862254] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.862292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.862316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.862338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.862360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.862382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.862405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.862431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.862472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.862496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.862518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.862540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.862566] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.862590] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.864577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.864593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.864607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.864625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.866130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.866148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.866165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.867662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.867679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.869486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.872421] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.872560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.872639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.872663] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.889238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.889264] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.889300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.889408] [drm:drm_mode_addfb2] [FB:75]
>[ 1266.889524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.905918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.905943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.905979] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.924209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.924228] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.924248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.924265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.924282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.924297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.924312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.924328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.924349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.924370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.924390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.924410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.924429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.924448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.924521] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.924556] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.924590] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.924617] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.924734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.924749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.924818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.924843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.924869] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.924896] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.924919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.924943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.924967] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.924991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.925014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.925037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.925058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.925064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.925085] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.925090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.925112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.925134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.925156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.925175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.925199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.925220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.925242] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.925264] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.925285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.925310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.925335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.925402] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.925425] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.925447] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.925505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.925530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.925552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.925575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.925597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.925620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.925646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.925670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.925694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.925716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.925739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.925764] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.925788] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.927786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.927803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.927820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.927838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.929343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.929359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.929373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.930867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.930885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.932690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.935616] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.935647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.935663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.935685] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1266.952390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.952416] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.952451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.952693] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.952751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.969078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1266.969102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1266.969138] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1266.987215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1266.987235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1266.987255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.987272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.987291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.987306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.987321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.987338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1266.987355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.987372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.987388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.987403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.987422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.987441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.987511] [drm:intel_power_well_disable [i915]] disabling display
>[ 1266.987546] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1266.987582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1266.987607] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1266.987718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1266.987733] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1266.987802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1266.987826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1266.987853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1266.987883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1266.987913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1266.987936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1266.987958] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1266.987980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1266.988000] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1266.988021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1266.988039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1266.988045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.988064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1266.988069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1266.988090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1266.988110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1266.988130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1266.988149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1266.988172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1266.988191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1266.988212] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1266.988231] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1266.988251] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1266.988272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1266.988296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1266.988359] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1266.988381] [drm:intel_power_well_enable [i915]] enabling display
>[ 1266.988402] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1266.988439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1266.988460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1266.988499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1266.988520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1266.988543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1266.988565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1266.988590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1266.988614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1266.988638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.988659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1266.988680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1266.988706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1266.988728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1266.990717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1266.990734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1266.990748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.990762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1266.992266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1266.992283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1266.992300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1266.993797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1266.993815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1266.995622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1266.998555] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1266.998631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1266.998648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1266.998669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.015372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.015398] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.015434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.015658] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.015722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.032052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.032078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.032116] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.050219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.050238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.050258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.050275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.050292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.050308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.050322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.050338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.050356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.050373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.050393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.050414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.050433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.050452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.050526] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.050561] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.050595] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.050620] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.050743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.050758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.050826] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.050850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.050877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.050906] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.050929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.050955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.050979] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.051003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.051025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.051048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.051069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.051075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.051097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.051102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.051126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.051147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.051169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.051190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.051215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.051243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.051264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.051283] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.051303] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.051324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.051348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.051410] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.051432] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.051453] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.051513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.051537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.051558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.051581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.051601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.051625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.051650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.051674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.051698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.051718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.051740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.051766] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.051787] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.053775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.053790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.053804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.053818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.055324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.055341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.055359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.056856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.056873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.058678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.061619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.061688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.061705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.061727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.078429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.078456] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.078539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.078663] [drm:drm_mode_addfb2] [FB:75]
>[ 1267.078727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.095110] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.095134] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.095170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.113222] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.113240] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.113262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.113282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.113304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.113323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.113343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.113362] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.113384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.113405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.113425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.113445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.113463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.113524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.113568] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.113603] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.113637] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.113663] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.113786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.113801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.113869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.113895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.113921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.113949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.113971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.113997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.114021] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.114046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.114068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.114092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.114112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.114119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.114140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.114146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.114169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.114190] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.114213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.114233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.114258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.114279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.114301] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.114322] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.114344] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.114367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.114393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.114462] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.114503] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.114528] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.114569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.114600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.114623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.114644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.114666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.114687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.114712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.114737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.114761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.114781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.114802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.114828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.114849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.116838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.116854] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.116869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.116883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.118409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.118424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.118438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.119933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.119949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.121753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.124698] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.124762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.124779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.124801] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.141505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.141531] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.141568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.141677] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.141743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.158185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.158211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.158248] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.177077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.177096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.177116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.177136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.177158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.177177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.177197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.177216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.177238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.177259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.177279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.177299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.177317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.177336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.177364] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.177387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.177412] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.177429] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.177570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.177585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.177656] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.177683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.177710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.177730] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.177749] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.177770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.177790] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.177809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.177830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.177850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.177869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.177874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.177893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.177897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.177917] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.177936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.177963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.177979] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.177996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.178011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.178025] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.178040] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.178053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.178069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.178085] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.178134] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.178156] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.178170] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.178195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.178211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.178225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.178238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.178251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.178265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.178281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.178296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.178310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.178323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.178336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.178353] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.178367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.180342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.180358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.180373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.180387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.181892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.181907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.181921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.183493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.183509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.185311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.188244] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.188319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.188336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.188358] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.205062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.205089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.205124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.205231] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.205317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.221765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.221791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.221829] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.240664] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.240683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.240703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.240720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.240738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.240753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.240768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.240784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.240802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.240818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.240838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.240859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.240878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.240903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.240934] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.240955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.240977] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.240993] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.241115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.241124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.241172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.241192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.241212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.241233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.241250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.241268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.241286] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.241303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.241320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.241336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.241352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.241356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.241371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.241374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.241390] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.241405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.241425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.241445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.241466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.241529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.241553] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.241576] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.241600] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.241627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.241656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.241716] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.241742] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.241766] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.241807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.241831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.241855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.241877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.241899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.241922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.241948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.241973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.241998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.242019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.242041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.242066] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.242090] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.244096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.244112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.244127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.244144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.245652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.245668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.245682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.247174] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.247190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.248996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.251934] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.252006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.252025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.252051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.268748] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.268774] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.268809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.268918] [drm:drm_mode_addfb2] [FB:75]
>[ 1267.268976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.285448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.285474] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.285564] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.304232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.304251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.304271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.304288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.304306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.304321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.304335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.304351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.304369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.304390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.304411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.304431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.304450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.304469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.304545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.304582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.304626] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.304652] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.304747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.304756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.304799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.304819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.304839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.304861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.304879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.304899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.304918] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.304938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.304957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.304976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.304994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.304999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.305017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.305021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.305040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.305059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.305078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.305096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.305115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.305133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.305152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.305171] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.305190] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.305209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.305230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.305274] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.305289] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.305304] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.305334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.305353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.305373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.305392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.305411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.305430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.305451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.305472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.305523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.305547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.305569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.305595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.305618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.307616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.307632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.307646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.307661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.309163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.309178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.309192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.310689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.310705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.312510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.315445] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.315550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.315578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.315662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.332260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.332286] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.332321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.332426] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.332530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.348941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.348966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.349002] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.367200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.367217] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.367237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.367255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.367275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.367293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.367310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.367328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.367348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.367367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.367386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.367404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.367421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.367438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.367464] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.367526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.367560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.367584] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.367692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.367701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.367742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.367760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.367779] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.367800] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.367817] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.367836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.367855] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.367873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.367892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.367909] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.367927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.367931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.367948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.367952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.367970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.367988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.368006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.368023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.368041] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.368059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.368077] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.368094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.368112] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.368131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.368151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.368192] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.368206] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.368220] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.368248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.368266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.368285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.368303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.368321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.368338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.368358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.368377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.368397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.368414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.368432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.368451] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.368469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.370474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.370504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.370521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.370539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.372053] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.372070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.372084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.373580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.373596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.375431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.378367] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.378440] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.378457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.378479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.395182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.395208] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.395244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.395354] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.395420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.411890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.411914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.411951] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.430239] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.430258] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.430278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.430295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.430313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.430328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.430343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.430359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.430377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.430393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.430409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.430425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.430439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.430453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.430480] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.430547] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.430581] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.430608] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.430732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.430746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.430814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.430838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.430864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.430893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.430916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.430941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.430964] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.430989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.431011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.431033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.431054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.431060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.431081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.431087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.431109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.431130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.431152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.431179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.431202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.431221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.431243] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.431265] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.431283] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.431306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.431331] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.431393] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.431415] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.431437] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.431473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.431513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.431536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.431557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.431579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.431600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.431625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.431651] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.431675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.431695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.431717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.431743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.431764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.433753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.433769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.433783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.433797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.435301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.435317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.435330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.436826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.436844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.438649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.441586] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.441659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.441676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.441698] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.458411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.458437] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.458474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.458711] [drm:drm_mode_addfb2] [FB:75]
>[ 1267.458777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.475082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.475107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.475147] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.493242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.493261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.493281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.493298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.493316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.493331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.493345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.493361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.493379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.493395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.493411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.493426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.493441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.493455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.493481] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.493549] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.493582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.493608] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.493731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.493746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.493814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.493837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.493864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.493893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.493915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.493940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.493964] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.493988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.494012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.494034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.494055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.494061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.494083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.494089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.494112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.494133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.494155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.494175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.494200] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.494221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.494243] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.494264] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.494285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.494311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.494337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.494405] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.494429] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.494452] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.494494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.494538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.494569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.494592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.494612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.494635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.494661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.494685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.494710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.494730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.494751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.494777] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.494798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.496788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.496804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.496818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.496833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.498340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.498356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.498370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.499866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.499881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.501686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.504624] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.504696] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.504713] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.504735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.521436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.521462] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.521535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.521738] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.521803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.538117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.538143] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.538180] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.556245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.556264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.556284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.556301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.556319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.556338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.556358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.556377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.556399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.556420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.556441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.556461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.556480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.556541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.556584] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.556619] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.556652] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.556678] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.556802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.556817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.556890] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.556912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.556937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.556963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.556983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.557007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.557028] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.557051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.557071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.557092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.557111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.557117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.557136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.557141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.557163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.557182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.557202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.557221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.557244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.557263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.557283] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.557302] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.557323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.557344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.557367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.557428] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.557449] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.557471] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.557526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.557548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.557571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.557592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.557614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.557635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.557660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.557684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.557709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.557729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.557750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.557776] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.557797] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.559786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.559802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.559816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.559830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.561334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.561350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.561363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.562859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.562875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.564679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.567580] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.567636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.567651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.567672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.584380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.584406] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.584441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.584662] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.584719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.601079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.601103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.601149] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.619988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.620006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.620027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.620043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.620061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.620076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.620091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.620107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.620124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.620141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.620156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.620172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.620186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.620200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.620227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.620249] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.620270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.620285] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.620398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.620409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.620456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.620477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.620499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.620561] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.620586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.620613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.620638] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.620662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.620685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.620708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.620729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.620736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.620757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.620764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.620786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.620807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.620831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.620853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.620878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.620899] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.620921] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.620944] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.620963] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.620980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.621001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.621044] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.621060] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.621075] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.621106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.621126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.621146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.621166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.621185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.621205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.621226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.621247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.621275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.621294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.621310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.621329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.621344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.623336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.623355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.623372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.623390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.624901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.624918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.624932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.626446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.626463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.628270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.631208] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.631279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.631295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.631318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.648020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.648046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.648081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.648189] [drm:drm_mode_addfb2] [FB:75]
>[ 1267.648246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.664701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.664725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.664771] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.682621] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.682639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.682660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.682677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.682694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.682709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.682724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.682740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.682758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.682775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.682791] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.682806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.682821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.682834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.682862] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.682884] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.682908] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.682924] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.683045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.683055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.683102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.683124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.683145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.683169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.683189] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.683210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.683230] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.683251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.683272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.683292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.683312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.683316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.683336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.683340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.683361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.683381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.683402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.683421] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.683442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.683462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.683482] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.683503] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.683568] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.683595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.683623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.683682] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.683704] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.683726] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.683769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.683794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.683818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.683842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.683861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.683879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.683897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.683913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.683928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.683943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.683957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.683975] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.683991] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.685979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.685996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.686010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.686025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.687558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.687574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.687588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.689088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.689104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.690914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.693861] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.693923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.693939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.693962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.710691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.710718] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.710756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.710870] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.710949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.727388] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.727412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.727450] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.746307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.746328] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.746350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.746370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.746392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.746411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.746431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.746450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.746472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.746493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.746559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.746589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.746612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.746636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.746679] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.746716] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.746750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.746777] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.746864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.746874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.746924] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.746940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.746956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.746977] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.746995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.747014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.747032] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.747050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.747068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.747100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.747117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.747120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.747135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.747138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.747153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.747167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.747181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.747194] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.747210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.747224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.747238] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.747251] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.747264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.747280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.747297] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.747340] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.747354] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.747366] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.747391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.747406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.747420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.747434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.747448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.747465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.747484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.747507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.747552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.747573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.747594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.747618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.747640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.749636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.749653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.749667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.749686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.751191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.751207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.751227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.752729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.752746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.754553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.757501] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.757563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.757580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.757602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.774311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.774336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.774370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.774479] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.774606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.791003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.791032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.791076] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.809265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.809285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.809305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.809322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.809339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.809355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.809369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.809386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.809407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.809428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.809449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.809469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.809488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.809508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.809587] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.809621] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.809646] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.809663] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.809769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.809783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.809851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.809870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.809904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.809925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.809942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.809959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.809976] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.809992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.810008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.810023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.810037] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.810042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.810056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.810061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.810075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.810089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.810103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.810129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.810145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.810158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.810172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.810185] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.810198] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.810213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.810230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.810265] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.810278] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.810292] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.810320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.810339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.810356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.810375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.810393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.810411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.810430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.810449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.810469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.810486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.810510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.810558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.810580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.812589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.812607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.812624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.812642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.814157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.814173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.814188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.815684] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.815701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.817509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.820457] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.820561] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.820589] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.820673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.837263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.837288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.837322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.837428] [drm:drm_mode_addfb2] [FB:75]
>[ 1267.837493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.853972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.853997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.854042] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.872219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.872238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.872258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.872276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.872293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.872309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.872324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.872340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.872358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.872375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.872390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.872406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.872421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.872435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.872462] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.872483] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.872504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.872560] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.872694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.872709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.872773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.872791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.872809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.872829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.872845] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.872862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.872880] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.872897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.872912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.872928] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.872942] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.872947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.872961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.872964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.872980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.872994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.873009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.873023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.873040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.873054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.873069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.873083] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.873097] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.873114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.873132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.873169] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.873184] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.873200] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.873230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.873250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.873271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.873291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.873310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.873330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.873351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.873379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.873397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.873415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.873432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.873451] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.873469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.875471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.875488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.875502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.875551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.877060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.877075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.877089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.878587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.878603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.880403] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.883345] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.883412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.883429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.883451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.900152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.900178] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.900213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.900322] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.900390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.916834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.916860] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.916906] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.935753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.935771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.935791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.935811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.935833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.935852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.935872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.935891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.935913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.935934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.935955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.935975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.935994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.936013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.936040] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.936063] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.936088] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.936105] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.936220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.936230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1267.936277] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1267.936297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1267.936316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1267.936337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1267.936354] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1267.936372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1267.936391] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1267.936407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1267.936424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1267.936440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1267.936455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1267.936459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.936474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1267.936477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1267.936493] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1267.936508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1267.936559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1267.936580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1267.936606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1267.936627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1267.936649] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1267.936670] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1267.936691] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1267.936716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.936742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1267.936815] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1267.936839] [drm:intel_power_well_enable [i915]] enabling display
>[ 1267.936861] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1267.936902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.936922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.936942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.936962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.936982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.937002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.937024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.937045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.937066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.937085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.937104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.937124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1267.937144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1267.939143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1267.939161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1267.939179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.939197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1267.940708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1267.940725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1267.940739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1267.942235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1267.942252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1267.944059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1267.946983] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1267.947016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1267.947032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1267.947054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1267.963755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.963780] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.963814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.963919] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.963976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1267.980461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1267.980486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1267.980567] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1267.999408] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1267.999427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1267.999447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1267.999464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1267.999481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1267.999497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1267.999511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1267.999570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1267.999600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1267.999628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1267.999655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1267.999680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1267.999702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1267.999725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1267.999769] [drm:intel_power_well_disable [i915]] disabling display
>[ 1267.999803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1267.999834] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1267.999861] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1267.999977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1267.999993] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.000058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.000077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.000096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.000116] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.000135] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.000155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.000174] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.000193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.000219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.000234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.000248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.000251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.000265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.000268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.000283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.000306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.000327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.000340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.000356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.000369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.000383] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.000396] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.000409] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.000425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.000441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.000485] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.000499] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.000512] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.000587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.000612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.000636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.000660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.000683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.000708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.000735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.000760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.000785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.000809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.000831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.000858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.000882] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.003121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.003139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.003154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.003169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.004675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.004690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.004703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.006195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.006211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.008035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.010973] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.011045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.011064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.011090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.027787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.027813] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.027848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.027956] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.028021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.044475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.044497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.044579] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.063450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.063468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.063489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.063506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.063566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.063590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.063616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.063641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.063670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.063697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.063723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.063749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.063770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.063793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.063836] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.063870] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.063902] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.063927] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.064047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.064057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.064104] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.064123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.064143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.064163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.064180] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.064198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.064216] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.064233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.064250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.064266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.064281] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.064285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.064300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.064304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.064319] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.064335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.064350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.064364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.064382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.064397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.064412] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.064432] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.064452] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.064474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.064496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.064599] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.064620] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.064640] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.064681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.064705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.064727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.064750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.064771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.064794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.064819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.064843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.064867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.064889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.064910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.064935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.064959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.066940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.066956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.066970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.066985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.068490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.068506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.068520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.070039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.070056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.071873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.074820] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.074883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.074900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.074922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.091626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.091652] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.091688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.091799] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.091865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.108305] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.108330] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.108375] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.127243] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.127262] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.127283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.127300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.127317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.127332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.127347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.127363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.127380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.127397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.127412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.127428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.127442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.127456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.127483] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.127505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.127526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.127588] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.127861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.127883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.127948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.127972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.127998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.128025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.128047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.128071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.128095] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.128118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.128141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.128162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.128183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.128188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.128209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.128214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.128236] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.128257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.128278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.128299] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.128320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.128341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.128362] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.128381] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.128402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.128423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.128448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.128511] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.128555] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.128577] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.128616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.128640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.128664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.128687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.128710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.128734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.128759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.128784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.128808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.128829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.128851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.128877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.129105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.131134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.131150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.131164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.131178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.132687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.132702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.132716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.134207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.134223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.136038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.138981] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.139047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.139071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.139091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.155781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.155806] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.155840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.155945] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.156009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.172469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.172495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.172578] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.191418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.191437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.191457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.191475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.191493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.191508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.191523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.191578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.191608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.191636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.191663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.191688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.191711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.191734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.191778] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.191813] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.191845] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.191870] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.191999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.192016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.192086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.192104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.192123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.192144] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.192160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.192177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.192194] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.192217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.192231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.192245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.192258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.192261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.192274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.192277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.192290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.192303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.192316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.192328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.192344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.192360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.192378] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.192396] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.192413] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.192432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.192451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.192497] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.192511] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.192526] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.192590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.192615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.192640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.192664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.192687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.192712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.192737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.192762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.192816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.192838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.192860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.192885] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.192909] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.194905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.194924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.194941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.194959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.196478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.196495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.196510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.198033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.198048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.199881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.202832] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.202890] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.202907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.202929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.219633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.219659] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.219694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.219801] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.219868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.236335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.236359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.236404] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.255243] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.255262] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.255282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.255299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.255317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.255332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.255347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.255363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.255381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.255397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.255413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.255429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.255443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.255457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.255484] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.255506] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.255527] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.255588] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.255714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.255728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.255805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.255827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.255851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.255878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.255899] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.255923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.255945] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.255967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.255987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.256008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.256027] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.256033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.256052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.256057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.256079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.256098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.256119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.256138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.256159] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.256179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.256198] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.256218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.256237] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.256260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.256285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.256347] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.256369] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.256390] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.256428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.256448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.256469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.256489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.256509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.256529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.256570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.256595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.256619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.256639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.256659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.256684] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.256706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.258699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.258715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.258729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.258743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.260247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.260265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.260282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.261784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.261801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.263604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.266533] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.266613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.266630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.266652] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.283354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.283380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.283416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.283555] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.283645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.300050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.300073] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.300119] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.318968] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.318988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.319008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.319025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.319043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.319059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.319074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.319091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.319108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.319125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.319140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.319156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.319170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.319184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.319211] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.319233] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.319254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.319269] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.319382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.319392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.319439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.319460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.319482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.319505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.319525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.319583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.319612] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.319639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.319665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.319690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.319715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.319722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.319744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.319751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.319775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.319799] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.319824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.319847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.319875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.319898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.319923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.319947] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.319971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.319999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.320027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.320101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.320125] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.320149] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.320191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.320216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.320242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.320266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.320290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.320315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.320342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.320368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.320395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.320418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.320440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.320466] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.320492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.322527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.322555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.322570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.322586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.324102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.324118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.324132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.325633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.325650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.327484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.330426] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.330494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.330511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.330533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.347235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.347261] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.347296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.347401] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.347465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.363916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.363940] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.363986] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.382823] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.382842] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.382863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.382880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.382897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.382913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.382928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.382944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.382965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.382986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.383007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.383027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.383046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.383065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.383093] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.383116] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.383141] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.383157] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.383279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.383289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.383336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.383357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.383378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.383409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.383426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.383445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.383463] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.383480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.383496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.383511] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.383526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.383569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.383594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.383601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.383625] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.383648] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.383672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.383695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.383722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.383745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.383769] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.383792] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.383815] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.383842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.383869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.383942] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.383966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.383989] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.384029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.384054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.384077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.384100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.384122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.384146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.384173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.384198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.384223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.384246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.384268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.384295] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.384319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.386323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.386339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.386353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.386368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.387879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.387894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.387908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.389404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.389419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.391245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.394174] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.394203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.394220] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.394242] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.410946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.410972] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.411007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.411114] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.411179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.427627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.427652] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.427697] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.446543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.446579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.446600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.446617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.446634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.446649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.446664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.446680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.446698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.446715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.446730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.446746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.446760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.446774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.446801] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.446822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.446843] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.446859] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.446977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.446988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.447034] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.447053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.447073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.447097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.447117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.447138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.447159] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.447179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.447200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.447220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.447240] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.447245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.447264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.447268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.447288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.447309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.447329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.447349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.447370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.447390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.447410] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.447431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.447451] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.447472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.447494] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.447543] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.447604] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.447632] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.447676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.447703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.447729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.447755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.447780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.447806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.447835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.447862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.447889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.447913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.447937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.447964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.447990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.450333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.450350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.450365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.450383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.451891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.451909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.451926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.453421] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.453438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.455242] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.458164] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.458199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.458216] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.458238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.474943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.474969] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.475004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.475120] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.475186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.491623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.491649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.491695] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.510577] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.510596] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.510616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.510633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.510650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.510665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.510680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.510696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.510714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.510730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.510746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.510762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.510776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.510790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.510817] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.510840] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.510865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.510881] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.511004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.511014] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.511062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.511082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.511102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.511126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.511146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.511167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.511187] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.511208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.511229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.511249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.511269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.511273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.511293] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.511296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.511317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.511337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.511358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.511378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.511399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.511419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.511439] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.511459] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.511480] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.511501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.511523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.511621] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.511646] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.511671] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.511715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.511740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.511766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.511789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.511814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.511838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.511865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.511892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.511919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.511940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.511962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.511991] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.512015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.514029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.514046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.514061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.514076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.515614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.515630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.515644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.517140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.517156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.518966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.521909] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.521976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.521993] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.522015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.538715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.538740] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.538774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.538876] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.538944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.555396] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.555419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.555455] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.573430] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.573449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.573469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.573487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.573504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.573519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.573535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.573553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.573618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.573647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.573673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.573699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.573721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.573744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.573789] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.573823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.573855] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.573880] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.574012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.574027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.574093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.574113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.574133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.574156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.574175] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.574194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.574213] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.574233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.574252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.574271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.574290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.574294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.574312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.574316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.574335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.574355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.574374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.574392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.574411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.574430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.574449] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.574468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.574487] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.574507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.574527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.574622] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.574646] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.574669] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.574710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.574735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.574759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.574782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.574805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.574828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.574854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.574878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.574902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.574924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.574946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.574970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.574993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.576994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.577011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.577025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.577040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.578545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.578573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.578588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.580086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.580103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.581914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.584859] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.584923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.584943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.584968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.601666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.601692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.601727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.601834] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.601891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.618346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.618370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.618406] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.636257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.636276] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.636296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.636313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.636331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.636347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.636362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.636378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.636395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.636412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.636428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.636443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.636458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.636471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.636498] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.636520] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.636541] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.636597] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.636718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.636732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.636802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.636820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.636846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.636864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.636880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.636899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.636917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.636935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.636953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.636971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.636988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.636993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.637010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.637014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.637032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.637050] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.637068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.637085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.637104] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.637121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.637140] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.637157] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.637175] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.637194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.637213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.637250] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.637264] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.637278] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.637307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.637325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.637343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.637361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.637379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.637397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.637417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.637436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.637456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.637473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.637491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.637509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.637527] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.639537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.639553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.639594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.639619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.641129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.641144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.641158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.642660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.642676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.644506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.647443] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.647515] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.647532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.647554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.664255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.664281] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.664316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.664424] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.664481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.680937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.680961] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.680998] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.698643] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.698662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.698682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.698700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.698717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.698733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.698747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.698763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.698781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.698797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.698813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.698828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.698842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.698856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.698883] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.698905] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.698926] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.698941] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.699061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.699071] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.699124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.699143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.699162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.699182] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.699199] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.699217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.699234] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.699251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.699270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.699290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.699310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.699314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.699333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.699337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.699357] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.699376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.699396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.699416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.699436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.699455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.699475] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.699494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.699514] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.699534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.699556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.699664] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.699686] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.699707] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.699749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.699775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.699797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.699819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.699842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.699862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.699880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.699896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.699912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.699926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.699940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.699957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.699973] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.701952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.701969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.701983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.701998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.703508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.703524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.703538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.705070] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.705086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.706987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.709586] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.709642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.709658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.709680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.726384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.726411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.726446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.726664] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.726736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.743084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.743108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.743144] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.761987] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.762006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.762026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.762043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.762060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.762075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.762090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.762106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.762124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.762140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.762156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.762172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.762186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.762200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.762227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.762249] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.762270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.762285] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.762412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.762421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.762467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.762486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.762505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.762527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.762546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.762567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.762618] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.762643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.762666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.762688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.762709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.762715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.762736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.762742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.762763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.762784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.762805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.762826] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.762849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.762870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.762891] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.762912] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.762932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.762957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.762983] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.763214] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.763230] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.763243] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.763272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.763288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.763304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.763318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.763333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.763348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.763369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.763394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.763409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.763423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.763436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.763452] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.763467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.765440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.765458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.765475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.765494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.767014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.767031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.767046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.768543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.768559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.770395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.773332] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.773404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.773421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.773443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.790147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.790173] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.790208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.790316] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.790380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.806848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.806873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.806908] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.825748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.825766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.825793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.825811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.825829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.825844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.825859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.825875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.825893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.825909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.825926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.825942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.825956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.825970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.825998] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.826028] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.826053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.826069] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.826193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.826203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.826250] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.826270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.826290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.826312] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.826329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.826347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.826365] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.826382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.826399] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.826419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.826439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.826443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.826463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.826467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.826487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.826508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.826529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.826555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.826633] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.826651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.826667] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.826682] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.826697] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.826714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.826732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.826778] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.826792] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.826806] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.826834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.826850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.826865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.826880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.826894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.826909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.826926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.826942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.826958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.826972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.826986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.827003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.827019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.829029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.829047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.829061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.829076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.830600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.830615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.830629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.832134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.832150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.833979] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.836925] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.836995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.837014] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.837040] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.853730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.853758] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.853796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.853905] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.853973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.870411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.870435] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.870471] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.889339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.889366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.889386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.889403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.889421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.889437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.889452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.889468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.889486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.889502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.889518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.889534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.889548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.889561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.889648] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.889684] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.889716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.889743] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.889873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.889890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.889970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.889993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.890018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.890045] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.890066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.890089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.890111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.890134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.890154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.890175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.890195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.890200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.890220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.890225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.890246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.890265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.890286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.890305] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.890327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.890346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.890367] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.890386] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.890406] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.890427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.890451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.890506] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.890528] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.890550] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.890612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.890635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.890655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.890678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.890698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.890721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.890746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.890771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.890795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.890815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.890837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.890863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.890885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.892880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.892896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.892910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.892926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.894432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.894448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.894462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.895966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.895984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.897789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.900721] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.900747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.900763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.900785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.917490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.917516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.917553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.917778] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.917843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.934170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.934194] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.934231] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1268.952304] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1268.952322] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1268.952342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.952359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.952377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.952393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.952408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.952424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.952442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.952458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.952474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.952490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.952509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.952528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.952556] [drm:intel_power_well_disable [i915]] disabling display
>[ 1268.952623] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1268.952661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.952688] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1268.952809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1268.952826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1268.952900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1268.952925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1268.952953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1268.952983] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1268.953006] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1268.953032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1268.953056] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1268.953080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1268.953103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1268.953126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1268.953147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1268.953153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.953174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1268.953179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1268.953202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1268.953224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1268.953253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1268.953272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1268.953295] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1268.953314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1268.953335] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1268.953354] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1268.953374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1268.953395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.953419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1268.953486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1268.953508] [drm:intel_power_well_enable [i915]] enabling display
>[ 1268.953530] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1268.953567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1268.953608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1268.953632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1268.953653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1268.953675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1268.953696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1268.953721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1268.953745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1268.953770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.953790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1268.953810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1268.953836] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1268.953858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1268.955852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1268.955869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1268.955885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.955903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1268.957409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1268.957427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1268.957444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1268.958942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1268.958959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1268.960765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1268.963712] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1268.963774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1268.963791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1268.963814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1268.980517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1268.980544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1268.980582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1268.980807] [drm:drm_mode_addfb2] [FB:75]
>[ 1268.980865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1268.997216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1268.997240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1268.997277] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.015331] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.015350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.015370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.015387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.015405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.015420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.015439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.015459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.015481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.015501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.015522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.015542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.015561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.015580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.015658] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.015693] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.015734] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.015759] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.015867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.015883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.015954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.015978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.016004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.016032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.016053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.016078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.016101] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.016123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.016145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.016166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.016186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.016191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.016212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.016218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.016239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.016259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.016280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.016300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.016324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.016343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.016364] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.016384] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.016405] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.016427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.016453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.016520] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.016543] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.016564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.016630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.016655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.016677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.016701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.016721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.016752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.016777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.016801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.016826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.016846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.016867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.016893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.016915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.018909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.018926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.018948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.018965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.020473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.020489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.020503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.022009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.022027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.023833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.026779] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.026842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.026859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.026881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.043584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.043622] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.043658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.043767] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.043831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.060265] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.060291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.060329] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.078361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.078380] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.078400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.078417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.078435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.078454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.078473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.078493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.078515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.078535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.078556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.078576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.078638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.078668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.078714] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.078749] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.078782] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.078808] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.078934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.078951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.079030] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.079053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.079079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.079105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.079126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.079150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.079172] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.079195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.079216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.079237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.079256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.079262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.079282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.079287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.079308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.079328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.079348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.079367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.079390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.079409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.079430] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.079449] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.079470] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.079491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.079516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.079583] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.079625] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.079649] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.079687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.079711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.079732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.079755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.079775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.079799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.079824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.079849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.079874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.079894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.079916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.079940] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.079963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.081956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.081972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.081986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.082001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.083529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.083544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.083558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.085060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.085079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.086884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.089814] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.089841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.089858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.089880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.106582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.106628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.106666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.106795] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.106860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.123286] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.123311] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.123348] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.141340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.141359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.141379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.141396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.141414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.141429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.141443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.141459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.141477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.141494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.141510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.141526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.141541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.141555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.141582] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.141655] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.141687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.141715] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.141841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.141859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.141933] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.141960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.141986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.142014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.142037] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.142063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.142087] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.142111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.142134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.142157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.142178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.142184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.142213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.142218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.142239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.142259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.142279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.142298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.142321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.142340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.142361] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.142380] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.142401] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.142422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.142446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.142514] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.142536] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.142558] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.142619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.142644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.142665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.142688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.142708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.142731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.142757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.142782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.142806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.142826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.142848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.142873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.142895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.144892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.144909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.144923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.144938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.146442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.146457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.146475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.147970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.147987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.149791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.152729] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.152802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.152821] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.152847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.169542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.169568] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.169652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.169797] [drm:drm_mode_addfb2] [FB:75]
>[ 1269.169876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.186235] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.186259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.186294] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.203482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.203500] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.203522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.203542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.203564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.203583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.203646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.203676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.203708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.203736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.203763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.203790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.203813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.203837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.203881] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.203916] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.203948] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.203974] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.204090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.204101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.204151] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.204170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.204188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.204210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.204230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.204249] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.204269] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.204288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.204308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.204327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.204345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.204349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.204368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.204372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.204391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.204418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.204434] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.204449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.204465] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.204482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.204500] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.204517] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.204534] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.204553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.204572] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.204653] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.204677] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.204699] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.204740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.204763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.204787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.204808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.204830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.204851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.204876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.204901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.204924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.204944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.204964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.204989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.205010] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.207007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.207024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.207041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.207059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.208566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.208585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.208637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.210143] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.210162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.212023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.214974] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.215033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.215049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.215071] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.231774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.231802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.231839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.231962] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.232038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.248467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.248490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.248525] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.267388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.267407] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.267427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.267444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.267462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.267477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.267491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.267508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.267525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.267542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.267557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.267573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.267587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.267646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.267689] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.267724] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.267756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.267782] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.267910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.267924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.267989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.268013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.268039] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.268066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.268088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.268113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.268137] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.268160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.268184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.268205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.268227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.268233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.268254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.268259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.268281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.268302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.268324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.268345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.268367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.268388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.268409] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.268430] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.268452] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.268474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.268498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.268551] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.268574] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.268596] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.268653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.268677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.268700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.268723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.268746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.268769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.268796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.268820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.268844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.268866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.268888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.268914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.268937] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.270929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.270945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.270959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.270973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.272478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.272494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.272507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.274004] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.274019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.275824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.278766] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.278834] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.278854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.278880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.295574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.295600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.295689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.295826] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.295891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.312267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.312290] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.312325] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.331158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.331179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.331201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.331221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.331242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.331262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.331281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.331301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.331323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.331343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.331364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.331383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.331402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.331421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.331449] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.331472] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.331497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.331513] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.331637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.331654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.331729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.331754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.331782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.331811] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.331834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.331859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.331884] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.331909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.331931] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.331954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.331975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.331981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.332003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.332009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.332032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.332053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.332075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.332096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.332121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.332142] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.332165] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.332186] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.332208] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.332231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.332258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.332317] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.332341] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.332371] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.332408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.332429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.332450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.332470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.332490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.332511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.332535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.332558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.332581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.332601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.332639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.332665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.332687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.334683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.334700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.334718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.334736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.336242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.336258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.336272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.337769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.337785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.339589] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.342537] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.342647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.342673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.342707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.359352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.359380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.359417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.359526] [drm:drm_mode_addfb2] [FB:75]
>[ 1269.359604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.376045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.376069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.376104] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.394958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.394977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.394997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.395014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.395032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.395047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.395062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.395078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.395095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.395111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.395127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.395142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.395156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.395170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.395198] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.395219] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.395240] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.395256] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.395375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.395385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.395433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.395452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.395475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.395505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.395525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.395543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.395560] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.395575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.395591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.395646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.395669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.395678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.395700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.395707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.395731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.395753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.395776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.395797] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.395824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.395845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.395869] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.395890] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.395914] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.395941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.395969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.396030] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.396054] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.396079] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.396122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.396148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.396172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.396196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.396219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.396243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.396270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.396296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.396322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.396344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.396364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.396391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.396414] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.398427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.398444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.398459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.398474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.399980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.399996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.400010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.401503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.401521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.403327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.406253] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.406284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.406300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.406322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.423027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.423053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.423088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.423209] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.423283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.439720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.439744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.439778] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.458642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.458662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.458682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.458699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.458717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.458736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.458756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.458775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.458797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.458818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.458838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.458859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.458878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.458896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.458925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.458947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.458972] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.458989] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.459114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.459124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.459169] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.459189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.459209] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.459231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.459250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.459270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.459289] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.459308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.459328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.459346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.459365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.459369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.459387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.459391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.459411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.459430] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.459449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.459468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.459487] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.459505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.459525] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.459544] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.459563] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.459582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.459603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.459684] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.459708] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.459731] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.459773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.459796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.459821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.459842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.459865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.459888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.459913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.459938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.459970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.459991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.460013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.460039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.460061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.462078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.462096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.462110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.462127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.463657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.463672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.463686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.465184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.465202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.467024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.469958] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.470033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.470049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.470074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.486776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.486802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.486837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.486948] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.487029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.503468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.503491] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.503526] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.522373] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.522392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.522413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.522430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.522447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.522463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.522477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.522494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.522512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.522528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.522545] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.522561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.522575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.522589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.522664] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.522700] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.522735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.522761] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.522885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.522899] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.522969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.522995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.523022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.523052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.523077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.523103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.523129] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.523154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.523179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.523203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.523226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.523232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.523254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.523261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.523285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.523308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.523332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.523355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.523380] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.523411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.523433] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.523454] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.523474] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.523497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.523522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.523574] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.523597] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.523634] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.523675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.523699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.523722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.523745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.523767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.523791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.523816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.523841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.523865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.523887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.523909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.523935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.523959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.525948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.525963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.525978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.525992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.527499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.527514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.527528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.529024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.529040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.530844] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.533781] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.533852] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.533868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.533890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.550594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.550666] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.550720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.550840] [drm:drm_mode_addfb2] [FB:75]
>[ 1269.550913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.567297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.567321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.567357] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.586206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.586225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.586245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.586262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.586283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.586303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.586323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.586342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.586364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.586385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.586405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.586426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.586444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.586463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.586491] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.586514] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.586539] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.586555] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.586682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.586699] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.586775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.586808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.586833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.586860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.586881] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.586904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.586926] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.586949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.586970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.586991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.587011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.587016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.587036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.587041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.587062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.587081] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.587102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.587121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.587144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.587162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.587183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.587202] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.587222] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.587243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.587267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.587334] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.587356] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.587379] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.587416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.587437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.587458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.587477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.587498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.587518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.587542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.587565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.587589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.587608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.587653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.587679] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.587700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.589697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.589714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.589729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.589744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.591246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.591262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.591275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.592770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.592786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.594590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.597530] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.597599] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.597650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.597689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.614343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.614369] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.614404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.614506] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.614568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.631022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.631046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.631082] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.649128] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.649148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.649171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.649191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.649212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.649232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.649251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.649271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.649292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.649313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.649334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.649353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.649373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.649392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.649420] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.649442] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.649467] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.649483] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.649582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.649593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.649692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.649719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.649749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.649779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.649803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.649830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.649856] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.649881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.649906] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.649931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.649954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.649960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.649982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.649988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.650012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.650035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.650058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.650081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.650107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.650131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.650154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.650185] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.650206] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.650230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.650256] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.650325] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.650347] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.650370] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.650407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.650430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.650461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.650484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.650506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.650530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.650555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.650579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.650603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.650640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.650662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.650688] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.650712] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.652718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.652736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.652750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.652766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.654269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.654284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.654298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.655793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.655809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.657610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.659595] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.659710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.659728] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.659752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.676411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.676435] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.676469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.676581] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.676709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.693092] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.693116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.693162] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.712023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.712042] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.712062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.712079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.712097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.712113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.712128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.712144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.712161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.712178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.712193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.712213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.712232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.712251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.712280] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.712303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.712328] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.712344] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.712473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.712483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.712528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.712546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.712565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.712585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.712601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.712617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.712664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.712690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.712713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.712737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.712758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.712765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.712786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.712792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.712815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.712836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.712858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.712878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.712903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.712923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.712945] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.712966] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.712988] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.713013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.713040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.713096] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.713119] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.713141] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.713179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.713201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.713223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.713243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.713264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.713285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.713310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.713333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.713357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.713377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.713397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.713420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.713443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.715449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.715465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.715479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.715493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.717012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.717029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.717044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.718576] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.718593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.720400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.723336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.723410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.723427] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.723449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.740151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.740179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.740216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.740326] [drm:drm_mode_addfb2] [FB:75]
>[ 1269.740394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.756833] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.756858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.756895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.775688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.775707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.775729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.775749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.775771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.775790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.775810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.775829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.775851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.775872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.775892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.775912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.775931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.775950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.775977] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.776000] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.776025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.776042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.776163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.776173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.776220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.776240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.776260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.776281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.776298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.776317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.776335] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.776352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.776370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.776386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.776401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.776405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.776420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.776424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.776439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.776459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.776479] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.776500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.776520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.776540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.776561] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.776581] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.776602] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.776623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.776690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.776764] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.776790] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.776814] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.776857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.776881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.776906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.776929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.776953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.776976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.777002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.777028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.777055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.777076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.777099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.777126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.777149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.779168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.779184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.779198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.779212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.780734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.780752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.780766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.782260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.782277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.784082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.787037] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.787091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.787110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.787135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.803834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.803860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.803897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.804008] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.804077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.820524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.820547] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.820582] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.839417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.839436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.839456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.839473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.839491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.839506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.839520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.839536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.839554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.839571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.839587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.839602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.839617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.839676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.839719] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.839754] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.839786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.839811] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.839935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.839950] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.840018] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.840042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.840076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.840102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.840123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.840146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.840168] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.840190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.840211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.840232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.840251] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.840256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.840276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.840281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.840302] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.840321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.840341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.840360] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.840383] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.840401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.840422] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.840441] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.840461] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.840482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.840506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.840568] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.840590] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.840611] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.840699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.840721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.840744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.840765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.840787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.840808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.840833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.840857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.840881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.840903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.840923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.840947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.840968] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.842955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.842971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.842987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.843006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.844510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.844527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.844544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.846040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.846058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.847861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.850290] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.850363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.850379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.850400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.867094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.867118] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.867152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.867253] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.867316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.883787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.883811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.883847] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.901752] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.901771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.901791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.901808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.901829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.901849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.901868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.901888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.901909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.901930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.901951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.901971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.901990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.902008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.902037] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.902060] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.902085] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.902101] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.902226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.902237] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.902284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.902303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.902323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.902352] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.902368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.902386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.902404] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.902421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.902438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.902456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.902475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.902479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.902499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.902502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.902522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.902542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.902562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.902581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.902601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.902621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.902677] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.902705] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.902728] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.902756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.902784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.902856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.902879] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.902902] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.902942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.902964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.902987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.903008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.903031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.903052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.903078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.903102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.903126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.903146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.903169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.903193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.903216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.905222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.905241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.905258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.905276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.906794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.906811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.906825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.908318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.908337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.910142] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.913100] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.913152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.913169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.913191] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.929894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.929920] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.929955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.930063] [drm:drm_mode_addfb2] [FB:75]
>[ 1269.930130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.946575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1269.946599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1269.946635] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1269.965527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1269.965546] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1269.965566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.965583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.965601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.965616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.965631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.965690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.965720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.965748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.965775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.965801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.965826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.965846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.965874] [drm:intel_power_well_disable [i915]] disabling display
>[ 1269.965897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1269.965923] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.965939] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1269.966038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1269.966052] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1269.966119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1269.966144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1269.966171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1269.966200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1269.966223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1269.966248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1269.966273] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1269.966297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1269.966321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1269.966343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1269.966365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1269.966371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.966393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1269.966398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1269.966421] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1269.966443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1269.966465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1269.966486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1269.966511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1269.966533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1269.966555] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1269.966576] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1269.966598] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1269.966622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1269.966789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1269.966850] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1269.966872] [drm:intel_power_well_enable [i915]] enabling display
>[ 1269.966893] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1269.966931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1269.966954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1269.966976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1269.966998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1269.967020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1269.967042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1269.967067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1269.967091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1269.967115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.967136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1269.967156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1269.967175] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1269.967193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1269.969191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1269.969208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1269.969223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.969238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1269.970763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1269.970780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1269.970795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1269.972295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1269.972313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1269.974132] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1269.977089] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1269.977142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1269.977162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1269.977188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1269.993884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1269.993910] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1269.993945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1269.994052] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.994110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.010557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.010581] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.010616] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.029482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.029502] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.029522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.029538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.029556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.029571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.029585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.029601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.029623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.029685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.029713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.029738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.029761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.029784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.029828] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.029865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.029899] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.029925] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.030011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.030021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.030065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.030085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.030113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.030132] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.030147] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.030163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.030179] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.030195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.030209] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.030224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.030237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.030241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.030254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.030257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.030270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.030283] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.030301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.030318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.030336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.030354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.030372] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.030389] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.030407] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.030427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.030447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.030482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.030496] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.030510] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.030538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.030556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.030574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.030592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.030610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.030628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.030681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.030707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.030731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.030751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.030771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.030796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.030817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.032814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.032830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.032844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.032859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.034363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.034379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.034392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.035887] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.035903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.037707] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.040636] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.040717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.040734] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.040755] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.057457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.057485] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.057522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.057665] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.057767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.074138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.074162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.074200] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.093032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.093052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.093071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.093088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.093105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.093120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.093135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.093151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.093168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.093184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.093200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.093216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.093230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.093244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.093271] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.093293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.093314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.093329] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.093449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.093459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.093506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.093526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.093546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.093567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.093584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.093602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.093620] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.093639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.093696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.093720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.093746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.093753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.093776] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.093783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.093807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.093831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.093856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.093880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.093907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.093930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.093955] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.093979] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.094003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.094030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.094058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.094118] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.094143] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.094167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.094208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.094232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.094256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.094278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.094301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.094323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.094350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.094376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.094408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.094430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.094451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.094476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.094499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.096498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.096515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.096529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.096543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.098058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.098075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.098090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.099595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.099612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.101417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.104341] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.104375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.104391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.104412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.121106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.121130] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.121163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.121268] [drm:drm_mode_addfb2] [FB:75]
>[ 1270.121331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.137805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.137829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.137866] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.155753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.155772] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.155792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.155809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.155827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.155842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.155857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.155873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.155890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.155910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.155931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.155952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.155971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.155990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.156018] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.156041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.156066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.156082] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.156203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.156213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.156261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.156280] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.156300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.156321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.156338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.156356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.156374] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.156394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.156415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.156435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.156456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.156459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.156480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.156483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.156504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.156524] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.156545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.156565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.156585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.156605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.156625] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.156646] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.156713] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.156743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.156773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.156835] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.156858] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.156883] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.156926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.156952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.156977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.157003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.157027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.157052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.157079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.157107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.157132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.157156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.157179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.157206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.157231] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.159252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.159270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.159285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.159300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.160808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.160824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.160837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.162331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.162347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.164153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.167200] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.167263] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.167279] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.167301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.184004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.184030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.184065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.184167] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.184237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.200685] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.200709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.200745] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.219596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.219615] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.219635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.219652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.219714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.219738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.219763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.219787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.219816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.219842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.219868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.219894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.219915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.219938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.219981] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.220015] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.220047] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.220072] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.220204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.220214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.220262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.220281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.220301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.220323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.220340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.220360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.220381] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.220401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.220422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.220442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.220462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.220466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.220486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.220489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.220510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.220530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.220551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.220571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.220591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.220611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.220631] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.220652] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.220708] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.220739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.220769] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.220834] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.220856] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.220879] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.220918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.220942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.220966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.220990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.221012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.221033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.221057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.221081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.221104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.221124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.221145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.221170] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.221192] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.223191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.223208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.223223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.223238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.224760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.224776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.224790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.226284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.226300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.228106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.231057] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.231115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.231132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.231154] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.247857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.247884] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.247922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.248022] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.248094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.264538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.264562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.264598] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.283447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.283466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.283487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.283504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.283522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.283537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.283552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.283568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.283586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.283603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.283619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.283634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.283648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.283706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.283749] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.283785] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.283817] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.283843] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.283974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.283991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.284065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.284092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.284120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.284150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.284174] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.284208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.284233] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.284257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.284280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.284303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.284325] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.284331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.284352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.284358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.284380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.284401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.284423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.284443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.284466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.284488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.284510] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.284530] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.284551] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.284575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.284601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.284656] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.284709] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.284733] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.284774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.284799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.284822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.284846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.284869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.284894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.284921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.284975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.285000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.285023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.285046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.285072] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.285095] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.287109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.287127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.287142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.287157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.288676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.288694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.288711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.290208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.290225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.292054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.295005] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.295064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.295081] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.295103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.311806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.311833] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.311868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.311971] [drm:drm_mode_addfb2] [FB:75]
>[ 1270.312033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.328508] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.328533] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.328569] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.347438] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.347457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.347477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.347494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.347512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.347531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.347550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.347570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.347591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.347612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.347633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.347653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.347714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.347739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.347784] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.347819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.347852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.347877] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.347989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.348003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.348071] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.348095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.348122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.348151] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.348174] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.348199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.348223] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.348247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.348269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.348292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.348313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.348319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.348342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.348347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.348371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.348392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.348414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.348434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.348460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.348481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.348511] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.348530] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.348551] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.348572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.348596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.348647] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.348686] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.348708] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.348746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.348767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.348790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.348811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.348833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.348854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.348879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.348904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.348929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.348949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.348970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.348997] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.349018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.351005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.351021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.351035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.351049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.352553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.352569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.352584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.354080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.354096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.355901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.358846] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.358910] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.358926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.358948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.375651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.375694] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.375729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.375836] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.375900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.392354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.392380] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.392418] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.410418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.410437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.410457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.410474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.410492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.410507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.410522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.410538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.410556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.410572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.410589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.410604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.410619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.410633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.410660] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.410727] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.410761] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.410789] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.410912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.410926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.411003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.411024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.411049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.411075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.411096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.411120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.411141] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.411163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.411183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.411204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.411222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.411228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.411247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.411252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.411273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.411292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.411313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.411332] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.411355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.411374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.411395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.411414] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.411434] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.411455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.411479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.411542] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.411564] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.411586] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.411622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.411643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.411665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.411701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.411724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.411745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.411771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.411795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.411819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.411839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.411860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.411885] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.411907] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.413896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.413913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.413931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.413949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.415457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.415473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.415488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.416985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.417004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.418812] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.421757] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.421822] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.421839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.421861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.438563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.438589] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.438624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.438798] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.438894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.455264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.455288] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.455324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.473226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.473245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.473265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.473282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.473300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.473315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.473330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.473346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.473364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.473380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.473396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.473412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.473426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.473440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.473467] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.473488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.473509] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.473525] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.473628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.473640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.473744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.473772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.473802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.473831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.473856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.473883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.473909] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.473935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.473960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.473984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.474008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.474014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.474036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.474042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.474066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.474089] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.474112] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.474135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.474161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.474184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.474214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.474235] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.474257] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.474281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.474306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.474361] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.474383] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.474405] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.474442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.474465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.474488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.474510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.474532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.474555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.474580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.474604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.474627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.474647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.474667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.474709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.474733] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.476727] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.476744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.476760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.476779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.478294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.478312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.478326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.479825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.479841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.481650] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.484613] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.484659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.484719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.484757] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.501431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.501458] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.501493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.501593] [drm:drm_mode_addfb2] [FB:75]
>[ 1270.501661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.518100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.518126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.518175] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.537035] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.537054] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.537074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.537091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.537109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.537124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.537138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.537155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.537172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.537189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.537205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.537221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.537235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.537249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.537276] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.537298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.537319] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.537335] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.537465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.537475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.537521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.537539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.537560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.537583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.537602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.537623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.537643] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.537662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.537726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.537750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.537772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.537779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.537800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.537838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.537862] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.537885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.537907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.537928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.537954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.537972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.537987] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.538001] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.538015] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.538031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.538049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.538088] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.538102] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.538117] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.538142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.538158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.538172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.538187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.538201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.538220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.538241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.538262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.538282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.538300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.538319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.538339] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.538355] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.540338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.540355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.540370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.540384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.541891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.541906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.541921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.543415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.543431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.545238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.548177] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.548247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.548264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.548285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.564999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.565023] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.565057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.565168] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.565234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.581669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.581715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.581750] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.600580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.600599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.600619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.600636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.600653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.600669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.600727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.600752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.600782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.600809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.600836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.600862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.600883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.600906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.600950] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.600984] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.601016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.601041] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.601168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.601179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.601225] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.601243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.601261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.601281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.601296] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.601314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.601331] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.601350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.601370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.601389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.601407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.601411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.601430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.601434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.601453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.601472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.601491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.601510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.601529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.601548] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.601567] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.601586] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.601605] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.601625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.601646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.601739] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.601763] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.601786] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.601827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.601852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.601876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.601900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.601922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.601946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.601971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.601996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.602021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.602042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.602064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.602090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.602112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.604106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.604122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.604138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.604156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.605675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.605708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.605724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.607221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.607238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.609050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.611999] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.612059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.612076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.612098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.628802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.628829] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.628867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.628977] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.629037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.645482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.645508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.645545] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.664375] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.664394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.664414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.664431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.664449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.664463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.664478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.664494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.664511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.664528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.664543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.664559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.664573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.664587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.664614] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.664636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.664657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.664672] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.664814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.664829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.664899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.664923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.664950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.664979] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.665001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.665026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.665056] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.665078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.665098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.665119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.665138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.665144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.665163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.665169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.665190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.665209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.665230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.665249] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.665272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.665291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.665311] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.665330] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.665350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.665372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.665396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.665459] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.665481] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.665502] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.665539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.665560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.665581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.665600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.665621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.665641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.665665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.665705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.665729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.665749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.665771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.665797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.665818] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.667809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.667825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.667840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.667859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.669364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.669382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.669399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.670897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.670914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.672736] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.675672] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.675746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.675763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.675785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.692490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.692516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.692551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.692658] [drm:drm_mode_addfb2] [FB:75]
>[ 1270.692768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.709190] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.709214] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.709250] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.727492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.727511] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.727531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.727548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.727565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.727580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.727595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.727611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.727629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.727646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.727662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.727678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.727735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.727757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.727801] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.727837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.727870] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.727896] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.727998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.728008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.728051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.728076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.728097] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.728117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.728134] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.728151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.728168] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.728183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.728199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.728213] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.728228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.728232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.728246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.728249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.728264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.728278] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.728302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.728315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.728330] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.728343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.728356] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.728369] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.728381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.728397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.728414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.728451] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.728464] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.728477] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.728504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.728523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.728541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.728560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.728578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.728596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.728616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.728635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.728654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.728674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.728719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.728745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.728767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.730761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.730778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.730792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.730807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.732310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.732328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.732345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.733845] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.733862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.735670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.738629] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.738719] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.738747] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.738772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.755427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.755453] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.755487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.755606] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.755679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.772119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.772144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.772191] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.791038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.791059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.791081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.791101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.791122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.791142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.791161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.791180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.791202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.791223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.791244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.791263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.791282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.791301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.791330] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.791353] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.791378] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.791394] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.791515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.791526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.791573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.791595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.791616] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.791639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.791659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.791680] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.791748] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.791773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.791797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.791820] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.791842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.791848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.791870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.791876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.791898] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.791920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.791942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.791963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.791988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.792009] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.792030] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.792051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.792073] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.792098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.792126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.792187] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.792203] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.792218] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.792248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.792268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.792289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.792308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.792328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.792347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.792369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.792390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.792411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.792430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.792450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.792470] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.792490] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.794471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.794488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.794503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.794518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.796026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.796041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.796055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.797549] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.797567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.799378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.802091] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.802133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.802150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.802172] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.818901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.818928] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.818966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.819076] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.819148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.835557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.835582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.835620] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.854481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.854501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.854521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.854538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.854555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.854570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.854584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.854600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.854618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.854634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.854650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.854666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.854680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.854737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.854780] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.854814] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.854848] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.854873] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.855001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.855018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.855093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.855128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.855154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.855181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.855203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.855229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.855253] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.855276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.855299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.855320] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.855341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.855346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.855367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.855382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.855402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.855424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.855445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.855466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.855490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.855511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.855530] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.855550] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.855572] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.855595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.855620] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.855687] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.855739] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.855762] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.855801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.855825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.855848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.855871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.855894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.855918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.855944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.855968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.855993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.856015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.856037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.856063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.856087] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.858081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.858098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.858112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.858128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.859637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.859652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.859665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.861162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.861179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.862984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.865930] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.865993] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.866009] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.866031] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.882716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.882740] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.882774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.882889] [drm:drm_mode_addfb2] [FB:75]
>[ 1270.882961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.899425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.899447] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.899495] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.917828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.917847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.917868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.917885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.917902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.917918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.917933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.917949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.917967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.917983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.918003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.918024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.918043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.918062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.918090] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.918113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.918138] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.918155] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.918263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.918275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.918324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.918342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.918361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.918381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.918396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.918414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.918430] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.918446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.918462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.918476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.918491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.918494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.918508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.918511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.918526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.918540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.918553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.918567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.918583] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.918597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.918611] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.918625] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.918638] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.918655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.918673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.918756] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.918779] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.918801] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.918842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.918865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.918887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.918910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.918931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.918954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.918979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.919005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.919030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.919052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.919074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.919101] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.919121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.921096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.921114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.921131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.921149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.922654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.922672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.922689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.924224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.924242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.926055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.929024] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.929063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.929080] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.929103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1270.945806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.945832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.945868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.945972] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.946039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.962486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1270.962510] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1270.962548] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1270.980459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1270.980478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1270.980498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.980515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.980532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.980547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.980562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.980578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1270.980596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.980613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.980663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.980684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.980743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.980766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.980811] [drm:intel_power_well_disable [i915]] disabling display
>[ 1270.980841] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1270.980864] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1270.980881] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1270.980980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1270.980996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1270.981055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1270.981072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1270.981091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1270.981111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1270.981126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1270.981144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1270.981160] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1270.981177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1270.981192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1270.981208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1270.981222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1270.981226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.981240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1270.981244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1270.981259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1270.981273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1270.981287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1270.981301] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1270.981317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1270.981332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1270.981347] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1270.981360] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1270.981374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1270.981391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1270.981409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1270.981450] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1270.981464] [drm:intel_power_well_enable [i915]] enabling display
>[ 1270.981479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1270.981505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1270.981520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1270.981536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1270.981550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1270.981565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1270.981580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1270.981598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1270.981613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1270.981634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1270.981654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1270.981673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1270.981698] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1270.981747] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1270.983751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1270.983767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1270.983781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.983799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1270.985315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1270.985333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1270.985347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1270.986850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1270.986866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1270.988677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1270.991626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1270.991687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1270.991746] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1270.991784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1271.008458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.008484] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1271.008519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.008648] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.008759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.025150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1271.025176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1271.025214] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1271.043465] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1271.043484] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1271.043505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.043522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.043539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.043558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.043578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.043598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.043620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.043641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.043661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.043681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.043700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.043763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.043812] [drm:intel_power_well_disable [i915]] disabling display
>[ 1271.043847] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1271.043881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1271.043907] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1271.044024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1271.044041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1271.044119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1271.044141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1271.044166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1271.044193] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1271.044214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1271.044238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1271.044260] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1271.044282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1271.044303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1271.044324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1271.044343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1271.044349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.044368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1271.044373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.044395] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1271.044414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1271.044434] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1271.044453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1271.044476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1271.044495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1271.044515] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1271.044534] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1271.044554] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1271.044575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.044600] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1271.044653] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1271.044675] [drm:intel_power_well_enable [i915]] enabling display
>[ 1271.044697] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1271.044755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.044777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.044800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.044820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.044842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.044864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.044888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.044914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.044938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.044958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.044979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.045005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1271.045026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1271.047017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1271.047035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1271.047053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.047071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1271.048577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1271.048594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1271.048612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.050110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1271.050126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1271.051930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1271.054861] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1271.054889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1271.054908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1271.054934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1271.071631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.071657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1271.071692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.071874] [drm:drm_mode_addfb2] [FB:75]
>[ 1271.071944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.088325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1271.088349] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1271.088384] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1271.106453] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1271.106471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1271.106491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.106511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.106533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.106553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.106572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.106591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.106613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.106634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.106654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.106674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.106693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.106752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.106796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1271.106832] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1271.106865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1271.106891] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1271.108308] [IGT] kms_flip: exiting, ret=0
>[ 1271.129198] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1271.129218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1271.129237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1271.129258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1271.129274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1271.129292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1271.129310] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1271.129329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1271.129349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1271.129369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1271.129389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1271.129393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.129413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1271.129416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.129436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1271.129456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1271.129475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1271.129495] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1271.129515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1271.129535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1271.129554] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1271.129574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1271.129594] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1271.129615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.129637] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1271.129692] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1271.129724] [drm:intel_power_well_enable [i915]] enabling display
>[ 1271.129741] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1271.129774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.129794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.129814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.129841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.129860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.129878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.129898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.129918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.129937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.129955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.129973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.129992] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1271.130010] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1271.131996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1271.132013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1271.132029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.132047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1271.133557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1271.133573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1271.133589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.135085] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1271.135101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1271.136913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1271.139948] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1271.140032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1271.140046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1271.140068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1271.140110] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1271.140125] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1271.156782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.156805] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1271.156841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.156968] Console: switching to colour frame buffer device 240x75
>[ 1271.287026] Console: switching to colour dummy device 80x25
>[ 1271.287121] [IGT] kms_flip: executing
>[ 1271.301247] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1271.301276] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1271.302776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1271.302797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1271.304780] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1271.304787] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1271.306776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1271.306797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1271.308776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1271.308782] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1271.308786] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1271.308802] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1271.308826] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1271.309863] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1271.310757] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1271.310775] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1271.310792] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1271.310815] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1271.311808] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1271.311832] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1271.312904] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1271.312907] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1271.312985] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1271.312987] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1271.312991] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1271.312993] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1271.312997] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1271.312999] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1271.313007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1271.313009] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.313012] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.313014] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.313017] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1271.313019] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1271.313022] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1271.313024] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1271.313027] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.313029] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.313032] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1271.313034] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1271.313036] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1271.313039] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1271.313041] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1271.313044] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1271.313046] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1271.313049] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1271.313051] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1271.313053] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1271.313056] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1271.313058] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1271.313061] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1271.313063] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1271.313065] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1271.313068] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1271.313070] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1271.313073] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1271.313075] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1271.313077] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1271.313080] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1271.313110] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1271.313127] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1271.314767] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1271.314786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1271.316777] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1271.316783] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1271.318774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1271.318794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1271.320774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1271.320779] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1271.320783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1271.320994] [IGT] kms_flip: starting subtest 2x-flip-vs-expired-vblank
>[ 1271.323404] [IGT] kms_flip: exiting, ret=77
>[ 1271.357058] Console: switching to colour frame buffer device 240x75
>[ 1271.488033] Console: switching to colour dummy device 80x25
>[ 1271.488128] [IGT] kms_flip: executing
>[ 1271.502261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1271.502291] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1271.503794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1271.503814] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1271.505786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1271.505792] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1271.507787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1271.507808] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1271.509788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1271.509794] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1271.509799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1271.509814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1271.509837] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1271.510873] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1271.511770] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1271.511788] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1271.511803] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1271.511817] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1271.512812] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1271.512836] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1271.513921] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1271.513924] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1271.514005] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1271.514007] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1271.514011] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1271.514013] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1271.514017] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1271.514019] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1271.514027] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1271.514030] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.514033] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.514035] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.514038] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1271.514040] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1271.514043] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1271.514045] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1271.514048] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.514050] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1271.514052] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1271.514055] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1271.514057] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1271.514060] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1271.514062] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1271.514065] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1271.514067] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1271.514069] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1271.514072] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1271.514074] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1271.514077] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1271.514079] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1271.514082] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1271.514084] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1271.514086] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1271.514089] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1271.514091] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1271.514094] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1271.514096] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1271.514099] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1271.514101] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1271.514131] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1271.514148] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1271.515783] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1271.515803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1271.517794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1271.517800] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1271.519787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1271.519807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1271.521797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1271.521803] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1271.521807] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1271.522012] [IGT] kms_flip: starting subtest plain-flip-fb-recreate
>[ 1271.522429] [drm:drm_mode_addfb2] [FB:75]
>[ 1271.522451] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.564821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1271.564874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.573805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1271.573829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1271.573868] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1271.592732] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1271.592790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1271.592814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1271.592853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.592871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.592889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.592904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.592919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.592935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.592953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.592969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.592985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.593000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.593014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.593028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.593056] [drm:intel_power_well_disable [i915]] disabling display
>[ 1271.593078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1271.593100] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1271.593117] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1271.593164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1271.593233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1271.593295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1271.593305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1271.593346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1271.593372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1271.593389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1271.593407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1271.593421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1271.593436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1271.593452] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1271.593466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1271.593480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1271.593494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1271.593507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1271.593510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.593523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1271.593526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1271.593539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1271.593552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1271.593564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1271.593577] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1271.593591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1271.593604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1271.593616] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1271.593629] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1271.593641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1271.593656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1271.593673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1271.596240] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1271.596254] [drm:intel_power_well_enable [i915]] enabling display
>[ 1271.596267] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1271.596294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1271.596309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1271.596323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1271.596337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1271.596350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1271.596364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1271.596380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1271.596394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1271.596409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.596422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1271.596434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1271.596450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1271.596465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1271.598450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1271.598469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1271.598486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.598504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1271.600017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1271.600033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1271.600048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1271.601545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1271.601561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1271.603371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1271.606296] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1271.606329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1271.606345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1271.606367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1271.606406] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1271.606423] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1271.623103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1271.623128] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1271.623163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1271.923502] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.940034] [drm:drm_mode_addfb2] [FB:75]
>[ 1271.956721] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.973402] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.990082] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.006780] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.023468] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.040164] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.056810] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.073490] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.090172] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.106854] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.123535] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.140216] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.156898] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.173602] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.190262] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.206944] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.223652] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.240306] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.256988] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.273670] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.290351] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.307033] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.323757] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.340417] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.357119] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.373840] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.390473] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.407123] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.423820] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.440486] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.457167] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.473877] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.490537] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.507225] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.523905] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.540677] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.557380] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.574048] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.590619] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.607301] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.624002] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.640679] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.657356] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.674042] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.690758] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.707414] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.724091] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.740779] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.757435] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.774132] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.790818] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.807480] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.824162] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.840885] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.857555] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.874233] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.890911] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.907591] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.924268] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.940933] [drm:drm_mode_addfb2] [FB:75]
>[ 1272.957614] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.974296] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.990998] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.007674] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.024349] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.041029] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.057726] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.074385] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.091067] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.107748] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.124429] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.141111] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.157793] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.174475] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.191156] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.207855] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.224523] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.241201] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.257883] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.274588] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.291246] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.307928] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.324609] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.341291] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.358003] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.374663] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.391351] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.408039] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.424713] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.441445] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.458063] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.474744] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.491425] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.508107] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.524788] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.541469] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.558150] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.574832] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.591514] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.608197] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.624924] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.641574] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.658260] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.674937] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.691616] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.708297] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.724982] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.741690] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.758340] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.775028] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.791830] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.808375] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.825056] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.841738] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.858419] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.875124] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.891846] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.908541] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.925213] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.941918] [drm:drm_mode_addfb2] [FB:75]
>[ 1273.958565] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.975191] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.991888] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.008554] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.025236] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.041917] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.058598] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.075280] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.091962] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.108668] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.125376] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.142077] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.158688] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.175369] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.192051] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.208732] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.225411] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.242094] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.258802] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.275458] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.292191] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.308879] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.325550] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.342184] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.358866] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.375548] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.392229] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.408936] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.425593] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.442290] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.458965] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.475665] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.492328] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.509001] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.525681] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.542363] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.559044] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.575726] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.592408] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.609090] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.625795] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.642504] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.659191] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.675864] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.692497] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.709179] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.725860] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.742542] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.759224] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.775947] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.792588] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.809269] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.825964] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.842656] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.859335] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.876008] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.892690] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.909368] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.926098] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.942762] [drm:drm_mode_addfb2] [FB:75]
>[ 1274.959445] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.976125] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.992800] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.009478] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.026154] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.042814] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.059495] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.076198] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.092872] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.109547] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.126231] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.143000] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.159610] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.176297] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.193000] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.209643] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.226322] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.242990] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.259671] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.276352] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.293033] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.309716] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.326397] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.343080] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.359812] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.376457] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.393135] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.409814] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.426486] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.443168] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.459850] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.476531] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.493213] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.509895] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.526575] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.543294] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.559955] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.576644] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.593323] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.610017] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.626678] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.643359] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.660037] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.676800] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.693503] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.710171] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.726841] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.743437] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.760118] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.776800] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.793479] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.810163] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.826844] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.843525] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.860207] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.876889] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.893570] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.910252] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.926933] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.943615] [drm:drm_mode_addfb2] [FB:75]
>[ 1275.960296] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.976978] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.993659] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.010342] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.027038] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.043729] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.060386] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.077139] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.093749] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.110431] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.127113] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.143793] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.160475] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.177156] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.193863] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.210573] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.227211] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.243899] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.260564] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.277245] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.293927] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.310610] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.327291] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.343974] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.360653] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.377386] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.394086] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.410725] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.427380] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.444062] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.460743] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.477425] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.494140] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.510788] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.527484] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.544158] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.560866] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.577578] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.594272] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.610877] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.627559] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.644260] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.660922] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.677604] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.694283] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.710966] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.727648] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.744411] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.761141] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.777693] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.794374] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.811073] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.827736] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.844419] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.861133] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.877795] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.894484] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.911161] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.927840] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.944520] [drm:drm_mode_addfb2] [FB:75]
>[ 1276.961190] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.977872] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.994554] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.011237] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.027916] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.044669] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.061365] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.078037] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.094712] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.111385] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.128085] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.144688] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.161370] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.178052] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.194732] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.211471] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.228120] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.244806] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.261487] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.278164] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.294820] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.311504] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.328185] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.344866] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.361548] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.378252] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.394911] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.411607] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.428281] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.444989] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.461701] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.478318] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.495001] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.511682] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.528364] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.545045] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.561727] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.578408] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.595130] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.611771] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.628517] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.645211] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.661884] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.678557] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.695233] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.711906] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.728585] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.745261] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.761905] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.778587] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.795305] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.811970] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.828632] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.845312] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.861994] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.878676] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.895382] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.912056] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.928734] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.945403] [drm:drm_mode_addfb2] [FB:75]
>[ 1277.962101] [drm:drm_mode_addfb2] [FB:79]
>[ 1277.978819] [drm:drm_mode_addfb2] [FB:78]
>[ 1277.995467] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.012164] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.028824] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.045503] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.062197] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.078860] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.095541] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.112224] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.128931] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.145648] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.162340] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.178945] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.195626] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.212308] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.228988] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.245672] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.262353] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.279056] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.295716] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.312397] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.329077] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.345760] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.362441] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.379121] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.395805] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.412509] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.429232] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.445850] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.462531] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.479211] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.495913] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.512603] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.529257] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.545940] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.562621] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.579335] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.595984] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.612666] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.629358] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.646049] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.662747] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.679426] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.696104] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.712756] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.729436] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.746118] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.762800] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.779480] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.796198] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.812844] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.829599] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.846305] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.862940] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.879625] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.896300] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.912977] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.929669] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.946331] [drm:drm_mode_addfb2] [FB:75]
>[ 1278.962978] [drm:drm_mode_addfb2] [FB:79]
>[ 1278.979661] [drm:drm_mode_addfb2] [FB:78]
>[ 1278.996342] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.013045] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.029752] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.046456] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.063068] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.079750] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.096453] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.113129] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.129806] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.146494] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.163234] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.179863] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.196550] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.213212] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.229884] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.246565] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.263246] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.279928] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.296610] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.313309] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.329973] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.346652] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.363335] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.380018] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.396737] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.413392] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.430072] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.446744] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.463462] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.480122] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.496799] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.513486] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.530162] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.546847] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.563543] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.580197] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.596873] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.613562] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.630256] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.646931] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.663614] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.680288] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.696995] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.713712] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.730405] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.747080] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.763694] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.780375] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.797057] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.813738] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.830420] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.847100] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.863783] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.880465] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.897146] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.913827] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.930509] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.947190] [drm:drm_mode_addfb2] [FB:75]
>[ 1279.963872] [drm:drm_mode_addfb2] [FB:79]
>[ 1279.980576] [drm:drm_mode_addfb2] [FB:78]
>[ 1279.997251] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.013917] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.030599] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.047280] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.063963] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.080644] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.097325] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.114006] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.130689] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.147370] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.164051] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.180734] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.197463] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.214118] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.230778] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.247531] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.264149] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.280829] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.297509] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.314189] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.330876] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.347549] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.364230] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.380912] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.397595] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.414291] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.430957] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.447638] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.464320] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.481002] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.497683] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.514364] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.531046] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.547727] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.564409] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.581111] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.597786] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.614511] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.631143] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.647823] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.664503] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.681183] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.697861] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.714543] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.731225] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.747906] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.764589] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.781269] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.797950] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.814633] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.831328] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.847996] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.864678] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.881386] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.898047] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.914726] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.931416] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.948189] [drm:drm_mode_addfb2] [FB:75]
>[ 1280.964823] [drm:drm_mode_addfb2] [FB:79]
>[ 1280.981496] [drm:drm_mode_addfb2] [FB:78]
>[ 1280.998172] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.014849] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.031527] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.048174] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.064856] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.081538] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.098218] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.114902] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.131582] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.148264] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.164945] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.181647] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.198345] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.215024] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.231672] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.248353] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.265035] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.281716] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.298443] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.315099] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.331762] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.348452] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.365124] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.381806] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.398522] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.415191] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.431867] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.448544] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.465369] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.481959] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.498639] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.515313] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.531989] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.548664] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.565304] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.581985] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.598704] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.615384] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.632030] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.648711] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.665428] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.682124] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.698780] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.715437] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.732119] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.748800] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.765497] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.782166] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.798845] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.815526] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.832228] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.848890] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.865572] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.882253] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.898934] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.915616] [drm:drm_mode_addfb2] [FB:79]
>[ 1281.932361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1281.948991] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1281.949017] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1281.949059] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1281.967909] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1281.967932] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1281.967949] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1281.967969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1281.967986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1281.968004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1281.968019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1281.968034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1281.968051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1281.968068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1281.968085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1281.968100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1281.968120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1281.968140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1281.968159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1281.968187] [drm:intel_power_well_disable [i915]] disabling display
>[ 1281.968210] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1281.968236] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1281.968254] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1281.968501] [drm:drm_mode_addfb2] [FB:75]
>[ 1281.968538] [drm:drm_mode_addfb2] [FB:78]
>[ 1281.994128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1281.994215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1281.994273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1281.994327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1281.994338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1281.994438] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1281.994462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1281.994489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1281.994515] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1281.994536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1281.994560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1281.994583] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1281.994605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1281.994626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1281.994647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1281.994667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1281.994672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1281.994692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1281.994697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1281.994719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1281.994738] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1281.994759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1281.994777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1281.994801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1281.994819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1281.994840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1281.994859] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1281.994879] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1281.994903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1281.994928] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1281.997459] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1281.997476] [drm:intel_power_well_enable [i915]] enabling display
>[ 1281.997491] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1281.997523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1281.997542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1281.997561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1281.997580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1281.997598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1281.997617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1281.997638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1281.997657] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1281.997677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1281.997696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1281.997712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1281.997732] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1281.997750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1281.999740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1281.999756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1281.999771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1281.999786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1282.001308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1282.001323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1282.001337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1282.002871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1282.002887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1282.004726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1282.007674] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1282.007736] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1282.007753] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1282.007775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1282.024482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1282.024508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1282.024543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1282.324780] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.341428] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.358113] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.374812] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.391536] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.408216] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.424852] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.441534] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.458216] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.474897] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.491579] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.508260] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.524941] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.541705] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.558491] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.575037] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.591712] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.608422] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.625063] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.641742] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.658450] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.675107] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.691784] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.708463] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.725130] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.741817] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.758497] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.775177] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.791855] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.808529] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.825210] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.841892] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.858573] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.875256] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.891936] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.908617] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.925298] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.942061] [drm:drm_mode_addfb2] [FB:75]
>[ 1282.958760] [drm:drm_mode_addfb2] [FB:78]
>[ 1282.975452] [drm:drm_mode_addfb2] [FB:79]
>[ 1282.992082] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.008768] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.025458] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.042109] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.058796] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.075489] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.092135] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.108816] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.125495] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.142170] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.158848] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.175530] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.192217] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.208899] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.225567] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.242340] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.259041] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.275710] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.292381] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.308976] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.325657] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.342339] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.359020] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.375702] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.392382] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.409091] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.425746] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.442427] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.459110] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.475792] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.492503] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.509218] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.525851] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.542548] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.559215] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.575903] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.592582] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.609262] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.625931] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.642607] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.659289] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.675970] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.692685] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.709334] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.726014] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.742777] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.759512] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.776060] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.792741] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.809422] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.826103] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.842850] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.859595] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.876199] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.892888] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.909560] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.926192] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.942946] [drm:drm_mode_addfb2] [FB:75]
>[ 1283.959585] [drm:drm_mode_addfb2] [FB:78]
>[ 1283.976239] [drm:drm_mode_addfb2] [FB:79]
>[ 1283.992920] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.009682] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.026287] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.042981] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.059658] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.076328] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.093040] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.109755] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.126388] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.143076] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.159755] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.176433] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.193098] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.209779] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.226461] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.243143] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.259825] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.276524] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.293188] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.309870] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.326551] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.343233] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.359915] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.376597] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.393304] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.409959] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.426640] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.443379] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.460064] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.476733] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.493409] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.510086] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.526729] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.543422] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.560093] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.576775] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.593456] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.610138] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.626818] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.643500] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.660182] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.676945] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.693630] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.710313] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.726973] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.743648] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.760320] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.777010] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.793684] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.810360] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.827025] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.843714] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.860391] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.877043] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.893798] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.910463] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.927120] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.943807] [drm:drm_mode_addfb2] [FB:75]
>[ 1284.960485] [drm:drm_mode_addfb2] [FB:78]
>[ 1284.977163] [drm:drm_mode_addfb2] [FB:79]
>[ 1284.993839] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.010506] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.027187] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.043875] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.060573] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.077222] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.093975] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.110653] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.127316] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.144004] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.160678] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.177312] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.194036] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.210701] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.227356] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.244038] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.260800] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.277411] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.294107] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.310774] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.327445] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.344137] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.360808] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.377527] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.394215] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.410853] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.427534] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.444216] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.460898] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.477588] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.494260] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.510942] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.527624] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.544306] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.560987] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.577669] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.594373] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.611096] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.627729] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.644424] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.661099] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.677778] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.694452] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.711143] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.727802] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.744483] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.761237] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.777864] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.794555] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.811352] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.827891] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.844608] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.861268] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.877948] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.894627] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.911300] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.927981] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.944661] [drm:drm_mode_addfb2] [FB:75]
>[ 1285.961344] [drm:drm_mode_addfb2] [FB:78]
>[ 1285.978026] [drm:drm_mode_addfb2] [FB:79]
>[ 1285.994707] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.011389] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.028071] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.044752] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.061434] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.078115] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.094796] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.111479] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.128160] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.144840] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.161523] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.178205] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.194884] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.211568] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.228249] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.244929] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.261728] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.278296] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.294974] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.311658] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.328338] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.345007] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.361704] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.378384] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.395127] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.411749] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.428429] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.445112] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.461793] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.478475] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.495156] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.511836] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.528519] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.545201] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.561882] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.578564] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.595245] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.611926] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.628608] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.645290] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.661971] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.678675] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.695335] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.712014] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.728698] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.745378] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.762061] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.778743] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.795425] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.812106] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.828787] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.845468] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.862150] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.878832] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.895513] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.912195] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.928876] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.945559] [drm:drm_mode_addfb2] [FB:75]
>[ 1286.962239] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.978921] [drm:drm_mode_addfb2] [FB:79]
>[ 1286.995604] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.012284] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.028966] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.045647] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.062329] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.079011] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.095713] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.112373] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.129055] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.145737] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.162419] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.179101] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.195783] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.212463] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.229144] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.245826] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.262508] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.279190] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.295871] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.312552] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.329233] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.345924] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.362598] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.379280] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.395961] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.412642] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.429322] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.446005] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.462708] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.479368] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.496050] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.512752] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.529412] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.546094] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.562776] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.579458] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.596140] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.612822] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.629502] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.646185] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.662866] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.679548] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.696229] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.712911] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.729592] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.746274] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.762955] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.779638] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.796318] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.813001] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.829680] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.846363] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.863044] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.879749] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.896407] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.913089] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.929771] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.946452] [drm:drm_mode_addfb2] [FB:75]
>[ 1287.963134] [drm:drm_mode_addfb2] [FB:78]
>[ 1287.979815] [drm:drm_mode_addfb2] [FB:79]
>[ 1287.996497] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.013179] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.029859] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.046542] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.063223] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.079905] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.096586] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.113268] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.129949] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.146631] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.163313] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.179995] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.196676] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.213358] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.230039] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.246720] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.263402] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.280082] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.296849] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.313495] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.330154] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.346844] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.363520] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.380197] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.396875] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.413555] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.430223] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.446912] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.463590] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.480263] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.496944] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.513625] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.530306] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.546988] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.563669] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.580352] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.597033] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.613715] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.630396] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.647078] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.663782] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.680442] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.697122] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.713826] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.730485] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.747168] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.763849] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.780531] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.797213] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.813894] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.830575] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.847257] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.863938] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.880620] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.897302] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.913983] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.930664] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.947347] [drm:drm_mode_addfb2] [FB:75]
>[ 1288.964028] [drm:drm_mode_addfb2] [FB:78]
>[ 1288.980710] [drm:drm_mode_addfb2] [FB:79]
>[ 1288.997391] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.014073] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.030753] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.047436] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.064118] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.080823] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.097481] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.114162] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.130843] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.147525] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.164207] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.180889] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.197570] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.214252] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.230932] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.247615] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.264296] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.280978] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.297659] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.314341] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.331022] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.347704] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.364385] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.381067] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.397748] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.414431] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.431111] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.447793] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.464475] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.481156] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.497859] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.514519] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.531201] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.547883] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.564564] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.581246] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.597927] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.614610] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.631290] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.647972] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.664655] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.681336] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.698017] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.714699] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.731378] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.748062] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.764744] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.781426] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.798107] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.814788] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.831468] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.848152] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.864854] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.881514] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.898196] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.914899] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.931557] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.948241] [drm:drm_mode_addfb2] [FB:75]
>[ 1289.964923] [drm:drm_mode_addfb2] [FB:78]
>[ 1289.981603] [drm:drm_mode_addfb2] [FB:79]
>[ 1289.998296] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.014967] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.031646] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.048329] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.065011] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.081692] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.098374] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.115056] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.131735] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.148420] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.165102] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.181783] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.198526] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.215147] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.231826] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.248509] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.265191] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.281896] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.298553] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.315236] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.331919] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.348599] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.365280] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.381962] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.398644] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.415324] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.432006] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.448687] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.465369] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.482051] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.498732] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.515414] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.532095] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.548777] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.565458] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.582140] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.598822] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.615501] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.632184] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.648866] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.665547] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.682230] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.698931] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.715592] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.732276] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.748956] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.765638] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.782319] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.799000] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.815681] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.832363] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.849045] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.865727] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.882408] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.899089] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.915771] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.932452] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.949134] [drm:drm_mode_addfb2] [FB:75]
>[ 1290.965816] [drm:drm_mode_addfb2] [FB:78]
>[ 1290.982498] [drm:drm_mode_addfb2] [FB:79]
>[ 1290.999179] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.015861] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.032542] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.049224] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.065927] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.082587] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.099269] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.115972] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.132632] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.149313] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.165995] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.182676] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.199358] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.216040] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.232721] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.249403] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.266085] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.282765] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.299448] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.316129] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.332811] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.349492] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.366173] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.382855] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.399596] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.416279] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.432981] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.449624] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.466264] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.482966] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.499627] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.516308] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.532990] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.549671] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.566353] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.583034] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.599716] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.616398] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.633081] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.649761] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.666443] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.683124] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.699806] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.716487] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.733168] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.749850] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.766531] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.783213] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.799895] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.816577] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.833258] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.849940] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.866621] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.883302] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.900006] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.916665] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.933347] [drm:drm_mode_addfb2] [FB:79]
>[ 1291.950030] [drm:drm_mode_addfb2] [FB:75]
>[ 1291.966710] [drm:drm_mode_addfb2] [FB:78]
>[ 1291.983391] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.000073] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.016755] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.033436] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.050118] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.066800] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.083481] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.100162] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.116844] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.133534] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.150208] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.166890] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.183569] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.200252] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.216934] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.233615] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.250296] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.266997] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.283660] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.300341] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.317044] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.333768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1292.333813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1292.333836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1292.333876] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1292.352724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1292.352743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1292.352764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1292.352782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1292.352800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1292.352819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1292.352838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1292.352858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1292.352880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1292.352901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1292.352922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1292.352942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1292.352961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1292.352980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1292.353061] [drm:intel_power_well_disable [i915]] disabling display
>[ 1292.353098] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1292.353135] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1292.353161] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1292.353336] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.353360] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.376477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1292.376563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1292.376619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1292.376673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1292.376684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1292.376731] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1292.376747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1292.376765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1292.376783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1292.376797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1292.376813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1292.376829] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1292.376844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1292.376858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1292.376872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1292.376884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1292.376888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1292.376905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1292.376908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1292.376926] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1292.376944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1292.376961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1292.376978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1292.377030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1292.377054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1292.377076] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1292.377096] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1292.377116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1292.377140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1292.377164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1292.379792] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1292.379808] [drm:intel_power_well_enable [i915]] enabling display
>[ 1292.379823] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1292.379853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1292.379870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1292.379886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1292.379904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1292.379923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1292.379942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1292.379962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1292.379982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1292.380044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1292.380067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1292.380087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1292.380112] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1292.380134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1292.382139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1292.382156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1292.382174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1292.382192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1292.383696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1292.383713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1292.383727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1292.385223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1292.385239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1292.387042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1292.389977] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1292.390053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1292.390070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1292.390092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1292.406805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1292.406832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1292.406870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1292.707094] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.723760] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.740442] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.757122] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.773807] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.790487] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.807168] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.823850] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.840531] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.857212] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.873895] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.890576] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.907257] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.923939] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.940620] [drm:drm_mode_addfb2] [FB:78]
>[ 1292.957301] [drm:drm_mode_addfb2] [FB:79]
>[ 1292.973983] [drm:drm_mode_addfb2] [FB:75]
>[ 1292.990666] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.007347] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.024044] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.040710] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.057390] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.074073] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.090755] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.107437] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.124118] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.140799] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.157481] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.174185] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.190909] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.207591] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.224277] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.240951] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.257626] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.274253] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.290934] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.307616] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.324297] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.340979] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.357660] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.374341] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.391024] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.407705] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.424386] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.441083] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.457749] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.474431] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.491111] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.507794] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.524476] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.541158] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.557897] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.574592] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.591263] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.607884] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.624565] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.641246] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.657928] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.674610] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.691290] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.707972] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.724654] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.741335] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.758017] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.774781] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.791381] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.808077] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.824743] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.841425] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.858107] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.874789] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.891470] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.908151] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.924857] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.941537] [drm:drm_mode_addfb2] [FB:78]
>[ 1293.958207] [drm:drm_mode_addfb2] [FB:79]
>[ 1293.974888] [drm:drm_mode_addfb2] [FB:75]
>[ 1293.991561] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.008265] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.024939] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.041617] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.058303] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.075027] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.091681] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.108369] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.125047] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.141693] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.158376] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.175058] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.191738] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.208420] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.225140] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.241783] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.258466] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.275146] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.291828] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.308510] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.325190] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.341873] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.358554] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.375236] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.391916] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.408598] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.425281] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.441961] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.458644] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.475325] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.492007] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.508688] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.525369] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.542051] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.558733] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.575415] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.592095] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.608772] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.625511] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.642231] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.658823] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.675505] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.692185] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.708866] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.725549] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.742278] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.758941] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.775627] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.792305] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.808982] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.825662] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.842320] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.859002] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.875683] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.892379] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.909046] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.925737] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.942418] [drm:drm_mode_addfb2] [FB:78]
>[ 1294.959091] [drm:drm_mode_addfb2] [FB:79]
>[ 1294.975772] [drm:drm_mode_addfb2] [FB:75]
>[ 1294.992455] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.009151] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.025817] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.042498] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.059182] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.075862] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.092544] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.109225] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.125906] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.142589] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.159270] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.175952] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.192634] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.209315] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.225996] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.242677] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.259382] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.276114] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.292793] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.309464] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.326141] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.342767] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.359448] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.376129] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.392798] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.409536] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.426210] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.442856] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.459554] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.476229] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.492976] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.509669] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.526264] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.542946] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.559627] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.576309] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.592991] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.609672] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.626354] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.643059] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.659769] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.676456] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.693128] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.709762] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.726442] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.743125] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.759806] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.776488] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.793169] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.809851] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.826583] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.843268] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.859938] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.876577] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.893259] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.909940] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.926621] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.943325] [drm:drm_mode_addfb2] [FB:78]
>[ 1295.960002] [drm:drm_mode_addfb2] [FB:79]
>[ 1295.976677] [drm:drm_mode_addfb2] [FB:75]
>[ 1295.993347] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.010111] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.026809] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.043393] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.060074] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.076756] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.093458] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.110136] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.126811] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.143494] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.160165] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.176919] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.193614] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.210349] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.226960] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.243572] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.260253] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.276934] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.293616] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.310345] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.327010] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.343687] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.360366] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.377044] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.393724] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.410387] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.427069] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.443750] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.460453] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.477130] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.493808] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.510476] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.527158] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.543839] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.560600] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.577202] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.593878] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.610586] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.627281] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.643940] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.660625] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.677328] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.693983] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.710672] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.727341] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.744030] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.760701] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.777382] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.794063] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.810744] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.827448] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.844108] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.860790] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.877471] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.894152] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.910859] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.927515] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.944196] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.960878] [drm:drm_mode_addfb2] [FB:79]
>[ 1296.977560] [drm:drm_mode_addfb2] [FB:75]
>[ 1296.994241] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.010919] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.027605] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.044302] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.060994] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.077650] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.094332] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.111014] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.127695] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.144376] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.161057] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.177739] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.194420] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.211121] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.227830] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.244517] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.261190] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.277828] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.294511] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.311192] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.327872] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.344554] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.361236] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.377998] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.394696] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.411369] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.428039] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.444644] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.461326] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.478008] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.494684] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.511441] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.528052] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.544733] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.561415] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.578121] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.594778] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.611460] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.628141] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.644822] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.661504] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.678186] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.694868] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.711549] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.728230] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.744911] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.761616] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.778274] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.794952] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.811638] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.828336] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.845001] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.861683] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.878415] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.895073] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.911759] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.928437] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.945116] [drm:drm_mode_addfb2] [FB:78]
>[ 1297.961773] [drm:drm_mode_addfb2] [FB:79]
>[ 1297.978454] [drm:drm_mode_addfb2] [FB:75]
>[ 1297.995135] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.011817] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.028521] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.045195] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.061874] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.078559] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.095280] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.111935] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.128622] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.145297] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.161952] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.178633] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.195315] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.211981] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.228680] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.245373] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.262041] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.278722] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.295404] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.312085] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.328766] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.345449] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.362130] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.378812] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.395494] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.412175] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.428855] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.445537] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.462219] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.478901] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.495582] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.512264] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.528945] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.545627] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.562309] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.578990] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.595672] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.612393] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.629035] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.645787] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.662485] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.679080] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.695762] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.712442] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.729124] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.745804] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.762510] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.779170] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.795867] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.812544] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.829215] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.845923] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.862577] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.879261] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.895941] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.912643] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.929322] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.945992] [drm:drm_mode_addfb2] [FB:78]
>[ 1298.962687] [drm:drm_mode_addfb2] [FB:79]
>[ 1298.979361] [drm:drm_mode_addfb2] [FB:75]
>[ 1298.996030] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.012713] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.029409] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.046077] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.062756] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.079438] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.096119] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.112801] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.129483] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.146201] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.162899] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.179585] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.196257] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.212890] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.229572] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.246253] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.262935] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.279617] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.296299] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.312980] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.329661] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.346343] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.363024] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.379706] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.396387] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.413064] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.429793] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.446467] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.463139] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.479817] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.496496] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.513174] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.529853] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.546533] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.563203] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.579884] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.596566] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.613249] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.629929] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.646610] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.663313] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.680016] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.696700] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.713375] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.730019] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.746700] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.763382] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.780064] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.796745] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.813466] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.830109] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.846790] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.863484] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.880181] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.896835] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.913516] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.930197] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.946879] [drm:drm_mode_addfb2] [FB:78]
>[ 1299.963583] [drm:drm_mode_addfb2] [FB:79]
>[ 1299.980260] [drm:drm_mode_addfb2] [FB:75]
>[ 1299.996938] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.013624] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.030365] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.047003] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.063686] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.080332] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.097013] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.113695] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.130376] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.147058] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.163740] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.180421] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.197153] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.213837] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.230529] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.247185] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.263829] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.280511] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.297192] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.313873] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.330578] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.347256] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.363933] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.380609] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.397282] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.414044] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.430644] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.447326] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.464007] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.480710] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.497388] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.514062] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.530734] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.547415] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.564097] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.580778] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.597460] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.614137] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.630824] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.647521] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.664186] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.680868] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.697581] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.714240] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.730928] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.747606] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.764288] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.780958] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.797639] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.814320] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.831002] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.847656] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.864365] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.881048] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.897728] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.914412] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.931116] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.947774] [drm:drm_mode_addfb2] [FB:78]
>[ 1300.964455] [drm:drm_mode_addfb2] [FB:79]
>[ 1300.981137] [drm:drm_mode_addfb2] [FB:75]
>[ 1300.997860] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.014544] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.031201] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.047881] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.064557] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.081238] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.098013] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.114589] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.131271] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.147952] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.164634] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.181315] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.197997] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.214703] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.231412] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.248099] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.264771] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.281448] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.298124] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.314768] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.331449] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.348130] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.364833] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.381494] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.398175] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.414938] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.431636] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.448306] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.464902] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.481583] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.498261] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.515012] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.531628] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.548310] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.564991] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.581671] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.598367] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.615103] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.631772] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.648392] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.665073] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.681838] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.698461] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.715124] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.731805] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.748488] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.765169] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.781851] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.798532] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.815215] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.831895] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.848610] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.865259] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.881940] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.898622] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.915304] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.931985] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.948667] [drm:drm_mode_addfb2] [FB:78]
>[ 1301.965366] [drm:drm_mode_addfb2] [FB:79]
>[ 1301.982094] [drm:drm_mode_addfb2] [FB:75]
>[ 1301.998712] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.015393] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.032076] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.048779] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.065455] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.082131] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.098819] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.115536] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.132193] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.148880] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.165558] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.182210] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.198892] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.215588] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.232255] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.248936] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.265639] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.282300] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.298998] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.315677] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.332415] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.349029] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.365709] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.382389] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.399070] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.415751] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.432433] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.449114] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.465796] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.482477] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.499159] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.515840] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.532522] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.549203] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.565885] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.582567] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.599279] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.615919] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.632649] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.649318] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.666025] [drm:drm_mode_addfb2] [FB:79]
>[ 1302.682705] [drm:drm_mode_addfb2] [FB:75]
>[ 1302.699362] [drm:drm_mode_addfb2] [FB:78]
>[ 1302.716118] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1302.716176] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1302.716207] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1302.716269] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1302.733129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1302.733148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1302.733169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1302.733186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1302.733204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1302.733223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1302.733243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1302.733262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1302.733284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1302.733305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1302.733324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1302.733346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1302.733365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1302.733384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1302.733413] [drm:intel_power_well_disable [i915]] disabling display
>[ 1302.733436] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1302.733461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1302.733478] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1302.735920] [IGT] kms_flip: exiting, ret=0
>[ 1302.763032] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1302.763053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1302.763074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1302.763097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1302.763117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1302.763137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1302.763157] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1302.763177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1302.763197] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1302.763216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1302.763236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1302.763240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1302.763260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1302.763263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1302.763283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1302.763303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1302.763323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1302.763342] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1302.763363] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1302.763382] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1302.763402] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1302.763422] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1302.763441] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1302.763462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1302.763485] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1302.763543] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1302.763560] [drm:intel_power_well_enable [i915]] enabling display
>[ 1302.763577] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1302.763610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1302.763645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1302.763665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1302.763685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1302.763705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1302.763725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1302.763747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1302.763769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1302.763790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1302.763809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1302.763829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1302.763850] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1302.763870] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1302.765864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1302.765879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1302.765893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1302.765907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1302.767419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1302.767433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1302.767445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1302.768945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1302.768958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1302.770773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1302.773603] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1302.773682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1302.773698] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1302.773721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1302.773768] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1302.773787] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1302.790454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1302.790479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1302.790515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1302.790660] Console: switching to colour frame buffer device 240x75
>[ 1302.924532] Console: switching to colour dummy device 80x25
>[ 1302.924663] [IGT] kms_flip: executing
>[ 1302.939147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1302.939176] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1302.940686] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1302.940707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1302.942677] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1302.942683] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1302.944677] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1302.944698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1302.946678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1302.946684] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1302.946688] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1302.946704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1302.946729] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1302.947773] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1302.948667] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1302.948687] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1302.948704] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1302.948722] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1302.949710] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1302.949735] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1302.950789] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1302.950792] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1302.950870] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1302.950872] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1302.950876] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1302.950878] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1302.950882] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1302.950884] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1302.950891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1302.950894] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1302.950896] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1302.950899] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1302.950901] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1302.950904] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1302.950906] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1302.950909] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1302.950911] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1302.950914] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1302.950916] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1302.950919] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1302.950921] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1302.950924] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1302.950926] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1302.950928] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1302.950931] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1302.950933] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1302.950936] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1302.950938] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1302.950941] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1302.950943] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1302.950945] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1302.950948] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1302.950950] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1302.950953] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1302.950955] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1302.950957] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1302.950960] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1302.950962] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1302.950964] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1302.950997] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1302.951015] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1302.952654] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1302.952674] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1302.954752] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1302.954757] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1302.956679] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1302.956700] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1302.958677] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1302.958683] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1302.958687] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1302.958897] [IGT] kms_flip: starting subtest wf_vblank
>[ 1302.959301] [drm:drm_mode_addfb2] [FB:77]
>[ 1302.959323] [drm:drm_mode_addfb2] [FB:79]
>[ 1303.001396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1303.001449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1303.007284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1303.007308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1303.007357] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1303.026231] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1303.026254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1303.026271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1303.026291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1303.026308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1303.026326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1303.026341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1303.026356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1303.026372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1303.026390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1303.026406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1303.026421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1303.026437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1303.026451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1303.026465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1303.026492] [drm:intel_power_well_disable [i915]] disabling display
>[ 1303.026514] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1303.026536] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1303.026553] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1303.026591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1303.026717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1303.026821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1303.026836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1303.026892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1303.026908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1303.026925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1303.026944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1303.026958] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1303.026974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1303.026990] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1303.027006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1303.027020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1303.027034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1303.027047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1303.027051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1303.027063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1303.027067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1303.027080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1303.027093] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1303.027106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1303.027118] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1303.027134] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1303.027147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1303.027160] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1303.027173] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1303.027186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1303.027201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1303.027218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1303.029730] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1303.029747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1303.029763] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1303.029792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1303.029812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1303.029831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1303.029849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1303.029868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1303.029887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1303.029907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1303.029927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1303.029946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1303.029965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1303.029983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1303.030003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1303.030021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1303.032002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1303.032019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1303.032036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1303.032055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1303.033576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1303.033592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1303.033606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1303.035131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1303.035146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1303.036993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1303.039942] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1303.040003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1303.040020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1303.040042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1303.040084] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1303.040104] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1303.056746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1303.056772] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1303.056807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1313.082512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1313.099085] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1313.099129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1313.099194] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1313.116189] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1313.116225] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1313.116327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1313.116365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1313.116398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1313.116434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1313.116466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1313.116498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1313.116530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1313.116566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1313.116602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1313.116636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1313.116670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1313.116702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1313.116734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1313.116780] [drm:intel_power_well_disable [i915]] disabling display
>[ 1313.116816] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1313.116858] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1313.116888] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1313.117144] [drm:drm_mode_addfb2] [FB:77]
>[ 1313.117182] [drm:drm_mode_addfb2] [FB:78]
>[ 1313.140442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1313.140528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1313.140586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1313.140641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1313.140650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1313.140700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1313.140718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1313.140737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1313.140756] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1313.140772] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1313.140788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1313.140805] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1313.140821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1313.140837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1313.140852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1313.140866] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1313.140869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1313.140883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1313.140886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1313.140905] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1313.140924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1313.140943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1313.140961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1313.140981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1313.140999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1313.141017] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1313.141036] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1313.141054] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1313.141074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1313.141095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1313.143707] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1313.143721] [drm:intel_power_well_enable [i915]] enabling display
>[ 1313.143734] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1313.143762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1313.143778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1313.143793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1313.143807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1313.143820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1313.143834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1313.143851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1313.143866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1313.143880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1313.143893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1313.143910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1313.143929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1313.143947] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1313.145937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1313.145954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1313.145969] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1313.145984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1313.147494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1313.147510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1313.147524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1313.149012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1313.149028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1313.150832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1313.153057] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1313.153134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1313.153150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1313.153173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1313.169875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1313.169901] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1313.169936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1323.195705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1323.195787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1323.195827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1323.196009] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1323.212893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1323.212916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1323.212940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1323.212961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1323.212982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1323.212999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1323.213017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1323.213036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1323.213057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1323.213077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1323.213096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1323.213116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1323.213132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1323.213149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1323.213182] [drm:intel_power_well_disable [i915]] disabling display
>[ 1323.213208] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1323.213237] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1323.213255] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1323.213488] [drm:drm_mode_addfb2] [FB:77]
>[ 1323.213515] [drm:drm_mode_addfb2] [FB:78]
>[ 1323.236779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1323.236900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1323.236973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1323.237022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1323.237033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1323.237080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1323.237097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1323.237114] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1323.237135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1323.237153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1323.237171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1323.237188] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1323.237206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1323.237224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1323.237241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1323.237258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1323.237262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1323.237279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1323.237282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1323.237300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1323.237317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1323.237334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1323.237352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1323.237369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1323.237386] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1323.237404] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1323.237421] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1323.237438] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1323.237457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1323.237476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1323.239992] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1323.240009] [drm:intel_power_well_enable [i915]] enabling display
>[ 1323.240025] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1323.240056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1323.240075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1323.240095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1323.240114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1323.240133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1323.240151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1323.240172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1323.240192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1323.240211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1323.240229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1323.240248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1323.240268] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1323.240287] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1323.242279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1323.242297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1323.242311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1323.242326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1323.243832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1323.243858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1323.243872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1323.245377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1323.245393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1323.247226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1323.250177] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1323.250236] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1323.250253] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1323.250276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1323.266979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1323.267005] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1323.267041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.292982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1333.293158] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1333.293248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1333.293388] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1333.311710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1333.311734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1333.311761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1333.311783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1333.311805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1333.311825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1333.311844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1333.311864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1333.311887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1333.311908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1333.311928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1333.311954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.311979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1333.312004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1333.312041] [drm:intel_power_well_disable [i915]] disabling display
>[ 1333.312070] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1333.312103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1333.312125] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1333.314792] [IGT] kms_flip: exiting, ret=0
>[ 1333.337884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1333.337904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1333.337923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1333.337946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1333.337966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1333.337987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1333.338007] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1333.338027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1333.338047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1333.338066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1333.338085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1333.338090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1333.338109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1333.338112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1333.338133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1333.338152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1333.338171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1333.338191] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1333.338211] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1333.338230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1333.338250] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1333.338269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1333.338289] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1333.338310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1333.338332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1333.338388] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1333.338405] [drm:intel_power_well_enable [i915]] enabling display
>[ 1333.338421] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1333.338468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1333.338489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1333.338509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1333.338529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1333.338549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1333.338568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1333.338591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1333.338612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1333.338633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.338653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1333.338672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1333.338693] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1333.338713] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1333.340715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1333.340731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1333.340745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1333.340760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1333.342273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1333.342286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1333.342299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1333.343800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1333.343813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1333.345627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1333.348671] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1333.348738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1333.348754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1333.348777] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1333.348823] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1333.348839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1333.365486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1333.365511] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1333.365551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.365685] Console: switching to colour frame buffer device 240x75
>[ 1333.670904] Console: switching to colour dummy device 80x25
>[ 1333.670998] [IGT] kms_flip: executing
>[ 1333.682005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1333.682034] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1333.683518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1333.683536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1333.685521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1333.685526] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1333.687527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1333.687548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1333.689529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1333.689535] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1333.689539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1333.689556] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1333.689579] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1333.690617] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1333.691514] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1333.691532] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1333.691546] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1333.691560] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1333.692559] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1333.692582] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1333.693661] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1333.693664] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1333.693743] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1333.693745] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1333.693749] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1333.693751] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1333.693755] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1333.693757] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1333.693764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1333.693767] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1333.693770] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1333.693772] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1333.693775] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1333.693777] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1333.693779] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1333.693782] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1333.693784] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1333.693787] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1333.693789] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1333.693792] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1333.693794] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1333.693796] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1333.693799] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1333.693801] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1333.693804] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1333.693806] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1333.693809] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1333.693811] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1333.693813] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1333.693816] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1333.693818] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1333.693821] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1333.693823] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1333.693826] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1333.693828] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1333.693830] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1333.693833] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1333.693835] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1333.693838] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1333.693868] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1333.693886] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1333.695519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1333.695536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1333.697535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1333.697541] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1333.699526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1333.699546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1333.701528] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1333.701534] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1333.701538] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1333.701759] [IGT] kms_flip: starting subtest plain-flip-ts-check
>[ 1333.702172] [drm:drm_mode_addfb2] [FB:75]
>[ 1333.702194] [drm:drm_mode_addfb2] [FB:79]
>[ 1333.744238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1333.744291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1333.749188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1333.749214] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1333.749263] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1333.767215] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1333.767238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1333.767254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1333.767277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1333.767296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1333.767318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1333.767338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1333.767357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1333.767376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1333.767398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1333.767419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1333.767439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1333.767460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.767520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1333.767545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1333.767589] [drm:intel_power_well_disable [i915]] disabling display
>[ 1333.767619] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1333.767643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1333.767661] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1333.767708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1333.767780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1333.767843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1333.767853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1333.767895] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1333.767913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1333.767932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1333.767952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1333.767968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1333.767985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1333.768002] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1333.768019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1333.768035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1333.768050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1333.768065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1333.768070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1333.768084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1333.768087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1333.768103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1333.768125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1333.768138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1333.768151] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1333.768166] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1333.768179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1333.768192] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1333.768205] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1333.768217] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1333.768232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1333.768250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1333.770858] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1333.770874] [drm:intel_power_well_enable [i915]] enabling display
>[ 1333.770890] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1333.770919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1333.770939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1333.770958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1333.770976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1333.770995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1333.771014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1333.771034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1333.771054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1333.771073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1333.771091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1333.771107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1333.771127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1333.771145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1333.773141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1333.773159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1333.773176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1333.773194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1333.774711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1333.774729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1333.774743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1333.776238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1333.776256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1333.778065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1333.781014] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1333.781074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1333.781091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1333.781113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1333.781152] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1333.781169] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1333.797818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1333.797843] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1333.797878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.107224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.123729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.123764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.123819] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.142678] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.142701] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.142718] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.142738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.142755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.142774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.142789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.142804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.142820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.142838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.142854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.142870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.142886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.142901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.142919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.142948] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.142972] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.142997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.143015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.143294] [drm:drm_mode_addfb2] [FB:75]
>[ 1344.143336] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.166402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.166491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1344.166548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1344.166604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1344.166614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.166664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.166682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.166700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.166720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.166736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.166753] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.166769] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1344.166785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1344.166801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.166815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.166829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.166833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.166851] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.166855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.166874] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.166892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.166911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.166929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1344.166948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.166967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.166985] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1344.167004] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1344.167023] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1344.167042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.167063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1344.169593] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.169610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.169624] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.169655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.169672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.169688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.169703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.169718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.169734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.169751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.169767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.169783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.169797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.169811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.169829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1344.169845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.171847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.171865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.171883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.171901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.173412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.173429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.173444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.174937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.174955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.176762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.179694] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1344.179771] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.179788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1344.179810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.196512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.196537] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1344.196570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.505840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.505890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.505915] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.505958] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.524787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.524807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.524827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.524844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.524862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.524878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.524893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.524909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.524927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.524943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.524959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.524975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.524989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.525003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.525032] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.525054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.525075] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.525091] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.525324] [drm:drm_mode_addfb2] [FB:75]
>[ 1354.525348] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.551148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1354.551235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.551293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1354.551349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1354.551360] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.551409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.551426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.551444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.551462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.551477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.551493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.551508] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1354.551523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1354.551538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.551551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.551565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.551568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.551581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.551584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.551598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.551611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.551623] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.551640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.551658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.551676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.551694] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1354.551711] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1354.551759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1354.551785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.551812] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1354.554425] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.554441] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.554456] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.554485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.554503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.554521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.554539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.554556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.554574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.554593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.554612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.554630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.554648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.554662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.554681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1354.554699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.556720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.556750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.556767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.556786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.558306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.558323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.558338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.559846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.559864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.561685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.564623] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1354.564695] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.564712] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1354.564787] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.581468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.581494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1354.581531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.890786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.890853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.890888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.890958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.907777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.907796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.907816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.907834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.907852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.907867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.907882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.907899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.907917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.907934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.907950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.907967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.907981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.907995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.908023] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.908045] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.908067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.908083] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.910535] [IGT] kms_flip: exiting, ret=0
>[ 1364.933763] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.933784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.933805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.933829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.933846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.933866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.933887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1364.933906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1364.933927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.933946] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.933966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.933971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.933990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.933993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.934013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.934033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.934053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.934072] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1364.934092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.934111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.934131] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1364.934151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1364.934170] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1364.934191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.934213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1364.934269] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.934286] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.934303] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.934336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.934379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.934399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.934418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.934436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.934455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.934476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.934496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.934516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.934534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.934552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.934573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1364.934591] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.936584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.936600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.936614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.936628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.938134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.938147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.938159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.939653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.939667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.941480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.944526] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1364.944591] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.944609] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1364.944635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.944682] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1364.944700] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1364.961336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.961380] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1364.961419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.961554] Console: switching to colour frame buffer device 240x75
>[ 1365.210369] Console: switching to colour dummy device 80x25
>[ 1365.210466] [IGT] kms_flip: executing
>[ 1365.220933] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1365.220962] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1365.222448] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1365.222468] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1365.224424] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1365.224430] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1365.226423] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1365.226443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1365.228425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1365.228431] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1365.228435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1365.228452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1365.228476] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1365.229507] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1365.230412] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1365.230429] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1365.230443] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1365.230457] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1365.231453] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1365.231476] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1365.233577] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1365.233580] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1365.233660] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1365.233662] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1365.233666] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1365.233668] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1365.233672] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1365.233674] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1365.233681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1365.233684] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.233686] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.233689] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.233691] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1365.233694] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1365.233696] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1365.233699] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1365.233701] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.233704] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.233706] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1365.233709] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1365.233711] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1365.233713] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1365.233716] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1365.233718] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1365.233721] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1365.233723] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1365.233725] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1365.233728] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1365.233730] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1365.233733] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1365.233735] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1365.233738] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1365.233740] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1365.233742] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1365.233745] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1365.233747] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1365.233750] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1365.233752] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1365.233754] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1365.233785] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1365.233803] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1365.235389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1365.235407] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1365.237503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1365.237508] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1365.239422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1365.239442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1365.241429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1365.241435] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1365.241439] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1365.241655] [IGT] kms_flip: starting subtest nonblocking-read
>[ 1365.243732] [IGT] kms_flip: exiting, ret=0
>[ 1365.278416] Console: switching to colour frame buffer device 240x75
>[ 1365.422177] Console: switching to colour dummy device 80x25
>[ 1365.422269] [IGT] kms_flip: executing
>[ 1365.432880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1365.432909] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1365.434438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1365.434458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1365.436436] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1365.436442] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1365.438437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1365.438456] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1365.440444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1365.440450] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1365.440454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1365.440469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1365.440492] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1365.441527] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1365.442424] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1365.442442] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1365.442457] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1365.442471] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1365.443469] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1365.443495] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1365.444551] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1365.444554] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1365.444634] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1365.444636] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1365.444640] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1365.444642] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1365.444646] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1365.444648] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1365.444655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1365.444658] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.444661] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.444663] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.444666] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1365.444668] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1365.444671] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1365.444673] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1365.444675] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.444678] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1365.444680] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1365.444683] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1365.444685] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1365.444688] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1365.444690] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1365.444692] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1365.444695] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1365.444697] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1365.444700] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1365.444702] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1365.444705] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1365.444707] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1365.444709] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1365.444712] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1365.444714] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1365.444717] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1365.444719] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1365.444721] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1365.444724] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1365.444726] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1365.444729] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1365.444758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1365.444776] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1365.446424] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1365.446441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1365.448439] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1365.448445] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1365.450521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1365.450540] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1365.452615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1365.452621] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1365.452625] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1365.452833] [IGT] kms_flip: starting subtest flip-vs-rmfb
>[ 1365.453238] [drm:drm_mode_addfb2] [FB:75]
>[ 1365.453260] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.495281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.495333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.511858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.511884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.511927] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.530798] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.530821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.530841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.530863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.530883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.530904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.530924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.530943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.530962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.530984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.531005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.531025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.531045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.531064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.531080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.531109] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.531131] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.531157] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.531175] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.531228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1365.531293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.531348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.531358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.531440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.531464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.531489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.531516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.531537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.531561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.531583] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.531606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.531630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.531651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.531672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.531678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.531699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.531705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.531727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.531748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.531769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.531790] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.531814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.531835] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.531853] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.531867] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.531880] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.531896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.531913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.534513] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.534528] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.534541] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.534568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.534583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.534597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.534611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.534624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.534639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.534655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.534670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.534684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.534697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.534710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.534727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.534741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.536725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.536743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.536757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.536772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.538276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.538292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.538306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.539801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.539819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.541624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.544576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.544632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.544649] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.544670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.544708] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.544724] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.561376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.561420] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.561454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.578073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.578083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.594820] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.594894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.628129] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.628154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.628193] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.647173] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.647205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.647229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.647257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.647282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.647308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.647330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.647351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.647374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.647466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.647504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.647544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.647580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.647612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.647646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.647711] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.647764] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.647813] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.647856] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.647975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.647989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.648054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.648079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.648106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.648136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.648160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.648185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.648210] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.648233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.648256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.648278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.648300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.648306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.648326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.648333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.648360] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.648392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.648449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.648471] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.648495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.648517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.648539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.648560] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.648581] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.648606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.648632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.648691] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.648715] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.648739] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.648782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.648806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.648831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.648856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.648880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.648904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.648939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.648962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.648979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.648993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.649007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.649024] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.649041] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.651024] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.651040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.651054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.651071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.652581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.652596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.652611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.654108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.654124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.655933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.658866] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.658942] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.658959] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.658981] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.659019] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.659036] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.675684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.675710] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.675747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.675846] [drm:drm_mode_addfb2] [FB:75]
>[ 1365.675911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.709042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.709067] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.709112] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.727975] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.727997] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.728014] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.728034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.728053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.728075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.728095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.728114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.728134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.728155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.728176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.728197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.728217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.728236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.728254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.728282] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.728305] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.728330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.728348] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.728453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.728469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.728545] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.728564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.728583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.728603] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.728618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.728636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.728653] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.728670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.728686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.728701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.728715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.728719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.728733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.728736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.728751] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.728765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.728779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.728792] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.728808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.728822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.728836] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.728857] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.728870] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.728884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.728901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.728938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.728952] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.728965] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.728992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.729010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.729028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.729046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.729064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.729081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.729101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.729119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.729138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.729155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.729170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.729189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.729207] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.731192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.731209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.731223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.731238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.732748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.732763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.732777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.734272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.734288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.736098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.739040] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.739105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.739121] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.739141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.739177] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.739194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.755878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.755903] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.755938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.756039] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.756098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.789240] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.789264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.789303] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.808179] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.808202] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.808218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.808238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.808255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.808272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.808288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.808302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.808318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.808336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.808352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.808368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.808384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.808398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.808458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.808503] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.808540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.808580] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.808608] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.808719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.808734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.808804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.808829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.808856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.808885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.808910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.808935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.808961] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.808985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.809010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.809033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.809055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.809061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.809083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.809089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.809112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.809134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.809156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.809179] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.809204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.809227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.809250] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.809272] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.809292] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.809317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.809344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.809428] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.809454] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.809476] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.809516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.809541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.809572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.809595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.809617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.809641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.809666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.809690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.809714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.809736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.809758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.809783] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.809806] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.811802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.811818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.811832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.811846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.813366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.813384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.813398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.816019] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.816040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.817856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.820795] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.820867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.820882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.820902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.820947] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.820970] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.837606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.837630] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.837663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.837755] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.837820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.870964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.870990] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.871037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.888960] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.888983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.888999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.889018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.889035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.889052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.889067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.889082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.889098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.889115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.889132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.889147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.889163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.889177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.889191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.889219] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.889241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.889262] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.889278] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.889377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.889387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.889495] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.889521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.889549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.889579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.889602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.889628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.889652] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.889676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.889699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.889722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.889743] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.889749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.889770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.889776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.889800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.889821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.889843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.889864] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.889888] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.889909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.889932] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.889952] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.889974] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.889997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.890024] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.890083] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.890107] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.890131] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.890170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.890193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.890217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.890239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.890268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.890289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.890313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.890337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.890360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.890380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.890400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.890442] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.890465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.892459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.892476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.892490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.892505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.894012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.894028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.894042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.895537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.895554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.897359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.900290] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.900318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.900334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.900356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.900405] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.900474] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.917063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.917089] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.917126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.917229] [drm:drm_mode_addfb2] [FB:75]
>[ 1365.917298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.950433] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1365.950458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.950503] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1365.969357] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1365.969381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1365.969401] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.969466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.969491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.969522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.969544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.969568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.969591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.969619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.969646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.969672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.969697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.969718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.969741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.969782] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.969815] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.969848] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.969875] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.969994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1365.970003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.970047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.970066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.970086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.970108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.970126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.970145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.970163] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1365.970182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1365.970201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.970219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.970237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.970241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.970259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.970262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.970281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.970300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.970318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.970337] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1365.970355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.970373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.970392] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1365.970410] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1365.970468] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1365.970495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.970522] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1365.970578] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.970603] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.970626] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.970664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.970696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.970718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.970742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.970763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.970784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.970809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.970832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.970856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.970875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.970897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.970922] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1365.970946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.972949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.972967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.972984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.973002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.974571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.974588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.974602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.976097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.976113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.977924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.980859] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1365.980934] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.980954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1365.980980] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.981021] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1365.981041] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1365.997686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.997711] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1365.997746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.997849] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.997915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.031055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.031078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.031113] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.049970] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.049992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.050008] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.050028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.050044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.050062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.050077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.050092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.050108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.050126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.050142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.050157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.050173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.050187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.050201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.050227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.050249] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.050270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.050287] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.050383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.050393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.050498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.050526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.050555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.050584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.050607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.050633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.050657] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.050681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.050704] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.050727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.050748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.050754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.050776] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.050789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.050810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.050829] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.050850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.050868] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.050891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.050910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.050931] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.050950] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.050970] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.050991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.051015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.051073] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.051096] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.051118] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.051154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.051174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.051196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.051216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.051236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.051257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.051280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.051303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.051326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.051345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.051365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.051387] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.051410] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.053447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.053463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.053478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.053493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.055008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.055025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.055039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.056549] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.056567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.058373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.061305] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.061382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.061402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.061471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.061523] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.061548] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.078126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.078151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.078185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.078290] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.078356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.111482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.111507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.111552] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.129731] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.129753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.129770] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.129789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.129806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.129824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.129840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.129855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.129871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.129889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.129905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.129921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.129937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.129951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.129965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.129992] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.130013] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.130035] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.130052] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.130160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.130169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.130217] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.130236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.130256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.130277] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.130294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.130312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.130330] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.130348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.130364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.130380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.130400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.130404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.130424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.130458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.130484] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.130508] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.130533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.130555] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.130583] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.130605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.130629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.130651] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.130675] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.130702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.130731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.130792] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.130817] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.130841] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.130881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.130904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.130927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.130949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.130972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.130994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.131021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.131046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.131071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.131092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.131114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.131139] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.131163] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.135356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.135375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.135391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.135407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.138043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.138062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.138078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.139591] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.139608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.141415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.144359] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.144386] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.144403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.144471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.144530] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.144557] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.161122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.161147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.161183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.161279] [drm:drm_mode_addfb2] [FB:75]
>[ 1366.161341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.194486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.194509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.194556] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.213405] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.213428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.213490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.213521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.213547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.213576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.213592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.213607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.213623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.213641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.213657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.213673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.213689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.213703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.213720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.213748] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.213772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.213797] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.213815] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.213891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.213901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.213946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.213963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.213982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.214001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.214020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.214041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.214060] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.214088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.214104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.214119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.214133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.214137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.214150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.214153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.214167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.214181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.214194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.214212] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.214230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.214248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.214265] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.214284] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.214302] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.214320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.214340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.214384] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.214399] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.214413] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.214475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.214498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.214519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.214539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.214560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.214581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.214605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.214628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.214650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.214670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.214690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.214714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.214736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.216725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.216742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.216759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.216777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.218283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.218299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.218313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.219808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.219824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.221629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.224565] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.224639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.224656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.224678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.224719] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.224739] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.241382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.241407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.241489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.241614] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.241677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.274737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.274761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.274798] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.293314] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.293336] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.293352] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.293371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.293388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.293406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.293422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.293481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.293507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.293538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.293565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.293591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.293618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.293641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.293657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.293684] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.293706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.293728] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.293746] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.293824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.293834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.293877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.293893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.293911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.293931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.293950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.293977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.293994] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.294008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.294023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.294036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.294050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.294053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.294066] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.294070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.294083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.294096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.294108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.294121] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.294136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.294148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.294162] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.294174] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.294187] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.294202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.294219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.294254] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.294268] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.294282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.294309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.294328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.294346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.294362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.294380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.294397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.294416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.294470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.294494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.294515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.294536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.294560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.294581] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.296577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.296593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.296608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.296623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.298127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.298145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.298162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.299661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.299678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.301483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.304415] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.304493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.304510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.304532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.304571] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.304587] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.321236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.321261] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.321295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.321407] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.321540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.354592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.354618] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.354656] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.373545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.373567] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.373584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.373603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.373620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.373638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.373653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.373669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.373685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.373703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.373719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.373736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.373752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.373766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.373780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.373807] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.373829] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.373849] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.373866] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.373963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.373977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.374047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.374074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.374101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.374130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.374153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.374179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.374204] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.374228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.374251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.374275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.374290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.374294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.374307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.374311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.374325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.374339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.374358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.374377] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.374396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.374415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.374434] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.374497] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.374522] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.374550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.374580] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.374641] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.374667] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.374691] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.374732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.374755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.374780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.374803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.374826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.374849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.374881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.374904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.374928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.374947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.374968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.374993] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.375014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.377020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.377036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.377050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.377065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.378582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.378599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.378614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.380111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.380130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.381943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.384900] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.384953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.384970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.384992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.385039] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.385057] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.401696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.401722] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.401756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.401858] [drm:drm_mode_addfb2] [FB:75]
>[ 1366.401925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.435052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.435079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.435125] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.453980] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.454002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.454018] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.454038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.454054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.454072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.454088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.454103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.454119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.454136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.454153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.454169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.454185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.454200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.454214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.454240] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.454262] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.454284] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.454301] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.454399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.454409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.454507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.454533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.454562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.454593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.454615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.454648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.454672] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.454694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.454716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.454736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.454757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.454763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.454783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.454788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.454809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.454829] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.454850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.454869] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.454892] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.454911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.454932] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.454951] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.454972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.454993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.455017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.455084] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.455107] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.455128] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.455164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.455185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.455207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.455226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.455247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.455267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.455291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.455314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.455337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.455356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.455377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.455399] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.455421] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.458507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.458525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.458540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.458555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.460068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.460084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.460098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.461605] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.461623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.463435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.466383] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.466494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.466521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.466556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.466615] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.466639] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.483201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.483227] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.483261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.483355] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.483424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.516557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.516582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.516618] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.535512] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.535534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.535550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.535570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.535587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.535604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.535620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.535635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.535650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.535668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.535685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.535701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.535717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.535731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.535745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.535772] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.535793] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.535814] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.535831] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.535945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.535955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.536002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.536023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.536045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.536068] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.536088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.536109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.536129] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.536150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.536170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.536191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.536210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.536214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.536234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.536238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.536259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.536279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.536299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.536319] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.536340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.536360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.536380] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.536400] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.536420] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.536441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.536509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.536583] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.536610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.536632] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.536675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.536700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.536724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.536748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.536773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.536799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.536827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.536854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.536880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.536904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.536928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.536956] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.536981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.539000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.539019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.539036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.539055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.540570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.540587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.540601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.542093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.542109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.543913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.546853] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.546922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.546939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.546961] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.547000] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.547016] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.563665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.563690] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.563724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.563817] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.563876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.597022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.597048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.597086] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.615930] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.615954] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.615974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.615996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.616016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.616037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.616057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.616076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.616095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.616117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.616138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.616159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.616179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.616197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.616217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.616245] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.616268] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.616293] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.616311] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.616402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.616413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.616505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.616531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.616561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.616592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.616615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.616643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.616668] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.616694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.616717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.616741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.616763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.616770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.616791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.616799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.616822] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.616844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.616867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.616887] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.616912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.616933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.616956] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.616977] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.616999] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.617025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.617051] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.617126] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.617149] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.617171] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.617208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.617228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.617250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.617269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.617290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.617311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.617334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.617358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.617380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.617400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.617420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.617443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.617485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.619481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.619497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.619512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.619530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.621046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.621064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.621078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.622588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.622606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.624419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.627353] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.627429] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.627449] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.627523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.627573] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.627600] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.644180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.644206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.644241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.644358] [drm:drm_mode_addfb2] [FB:75]
>[ 1366.644429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.677560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.677585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.677630] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.696632] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.696665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.696690] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.696720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.696746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.696774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.696798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.696821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.696850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.696884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.696916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.696948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.696979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.697009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.697038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.697081] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.697116] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.697154] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.697182] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.697342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.697357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.697430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.697460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.697533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.697583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.697619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.697664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.697703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.697743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.697780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.697819] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.697852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.697864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.697899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.697909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.697947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.697980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.698017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.698050] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.698091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.698124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.698161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.698194] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.698229] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.698270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.698314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.698410] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.698447] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.698509] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.698549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.698571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.698595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.698617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.698640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.698663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.698688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.698715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.698742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.698764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.698787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.698815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.698839] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.700842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.700860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.700877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.700895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.702404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.702421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.702435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.703961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.703977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.705809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.708753] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.708819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.708838] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.708864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.708905] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.708924] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.725561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.725587] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.725624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.725726] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.725794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.758918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.758942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.758979] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.778805] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.778827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.778844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.778864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.778881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.778898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.778913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.778928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.778944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.778962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.778978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.778995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.779011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.779025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.779039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.779066] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.779088] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.779110] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.779127] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.779249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.779260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.779307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.779327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.779347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.779377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.779393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.779412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.779430] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.779450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.779514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.779537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.779562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.779569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.779593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.779599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.779624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.779646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.779669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.779691] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.779717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.779739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.779762] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.779784] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.779808] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.779833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.779861] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.779924] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.779950] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.779974] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.780017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.780042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.780066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.780089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.780112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.780137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.780164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.780190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.780214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.780235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.780257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.780282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.780306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.782321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.782338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.782353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.782368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.783876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.783892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.783908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.786492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.786512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.788316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.791239] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.791274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.791291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.791314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.791355] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.791373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.808020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.808046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.808082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.808189] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.808258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.841376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.841400] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.841437] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.860304] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.860326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.860342] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.860361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.860378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.860396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.860411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.860425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.860442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.860463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.860525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.860553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.860579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.860601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.860625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.860669] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.860705] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.860738] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.860767] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.860848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.860857] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.860900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.860917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.860935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.860955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.860971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.860988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.861005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.861021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.861037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.861051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.861065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.861069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.861084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.861087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.861102] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.861116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.861130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.861143] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.861160] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.861181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.861195] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.861208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.861221] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.861236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.861253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.861287] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.861301] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.861314] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.861338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.861353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.861367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.861380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.861392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.861407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.861422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.861438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.861452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.861498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.861519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.861542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.861563] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.863567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.863583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.863598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.863613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.865116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.865131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.865145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.866641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.866659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.868468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.871397] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.871435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.871451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.871545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.871681] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.871697] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.888181] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.888207] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.888241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.888356] [drm:drm_mode_addfb2] [FB:75]
>[ 1366.888430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.921537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1366.921562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.921599] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1366.940451] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1366.940505] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1366.940532] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.940561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.940587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.940616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.940640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.940656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.940672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.940692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.940709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.940725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.940741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.940756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.940770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.940796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.940818] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.940840] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.940857] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.940938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1366.940948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.940991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.941007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.941033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.941051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.941065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.941081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.941096] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1366.941110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1366.941125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.941138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.941151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.941155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.941167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.941171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.941183] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.941196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.941209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.941221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1366.941236] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.941249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.941262] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1366.941274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1366.941287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1366.941302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.941318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1366.941353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.941367] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.941380] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.941406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.941425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.941443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.941462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.941509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.941532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.941556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.941578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.941601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.941620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.941640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.941663] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1366.941684] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.943678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.943694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.943709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.943723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.945225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.945241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.945254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.946751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.946767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.948570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.951458] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1366.951528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.951543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1366.951564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.951605] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1366.951620] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1366.968277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.968303] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1366.968339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.968510] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.968600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.001629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.001656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.001696] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.020545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.020568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.020584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.020604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.020620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.020641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.020661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.020681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.020700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.020722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.020743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.020763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.020784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.020803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.020822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.020850] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.020873] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.020898] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.020916] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.021032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.021042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.021089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.021110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.021132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.021156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.021176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.021197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.021217] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.021238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.021258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.021278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.021298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.021303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.021322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.021326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.021347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.021367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.021387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.021407] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.021427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.021447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.021467] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.021530] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.021555] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.021582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.021608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.021668] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.021691] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.021713] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.021755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.021780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.021804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.021829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.021848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.021864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.021885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.021906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.021927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.021946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.021966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.021987] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.022007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.024016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.024033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.024048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.024063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.025579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.025594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.025608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.027104] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.027120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.028932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.031887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.031940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.031955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.031976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.032021] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.032045] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.048686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.048711] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.048745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.048858] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.048925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.082041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.082065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.082101] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.100954] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.100975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.100994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.101016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.101036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.101058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.101078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.101097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.101116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.101138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.101159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.101179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.101198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.101217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.101236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.101264] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.101287] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.101312] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.101330] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.101428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.101438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.101524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.101557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.101582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.101608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.101630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.101653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.101675] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.101696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.101717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.101738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.101757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.101764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.101783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.101788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.101811] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.101831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.101851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.101870] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.101893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.101913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.101935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.101956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.101976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.102000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.102025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.102093] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.102117] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.102139] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.102173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.102188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.102202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.102216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.102229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.102245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.102261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.102275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.102290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.102303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.102316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.102332] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.102347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.104324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.104340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.104354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.104368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.105880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.105895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.105908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.107439] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.107457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.109300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.112222] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.112259] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.112279] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.112304] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.112344] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.112364] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.129003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.129030] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.129067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.129168] [drm:drm_mode_addfb2] [FB:75]
>[ 1367.129235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.162359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.162383] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.162419] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.181278] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.181302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.181322] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.181344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.181364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.181385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.181405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.181424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.181444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.181465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.181486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.181553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.181581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.181605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.181628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.181672] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.181709] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.181743] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.181772] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.181856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.181866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.181910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.181927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.181946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.181965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.181982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.181999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.182016] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.182032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.182049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.182064] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.182078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.182082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.182096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.182099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.182114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.182128] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.182143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.182156] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.182173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.182187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.182202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.182215] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.182229] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.182246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.182267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.182306] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.182329] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.182343] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.182367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.182382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.182397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.182410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.182428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.182446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.182466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.182489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.182535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.182556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.182575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.182599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.182620] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.184616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.184632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.184649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.184667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.186171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.186188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.186202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.187699] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.187715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.189520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.192450] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.192478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.192539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.192573] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.192680] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.192696] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.209225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.209252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.209289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.209390] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.209458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.242578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.242603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.242639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.261643] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.261673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.261694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.261720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.261743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.261766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.261786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.261805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.261827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.261850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.261873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.261894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.261915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.261934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.261952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.261988] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.262016] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.262045] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.262068] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.262211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.262224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.262287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.262313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.262340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.262369] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.262391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.262415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.262439] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.262462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.262484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.262570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.262597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.262607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.262635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.262643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.262673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.262700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.262729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.262756] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.262788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.262815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.262844] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.262871] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.262899] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.262933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.262967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.263057] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.263087] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.263116] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.263164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.263194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.263222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.263249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.263276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.263304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.263338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.263370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.263401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.263427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.263454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.263484] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.263544] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.265578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.265597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.265614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.265632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.267141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.267158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.267173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.268669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.268685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.270493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.273434] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.273462] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.273478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.273550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.273714] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.273731] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.290207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.290232] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.290267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.290369] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.290435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.323562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.323588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.323626] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.342478] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.342518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.342534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.342554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.342570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.342588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.342604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.342618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.342634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.342652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.342669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.342685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.342701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.342715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.342729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.342756] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.342778] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.342799] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.342816] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.342931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.342941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.342988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.343007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.343027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.343048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.343064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.343082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.343100] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.343120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.343141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.343162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.343181] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.343186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.343206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.343209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.343230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.343250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.343270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.343290] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.343311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.343331] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.343351] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.343372] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.343392] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.343413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.343435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.343486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.343546] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.343571] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.343613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.343638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.343665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.343688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.343713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.343737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.343764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.343791] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.343824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.343844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.343866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.343892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.343913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.345911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.345928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.345942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.345956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.347475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.347493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.347545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.349053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.349069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.350885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.353831] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.353895] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.353912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.353934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.353971] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.353988] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.370638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.370664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.370698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.370798] [drm:drm_mode_addfb2] [FB:75]
>[ 1367.370864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.403994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.404019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.404055] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.422901] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.422924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.422940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.422960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.422977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.422995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.423010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.423024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.423040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.423059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.423075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.423091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.423107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.423121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.423135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.423162] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.423184] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.423206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.423223] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.423331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.423340] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.423387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.423409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.423430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.423453] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.423474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.423495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.423561] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.423585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.423611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.423633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.423656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.423661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.423684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.423689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.423712] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.423734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.423757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.423778] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.423803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.423824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.423846] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.423867] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.423889] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.423912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.423938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.424013] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.424037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.424060] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.424100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.424124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.424146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.424169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.424190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.424214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.424240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.424265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.424291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.424312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.424334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.424358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.424382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.426393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.426410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.426425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.426440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.427947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.427962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.427976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.429471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.429486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.432392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.435327] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.435403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.435420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.435442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.435480] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.435496] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.452147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.452172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.452209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.452311] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.452371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.485502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.485544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.485580] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.504417] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.504441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.504461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.504483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.504503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.504570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.504597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.504623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.504649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.504679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.504697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.504713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.504730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.504744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.504759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.504785] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.504807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.504829] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.504847] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.504921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.504930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.504973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.504990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.505009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.505028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.505043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.505061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.505077] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.505094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.505110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.505125] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.505139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.505143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.505156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.505160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.505175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.505189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.505204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.505217] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.505234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.505248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.505263] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.505276] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.505290] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.505313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.505329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.505365] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.505379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.505391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.505415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.505430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.505443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.505461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.505479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.505498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.505543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.505565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.505588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.505608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.505627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.505652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.505673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.507668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.507685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.507699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.507714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.509217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.509233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.509246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.510743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.510762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.512571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.515502] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.515580] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.515595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.515617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.515653] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.515669] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.532324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.532350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.532387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.532490] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.532620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.565680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.565705] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.565740] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.584556] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.584580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.584600] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.584621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.584641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.584663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.584683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.584702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.584721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.584743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.584764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.584784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.584804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.584824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.584842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.584870] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.584893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.584918] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.584936] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.585051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.585060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.585108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.585127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.585146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.585167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.585184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.585202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.585220] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.585240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.585261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.585281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.585301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.585305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.585326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.585329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.585350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.585370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.585390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.585410] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.585431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.585451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.585471] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.585491] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.585511] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.585577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.585605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.585681] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.585707] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.585732] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.585773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.585798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.585824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.585846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.585869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.585892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.585918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.585943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.585968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.585989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.586012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.586039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.586062] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.588073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.588090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.588105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.588120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.589647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.589665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.589679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.591175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.591192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.593015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.595968] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.596025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.596045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.596070] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.596111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.596130] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.612769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.612794] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.612828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.612928] [drm:drm_mode_addfb2] [FB:75]
>[ 1367.612993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.646124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.646150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.646189] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.665046] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.665069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.665085] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.665105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.665122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.665139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.665154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.665169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.665185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.665203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.665219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.665236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.665252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.665266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.665280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.665306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.665328] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.665349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.665366] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.665463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.665473] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.665566] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.665592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.665622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.665652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.665675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.665702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.665727] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.665752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.665776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.665800] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.665822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.665829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.665851] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.665856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.665879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.665903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.665925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.665948] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.665971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.665993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.666021] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.666042] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.666061] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.666084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.666108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.666176] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.666198] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.666219] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.666255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.666277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.666297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.666318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.666337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.666358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.666383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.666406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.666428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.666447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.666467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.666490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.666512] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.668540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.668557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.668571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.668586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.670092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.670108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.670122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.671621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.671637] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.673467] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.676398] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.676427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.676446] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.676472] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.676513] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.676568] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.693168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.693193] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.693229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.693333] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.693411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.726542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.726565] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.726600] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.745473] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.745495] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.745512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.745577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.745604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.745634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.745659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.745683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.745704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.745723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.745740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.745756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.745772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.745787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.745801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.745828] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.745851] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.745880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.745896] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.745970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.745979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.746019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.746034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.746051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.746070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.746085] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.746100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.746116] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.746130] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.746145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.746163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.746181] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.746185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.746202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.746206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.746225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.746244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.746262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.746280] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.746298] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.746316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.746335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.746353] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.746372] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.746391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.746412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.746457] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.746472] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.746486] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.746519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.746564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.746587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.746609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.746631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.746654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.746679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.746702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.746726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.746746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.746767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.746792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.746814] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.748805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.748822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.748836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.748851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.750354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.750369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.750382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.751881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.751896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.753699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.756639] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.756709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.756726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.756747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.756785] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.756802] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.773454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.773479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.773513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.773716] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.773782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.806808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.806832] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.806869] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.824784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.824806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.824822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.824842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.824859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.824876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.824892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.824906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.824922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.824940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.824957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.824973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.824988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.825003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.825016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.825044] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.825067] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.825092] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.825110] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.825228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.825238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.825285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.825305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.825325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.825346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.825363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.825380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.825398] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.825415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.825432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.825448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.825463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.825467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.825482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.825486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.825506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.825527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.825578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.825601] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.825628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.825650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.825674] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.825696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.825720] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.825747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.825775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.825852] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.826138] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.826162] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.826202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.826227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.826250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.826273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.826294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.826318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.826344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.826369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.826395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.826416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.826438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.826465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.826488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.828503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.828520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.828567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.828592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.831179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.831199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.831218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.832727] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.832745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.834554] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.837484] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.837511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.837570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.837608] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.837750] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.837767] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.854257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.854282] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.854317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.854416] [drm:drm_mode_addfb2] [FB:75]
>[ 1367.854474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.887612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.887638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.887677] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.906524] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.906563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.906579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.906598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.906615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.906633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.906648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.906662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.906678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.906696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.906716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.906737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.906757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.906776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.906795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.906823] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.906847] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.906872] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.906890] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.906999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.907009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.907056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.907075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.907095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.907116] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.907132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.907150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.907169] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.907186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.907206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.907226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.907246] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.907250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.907270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.907274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.907294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.907315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.907335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.907355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.907375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.907395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.907415] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.907436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.907456] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.907477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.907499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.907597] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.907623] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.907648] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.907690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.907717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.907740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.907765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.907788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.907813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.907841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.907868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.907895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.907917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.907941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.907968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.907991] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.910021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.910039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.910054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.910068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.911613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.911630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.911645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.913145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.913161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.914967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.917912] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.917976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.917996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.918021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.918062] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.918081] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1367.934719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.934745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.934780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.934881] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.934945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.968076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1367.968101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.968137] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1367.987009] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1367.987032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1367.987048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.987067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.987084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.987102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.987117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.987132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.987147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.987168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.987189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.987210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.987231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.987250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.987269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.987297] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.987320] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.987345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1367.987363] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.987461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1367.987472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.987525] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.987580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.987610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.987640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.987664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.987692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.987717] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1367.987742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1367.987765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.987790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.987811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.987819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.987841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.987847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.987870] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.988144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.988167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.988190] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1367.988214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.988238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.988259] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1367.988289] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1367.988308] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1367.988331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.988356] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1367.988425] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.988448] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.988469] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.988505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.988528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.988571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.988592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.988614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.988635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.988660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.988684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.988708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.988728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.988749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.988775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1367.988796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.990962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.990978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.990993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.991007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.992582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.992598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.992612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.994117] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.994136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.995953] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.998901] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1367.998964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.998981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1367.999006] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.999046] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1367.999066] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.015700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.015725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.015761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.015866] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.015943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.049053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.049076] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.049111] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.067967] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.067989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.068006] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.068025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.068042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.068060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.068076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.068090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.068107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.068128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.068149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.068170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.068190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.068209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.068228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.068256] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.068279] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.068304] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.068322] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.068437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.068447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.068494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.068513] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.068533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.068589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.068614] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.068641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.068668] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.068692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.068719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.068741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.068765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.068772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.068795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.068801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.068826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.068847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.068871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.068892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.068918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.068947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.068970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.068991] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.069014] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.069039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.069065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.069125] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.069149] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.069172] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.069210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.069234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.069255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.069277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.069297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.069320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.069345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.069370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.069394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.069414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.069435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.069459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.069482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.071503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.071519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.071534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.071580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.073102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.073119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.073134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.074645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.074661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.076487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.079418] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.079496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.079513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.079535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.079710] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.079727] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.096241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.096266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.096300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.096401] [drm:drm_mode_addfb2] [FB:75]
>[ 1368.096467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.129595] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.129619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.129656] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.148505] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.148528] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.148590] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.148620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.148647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.148675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.148692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.148706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.148723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.148741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.148759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.148775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.148791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.148805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.148819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.148846] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.148868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.148890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.148907] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.148986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.148996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.149038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.149055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.149073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.149092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.149108] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.149125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.149141] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.149157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.149173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.149187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.149202] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.149206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.149219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.149223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.149237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.149251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.149266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.149279] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.149296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.149310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.149324] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.149338] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.149352] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.149368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.149386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.149424] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.149439] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.149453] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.149479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.149495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.149509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.149528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.149579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.149603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.149629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.149653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.149677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.149698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.149720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.149746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.149769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.151768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.151785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.151799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.151814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.153317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.153333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.153346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.155916] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.155936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.157744] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.160684] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.160753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.160769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.160791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.160830] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.160846] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.177498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.177523] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.177605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.177729] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.177794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.210853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.210878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.210914] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.229619] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.229642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.229659] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.229678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.229695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.229713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.229728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.229743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.229759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.229777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.229793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.229809] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.229825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.229839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.229853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.229880] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.229902] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.229923] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.229941] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.230056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.230066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.230112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.230132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.230152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.230173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.230190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.230208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.230228] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.230249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.230270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.230290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.230310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.230314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.230334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.230337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.230358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.230378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.230398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.230418] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.230439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.230459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.230479] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.230499] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.230520] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.230541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.230606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.230681] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.230707] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.230732] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.230773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.231096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.231121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.231146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.231168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.231192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.231220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.231246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.231271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.231292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.231315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.231340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.231364] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.233365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.233381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.233396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.233412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.234930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.234947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.234962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.236455] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.236471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.238278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.241209] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.241288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.241307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.241333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.241374] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.241393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.258032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.258057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.258092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.258192] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.258249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.291386] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.291411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.291447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.310257] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.310278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.310295] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.310314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.310331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.310349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.310364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.310379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.310395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.310413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.310430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.310446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.310462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.310477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.310490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.310517] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.310539] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.310606] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.310633] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.310734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.310748] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.310818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.310838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.310857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.310877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.310892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.310912] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.310932] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.310952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.310973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.310992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.311012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.311016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.311035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.311040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.311060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.311079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.311099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.311118] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.311138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.311157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.311176] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.311195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.311214] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.311235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.311256] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.311302] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.311318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.311334] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.311364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.311384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.311403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.311422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.311449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.311466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.311483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.311498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.311514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.311527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.311540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.311580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.311603] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.313595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.313612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.313626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.313643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.315148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.315164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.315180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.316692] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.316710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.318524] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.321458] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.321533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.321550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.321629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.321684] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.321709] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.338285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.338310] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.338345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.338437] [drm:drm_mode_addfb2] [FB:75]
>[ 1368.338499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.371665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.371690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.371727] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.389150] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.389173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.389189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.389209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.389226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.389244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.389259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.389274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.389293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.389315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.389336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.389356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.389376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.389395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.389414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.389442] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.389465] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.389491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.389509] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.389623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.389639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.389716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.389744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.389773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.389803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.389824] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.389843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.389860] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.389877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.389893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.389908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.389923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.389927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.389941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.389945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.389960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.389974] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.389989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.390002] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.390020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.390034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.390054] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.390074] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.390094] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.390114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.390136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.390178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.390195] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.390210] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.390248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.390265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.390280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.390295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.390309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.390324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.390340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.390356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.390371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.390384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.390397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.390414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.390429] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.392403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.392419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.392433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.392448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.393955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.393970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.393984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.395508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.395524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.397330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.400262] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.400339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.400356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.400379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.400423] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.400438] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.417083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.417108] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.417142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.417241] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.417305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.450439] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.450463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.450499] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.469359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.469381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.469398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.469417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.469434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.469452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.469471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.469491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.469510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.469532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.469553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.469620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.469648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.469672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.469695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.469733] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.469756] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.469779] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.469796] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.469877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.469886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.469929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.469946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.469971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.469989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.470004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.470020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.470035] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.470050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.470064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.470077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.470090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.470094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.470110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.470114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.470132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.470150] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.470168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.470186] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.470204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.470221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.470240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.470257] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.470275] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.470294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.470314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.470349] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.470364] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.470378] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.470405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.470423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.470441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.470459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.470477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.470494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.470514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.470532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.470554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.470599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.470621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.470646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.470667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.472662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.472679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.472693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.472707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.474210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.474225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.474239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.475736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.475752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.478659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.481604] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.481668] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.481686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.481707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.481746] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.481763] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.498412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.498438] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.498472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.498612] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.498711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.531767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.531791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.531829] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.550678] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.550699] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.550716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.550735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.550752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.550769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.550785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.550800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.550816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.550834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.550854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.550875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.550896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.550915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.550934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.550962] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.550984] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.551009] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.551028] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.551145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.551154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.551202] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.551221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.551241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.551262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.551279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.551297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.551315] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.551332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.551349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.551365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.551380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.551384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.551399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.551403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.551418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.551433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.551448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.551463] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.551480] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.551495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.551510] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.551525] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.551540] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.551557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.551621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.551696] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.551722] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.551747] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.551788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.551812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.551836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.551859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.551882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.551906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.551935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.551961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.551987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.552010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.552033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.552060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.552085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.554109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.554126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.554141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.554156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.555685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.555702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.555717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.557214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.557230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.559035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.561987] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.562044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.562062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.562087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.562125] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.562144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.578788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.578813] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.578848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.578950] [drm:drm_mode_addfb2] [FB:75]
>[ 1368.579017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.612144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.612169] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.612205] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.630363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.630385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.630402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.630421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.630438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.630456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.630471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.630486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.630502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.630520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.630537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.630553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.630569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.630627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.630649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.630693] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.630729] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.630770] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.630798] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.630888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.630897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.630938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.630954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.630971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.630990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.631005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.631021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.631037] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.631052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.631067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.631080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.631093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.631097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.631110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.631114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.631127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.631141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.631154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.631167] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.631183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.631196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.631210] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.631223] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.631236] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.631251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.631268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.631305] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.631320] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.631335] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.631364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.631382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.631402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.631420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.631439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.631457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.631478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.631498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.631518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.631536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.631555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.631607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.631630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.633627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.633644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.633658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.633673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.635186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.635204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.635218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.636731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.636749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.638558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.641498] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.641609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.641636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.641674] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.641822] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.641840] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.658319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.658345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.658379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.658478] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.658544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.691676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.691700] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.691737] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.710614] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.710637] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.710653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.710672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.710689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.710707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.710722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.710737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.710755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.710777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.710798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.710819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.710839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.710858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.710878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.710905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.710928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.710954] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.710972] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.711080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.711090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.711136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.711156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.711177] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.711201] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.711221] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.711241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.711262] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.711282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.711303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.711323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.711343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.711347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.711367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.711370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.711391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.711411] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.711431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.711451] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.711471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.711491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.711511] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.711531] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.711551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.711573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.711638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.711711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.711737] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.711762] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.711803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.711827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.711851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.711874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.711898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.711922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.711948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.711973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.711998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.712020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.712042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.712069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.712092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.714123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.714141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.714157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.714176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.715691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.715708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.715722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.717214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.717230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.719030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.721962] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.722038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.722055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.722077] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.722116] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.722132] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.738783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.738808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.738843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.738944] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.739001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.772139] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.772163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.772199] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.790897] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.790919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.790935] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.790955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.790972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.790990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.791006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.791021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.791037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.791055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.791072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.791088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.791103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.791118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.791132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.791159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.791180] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.791201] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.791219] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.791329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.791339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.791386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.791405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.791425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.791446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.791463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.791481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.791499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.791516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.791532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.791547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.791562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.791566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.791624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.791631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.791656] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.791678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.791702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.791723] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.791750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.791771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.791795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.791816] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.791839] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.791866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.791894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.791972] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.791997] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.792021] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.792061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.792085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.792107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.792130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.792150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.792174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.792200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.792225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.792250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.792274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.792295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.792320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.792343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.795430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.795447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.795462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.795477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.796993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.797011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.797026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.798606] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.798623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.800425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.803358] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.803436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.803453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.803475] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.803513] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.803530] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.820179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.820205] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.820239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.820341] [drm:drm_mode_addfb2] [FB:75]
>[ 1368.820406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.853535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.853559] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.853639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.872511] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.872535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.872554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.872576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.872642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.872674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.872700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.872725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.872751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.872780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.872806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.872832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.872858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.872881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.872903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.872947] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.872982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.873014] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.873042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.873154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.873164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.873212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.873231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.873251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.873272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.873288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.873306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.873325] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.873342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.873358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.873382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.873396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.873399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.873413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.873417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.873431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.873445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.873459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.873472] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.873490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.873508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.873527] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.873546] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.873564] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.873583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.873638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.873703] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.873725] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.873744] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.873783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.873807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.873828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.873851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.873872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.873895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.873920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.873944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.873967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.873989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.874010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.874036] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.874060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.876067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.876085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.876099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.876114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.877652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.877669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.877683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.879182] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.879200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.881021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.883976] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.884030] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.884047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.884068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.884107] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.884124] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.900775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.900800] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.900836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.900941] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.901008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.934130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1368.934155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.934192] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1368.953060] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1368.953082] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1368.953098] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.953117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.953134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.953151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.953167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.953182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.953200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.953222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.953243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.953264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.953284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.953303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.953322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.953350] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.953373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.953398] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.953416] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.953532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1368.953542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.953593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.953650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.953678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.953708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.953732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.953760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.953784] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.953810] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.953833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.953856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.953878] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.953885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.953907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.953913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.953936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.953957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.953982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.954003] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.954029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.954049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.954071] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.954092] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.954114] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.954140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.954166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.954241] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.954265] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.954289] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.954335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.954358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.954379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.954400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.954420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.954442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.954467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.954491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.954514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.954534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.954555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.954578] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.954623] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.956621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.956638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.956652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.956667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.958173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.958189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.958203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.959702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.959718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.961538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.964469] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.964496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.964512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.964534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.964578] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.964635] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.981239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.981265] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.981299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.981401] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.981467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.014596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.014638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.014677] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.033167] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.033189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.033206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.033226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.033242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.033260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.033276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.033291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.033307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.033328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.033349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.033370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.033390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.033409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.033428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.033456] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.033478] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.033504] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.033522] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.033655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.033671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.033746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.033772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.033799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.033828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.033851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.033876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.033900] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.033924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.033947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.033970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.033990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.033997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.034018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.034023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.034046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.034067] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.034090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.034111] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.034135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.034164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.034184] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.034203] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.034223] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.034245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.034269] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.034338] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.034361] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.034383] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.034418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.034439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.034460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.034480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.034501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.034521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.034545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.034568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.034591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.034635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.034658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.034684] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.034706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.036700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.036716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.036730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.036744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.038250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.038266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.038279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.039779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.039795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.041620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.044554] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.044670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.044697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.044734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.044793] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.044820] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.061381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.061407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.061441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.061543] [drm:drm_mode_addfb2] [FB:75]
>[ 1369.061657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.094763] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.094787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.094833] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.113691] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.113715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.113735] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.113757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.113777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.113799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.113818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.113838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.113857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.113879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.113900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.113920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.113941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.113960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.113979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.114006] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.114030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.114055] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.114073] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.114190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.114200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.114247] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.114266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.114286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.114307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.114324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.114344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.114365] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.114386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.114406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.114426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.114446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.114450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.114470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.114474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.114495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.114515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.114535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.114555] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.114576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.114596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.114662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.114688] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.114713] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.114742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.114770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.114846] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.114870] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.114894] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.114935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.114960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.114982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.115005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.115026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.115050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.115081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.115105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.115128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.115147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.115167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.115192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.115212] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.117210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.117226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.117240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.117255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.118774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.118792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.118809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.121391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.121410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.123226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.126162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.126236] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.126252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.126275] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.126318] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.126333] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.142987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.143012] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.143047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.143140] [drm:drm_mode_addfb2] [FB:79]
>[ 1369.143200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.176368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.176393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.176430] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.195287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.195309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.195326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.195346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.195363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.195381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.195396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.195411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.195427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.195445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.195462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.195482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.195503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.195522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.195541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.195569] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.195592] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.195664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.195691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.195790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.195804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.195875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.195900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.195920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.195940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.195956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.195974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.195992] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.196008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.196024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.196039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.196055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.196059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.196073] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.196077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.196091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.196105] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.196120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.196141] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.196156] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.196169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.196183] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.196195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.196209] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.196224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.196241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.196276] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.196290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.196303] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.196327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.196341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.196355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.196368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.196381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.196395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.196410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.196425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.196439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.196452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.196464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.196480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.196495] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.198473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.198489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.198503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.198518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.200028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.200043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.200056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.201555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.201570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.203380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.206306] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.206337] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.206353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.206381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.206416] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.206431] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.223091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.223116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.223151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.223251] [drm:drm_mode_addfb2] [FB:78]
>[ 1369.223314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.256471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.256496] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.256532] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.275408] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.275431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.275447] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.275468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.275489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.275510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.275530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.275549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.275568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.275590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.275611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.275676] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.275703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.275729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.275752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.275796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.275832] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.275867] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.275895] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.275983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.275992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.276044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.276060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.276077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.276095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.276110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.276126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.276141] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.276155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.276170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.276184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.276197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.276200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.276214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.276217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.276230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.276244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.276257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.276269] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.276284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.276297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.276310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.276323] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.276336] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.276351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.276367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.276402] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.276416] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.276429] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.276453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.276467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.276482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.276495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.276512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.276531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.276550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.276569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.276589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.276610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.276654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.276678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.276701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.278696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.278713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.278727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.278742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.280250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.280265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.280279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.281780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.281796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.283636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.286567] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.286594] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.286611] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.286682] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.286839] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.286857] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.303338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.303363] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.303399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.303502] [drm:drm_mode_addfb2] [FB:75]
>[ 1369.303570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.336685] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.336709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.336745] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.355660] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.355682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.355698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.355717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.355735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.355753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.355769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.355783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.355799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.355818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.355834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.355851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.355867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.355882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.355896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.355922] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.355946] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.355971] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.355989] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.356103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.356113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.356160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.356180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.356200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.356221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.356237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.356256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.356273] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.356290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.356307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.356323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.356338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.356341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.356356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.356359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.356375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.356390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.356405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.356419] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.356437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.356452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.356471] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.356492] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.356512] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.356534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.356556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.356597] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.356614] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.356675] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.356717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.356742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.356767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.356790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.356814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.356838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.356866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.356893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.356920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.356942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.356965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.356993] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.357017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.359031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.359048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.359063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.359078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.360586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.360602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.360649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.362156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.362174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.363996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.366942] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.367006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.367023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.367045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.367083] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.367100] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.383751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.383777] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.383811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.383914] [drm:drm_mode_addfb2] [FB:79]
>[ 1369.383981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.417106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.417132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.417171] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.436026] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.436048] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.436064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.436083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.436100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.436118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.436133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.436148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.436164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.436182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.436199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.436215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.436231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.436245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.436259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.436286] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.436308] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.436331] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.436350] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.436467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.436477] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.436524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.436543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.436563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.436587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.436607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.436673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.436698] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.436724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.436748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.436772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.436794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.436801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.436824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.436831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.436855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.436877] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.436900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.436921] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.436947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.436968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.436991] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.437013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.437036] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.437063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.437090] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.437152] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.437177] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.437201] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.437239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.437262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.437285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.437306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.437329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.437351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.437376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.437401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.437426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.437446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.437468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.437495] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.437517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.441728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.441747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.441763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.441780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.444357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.444376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.444395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.445896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.445914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.447721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.450653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.450732] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.450751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.450777] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.450817] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.450836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.467475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.467501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.467535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.467688] [drm:drm_mode_addfb2] [FB:78]
>[ 1369.467782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.500831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.500856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.500892] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.519786] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.519808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.519824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.519845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.519865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.519887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.519907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.519926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.519945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.519967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.519988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.520008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.520029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.520048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.520067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.520095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.520118] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.520143] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.520161] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.520278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.520288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.520334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.520354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.520374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.520398] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.520418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.520439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.520460] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.520480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.520501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.520521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.520540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.520544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.520564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.520568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.520589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.520609] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.520629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.520683] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.520709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.520734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.520757] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.520780] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.520802] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.520827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.520853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.520916] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.520941] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.520964] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.521004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.521021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.521037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.521052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.521066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.521085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.521107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.521128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.521150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.521169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.521188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.521209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.521229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.523242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.523260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.523278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.523296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.524821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.524838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.524853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.526347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.526364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.528168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.531099] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.531127] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.531146] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.531172] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.531213] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.531232] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.547871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.547898] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.547935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.548037] [drm:drm_mode_addfb2] [FB:75]
>[ 1369.548097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.581228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.581253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.581289] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.600134] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.600156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.600173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.600194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.600214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.600236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.600256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.600276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.600295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.600316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.600337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.600356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.600376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.600396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.600414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.600442] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.600466] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.600490] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.600509] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.600606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.600616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.600720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.600744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.600768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.600795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.600816] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.600839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.600861] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.600883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.600904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.600925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.600944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.600949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.600969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.600974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.600995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.601014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.601034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.601052] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.601075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.601095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.601115] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.601134] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.601154] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.601176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.601200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.601253] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.601275] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.601297] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.601333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.601355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.601375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.601396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.601415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.601436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.601460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.601483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.601505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.601524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.601545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.601569] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.601590] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.603598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.603615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.603665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.603691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.605221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.605246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.605269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.606777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.606793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.608599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.611519] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.611557] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.611574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.611596] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.611673] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.611699] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.628302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.628328] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.628364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.628470] [drm:drm_mode_addfb2] [FB:79]
>[ 1369.628532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.661658] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.661683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.661719] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.680677] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.680705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.680725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.680749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.680769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.680790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.680809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.680827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.680846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.680868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.680893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.680919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.680944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.680968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.680991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.681026] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.681054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.681086] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.681108] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.681243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.681256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.681314] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.681338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.681363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.681389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.681409] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.681432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.681454] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.681476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.681497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.681516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.681535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.681540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.681559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.681563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.681583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.681602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.681620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.681691] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.681723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.681751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.681781] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.681808] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.681837] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.681870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.681905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.681989] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.682023] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.682053] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.682101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.682133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.682161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.682189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.682215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.682244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.682276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.682307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.682338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.682364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.682391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.682424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.682453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.684508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.684529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.684547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.684565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.686110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.686129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.686147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.687675] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.687695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.689546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.692555] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.692611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.692631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.692705] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.692775] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.692803] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.709351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.709376] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.709410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.709504] [drm:drm_mode_addfb2] [FB:78]
>[ 1369.709571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.742707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.742732] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.742768] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.761612] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.761634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.761694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.761725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.761750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.761778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.761800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.761823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.761846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.761874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.761900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.761925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.761951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.761972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.761994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.762037] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.762071] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.762102] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.762129] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.762243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.762254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.762301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.762327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.762345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.762364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.762379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.762396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.762412] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.762428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.762443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.762458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.762472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.762475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.762489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.762492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.762506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.762520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.762534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.762547] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.762563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.762577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.762591] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.762604] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.762617] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.762633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.762690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.762756] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.762777] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.762799] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.762838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.762860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.762882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.762904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.762925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.762947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.762972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.762996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.763021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.763042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.763063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.763089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.763109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.765113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.765131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.765148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.765166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.767782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.767801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.767817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.769314] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.769331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.771154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.774087] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.774164] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.774183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.774209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.774251] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.774270] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.790908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.790933] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.790968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.791060] [drm:drm_mode_addfb2] [FB:75]
>[ 1369.791129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.824263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.824288] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.824324] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.843171] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.843194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.843210] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.843229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.843246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.843264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.843279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.843294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.843311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.843328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.843345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.843361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.843377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.843391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.843405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.843432] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.843453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.843475] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.843492] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.843588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.843599] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.843654] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.843705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.843736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.843766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.843789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.843816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.843840] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.843866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.843889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.843913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.843933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.843939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.843960] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.843966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.843990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.844011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.844033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.844053] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.844084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.844103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.844123] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.844142] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.844162] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.844183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.844207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.844277] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.844300] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.844322] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.844357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.844378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.844399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.844419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.844440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.844460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.844483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.844506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.844529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.844548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.844568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.844593] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.844613] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.846621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.846638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.846686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.846711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.848224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.848240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.848254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.849752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.849768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.851591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.854514] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.854548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.854564] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.854586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.854623] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.854640] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.871294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.871319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.871353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.871452] [drm:drm_mode_addfb2] [FB:79]
>[ 1369.871517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.904651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.904697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.904733] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1369.923585] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1369.923608] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1369.923624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1369.923644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.923706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.923739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.923764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.923790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.923816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.923846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.923873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.923899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.923925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.923948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.923972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.924015] [drm:intel_power_well_disable [i915]] disabling display
>[ 1369.924050] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1369.924082] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.924111] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1369.924212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1369.924222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1369.924267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1369.924285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1369.924304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1369.924325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1369.924344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1369.924364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1369.924383] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1369.924402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1369.924421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1369.924440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1369.924459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1369.924462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.924481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1369.924485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.924504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1369.924523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1369.924542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1369.924561] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1369.924580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1369.924598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1369.924617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1369.924636] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1369.924697] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1369.924725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.924752] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1369.924825] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1369.925013] [drm:intel_power_well_enable [i915]] enabling display
>[ 1369.925026] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1369.925054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1369.925072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1369.925090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1369.925108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1369.925126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1369.925144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1369.925163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1369.925182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1369.925201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.925219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1369.925237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1369.925255] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1369.925273] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1369.927257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1369.927276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1369.927293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.927311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1369.928836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1369.928853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1369.928868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1369.930363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1369.930380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1369.932186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1369.935118] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1369.935194] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1369.935209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1369.935230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1369.935265] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1369.935280] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1369.951940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1369.951965] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1369.952000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1369.952100] [drm:drm_mode_addfb2] [FB:78]
>[ 1369.952167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1369.985294] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1369.985319] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1369.985355] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.004209] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.004231] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.004247] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.004267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.004284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.004305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.004325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.004344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.004364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.004385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.004406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.004427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.004447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.004466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.004485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.004513] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.004536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.004561] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.004580] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.004700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.004717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.004787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.004806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.004825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.004845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.004868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.004884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.004900] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.004916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.004930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.004944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.004957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.004961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.004974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.004978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.004996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.005014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.005032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.005050] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.005068] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.005086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.005104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.005121] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.005140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.005159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.005179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.005225] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.005240] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.005255] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.005282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.005300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.005318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.005336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.005354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.005372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.005391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.005411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.005430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.005448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.005466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.005484] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.005503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.007495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.007512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.007527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.007542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.009051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.009067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.009081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.010601] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.010617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.012423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.015356] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.015432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.015448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.015470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.015508] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.015525] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.032177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.032202] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.032236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.032335] [drm:drm_mode_addfb2] [FB:75]
>[ 1370.032393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.065532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.065558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.065596] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.083691] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.083712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.083728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.083748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.083767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.083789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.083809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.083828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.083847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.083869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.083890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.083911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.083930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.083949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.083968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.083996] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.084019] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.084044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.084062] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.084170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.084180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.084227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.084247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.084267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.084290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.084310] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.084331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.084352] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.084372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.084393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.084413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.084433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.084437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.084457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.084460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.084481] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.084501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.084521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.084541] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.084561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.084581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.084601] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.084621] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.084641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.084663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.084710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.084783] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.084809] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.084833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.084874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.084899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.084923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.084945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.084969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.084993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.085020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.085046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.085071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.085092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.085115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.085142] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.085164] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.087182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.087199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.087217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.087235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.088770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.088788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.088806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.090302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.090320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.092128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.095070] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.095137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.095154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.095176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.095214] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.095231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.111879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.111903] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.111936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.112029] [drm:drm_mode_addfb2] [FB:79]
>[ 1370.112095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.145237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.145260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.145295] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.164233] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.164261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.164282] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.164307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.164328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.164355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.164381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.164406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.164431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.164459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.164486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.164513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.164538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.164563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.164587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.164623] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.164652] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.164745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.164780] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.164921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.164940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.165031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.165061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.165086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.165114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.165139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.165165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.165190] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.165216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.165241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.165267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.165292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.165298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.165322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.165327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.165352] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.165378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.165402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.165427] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.165452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.165477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.165502] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.165527] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.165552] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.165578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.165604] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.165654] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.165718] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.165746] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.165797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.165828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.165857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.165886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.165913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.165942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.165974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.166005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.166037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.166066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.166092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.166125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.166157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.168237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.168259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.168278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.168297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.169889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.169914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.169938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.171470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.171493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.173335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.176282] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.176345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.176362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.176385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.176424] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.176444] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.193083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.193108] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.193143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.193235] [drm:drm_mode_addfb2] [FB:78]
>[ 1370.193303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.226461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.226490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.226533] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.245400] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.245422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.245441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.245463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.245483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.245505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.245525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.245544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.245563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.245584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.245605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.245625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.245645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.245664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.245727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.245772] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.245809] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.245845] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.245874] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.245974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.245984] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.246028] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.246045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.246064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.246084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.246101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.246122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.246142] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.246162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.246181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.246201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.246220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.246225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.246244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.246248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.246274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.246291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.246306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.246320] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.246336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.246350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.246364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.246377] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.246390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.246406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.246423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.246457] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.246470] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.246484] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.246512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.246530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.246547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.246564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.246583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.246601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.246620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.246639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.246658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.246698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.246721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.246746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.246768] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.248758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.248774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.248788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.248803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.250305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.250320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.250333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.251829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.251845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.253651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.256604] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.256660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.256717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.256755] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.256899] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.256916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.273403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.273429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.273463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.273563] [drm:drm_mode_addfb2] [FB:75]
>[ 1370.273629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.306759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.306784] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.306821] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.325670] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.325708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.325724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.325743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.325760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.325778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.325793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.325808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.325824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.325842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.325858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.325874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.325890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.325905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.325918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.325945] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.325967] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.325989] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.326007] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.326120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.326130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.326175] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.326196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.326216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.326239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.326258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.326278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.326298] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.326318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.326338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.326357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.326376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.326380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.326399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.326403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.326423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.326443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.326462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.326482] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.326502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.326521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.326540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.326560] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.326580] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.326600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.326622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.326671] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.326734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.326757] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.326799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.326823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.326846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.326868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.326889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.326912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.326937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.326960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.326984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.327005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.327026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.327051] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.327074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.329077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.329096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.329113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.329131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.330707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.330724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.330738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.332248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.332266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.334095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.337041] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.337106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.337126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.337152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.337192] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.337212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.353850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.353876] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.353910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.354011] [drm:drm_mode_addfb2] [FB:79]
>[ 1370.354078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.387233] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.387270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.387325] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.406166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.406188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.406204] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.406223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.406240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.406258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.406274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.406288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.406304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.406322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.406339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.406355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.406371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.406385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.406399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.406426] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.406448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.406468] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.406485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.406601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.406611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.406658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.406677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.406736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.406764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.406787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.406820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.406843] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.406866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.406887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.406908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.406928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.406935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.406954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.406960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.406981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.407001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.407021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.407042] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.407066] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.407086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.407107] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.407127] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.407149] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.407173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.407199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.407268] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.407293] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.407316] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.407355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.407379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.407402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.407418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.407431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.407447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.407463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.407478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.407493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.407507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.407520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.407537] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.407553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.409544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.409562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.409576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.409591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.411099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.411115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.411131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.412629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.412646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.414452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.417387] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.417461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.417478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.417500] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.417538] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.417554] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.434206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.434231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.434268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.434370] [drm:drm_mode_addfb2] [FB:78]
>[ 1370.434431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.467561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.467587] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.467626] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.486085] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.486108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.486124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.486144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.486160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.486178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.486194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.486209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.486225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.486242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.486259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.486275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.486291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.486305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.486319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.486346] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.486368] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.486390] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.486407] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.486515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.486526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.486573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.486592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.486612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.486633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.486649] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.486667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.486724] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.486749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.486772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.486794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.486817] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.486824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.486845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.486851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.486873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.486894] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.486916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.486937] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.486962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.486983] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.487005] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.487026] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.487048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.487073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.487098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.487358] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.487374] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.487388] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.487417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.487434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.487450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.487465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.487480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.487496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.487513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.487529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.487545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.487559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.487573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.487591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.487608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.489598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.489615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.489630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.489645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.491152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.491167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.491181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.492677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.492703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.494506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.497438] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.497516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.497533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.497554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.497593] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.497612] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.514259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.514284] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.514318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.514419] [drm:drm_mode_addfb2] [FB:75]
>[ 1370.514484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.547615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.547640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.547676] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.566639] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.566662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.566679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.566743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.566770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.566800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.566823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.566848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.566871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.566900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.566926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.566952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.566978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.567000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.567023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.567067] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.567102] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.567135] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.567165] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.567281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.567292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.567340] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.567360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.567381] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.567403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.567423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.567445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.567466] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.567487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.567508] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.567529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.567550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.567554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.567575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.567579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.567600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.567621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.567642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.567663] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.567684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.567750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.567776] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.567800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.567824] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.567851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.567879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.567954] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.567979] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.568005] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.568049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.568076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.568101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.568127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.568152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.568178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.568207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.568234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.568261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.568277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.568292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.568311] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.568327] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.570319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.570335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.570350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.570365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.571887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.571904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.571919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.573413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.573430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.575237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.578170] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.578247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.578264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.578286] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.578324] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.578341] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.594991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.595017] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.595051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.595150] [drm:drm_mode_addfb2] [FB:79]
>[ 1370.595216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.628346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.628371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.628407] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.647205] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.647227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.647244] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.647263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.647280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.647298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.647314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.647329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.647345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.647367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.647388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.647409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.647429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.647448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.647467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.647495] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.647518] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.647544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.647562] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.647660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.647671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.647776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.647802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.647828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.647858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.647880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.647906] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.647930] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.647955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.647978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.648001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.648021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.648028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.648049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.648054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.648077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.648098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.648121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.648141] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.648166] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.648187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.648209] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.648230] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.648251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.648276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.648303] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.648374] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.648400] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.648423] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.648462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.648492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.648513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.648533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.648554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.648574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.648598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.648620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.648643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.648662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.648682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.648728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.648749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.650743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.650760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.650775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.650789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.652296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.652311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.652325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.653823] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.653838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.655644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.658566] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.658602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.658621] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.658647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.658693] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.658746] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.675346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.675371] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.675405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.675507] [drm:drm_mode_addfb2] [FB:78]
>[ 1370.675572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.708702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.708743] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.708779] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.727407] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.727431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.727448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.727471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.727492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.727516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.727537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.727558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.727578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.727601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.727624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.727645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.727666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.727686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.727753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.727798] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.727838] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.727874] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.727904] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.728025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.728041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.728115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.728143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.728173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.728204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.728231] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.728259] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.728288] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.728315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.728342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.728368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.728393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.728400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.728424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.728430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.728456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.728481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.728506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.728530] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.728558] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.728582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.728607] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.728630] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.728654] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.728682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.728732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.728807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.728836] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.728862] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.728905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.728933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.728960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.728986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.729011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.729037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.729067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.729094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.729121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.729146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.729172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.729200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.729227] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.731289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.731309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.731325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.731344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.732872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.732892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.732912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.734420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.734439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.736259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.739205] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.739269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.739286] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.739309] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.739348] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.739368] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.756021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.756046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.756080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.756179] [drm:drm_mode_addfb2] [FB:75]
>[ 1370.756244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.789369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.789396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.789435] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.808311] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.808334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.808350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.808369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.808386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.808404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.808419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.808434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.808450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.808471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.808492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.808513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.808533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.808552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.808572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.808600] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.808623] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.808648] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.808666] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.808808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.808823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.808894] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.808921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.808949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.808980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.809004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.809031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.809057] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.809089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.809112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.809133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.809155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.809160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.809181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.809186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.809208] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.809229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.809250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.809271] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.809296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.809317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.809336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.809358] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.809380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.809404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.809428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.809491] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.809514] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.809536] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.809573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.809596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.809618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.809641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.809661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.809683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.809726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.809749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.809774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.809796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.809819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.809845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.809869] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.811858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.811874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.811888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.811903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.813406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.813424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.813442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.814939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.814956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.816761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.819692] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.819772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.819792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.819817] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.819858] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.819877] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.836515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.836542] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.836579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.836682] [drm:drm_mode_addfb2] [FB:79]
>[ 1370.836793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.869871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.869897] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.869935] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.888784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.888806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.888826] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.888848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.888868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.888890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.888909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.888929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.888948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.888970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.888991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.889011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.889031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.889050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.889069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.889096] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.889119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.889144] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.889162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.889272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.889282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.889329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.889348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.889368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.889389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.889405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.889423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.889441] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.889458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.889475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.889491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.889506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.889509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.889524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.889528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.889543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.889558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.889574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.889588] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.889606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.889621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.889635] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.889650] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.889670] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.889691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.889741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.889812] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.889837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.889862] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.889903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.889930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.889953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.889977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.889999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.890377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.890405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.890432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.890458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.890479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.890502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.890529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.890553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.892553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.892570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.892584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.892602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.894110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.894126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.894140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.895651] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.895669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.897477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.900409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.900486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.900503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.900525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.900563] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.900583] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.917231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.917258] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.917295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.917397] [drm:drm_mode_addfb2] [FB:78]
>[ 1370.917458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.950586] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1370.950611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1370.950646] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1370.969505] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1370.969527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1370.969543] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1370.969563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.969580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.969597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.969613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.969628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.969644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.969662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.969679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.969695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.969711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.969771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.969794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.969837] [drm:intel_power_well_disable [i915]] disabling display
>[ 1370.969872] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1370.969906] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.969934] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1370.970045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1370.970059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1370.970128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1370.970154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1370.970182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1370.970211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1370.970236] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1370.970262] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1370.970289] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1370.970313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1370.970338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1370.970362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1370.970385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1370.970391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.970414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1370.970420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1370.970443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1370.970467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1370.970491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1370.970514] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1370.970540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1370.970563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1370.970587] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1370.970608] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1370.970631] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1370.970656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1370.970684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1370.970772] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1370.970806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1370.970829] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1370.970866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1370.970889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1370.970912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1370.970935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1370.970957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1370.970979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1370.971003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1370.971027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1370.971050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.971072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1370.971093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1370.971117] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1370.971140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1370.973130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1370.973148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1370.973165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.973183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1370.974695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1370.974712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1370.974763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1370.976263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1370.976281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1370.978112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1370.981052] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1370.981122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1370.981142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1370.981168] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1370.981208] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1370.981227] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1370.997865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1370.997890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1370.997925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1370.998026] [drm:drm_mode_addfb2] [FB:75]
>[ 1370.998092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.031219] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.031245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.031283] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.050131] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.050153] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.050169] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.050191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.050211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.050232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.050252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.050272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.050291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.050313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.050334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.050354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.050374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.050393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.050412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.050440] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.050463] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.050488] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.050506] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.050625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.050635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.050679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.050697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.050716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.050773] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.050796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.050823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.050846] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.050870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.050892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.050915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.050935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.050943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.050963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.050970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.050992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.051013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.051035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.051055] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.051080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.051100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.051122] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.051143] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.051164] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.051189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.051215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.051573] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.051596] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.051618] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.051655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.051677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.051699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.051719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.051757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.051779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.051804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.051828] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.051852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.052010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.052031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.052056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.052077] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.054078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.054095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.054109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.054124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.055627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.055643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.055656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.057153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.057169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.058973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.061913] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.061982] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.061999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.062021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.062059] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.062075] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.078742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.078767] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.078801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.078901] [drm:drm_mode_addfb2] [FB:79]
>[ 1371.078967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.112082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.112108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.112146] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.130994] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.131016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.131033] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.131053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.131070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.131091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.131111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.131130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.131150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.131171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.131192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.131213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.131232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.131251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.131270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.131298] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.131321] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.131346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.131364] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.131481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.131491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.131538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.131558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.131577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.131599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.131616] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.131634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.131652] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.131669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.131686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.131701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.131721] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.131758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.131784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.131791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.131817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.131840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.131864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.131886] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.131912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.131934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.131958] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.131980] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.132003] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.132030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.132059] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.132443] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.132468] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.132491] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.132532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.132555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.132578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.132606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.132627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.132648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.132671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.132694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.132718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.132759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.132779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.132804] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.132826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.134974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.134991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.135005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.135020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.136527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.136542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.136556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.138055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.138071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.139881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.142827] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.142891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.142908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.142930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.142968] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.142985] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.159637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.159663] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.159697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.159915] [drm:drm_mode_addfb2] [FB:78]
>[ 1371.159980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.193023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.193047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.193084] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.211965] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.211989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.212009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.212030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.212050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.212072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.212092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.212111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.212130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.212152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.212173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.212193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.212213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.212232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.212251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.212279] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.212301] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.212326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.212344] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.212459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.212469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.212512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.212529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.212548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.212567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.212583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.212599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.212616] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.212632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.212647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.212661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.212675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.212679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.212693] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.212696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.212710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.212724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.212780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.212801] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.212826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.212846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.212868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.212888] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.212909] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.212931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.212956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.213011] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.213036] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.213058] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.213095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.213116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.213139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.213159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.213180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.213201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.213224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.213247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.213270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.213289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.213310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.213332] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.213354] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.215355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.215372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.215387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.215401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.216912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.216927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.216940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.218435] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.218451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.220261] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.223185] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.223218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.223235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.223257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.223295] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.223311] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.239972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.239997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.240032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.240133] [drm:drm_mode_addfb2] [FB:75]
>[ 1371.240200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.273352] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.273378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.273416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.292285] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.292307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.292323] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.292343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.292360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.292378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.292393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.292408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.292424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.292442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.292459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.292475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.292491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.292509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.292529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.292557] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.292579] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.292605] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.292623] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.292713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.292761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.292837] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.292864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.292892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.292922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.292945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.292971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.292996] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.293022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.293044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.293068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.293089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.293095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.293116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.293122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.293145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.293166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.293195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.293214] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.293237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.293256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.293278] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.293297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.293317] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.293338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.293362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.293419] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.293442] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.293463] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.293499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.293520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.293542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.293561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.293582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.293603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.293626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.293649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.293673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.293692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.293712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.293737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.293779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.296874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.296893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.296908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.296924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.301636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.301655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.301671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.304275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.304293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.306116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.309054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.309125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.309142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.309164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.309202] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.309218] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.325867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.325890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.325922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.326020] [drm:drm_mode_addfb2] [FB:79]
>[ 1371.326075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.359257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.359283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.359321] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.377526] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.377559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.377583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.377611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.377636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.377662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.377684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.377706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.377729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.377827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.377870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.377910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.377949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.377984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.378018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.378083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.378134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.378181] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.378222] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.378377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.378401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.378507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.378545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.378585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.378629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.378663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.378701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.378736] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.378814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.378850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.378886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.378919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.378931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.378964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.378974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.379010] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.379043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.379078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.379109] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.379148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.379180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.379214] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.379246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.379280] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.379320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.379359] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.379456] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.379491] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.379524] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.379579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.379611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.379644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.379675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.379707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.379739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.379801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.379838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.379876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.379907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.379941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.379981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.380014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.382092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.382117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.382139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.382162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.383742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.383785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.383807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.385378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.385405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.387296] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.390234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.390308] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.390332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.390352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.390396] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.390419] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.407052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.407078] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.407112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.407214] [drm:drm_mode_addfb2] [FB:78]
>[ 1371.407279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.440424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.440454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.440509] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.459402] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.459424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.459441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.459461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.459480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.459502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.459522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.459541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.459560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.459582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.459603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.459623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.459643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.459663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.459681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.459709] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.459732] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.459802] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.459832] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.459943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.459958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.460032] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.460054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.460079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.460105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.460126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.460149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.460171] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.460193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.460213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.460234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.460254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.460259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.460279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.460284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.460305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.460324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.460344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.460363] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.460385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.460404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.460425] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.460444] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.460464] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.460485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.460509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.460572] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.460594] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.460616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.460652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.460673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.460694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.460714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.460735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.460778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.460803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.460827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.460852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.460872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.460893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.460919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.460941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.462929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.462945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.462959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.462973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.464477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.464492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.464506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.466001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.466017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.467821] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.470745] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.470831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.470848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.470869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.470917] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.470943] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.487573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.487598] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.487633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.487761] [drm:drm_mode_addfb2] [FB:75]
>[ 1371.487862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.520930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.520954] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.520999] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.539843] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.539866] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.539882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.539901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.539918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.539936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.539955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.539975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.539995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.540016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.540037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.540057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.540078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.540097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.540116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.540144] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.540167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.540191] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.540210] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.540325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.540335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.540382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.540402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.540423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.540446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.540466] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.540487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.540508] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.540528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.540549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.540569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.540589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.540593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.540612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.540616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.540637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.540657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.540677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.540697] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.540718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.540738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.540803] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.540832] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.540858] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.540887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.540916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.540975] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.541001] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.541027] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.541068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.541093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.541118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.541143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.541167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.541192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.541219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.541245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.541271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.541294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.541317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.541345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.541370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.543385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.543402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.543417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.543432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.544940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.544956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.544970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.546461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.546477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.548284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.551216] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.551293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.551310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.551333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.551380] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.551406] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.568036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.568062] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.568099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.568199] [drm:drm_mode_addfb2] [FB:79]
>[ 1371.568267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.601392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.601417] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.601462] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.620353] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.620375] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.620392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.620411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.620428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.620446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.620462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.620477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.620493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.620511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.620528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.620544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.620560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.620574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.620588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.620615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.620636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.620658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.620675] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.620804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.620821] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.620898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.620927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.620956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.620986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.621011] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.621038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.621065] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.621090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.621115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.621139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.621162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.621168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.621191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.621197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.621220] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.621244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.621267] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.621290] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.621315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.621339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.621362] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.621386] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.621410] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.621434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.621462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.621522] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.621548] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.621572] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.621620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.621643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.621665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.621688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.621710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.621732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.621777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.621801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.621827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.621849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.621872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.621898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.621922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.623921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.623940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.623957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.623975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.625482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.625499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.625513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.627009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.627025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.628828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.631769] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.631838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.631862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.631885] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.631930] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.631954] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.648582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.648608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.648645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.648739] [drm:drm_mode_addfb2] [FB:78]
>[ 1371.648875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.681937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.681963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.682008] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.700617] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.700640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.700657] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.700678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.700695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.700717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.700737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.700758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.700821] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.700853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.700882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.700910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.700937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.700960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.700985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.701030] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.701066] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.701099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.701128] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.701252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.701269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.701340] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.701358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.701377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.701397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.701413] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.701430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.701449] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.701469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.701488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.701507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.701526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.701530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.701548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.701552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.701572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.701591] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.701610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.701629] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.701648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.701667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.701686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.701705] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.701723] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.701743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.701809] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.701873] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.701900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.701924] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.701965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.701991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.702017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.702042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.702064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.702089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.702116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.702142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.702168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.702190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.702213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.702241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.702266] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.704290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.704307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.704322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.704337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.705866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.705884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.705898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.707393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.707409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.709216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.712162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.712226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.712242] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.712265] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.712312] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.712338] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.728970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.728995] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.729030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.729130] [drm:drm_mode_addfb2] [FB:75]
>[ 1371.729188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.762325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.762349] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.762394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.781281] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.781303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.781323] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.781345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.781365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.781387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.781406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.781426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.781445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.781466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.781487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.781507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.781528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.781547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.781566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.781594] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.781616] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.781642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.781660] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.781771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.781788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.781844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.781872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.781901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.781931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.781956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.781983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.782009] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.782035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.782057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.782072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.782087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.782090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.782104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.782108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.782122] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.782136] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.782150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.782164] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.782180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.782194] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.782208] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.782221] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.782234] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.782251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.782269] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.782317] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.782333] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.782347] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.782373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.782388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.782402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.782424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.782437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.782450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.782465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.782479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.782494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.782506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.782519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.782534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.782549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.784525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.784541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.784556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.784571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.786077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.786092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.786106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.787598] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.787614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.789419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.792329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.792375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.792391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.792413] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.792460] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.792485] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.809123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.809148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.809184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.809287] [drm:drm_mode_addfb2] [FB:79]
>[ 1371.809354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.842478] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.842504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.842550] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.861405] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.861428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.861444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.861463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.861480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.861498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.861514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.861528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.861544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.861562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.861579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.861594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.861610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.861624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.861638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.861665] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.861687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.861708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.861725] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.861851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.861865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.861910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.861927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.861945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.861965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.861983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.862004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.862024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.862044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.862064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.862083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.862102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.862107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.862125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.862129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.862147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.862166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.862194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.862211] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.862227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.862243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.862257] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.862271] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.862285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.862301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.862317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.862359] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.862374] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.862386] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.862411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.862426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.862440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.862453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.862467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.862481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.862496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.862511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.862525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.862538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.862551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.862567] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.862582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.864562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.864581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.864598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.864616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.866127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.866144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.866158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.867651] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.867667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.869473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.872413] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.872480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.872496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.872517] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.872562] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.872586] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.889226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.889252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.889288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.889391] [drm:drm_mode_addfb2] [FB:78]
>[ 1371.889458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.922581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1371.922606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1371.922651] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1371.941493] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1371.941515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1371.941531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1371.941551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.941568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.941585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.941601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.941615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.941631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.941649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.941665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.941681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.941698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.941712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.941725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.941752] [drm:intel_power_well_disable [i915]] disabling display
>[ 1371.941816] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1371.941848] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.941878] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1371.941989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1371.942010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1371.942072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1371.942088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1371.942105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1371.942123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1371.942137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1371.942153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1371.942169] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1371.942184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1371.942197] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1371.942211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1371.942224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1371.942229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.942241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1371.942244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1371.942258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1371.942271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1371.942284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1371.942296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1371.942312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1371.942325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1371.942338] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1371.942350] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1371.942364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1371.942378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.942395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1371.942437] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1371.942451] [drm:intel_power_well_enable [i915]] enabling display
>[ 1371.942464] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1371.942489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1371.942503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1371.942518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1371.942531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1371.942544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1371.942561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1371.942581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1371.942601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1371.942620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.942638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1371.942656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1371.942675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1371.942693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1371.944673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1371.944690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1371.944707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.944725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1371.946235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1371.946252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1371.946270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1371.947765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1371.947796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1371.950679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1371.953612] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1371.953689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1371.953706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1371.953728] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1371.953775] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1371.953942] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1371.970433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1371.970458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1371.970493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1371.970592] [drm:drm_mode_addfb2] [FB:75]
>[ 1371.970657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.003804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.003829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.003874] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.022837] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.022862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.022881] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.022904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.022923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.022944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.022965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.022988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.023010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.023034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.023058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.023082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.023104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.023126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.023148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.023179] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.023206] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.023234] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.023255] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.023384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.023396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.023450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.023472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.023495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.023523] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.023546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.023570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.023594] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.023617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.023641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.023664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.023687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.023691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.023714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.023718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.023742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.023766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.023848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.023873] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.023899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.023922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.023945] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.023968] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.023989] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.024014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.024040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.024114] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.024138] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.024163] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.024192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.024208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.024224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.024239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.024258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.024277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.024299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.024321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.024341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.024361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.024378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.024400] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.024419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.026415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.026433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.026450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.026468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.027978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.027995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.028009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.029504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.029521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.031325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.034257] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.034335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.034351] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.034374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.034422] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.034447] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.051078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.051104] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.051141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.051244] [drm:drm_mode_addfb2] [FB:79]
>[ 1372.051313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.084434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.084460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.084506] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.103269] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.103291] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.103307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.103327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.103344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.103365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.103385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.103404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.103423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.103445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.103466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.103487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.103506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.103526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.103545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.103572] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.103595] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.103621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.103639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.103742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.103753] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.103851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.103876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.103903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.103932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.103955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.103980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.104003] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.104027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.104049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.104070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.104090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.104096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.104117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.104122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.104144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.104163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.104184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.104203] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.104226] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.104246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.104267] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.104286] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.104307] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.104329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.104353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.104421] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.104444] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.104466] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.104503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.104524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.104547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.104567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.104588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.104609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.104633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.104657] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.104688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.104707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.104728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.104750] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.104772] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.106799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.106816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.106830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.106845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.108364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.108381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.108396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.109897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.109913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.111726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.114657] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.114684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.114701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.114723] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.114772] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.114832] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.131428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.131453] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.131488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.131588] [drm:drm_mode_addfb2] [FB:78]
>[ 1372.131645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.164785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.164825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.164871] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.183756] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.183778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.183838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.183866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.183893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.183920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.183943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.183966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.183988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.184016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.184042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.184067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.184092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.184114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.184136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.184177] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.184211] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.184242] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.184269] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.184372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.184383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.184429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.184447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.184466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.184488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.184507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.184527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.184546] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.184565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.184584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.184603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.184622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.184626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.184644] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.184648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.184674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.184690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.184705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.184719] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.184734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.184748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.184761] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.184774] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.184830] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.184856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.184883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.184951] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.184975] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.184997] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.185037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.185061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.185084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.185106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.185128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.185151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.185176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.185199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.185224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.185245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.185267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.185292] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.185315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.187327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.187343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.187358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.187377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.188896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.188913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.188928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.190421] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.190437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.192245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.195192] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.195255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.195272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.195293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.195332] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.195349] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.211996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.212020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.212053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.212156] [drm:drm_mode_addfb2] [FB:75]
>[ 1372.212228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.245354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.245377] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.245411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.264265] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.264287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.264303] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.264323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.264342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.264364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.264384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.264403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.264423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.264445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.264465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.264486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.264506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.264525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.264544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.264572] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.264594] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.264620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.264638] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.264733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.264745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.264799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.264852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.264883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.264913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.264936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.264964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.264989] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.265015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.265038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.265063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.265085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.265093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.265114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.265120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.265143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.265168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.265190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.265213] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.265236] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.265258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.265279] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.265302] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.265322] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.265347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.265374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.265436] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.265461] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.265485] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.265529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.265550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.265571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.265591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.265611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.265632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.265655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.265678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.265701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.265720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.265740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.265765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.265786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.267817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.267833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.267847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.267861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.269373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.269388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.269402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.270912] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.270930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.272741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.275672] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.275750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.275765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.275785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.275956] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.275972] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.292495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.292521] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.292558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.292662] [drm:drm_mode_addfb2] [FB:79]
>[ 1372.292729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.325850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.325874] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.325911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.344760] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.344784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.344849] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.344880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.344907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.344935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.344955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.344971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.344987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.345006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.345024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.345040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.345061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.345080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.345100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.345129] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.345152] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.345177] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.345195] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.345279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.345288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.345329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.345346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.345363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.345384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.345401] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.345420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.345438] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.345457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.345474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.345492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.345509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.345514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.345531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.345535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.345553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.345571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.345589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.345606] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.345624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.345641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.345660] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.345678] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.345695] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.345714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.345734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.345771] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.345788] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.345833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.345872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.345894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.345916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.345936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.345957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.345978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.346002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.346025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.346048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.346067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.346087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.346111] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.346132] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.348126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.348144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.348161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.348179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.349685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.349701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.349716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.351212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.351228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.353031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.355976] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.356041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.356060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.356086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.356127] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.356146] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.372784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.372826] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.372861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.372960] [drm:drm_mode_addfb2] [FB:78]
>[ 1372.373025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.406140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.406164] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.406200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.425047] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.425069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.425086] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.425105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.425122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.425140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.425155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.425174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.425194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.425215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.425236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.425257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.425277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.425296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.425315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.425343] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.425366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.425391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.425409] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.425525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.425535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.425582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.425602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.425622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.425643] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.425659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.425677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.425696] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.425713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.425730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.425746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.425761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.425765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.425780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.425783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.425804] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.425859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.425882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.425907] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.425931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.425955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.425977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.426000] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.426022] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.426049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.426078] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.426151] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.426175] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.426200] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.426239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.426262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.426285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.426307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.426329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.426351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.426377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.426402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.426427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.426448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.426471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.426496] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.426520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.428530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.428547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.428562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.428577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.430083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.430098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.430114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.431607] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.431625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.433431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.436363] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.436439] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.436454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.436474] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.436509] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.436524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.453173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.453198] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.453232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.453325] [drm:drm_mode_addfb2] [FB:75]
>[ 1372.453394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.486573] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.486597] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.486634] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.505491] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.505513] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.505529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.505549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.505565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.505583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.505598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.505613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.505629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.505647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.505663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.505679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.505695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.505709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.505723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.505750] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.505772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.505792] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.505856] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.505971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.505986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.506055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.506078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.506105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.506134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.506157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.506189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.506210] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.506232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.506253] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.506274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.506293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.506298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.506317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.506323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.506344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.506363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.506383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.506402] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.506425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.506444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.506464] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.506483] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.506503] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.506525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.506548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.506600] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.506622] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.506644] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.506679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.506700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.506721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.506740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.506761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.506781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.506804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.506845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.506870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.506890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.506912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.506938] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.506959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.508957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.508974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.508989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.509003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.510506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.510524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.510542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.512038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.512055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.513861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.516791] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.516872] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.516891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.516917] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.516967] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.516993] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.533613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.533640] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.533677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.533780] [drm:drm_mode_addfb2] [FB:79]
>[ 1372.533908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.566970] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.566994] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.567039] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.585935] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.585957] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.585974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.585995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.586015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.586037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.586057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.586076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.586095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.586117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.586138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.586157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.586178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.586197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.586216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.586244] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.586266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.586292] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.586310] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.586418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.586428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.586475] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.586496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.586517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.586541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.586561] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.586582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.586602] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.586623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.586643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.586663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.586683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.586687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.586707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.586711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.586731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.586752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.586772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.586792] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.586812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.586872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.586898] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.586923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.586946] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.586973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.587002] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.587065] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.587091] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.587115] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.587156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.587182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.587207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.587231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.587255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.587279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.587306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.587332] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.587358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.587382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.587405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.587432] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.587458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.589461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.589478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.589495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.589513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.591030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.591048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.591062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.592555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.592571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.595456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.598389] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.598467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.598484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.598506] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.598554] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.598580] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.615211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.615237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.615275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.615377] [drm:drm_mode_addfb2] [FB:78]
>[ 1372.615438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.648566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.648590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.648636] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.667493] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.667515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.667531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.667551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.667568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.667585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.667600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.667615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.667631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.667649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.667665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.667681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.667697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.667711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.667725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.667751] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.667773] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.667794] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.667811] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.667947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.667962] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.668031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.668057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.668084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.668104] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.668119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.668137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.668154] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.668170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.668185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.668199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.668213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.668218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.668231] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.668235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.668250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.668264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.668278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.668291] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.668308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.668322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.668337] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.668350] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.668365] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.668381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.668399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.668445] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.668460] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.668474] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.668500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.668517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.668532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.668546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.668560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.668576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.668593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.668609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.668625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.668639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.668653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.668671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.668687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.670661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.670677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.670691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.670705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.672212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.672230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.672247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.673762] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.673779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.675585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.678504] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.678541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.678558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.678579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.678627] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.678652] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.695287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.695312] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.695347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.695447] [drm:drm_mode_addfb2] [FB:75]
>[ 1372.695510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.728642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.728667] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.728711] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.747596] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.747618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.747635] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.747654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.747671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.747688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.747703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.747718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.747734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.747752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.747768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.747784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.747800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.747814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.747871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.747915] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.747952] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.747986] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.748015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.748102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.748112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.748155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.748172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.748191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.748214] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.748233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.748254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.748274] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.748294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.748313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.748333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.748353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.748357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.748376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.748380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.748400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.748419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.748438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.748457] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.748477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.748496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.748515] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.748532] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.748551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.748571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.748593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.748633] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.748649] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.748665] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.748694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.748721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.748737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.748755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.748774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.748791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.748813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.748859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.748883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.748903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.748923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.748947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.748969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.750964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.750980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.750994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.751009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.752512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.752527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.752540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.754036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.754053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.755859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.758789] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.758816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.758875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.758912] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.759048] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.759066] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.775558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.775582] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.775615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.775713] [drm:drm_mode_addfb2] [FB:79]
>[ 1372.775776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.808917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.808943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.808982] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.827861] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.827884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.827900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.827919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.827936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.827953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.827969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.827984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.828000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.828018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.828034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.828050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.828066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.828080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.828094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.828121] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.828142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.828163] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.828180] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.828293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.828303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.828350] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.828371] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.828393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.828416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.828436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.828457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.828477] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.828497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.828518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.828538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.828557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.828561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.828581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.828585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.828606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.828626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.828646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.828666] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.828687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.828707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.828727] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.828747] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.828767] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.828788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.828810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.828905] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.828930] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.828955] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.828997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.829022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.829047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.829070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.829094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.829118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.829146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.829173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.829200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.829222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.829246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.829274] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.829297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.831303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.831320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.831335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.831350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.832884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.832899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.832913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.834409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.834426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.836234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.839179] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.839243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.839260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.839282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.839321] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.839338] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.855987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.856012] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.856046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.856147] [drm:drm_mode_addfb2] [FB:78]
>[ 1372.856213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.889342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.889367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.889403] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.908248] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.908270] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.908286] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.908306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.908322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.908340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.908355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.908370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.908386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.908404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.908421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.908437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.908452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.908466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.908480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.908507] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.908529] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.908550] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.908567] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.908683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.908693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.908740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.908759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.908780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.908801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.908818] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.908877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.908903] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.908928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.908954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.908977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.909001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.909007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.909031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.909037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.909062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.909084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.909108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.909129] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.909155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.909177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.909200] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.909222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.909245] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.909273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.909301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.909689] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.909713] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.909737] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.909777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.909801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.909825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.909873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.909895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.909921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.909949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.909975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.910092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.910114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.910135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.910161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.910184] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.912195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.912212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.912227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.912242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.913771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.913787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.913800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.915295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.915311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.917114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.920059] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.920124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.920141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.920163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1372.920202] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1372.920218] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1372.936869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.936895] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.936932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.937036] [drm:drm_mode_addfb2] [FB:75]
>[ 1372.937106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.970223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1372.970247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1372.970283] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1372.988367] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1372.988390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1372.988407] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1372.988427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.988444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.988462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.988478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.988493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.988510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1372.988529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.988546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.988562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.988578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.988593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.988607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.988634] [drm:intel_power_well_disable [i915]] disabling display
>[ 1372.988657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1372.988678] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1372.988696] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1372.988797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1372.988808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1372.988918] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1372.988945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1372.988975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1372.989007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1372.989033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1372.989061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1372.989089] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1372.989116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1372.989142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1372.989167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1372.989191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1372.989198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.989222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1372.989228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1372.989253] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1372.989277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1372.989299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1372.989322] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1372.989347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1372.989370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1372.989391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1372.989415] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1372.989436] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1372.989462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1372.989490] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1372.989564] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1372.989590] [drm:intel_power_well_enable [i915]] enabling display
>[ 1372.989614] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1372.989654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1372.989678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1372.989702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1372.989725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1372.989747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1372.989770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1372.989797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1372.989823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1372.989874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1372.989897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1372.989922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1372.989951] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1372.989975] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1372.991979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1372.991996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1372.992011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.992025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1372.993528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1372.993543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1372.993557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1372.995053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1372.995069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1372.996872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1372.999803] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1372.999921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1372.999947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1372.999985] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.000135] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.000152] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.016626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.016652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.016686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.016787] [drm:drm_mode_addfb2] [FB:79]
>[ 1373.016890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.049979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.050003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.050041] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.068894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.068916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.068935] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.068957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.068977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.068998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.069017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.069037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.069056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.069078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.069099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.069119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.069140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.069159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.069178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.069206] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.069229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.069254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.069272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.069379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.069389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.069436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.069455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.069475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.069496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.069515] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.069536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.069557] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.069577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.069598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.069618] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.069638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.069642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.069662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.069665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.069686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.069706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.069727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.069747] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.069767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.069787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.069807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.069828] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.069892] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.069919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.069949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.070021] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.070047] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.070071] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.070112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.070434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.070458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.070483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.070505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.070529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.070556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.070581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.070606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.070627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.070649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.070674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.070699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.072704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.072721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.072736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.072752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.074258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.074274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.074287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.075782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.075798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.077603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.079770] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.079803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.079820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.079889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.080040] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.080056] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.096549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.096576] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.096613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.096717] [drm:drm_mode_addfb2] [FB:78]
>[ 1373.096784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.129903] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.129928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.129967] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.148855] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.148894] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.148910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.148930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.148947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.148965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.148980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.148995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.149011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.149029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.149045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.149065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.149086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.149106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.149124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.149152] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.149175] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.149200] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.149218] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.149331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.149342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.149389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.149408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.149428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.149449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.149465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.149484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.149501] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.149518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.149535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.149550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.149565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.149569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.149584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.149588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.149603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.149623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.149644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.149664] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.149684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.149704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.149725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.149745] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.149765] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.149786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.149808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.149898] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.149925] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.149947] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.149989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.150016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.150040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.150065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.150087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.150113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.150141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.150167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.150194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.150216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.150240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.150268] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.150292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.152640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.152657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.152672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.152687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.154193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.154209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.154223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.155715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.155731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.157536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.160469] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.160546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.160562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.160584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.160622] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.160639] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.177291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.177316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.177350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.177451] [drm:drm_mode_addfb2] [FB:75]
>[ 1373.177516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.210645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.210670] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.210707] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.229569] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.229591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.229607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.229627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.229643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.229665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.229684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.229704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.229723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.229745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.229766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.229787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.229807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.229825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.229845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.229922] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.229959] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.229994] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.230022] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.230135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.230150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.230218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.230251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.230277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.230305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.230327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.230352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.230376] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.230399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.230421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.230443] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.230465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.230471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.230491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.230497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.230518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.230540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.230562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.230583] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.230607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.230628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.230649] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.230670] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.230689] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.230712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.230737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.230800] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.230824] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.230846] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.230905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.230929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.230953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.230975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.230997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.231021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.231047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.231072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.231096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.231118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.231140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.231166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.231190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.233179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.233195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.233209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.233223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.235802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.235823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.235842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.237387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.237405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.240292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.243239] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.243302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.243319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.243341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.243379] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.243395] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.260046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.260071] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.260106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.260204] [drm:drm_mode_addfb2] [FB:79]
>[ 1373.260269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.293426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.293463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.293516] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.312439] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.312464] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.312486] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.312511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.312534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.312558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.312581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.312603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.312625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.312650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.312674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.312698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.312720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.312742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.312764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.312796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.312822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.312850] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.312926] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.313059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.313076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.313155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.313185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.313217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.313251] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.313280] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.313310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.313341] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.313369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.313398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.313425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.313452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.313459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.313484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.313491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.313518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.313545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.313572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.313598] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.313626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.313653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.313681] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.313708] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.313734] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.313764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.313796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.313894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.313919] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.313941] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.313980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.314005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.314030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.314053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.314076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.314098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.314125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.314151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.314176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.314205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.314228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.314253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.314276] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.316266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.316282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.316297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.316312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.317818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.317833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.317847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.319391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.319409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.321231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.324168] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.324241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.324258] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.324280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.324318] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.324338] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.340985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.341010] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.341045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.341142] [drm:drm_mode_addfb2] [FB:78]
>[ 1373.341209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.374363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.374403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.374462] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.393145] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.393174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.393197] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.393223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.393247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.393273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.393296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.393319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.393343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.393368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.393393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.393418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.393441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.393464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.393486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.393520] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.393547] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.393577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.393598] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.393729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.393741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.393797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.393820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.393844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.393922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.393952] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.393985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.394015] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.394046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.394074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.394103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.394128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.394137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.394163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.394171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.394200] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.394226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.394254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.394279] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.394310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.394336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.394364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.394390] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.394418] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.394448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.394481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.394937] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.394966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.394992] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.395039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.395066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.395094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.395119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.395145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.395172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.395203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.395232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.395262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.395286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.395311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.395340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.395368] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.397411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.397432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.397451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.397470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.399018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.399040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.399058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.400582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.400602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.402442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.405445] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.405506] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.405525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.405550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.405593] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.405612] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.422252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.422280] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.422318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.422428] [drm:drm_mode_addfb2] [FB:75]
>[ 1373.422491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.455617] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.455646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.455689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.474720] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.474750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.474776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.474804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.474830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.474858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.474942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.474981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.475016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.475056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.475092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.475126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.475161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.475191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.475221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.475274] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.475318] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.475360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.475396] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.475527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.475542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.475611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.475629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.475648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.475670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.475689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.475709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.475728] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.475747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.475767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.475785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.475804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.475808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.475826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.475830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.475849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.475910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.475935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.475958] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.475984] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.476007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.476036] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.476056] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.476077] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.476100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.476125] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.476326] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.476341] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.476354] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.476382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.476398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.476413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.476427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.476440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.476455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.476471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.476487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.476502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.476515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.476529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.476546] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.476561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.478552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.478569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.478584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.478599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.480105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.480120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.480134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.481625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.481641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.483445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.486378] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.486454] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.486471] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.486493] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.486531] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.486548] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.503199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.503225] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.503259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.503359] [drm:drm_mode_addfb2] [FB:79]
>[ 1373.503416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.536554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.536578] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.536615] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.555460] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.555482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.555499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.555518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.555535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.555553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.555568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.555583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.555599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.555617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.555634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.555650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.555666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.555680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.555699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.555727] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.555750] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.555775] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.555794] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.555926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.555943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.556017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.556045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.556073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.556102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.556126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.556152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.556178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.556201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.556224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.556245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.556267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.556273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.556294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.556300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.556323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.556343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.556365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.556385] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.556410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.556430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.556451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.556472] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.556493] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.556516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.556541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.556612] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.556635] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.556658] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.556695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.556717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.556740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.556760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.556782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.556804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.556829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.556854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.556908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.556928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.556950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.556976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.556997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.558994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.559011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.559026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.559041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.560544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.560562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.560579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.562077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.562094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.563898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.566829] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.566948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.566977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.567015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.567167] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.567183] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.583651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.583677] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.583711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.583814] [drm:drm_mode_addfb2] [FB:78]
>[ 1373.583924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.617006] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.617031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.617068] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.635921] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.635943] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.635959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.635979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.635996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.636014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.636029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.636045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.636061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.636079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.636095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.636111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.636127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.636142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.636156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.636183] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.636205] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.636225] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.636242] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.636356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.636367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.636414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.636435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.636456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.636480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.636500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.636521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.636541] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.636561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.636582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.636602] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.636622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.636626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.636646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.636650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.636670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.636691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.636711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.636731] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.636752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.636771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.636791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.636812] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.636832] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.636853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.636875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.636982] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.637008] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.637032] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.637075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.637102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.637126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.637151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.637173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.637198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.637226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.637584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.637610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.637632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.637656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.637683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.637706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.639716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.639733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.639748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.639763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.641271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.641286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.641300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.642822] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.642840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.644647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.647579] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.647656] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.647673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.647695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.647734] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.647752] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.664400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.664425] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.664460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.664559] [drm:drm_mode_addfb2] [FB:75]
>[ 1373.664625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.697756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.697781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.697817] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.716668] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.716692] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.716712] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.716734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.716753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.716775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.716795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.716814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.716833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.716855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.716875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.716944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.716976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.717002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.717028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.717072] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.717107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.717141] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.717169] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.717283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.717298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.717367] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.717393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.717421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.717450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.717474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.717500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.717525] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.717550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.717575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.717605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.717627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.717632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.717652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.717658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.717679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.717700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.717719] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.717739] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.717763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.717783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.717803] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.717823] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.717844] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.717865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.717911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.717966] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.717990] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.718012] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.718049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.718072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.718095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.718117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.718139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.718162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.718186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.718210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.718233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.718254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.718275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.718297] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.718320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.720309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.720325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.720339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.720354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.721860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.721876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.721920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.723419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.723434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.725264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.728208] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.728273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.728290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.728312] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.728350] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.728367] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.745019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.745044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.745078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.745178] [drm:drm_mode_addfb2] [FB:79]
>[ 1373.745243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.778406] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.778446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.778504] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.797400] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.797425] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.797445] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.797467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.797486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.797508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.797528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.797547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.797567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.797589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.797609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.797629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.797650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.797669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.797688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.797716] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.797739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.797763] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.797781] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.797909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.797927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.798003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.798029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.798056] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.798085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.798107] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.798133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.798157] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.798181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.798204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.798227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.798248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.798255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.798276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.798282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.798305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.798326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.798348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.798369] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.798394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.798415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.798438] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.798465] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.798486] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.798507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.798531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.798598] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.798620] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.798641] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.798677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.798698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.798719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.798738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.798759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.798779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.798802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.798825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.798849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.798867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.798909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.798935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.798957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.800954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.800972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.800989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.801007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.802516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.802534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.802551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.804048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.804065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.805870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.808813] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.808840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.808857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.808879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.808971] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.808997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.825586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.825611] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.825645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.825736] [drm:drm_mode_addfb2] [FB:78]
>[ 1373.825805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.858940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.858964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.859001] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.877845] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.877868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.877884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.877952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.877982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.878011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.878036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.878061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.878087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.878116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.878143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.878169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.878194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.878218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.878240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.878284] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.878318] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.878356] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.878382] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.878502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.878511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.878554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.878574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.878593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.878615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.878633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.878652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.878671] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.878689] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.878708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.878726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.878745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.878748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.878766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.878770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.878788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.878807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.878826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.878844] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.878863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.878881] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.878937] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.878960] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.878981] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.879005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.879029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.879095] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.879119] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.879141] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.879180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.879204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.879227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.879249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.879271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.879295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.879320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.879345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.879369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.879390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.879404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.879421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.879436] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.881426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.881443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.881457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.881472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.883001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.883019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.883037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.884533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.884550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.886355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.889287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.889371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.889388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.889409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.889448] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.889465] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.906111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.906136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.906171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.906271] [drm:drm_mode_addfb2] [FB:75]
>[ 1373.906329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.939465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1373.939489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1373.939525] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1373.958421] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1373.958443] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1373.958460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1373.958479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.958495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.958513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.958532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.958552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.958571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.958592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.958613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.958634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.958654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.958674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.958693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.958720] [drm:intel_power_well_disable [i915]] disabling display
>[ 1373.958743] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1373.958768] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.958786] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1373.958876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1373.958912] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1373.958988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1373.959020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1373.959046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1373.959072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1373.959093] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1373.959117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1373.959139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1373.959161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1373.959182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1373.959204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1373.959223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1373.959229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.959249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1373.959254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1373.959275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1373.959294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1373.959314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1373.959333] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1373.959356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1373.959375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1373.959396] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1373.959415] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1373.959435] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1373.959456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1373.959480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1373.959548] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1373.959570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1373.959591] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1373.959627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1373.959647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1373.959669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1373.959688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1373.959709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1373.959729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1373.959753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1373.959777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1373.959800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.959819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1373.959839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1373.959864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1373.959885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1373.963005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1373.963022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1373.963036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.963051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1373.964570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1373.964586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1373.964600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1373.966096] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1373.966112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1373.967916] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1373.970847] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1373.970874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1373.970891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1373.970963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1373.971022] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1373.971047] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1373.987620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1373.987645] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1373.987679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1373.987773] [drm:drm_mode_addfb2] [FB:79]
>[ 1373.987839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.020975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.020999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.021037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.039891] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.039932] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.039952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.039974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.039993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.040015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.040035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.040054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.040073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.040095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.040116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.040136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.040156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.040175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.040194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.040222] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.040245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.040270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.040288] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.040403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.040413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.040461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.040480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.040500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.040521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.040539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.040560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.040581] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.040601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.040622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.040642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.040662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.040665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.040685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.040689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.040710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.040730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.040750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.040770] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.040791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.040811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.040831] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.040851] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.040871] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.040892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.040956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.041031] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.041057] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.041082] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.041123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.041148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.041174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.041196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.041220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.041244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.041271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.041297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.041322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.041344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.041366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.041393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.041416] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.043439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.043455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.043470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.043485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.044996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.045012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.045025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.046518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.046534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.048338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.051283] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.051347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.051364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.051386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.051425] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.051442] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.068092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.068117] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.068152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.068243] [drm:drm_mode_addfb2] [FB:78]
>[ 1374.068310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.101448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.101474] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.101512] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.119745] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.119769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.119789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.119810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.119830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.119852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.119871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.119891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.119956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.119990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.120019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.120046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.120073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.120097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.120122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.120166] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.120201] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.120233] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.120261] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.120381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.120399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.120465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.120483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.120502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.120522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.120544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.120560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.120576] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.120593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.120611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.120629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.120646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.120649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.120666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.120670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.120688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.120705] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.120722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.120739] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.120757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.120774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.120791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.120809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.120826] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.120844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.120863] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.120945] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.120967] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.120988] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.121026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.121048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.121070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.121090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.121111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.121132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.121158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.121182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.121204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.121226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.121247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.121272] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.121296] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.123303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.123321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.123335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.123350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.124858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.124874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.124888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.126432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.126448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.128270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.131210] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.131280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.131297] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.131319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.131358] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.131375] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.148027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.148053] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.148087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.148187] [drm:drm_mode_addfb2] [FB:75]
>[ 1374.148254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.181420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.181464] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.181528] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.200414] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.200436] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.200453] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.200474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.200494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.200516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.200536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.200555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.200574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.200596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.200617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.200637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.200656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.200675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.200694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.200722] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.200745] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.200771] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.200789] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.200887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.200937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.201013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.201038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.201065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.201094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.201117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.201143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.201167] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.201191] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.201214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.201245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.201264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.201270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.201289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.201294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.201315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.201334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.201354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.201373] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.201396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.201415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.201435] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.201454] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.201474] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.201496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.201520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.201588] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.201611] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.201632] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.201668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.201690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.201711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.201731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.201751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.201772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.201795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.201818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.201841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.201861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.201881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.201903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.201946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.203942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.203959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.203973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.203988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.205493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.205508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.205522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.207019] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.207034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.208856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.211787] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.211814] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.211833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.211859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.211899] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.211960] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.228559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.228586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.228623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.228724] [drm:drm_mode_addfb2] [FB:79]
>[ 1374.228793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.261915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.261955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.261992] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.280976] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.281003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.281023] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.281048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.281069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.281090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.281109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.281127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.281147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.281169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.281189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.281209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.281229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.281246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.281264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.281297] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.281323] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.281349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.281370] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.281506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.281519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.281578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.281602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.281627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.281654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.281674] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.281696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.281718] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.281739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.281760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.281779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.281798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.281803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.281822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.281826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.281845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.281864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.281888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.281913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.281986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.282016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.282047] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.282074] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.282104] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.282137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.282172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.282262] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.282294] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.282324] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.282373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.282403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.282430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.282458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.282484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.282514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.282546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.282578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.282609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.282635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.282664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.282705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.282732] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.284755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.284772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.284786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.284801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.286307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.286325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.286343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.287855] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.287872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.289678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.292602] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.292636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.292653] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.292678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.292718] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.292738] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.309382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.309407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.309441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.309541] [drm:drm_mode_addfb2] [FB:78]
>[ 1374.309599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.342737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.342761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.342797] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.361637] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.361658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.361675] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.361694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.361713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.361735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.361755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.361775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.361794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.361816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.361837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.361857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.361877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.361896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.361915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.361994] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.362030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.362066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.362094] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.362193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.362208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.362277] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.362303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.362332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.362361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.362387] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.362413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.362439] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.362464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.362490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.362514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.362537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.362543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.362565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.362571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.362595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.362619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.362642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.362664] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.362689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.362712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.362736] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.362759] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.362782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.362808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.362835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.362910] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.362954] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.362975] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.363013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.363037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.363061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.363084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.363106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.363129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.363154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.363179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.363203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.363225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.363247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.363273] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.363296] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.365285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.365301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.365315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.365329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.366866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.366881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.366895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.368420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.368436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.370271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.373216] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.373280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.373297] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.373319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.373357] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.373374] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.390025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.390050] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.390084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.390194] [drm:drm_mode_addfb2] [FB:75]
>[ 1374.390264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.423379] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.423404] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.423441] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.442295] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.442318] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.442334] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.442356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.442376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.442398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.442417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.442437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.442456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.442477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.442498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.442519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.442539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.442558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.442577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.442604] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.442627] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.442652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.442670] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.442785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.442795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.442842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.442862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.442889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.442911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.442971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.443000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.443024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.443048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.443071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.443094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.443115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.443122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.443143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.443149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.443171] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.443191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.443213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.443233] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.443259] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.443279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.443301] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.443321] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.443343] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.443368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.443395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.443452] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.443475] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.443497] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.443534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.443555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.443577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.443597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.443618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.443638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.443663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.443687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.443712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.443731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.443753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.443776] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.443798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.445809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.445826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.445841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.445856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.447365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.447383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.447401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.448900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.448917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.450751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.453683] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.453760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.453777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.453799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.453837] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.453853] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.470504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.470530] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.470567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.470660] [drm:drm_mode_addfb2] [FB:79]
>[ 1374.470730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.503856] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.503879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.503914] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.522879] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.522904] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.522925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.522994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.523025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.523055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.523082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.523107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.523134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.523164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.523192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.523219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.523246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.523270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.523293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.523338] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.523374] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.523407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.523436] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.523555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.523565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.523614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.523636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.523658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.523682] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.523703] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.523725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.523746] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.523767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.523788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.523809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.523829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.523833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.523854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.523858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.523879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.523900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.523921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.523987] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.524015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.524040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.524065] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.524088] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.524111] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.524138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.524166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.524229] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.524256] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.524281] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.524322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.524339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.524355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.524371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.524386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.524403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.524425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.524447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.524468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.524488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.524506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.524529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.524549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.526558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.526577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.526594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.526612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.528122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.528139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.528153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.529647] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.529665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.531473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.534405] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.534482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.534499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.534521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.534560] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.534577] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.551226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.551252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.551288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.551390] [drm:drm_mode_addfb2] [FB:78]
>[ 1374.551458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.584617] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.584656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.584715] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.603581] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.603603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.603619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.603639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.603656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.603673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.603688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.603703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.603719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.603737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.603753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.603770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.603786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.603800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.603814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.603841] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.603863] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.603884] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.603901] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.604042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.604057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.604125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.604152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.604180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.604209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.604234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.604260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.604286] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.604311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.604335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.604359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.604382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.604389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.604411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.604417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.604440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.604463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.604486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.604508] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.604541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.604562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.604582] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.604602] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.604624] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.604647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.604672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.604734] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.604757] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.604779] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.604816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.604839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.604862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.604884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.604904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.604926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.604974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.604997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.605022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.605044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.605067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.605092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.605116] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.607106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.607122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.607136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.607150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.608654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.608672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.608689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.610187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.610203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.612009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.614934] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.615018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.615034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.615056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.615094] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.615111] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.631762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.631787] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.631822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.631956] [drm:drm_mode_addfb2] [FB:75]
>[ 1374.632061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.665117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.665144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.665182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.684031] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.684053] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.684069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.684089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.684106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.684123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.684138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.684153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.684169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.684187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.684204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.684220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.684236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.684250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.684264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.684291] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.684313] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.684334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.684351] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.684465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.684476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.684523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.684544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.684565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.684589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.684609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.684630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.684650] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.684671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.684691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.684711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.684732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.684736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.684756] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.684759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.684780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.684800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.684820] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.684840] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.684861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.684881] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.684901] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.684921] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.684984] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.685011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.685041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.685101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.685126] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.685151] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.685192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.685218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.685241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.685266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.685288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.685312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.685338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.685365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.685391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.685412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.685434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.685468] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.685489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.687493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.687511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.687529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.687547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.689069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.689087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.689102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.690594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.690614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.692442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.695394] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.695451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.695468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.695490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.695531] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.695550] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.712195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.712221] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.712256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.712357] [drm:drm_mode_addfb2] [FB:79]
>[ 1374.712415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.745552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.745577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.745614] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.764523] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.764547] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.764564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.764585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.764603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.764622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.764639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.764654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.764671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.764694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.764716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.764738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.764760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.764780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.764801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.764830] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.764855] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.764881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.764900] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.765033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.765050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.765136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.765165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.765194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.765226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.765252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.765281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.765309] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.765335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.765362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.765387] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.765412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.765419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.765443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.765449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.765474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.765499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.765524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.765548] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.765577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.765601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.765627] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.765652] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.765675] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.765702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.765731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.765807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.765834] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.765860] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.765902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.765928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.765973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.766001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.766025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.766052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.766081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.766111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.766139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.766165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.766191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.766221] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.766248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.768258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.768276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.768293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.768314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.769823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.769839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.769853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.771350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.771366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.773169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.777195] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.777239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.777256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.777278] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.777317] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.777333] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.793985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.794010] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.794044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.794161] [drm:drm_mode_addfb2] [FB:78]
>[ 1374.794219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.827341] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.827365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.827401] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.846296] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.846320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.846340] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.846362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.846382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.846403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.846423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.846442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.846461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.846483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.846504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.846523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.846544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.846563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.846582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.846610] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.846633] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.846658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.846676] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.846790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.846800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.846847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.846867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.846887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.846908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.846925] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.846943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.847003] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.847028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.847051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.847074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.847095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.847102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.847123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.847130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.847152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.847173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.847195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.847216] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.847240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.847261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.847283] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.847304] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.847325] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.847350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.847375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.847436] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.847461] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.847485] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.847527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.847552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.847577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.847601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.847626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.847651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.847679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.847704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.847721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.847735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.847755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.847776] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.847796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.849789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.849806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.849821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.849836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.851345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.851363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.851380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.852897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.852915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.854723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.857655] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.857734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.857754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.857780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.857820] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.857839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.874476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.874501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.874536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.874635] [drm:drm_mode_addfb2] [FB:75]
>[ 1374.874700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.907832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.907857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.907893] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1374.926815] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1374.926842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1374.926865] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1374.926890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.926913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.926938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.927013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.927047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.927079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.927114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.927146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.927176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.927206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.927233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.927260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.927306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1374.927346] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1374.927383] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.927415] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1374.927548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1374.927560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1374.927613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1374.927634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1374.927656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1374.927678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1374.927697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1374.927716] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1374.927736] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1374.927754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1374.927772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1374.927788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1374.927805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1374.927809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.927825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1374.927829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1374.927845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1374.927861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1374.927878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1374.927893] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1374.927912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1374.927928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1374.927944] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1374.928018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1374.928043] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1374.928073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.928105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1374.928169] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1374.928199] [drm:intel_power_well_enable [i915]] enabling display
>[ 1374.928227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1374.928271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1374.928301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1374.928328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1374.928354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1374.928378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1374.928406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1374.928436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1374.928465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1374.928493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.928517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1374.928542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1374.928570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1374.928599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1374.930645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1374.930665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1374.930683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.930702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1374.932231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1374.932249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1374.932270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1374.933784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1374.933806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1374.935635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1374.939657] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1374.939707] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1374.939724] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1374.939748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1374.939789] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1374.939809] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1374.956451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1374.956476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1374.956511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1374.956610] [drm:drm_mode_addfb2] [FB:79]
>[ 1374.956675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1374.989807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1374.989831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1374.989868] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.008729] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.008751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.008767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.008787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.008804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.008822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.008837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.008852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.008868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.008886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.008903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.008918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.008934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.008948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.009007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.009050] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.009085] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.009118] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.009146] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.009259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.009273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.009342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.009368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.009395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.009425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.009450] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.009476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.009502] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.009527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.009552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.009575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.009598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.009605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.009627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.009633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.009657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.009681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.009704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.009728] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.009753] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.009777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.009800] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.009822] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.009845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.009870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.009898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.009989] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.010013] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.010034] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.010072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.010097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.010119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.010142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.010164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.010188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.010213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.010238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.010262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.010284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.010305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.010331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.010354] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.012347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.012363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.012377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.012391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.013897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.013913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.013927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.015420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.015437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.017241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.020184] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.020249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.020265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.020286] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.020322] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.020340] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.036995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.037020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.037055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.037154] [drm:drm_mode_addfb2] [FB:78]
>[ 1375.037220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.070350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.070374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.070411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.089264] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.089286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.089302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.089321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.089338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.089356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.089372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.089391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.089410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.089432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.089453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.089474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.089495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.089514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.089532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.089560] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.089583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.089608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.089626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.089742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.089753] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.089799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.089819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.089839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.089866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.089882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.089902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.089922] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.089942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.089962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.090021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.090045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.090052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.090075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.090082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.090108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.090130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.090153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.090174] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.090201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.090222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.090245] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.090266] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.090288] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.090315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.090342] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.090403] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.090427] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.090451] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.090488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.090510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.090534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.090555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.090576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.090598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.090622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.090647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.090671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.090691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.090712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.090738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.090760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.092762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.092779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.092794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.092808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.094313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.094328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.094342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.095834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.095850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.097656] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.100588] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.100665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.100682] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.100704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.100742] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.100762] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.117409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.117436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.117473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.117576] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.117646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.150765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.150791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.150830] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.169664] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.169685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.169702] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.169721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.169738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.169756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.169772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.169787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.169803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.169821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.169838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.169854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.169870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.169889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.169908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.169936] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.169959] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.170030] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.170058] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.170158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.170172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.170242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.170260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.170278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.170298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.170315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.170332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.170349] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.170368] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.170388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.170408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.170427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.170431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.170450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.170454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.170474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.170494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.170514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.170533] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.170553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.170572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.170592] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.170611] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.170630] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.170651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.170672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.170726] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.170741] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.170753] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.170781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.170797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.170812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.170826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.170843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.170861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.170881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.170900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.170919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.170936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.170955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.171002] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.171026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.173015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.173031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.173046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.173060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.174588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.174604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.174618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.176134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.176153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.177963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.180912] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.181019] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.181044] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.181079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.181132] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.181156] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.197729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.197755] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.197792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.197897] [drm:drm_mode_addfb2] [FB:79]
>[ 1375.197958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.231084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.231110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.231157] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.250046] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.250068] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.250088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.250109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.250130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.250151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.250171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.250190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.250209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.250231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.250252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.250273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.250293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.250312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.250331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.250359] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.250382] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.250407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.250425] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.250533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.250543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.250591] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.250617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.250635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.250654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.250669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.250686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.250703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.250719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.250734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.250749] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.250763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.250766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.250780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.250784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.250798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.250812] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.250826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.250840] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.250856] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.250869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.250883] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.250897] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.250911] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.250930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.250950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.251028] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.251052] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.251074] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.251113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.251137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.251158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.251181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.251201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.251225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.251250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.251275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.251300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.251320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.251341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.251367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.251389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.253391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.253408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.253422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.253437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.254944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.254961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.255011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.257587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.257605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.259417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.262362] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.262426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.262443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.262465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.262513] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.262540] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.279170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.279195] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.279230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.279331] [drm:drm_mode_addfb2] [FB:78]
>[ 1375.279395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.312526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.312552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.312598] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.331499] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.331522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.331538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.331557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.331574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.331592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.331607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.331622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.331638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.331656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.331672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.331688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.331704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.331719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.331732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.331760] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.331782] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.331803] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.331820] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.331917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.331929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.331984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.332035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.332066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.332096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.332120] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.332148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.332173] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.332199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.332222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.332246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.332267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.332274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.332296] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.332304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.332327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.332355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.332375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.332394] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.332417] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.332436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.332456] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.332475] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.332495] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.332519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.332543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.332600] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.332622] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.332644] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.332680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.332701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.332722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.332742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.332763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.332783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.332806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.332829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.332852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.332871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.332891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.332914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.332936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.334947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.334964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.335010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.335036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.336546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.336562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.336575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.338082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.338100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.339928] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.342859] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.342886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.342903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.342925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.342974] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.343035] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.359625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.359649] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.359682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.359795] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.359866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.393002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.393027] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.393073] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.411917] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.411940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.411959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.411981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.412043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.412074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.412098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.412123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.412147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.412175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.412202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.412227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.412253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.412274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.412296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.412339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.412373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.412405] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.412433] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.412548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.412559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.412606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.412627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.412649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.412672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.412692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.412713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.412734] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.412754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.412774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.412794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.412814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.412818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.412838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.412842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.412862] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.412883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.412903] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.412923] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.412943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.412963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.412984] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.413039] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.413067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.413096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.413126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.413192] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.413216] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.413239] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.413276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.413301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.413324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.413347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.413366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.413389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.413414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.413437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.413461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.413482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.413501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.413526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.413549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.415546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.415565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.415582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.415600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.417119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.417138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.417155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.418653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.418671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.420499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.423434] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.423508] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.423525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.423546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.423585] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.423602] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.440254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.440280] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.440317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.440430] [drm:drm_mode_addfb2] [FB:79]
>[ 1375.440505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.473609] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.473633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.473679] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.492541] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.492563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.492580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.492602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.492622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.492644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.492663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.492683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.492702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.492724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.492745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.492765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.492786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.492805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.492824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.492852] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.492875] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.492900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.492918] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.493040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.493056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.493130] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.493156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.493183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.493211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.493234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.493260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.493285] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.493309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.493332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.493355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.493377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.493382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.493403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.493409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.493431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.493453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.493474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.493495] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.493520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.493542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.493564] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.493586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.493608] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.493632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.493658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.493728] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.493752] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.493775] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.493813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.493837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.493860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.493882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.493905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.493929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.493954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.493986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.494037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.494059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.494081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.494107] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.494131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.496128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.496145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.496160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.496175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.497676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.497691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.497704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.499198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.499214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.501016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.503946] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.503973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.504022] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.504058] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.504123] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.504145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.520720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.520745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.520780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.520892] [drm:drm_mode_addfb2] [FB:78]
>[ 1375.520966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.554074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.554099] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.554135] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.573024] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.573046] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.573063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.573084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.573104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.573126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.573145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.573165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.573184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.573206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.573226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.573247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.573267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.573286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.573305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.573333] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.573355] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.573380] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.573398] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.573505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.573515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.573561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.573581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.573601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.573623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.573641] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.573661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.573681] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1375.573700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1375.573719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.573738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.573757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.573761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.573779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.573783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.573802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.573821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.573840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.573859] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1375.573883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.573910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.573935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1375.573958] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1375.573981] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1375.574049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.574077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1375.574148] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.574173] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.574197] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.574238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.574262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.574286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.574309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.574331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.574354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.574379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.574404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.574428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.574450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.574471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.574497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1375.574521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.576547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.576564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.576579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.576594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.578120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.578137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.578152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.579645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.579660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.581464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.584409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1375.584473] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.584490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1375.584512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.584549] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1375.584566] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1375.601217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.601243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.601277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.601376] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.601434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.634565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1375.634591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.634630] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1375.653493] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1375.653516] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1375.653532] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.653551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.653568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.653585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.653601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.653616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.653632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.653650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.653667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.653683] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.653699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.653713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.653727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.653754] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.653776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.653798] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1375.653815] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.654091] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.654132] [drm:drm_mode_addfb2] [FB:78]
>[ 1375.677219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1375.677305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.677362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1375.677415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.677425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.677473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.677491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.677510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.677530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.677548] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.677566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.677584] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1375.677601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1375.677619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.677636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.677653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.677657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.677674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.677677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.677695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.677712] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.677730] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.677747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1375.677765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.677782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.677799] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1375.677817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1375.677834] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1375.677853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.677872] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1375.680401] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.680417] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.680432] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.680461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.680478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.680494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.680509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.680524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.680539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.680556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.680572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.680591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.680609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.680628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.680648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1375.680667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.682661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.682678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.682692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.682707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.684224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.684241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.684255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.685749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.685765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.687571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.690506] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1375.690582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.690599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1375.690622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.707325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.707351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.707386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.724034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.724044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.740767] [drm:drm_mode_addfb2] [FB:79]
>[ 1375.740836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.757388] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1375.757414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.757454] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1375.776308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1375.776327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.776347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.776364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.776382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.776397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.776411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.776427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.776445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.776463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.776484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.776505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.776524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.776543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.776571] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.776594] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.776619] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.776636] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.776748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.776758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.776803] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.776821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.776840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.776859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.776875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.776892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.776909] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1375.776925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1375.776941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.776959] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.776978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.776982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.777001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.777042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.777069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.777093] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.777118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.777140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1375.777167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.777189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.777213] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1375.777235] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1375.777258] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1375.777285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.777313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1375.777385] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.777410] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.777435] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.777475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.777499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.777522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.777544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.777565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.777589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.777615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.777641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.777666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.777687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.777709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.777733] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1375.777758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.779762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.779779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.779794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.779809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.781316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.781331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.781345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.782837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.782854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.784661] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.787592] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1375.787670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.787686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1375.787715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.804413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.804439] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.804473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.804575] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.804642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.821093] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1375.821119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.821157] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1375.840005] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1375.840047] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.840068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.840085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.840103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.840118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.840137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.840157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.840179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.840199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.840220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.840240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.840259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.840278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.840306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.840329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.840353] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.840370] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.840465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.840476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.840523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.840544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.840565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.840589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.840609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.840630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.840650] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1375.840671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1375.840691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.840711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.840731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.840735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.840755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.840759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.840780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.840800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.840820] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.840840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1375.840860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.840880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.840901] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1375.840921] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1375.840941] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1375.840963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.840984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1375.841105] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.841130] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.841155] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.841199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.841224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.841249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.841272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.841296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.841681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.841710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.841737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.841763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.841785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.841807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.841833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1375.841857] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.843867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.843884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.843902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.843920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.845433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.845451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.845468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.846969] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.846987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.848828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.851765] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1375.851838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.851854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1375.851876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.868609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.868636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.868673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.868778] [drm:drm_mode_addfb2] [FB:78]
>[ 1375.868838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.885277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1375.885302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.885339] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1375.903245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1375.903264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.903285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.903302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.903320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.903336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.903351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.903367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.903385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.903402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.903418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.903434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.903448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.903463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.903490] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.903512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.903536] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.903553] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.903660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.903671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.903718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.903737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.903757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.903779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.903799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.903820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.903841] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1375.903861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1375.903882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.903902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.903922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.903926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.903946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.903949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.903970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.903990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.904011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.904072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1375.904098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.904125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.904148] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1375.904173] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1375.904196] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1375.904224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.904252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1375.904327] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.904351] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.904374] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.904416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.904439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.904463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.904485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.904508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.904531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.904556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.904582] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.904607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.904628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.904651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.904678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1375.904701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.906721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.906738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.906753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.906768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.908276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.908291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.908305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.909797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.909813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.911619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.914551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1375.914626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.914641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1375.914662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.931370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.931396] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.931431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.931542] [drm:drm_mode_addfb2] [FB:79]
>[ 1375.931614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.948065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1375.948089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1375.948134] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1375.966981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1375.967001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1375.967066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.967092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.967121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.967143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.967167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.967190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.967218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.967244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.967271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.967296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.967317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.967340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.967383] [drm:intel_power_well_disable [i915]] disabling display
>[ 1375.967417] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1375.967448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.967474] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1375.967586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1375.967596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1375.967643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1375.967663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1375.967682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1375.967703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1375.967720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1375.967739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1375.967757] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1375.967774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1375.967790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1375.967806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1375.967828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1375.967832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.967846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1375.967850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1375.967865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1375.967879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1375.967893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1375.967907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1375.967924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1375.967939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1375.967953] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1375.967968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1375.967982] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1375.967998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1375.968064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1375.968138] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1375.968161] [drm:intel_power_well_enable [i915]] enabling display
>[ 1375.968186] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1375.968226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1375.968251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1375.968276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1375.968300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1375.968323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1375.968348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1375.968374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1375.968399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1375.968423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.968444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1375.968467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1375.968494] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1375.968518] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1375.970534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1375.970550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1375.970564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.970580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1375.972103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1375.972121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1375.972135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1375.973632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1375.973649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1375.975458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1375.978403] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1375.978468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1375.978484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1375.978506] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1375.995210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1375.995236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1375.995270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1375.995383] [drm:drm_mode_addfb2] [FB:75]
>[ 1375.995457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.011911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.011935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.011981] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.030785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.030804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.030824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.030841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.030859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.030874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.030889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.030905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.030923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.030940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.030956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.030972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.030987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.031001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.031077] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.031114] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.031148] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.031174] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.031272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.031281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.031332] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.031349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.031366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.031386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.031403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.031422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.031440] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.031458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.031477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.031495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.031512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.031517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.031534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.031537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.031555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.031573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.031590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.031608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.031626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.031643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.031661] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.031678] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.031696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.031715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.031734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.031777] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.031791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.031805] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.031833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.031851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.031869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.031886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.031905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.031922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.031942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.031961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.031981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.031998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.032017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.032060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.032084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.034073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.034089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.034103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.034118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.035624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.035639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.035653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.037155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.037173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.038978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.041908] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.041936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.041953] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.041975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.058678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.058705] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.058742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.058842] [drm:drm_mode_addfb2] [FB:78]
>[ 1376.058909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.075359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.075383] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.075428] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.094274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.094293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.094315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.094335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.094356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.094376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.094395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.094415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.094437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.094457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.094478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.094498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.094518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.094537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.094565] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.094587] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.094612] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.094628] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.094744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.094754] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.094802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.094821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.094841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.094863] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.094884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.094905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.094925] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.094945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.094966] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.094986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.095006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.095049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.095077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.095084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.095112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.095136] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.095160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.095183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.095210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.095232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.095256] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.095278] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.095301] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.095330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.095358] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.095418] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.095441] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.095465] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.095506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.095530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.095552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.095575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.095596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.095620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.095646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.095671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.095696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.095716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.095738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.095763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.095787] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.097790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.097807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.097822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.097837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.100421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.100440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.100456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.101983] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.101999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.103830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.106764] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.106839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.106856] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.106878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.123581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.123607] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.123642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.123742] [drm:drm_mode_addfb2] [FB:79]
>[ 1376.123809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.140270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.140294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.140340] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.159196] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.159215] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.159235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.159252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.159270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.159285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.159300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.159316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.159334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.159351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.159367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.159383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.159398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.159412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.159439] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.159461] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.159486] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.159502] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.159619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.159629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.159676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.159696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.159716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.159740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.159760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.159781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.159801] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.159821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.159842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.159862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.159882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.159886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.159905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.159909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.159930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.159950] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.159970] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.159990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.160011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.160072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.160099] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.160125] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.160148] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.160176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.160205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.160265] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.160290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.160314] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.160355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.160378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.160402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.160425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.160449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.160472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.160498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.160523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.160548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.160569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.160592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.160619] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.160641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.162646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.162662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.162676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.162691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.165333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.165353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.165372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.166868] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.166885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.168691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.171632] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.171699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.171715] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.171736] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.188442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.188468] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.188503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.188602] [drm:drm_mode_addfb2] [FB:75]
>[ 1376.188661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.205144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.205168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.205214] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.224066] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.224085] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.224105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.224122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.224140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.224155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.224170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.224186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.224207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.224228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.224249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.224269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.224288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.224307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.224335] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.224358] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.224382] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.224399] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.224505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.224516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.224563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.224582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.224602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.224623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.224640] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.224658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.224676] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.224693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.224710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.224725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.224741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.224744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.224763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.224767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.224788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.224808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.224828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.224848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.224869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.224889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.224909] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.224929] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.224949] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.224970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.224992] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.225070] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.225097] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.225122] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.225165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.225192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.225216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.225241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.225264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.225289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.225317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.225345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.225373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.225395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.225419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.225447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.225471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.227496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.227513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.227528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.227543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.229064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.229080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.229093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.230604] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.230622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.232432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.235377] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.235442] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.235459] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.235481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.252185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.252212] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.252249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.252351] [drm:drm_mode_addfb2] [FB:78]
>[ 1376.252411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.268864] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.268889] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.268934] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.287809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.287828] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.287849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.287866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.287884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.287899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.287914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.287933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.287955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.287976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.287997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.288018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.288081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.288110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.288156] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.288190] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.288229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.288253] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.288358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.288374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.288441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.288464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.288489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.288517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.288537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.288561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.288583] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.288605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.288626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.288648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.288667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.288673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.288692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.288697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.288719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.288738] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.288759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.288777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.288800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.288819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.288840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.288859] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.288879] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.288903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.288928] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.288980] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.289002] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.289024] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.289094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.289116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.289140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.289161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.289182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.289203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.289228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.289253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.289277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.289297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.289319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.289343] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.289366] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.291370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.291388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.291402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.291418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.292920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.292936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.292949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.294445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.294461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.296264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.299204] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.299273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.299290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.299312] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.316016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.316086] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.316141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.316242] [drm:drm_mode_addfb2] [FB:79]
>[ 1376.316305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.332718] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.332742] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.332787] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.351634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.351653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.351673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.351690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.351708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.351723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.351737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.351753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.351771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.351787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.351807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.351828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.351847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.351866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.351894] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.351917] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.351942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.351958] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.352086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.352104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.352180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.352205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.352233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.352262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.352285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.352311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.352335] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.352360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.352382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.352405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.352426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.352432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.352454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.352459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.352483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.352504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.352526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.352546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.352571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.352592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.352615] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.352635] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.352657] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.352687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.352711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.352776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.352799] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.352820] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.352857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.352877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.352899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.352918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.352939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.352959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.352983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.353006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.353029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.353071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.353094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.353117] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.353140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.355135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.355153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.355167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.355182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.356686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.356701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.356715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.359290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.359310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.361117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.364063] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.364126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.364143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.364166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.380869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.380894] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.380929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.381061] [drm:drm_mode_addfb2] [FB:75]
>[ 1376.381163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.397549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.397575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.397621] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.416479] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.416498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.416518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.416536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.416553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.416569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.416584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.416599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.416617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.416638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.416658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.416679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.416698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.416717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.416745] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.416768] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.416793] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.416809] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.416924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.416934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.416981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.417001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.417021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.417041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.417101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.417127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.417155] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.417178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.417204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.417226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.417250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.417256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.417279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.417286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.417310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.417332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.417355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.417377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.417403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.417425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.417448] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.417470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.417493] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.417520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.417547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.417621] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.417646] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.417670] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.417712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.417739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.417764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.417787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.417811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.417835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.417862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.417887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.417913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.417933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.417956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.417983] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.418006] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.420022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.420040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.420089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.420116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.421624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.421639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.421653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.423151] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.423167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.424988] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.427919] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.427946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.427962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.427984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.444689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.444715] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.444752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.444855] [drm:drm_mode_addfb2] [FB:78]
>[ 1376.444923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.461390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.461415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.461460] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.480327] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.480347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.480367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.480384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.480403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.480418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.480433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.480449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.480467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.480484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.480500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.480515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.480530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.480544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.480571] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.480593] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.480617] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.480633] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.480748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.480758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.480805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.480824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.480845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.480869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.480889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.480910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.480930] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.480951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.480971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.480991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.481011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.481015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.481035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.481082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.481112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.481140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.481167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.481192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.481220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.481245] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.481270] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.481294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.481319] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.481346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.481375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.481434] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.481459] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.481482] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.481524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.481549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.481573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.481597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.481620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.481645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.481672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.481698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.481724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.481747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.481770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.481797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.481822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.483828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.483846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.483863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.483882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.485390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.485408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.485425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.486920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.486937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.488742] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.491681] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.491750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.491766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.491787] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.508494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.508520] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.508555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.508655] [drm:drm_mode_addfb2] [FB:79]
>[ 1376.508722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.525195] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.525220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.525267] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.544115] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.544134] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.544154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.544171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.544192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.544212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.544231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.544251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.544272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.544293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.544314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.544335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.544354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.544373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.544400] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.544423] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.544448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.544464] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.544571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.544581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.544628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.544647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.544667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.544687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.544704] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.544722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.544740] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.544758] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.544774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.544790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.544805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.544809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.544824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.544827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.544843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.544858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.544875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.544895] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.544916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.544936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.544956] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.544976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.544996] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.545018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.545039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.545137] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.545163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.545188] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.545231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.545258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.545284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.545310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.545335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.545362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.545390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.545417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.545444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.545468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.545491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.545520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.545545] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.547571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.547590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.547607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.547626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.550267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.550285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.550303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.551797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.551815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.554701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.557635] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.557712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.557729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.557751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.574443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.574469] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.574503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.574596] [drm:drm_mode_addfb2] [FB:75]
>[ 1376.574656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.591164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.591188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.591234] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.610096] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.610115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.610135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.610152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.610170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.610185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.610200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.610216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.610234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.610251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.610267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.610287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.610306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.610325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.610353] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.610376] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.610401] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.610417] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.610526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.610536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.610583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.610602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.610622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.610643] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.610659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.610677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.610696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.610712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.610729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.610745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.610760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.610764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.610779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.610783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.610799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.610814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.610834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.610854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.610875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.610895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.610915] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.610935] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.610955] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.610977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.610998] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.611038] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.611101] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.611128] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.611173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.611201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.611228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.611253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.611279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.611305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.611333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.611360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.611386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.611410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.611435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.611463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.611489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.613510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.613527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.613542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.613557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.615078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.615093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.615107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.616602] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.616620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.618429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.621369] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.621437] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.621454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.621476] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.638180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.638206] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.638240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.638341] [drm:drm_mode_addfb2] [FB:78]
>[ 1376.638406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.654882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.654906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.654952] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.673789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.673808] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.673828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.673848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.673870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.673889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.673909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.673928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.673950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.673971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.673991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.674012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.674031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.674050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.674124] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.674159] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.674195] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.674220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.674335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.674352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.674428] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.674456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.674484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.674514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.674538] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.674565] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.674591] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.674617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.674642] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.674666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.674691] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.674697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.674720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.674726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.674750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.674773] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.674796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.674817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.674843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.674866] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.674889] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.674910] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.674933] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.674959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.674987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.675048] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.675106] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.675129] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.675170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.675192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.675215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.675238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.675261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.675285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.675311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.675335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.675360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.675382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.675404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.675430] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.675453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.677449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.677467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.677484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.677503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.679011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.679027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.679041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.680582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.680599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.682424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.685370] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.685433] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.685449] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.685470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.702175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.702202] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.702239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.702339] [drm:drm_mode_addfb2] [FB:79]
>[ 1376.702405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.718857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.718881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.718926] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.737780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.737799] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.737819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.737837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.737854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.737869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.737884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.737900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.737917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.737934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.737950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.737965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.737979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.737993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.738020] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.738042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.738105] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.738133] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.738247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.738261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.738331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.738355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.738382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.738410] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.738433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.738458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.738482] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.738506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.738535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.738556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.738575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.738580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.738600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.738605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.738627] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.738646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.738667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.738685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.738708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.738727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.738748] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.738767] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.738787] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.738809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.738832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.738894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.738916] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.738937] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.738974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.738994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.739015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.739034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.739055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.739093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.739119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.739143] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.739167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.739187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.739208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.739233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.739255] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.741242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.741258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.741272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.741286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.742790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.742805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.742819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.744315] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.744331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.746139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.749080] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.749149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.749168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.749194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.765882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.765906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.765940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.766038] [drm:drm_mode_addfb2] [FB:75]
>[ 1376.766155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.782599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.782623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.782668] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.801542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.801562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.801582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.801599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.801617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.801632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.801651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.801670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.801693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.801713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.801734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.801754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.801773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.801792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.801820] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.801843] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.801868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.801884] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.801990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.802001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.802053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.802110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.802139] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.802169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.802194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.802221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.802247] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.802273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.802298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.802322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.802345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.802352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.802374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.802380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.802402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.802426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.802450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.802472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.802499] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.802521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.802544] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.802566] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.802589] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.802615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.802642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.802700] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.802724] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.802748] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.802787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.802811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.802835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.802858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.802879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.802903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.802929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.802955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.802987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.803009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.803031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.803054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.803095] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.805091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.805107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.805121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.805135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.806650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.806667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.806682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.808201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.808220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.810028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.812959] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.812986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.813002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.813025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.829728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.829754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.829789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.829888] [drm:drm_mode_addfb2] [FB:78]
>[ 1376.829953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.846409] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.846433] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.846478] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.865338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.865359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.865381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.865401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.865422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.865442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.865461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.865481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.865502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.865523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.865543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.865564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.865583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.865602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.865630] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.865652] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.865677] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.865694] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.865809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.865819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.865866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.865886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.865906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.865927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.865944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.865961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.865979] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.865997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.866013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.866029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.866045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.866049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.866064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.866116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.866140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.866162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.866184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.866205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.866230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.866251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.866273] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.866294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.866316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.866341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.866367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.866424] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.866448] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.866473] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.866504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.866520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.866535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.866550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.866564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.866580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.866596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.866612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.866628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.866642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.866657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.866674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.866694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.868691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.868708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.868726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.868744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.870255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.870271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.870285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.871778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.871794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.873601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.876533] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.876610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.876630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.876656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.893351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.893377] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.893412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.893511] [drm:drm_mode_addfb2] [FB:79]
>[ 1376.893569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.910042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.910064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.910152] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.928831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.928850] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.928870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.928887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.928905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.928920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.928934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.928950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.928968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.928984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.929000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.929020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.929039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.929058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.929132] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.929167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.929201] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.929227] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.929328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.929342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.929411] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.929437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.929465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.929495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.929519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.929546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.929572] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.929597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.929621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.929645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.929668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.929675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.929697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.929703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.929727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.929750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.929775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.929798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.929824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.929848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.929871] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.929900] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.929921] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.929944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.929969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.930033] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.930056] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.930096] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.930136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.930160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.930183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.930206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.930229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.930252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.930278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.930303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.930327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.930349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.930371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.930397] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.930421] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.932410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.932426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.932440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.932454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.933956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.933972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.933985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.935483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.935501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1376.937305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1376.940239] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1376.940314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1376.940331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1376.940353] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1376.957057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.957098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.957133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.957232] [drm:drm_mode_addfb2] [FB:75]
>[ 1376.957296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.973737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1376.973761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1376.973797] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1376.992644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1376.992663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1376.992683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.992703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.992725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.992744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.992764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.992783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1376.992805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.992826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.992846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.992866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.992885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.992904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.992932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1376.992955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1376.992979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1376.992996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1376.993114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1376.993132] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1376.993207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1376.993232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1376.993260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1376.993289] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1376.993312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1376.993338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1376.993370] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1376.993392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1376.993413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1376.993434] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1376.993453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1376.993458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.993478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1376.993483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1376.993504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1376.993524] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1376.993544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1376.993563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1376.993585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1376.993604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1376.993625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1376.993643] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1376.993664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1376.993686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1376.993710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1376.993763] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1376.993785] [drm:intel_power_well_enable [i915]] enabling display
>[ 1376.993806] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1376.993843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1376.993865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1376.993885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1376.993905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1376.993925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1376.993946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1376.993970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1376.993994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1376.994016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1376.994035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1376.994056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1376.994078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1376.994122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1376.996131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1376.996148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1376.996163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.996178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1376.997684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1376.997699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1376.997713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1376.999209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1376.999225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.001031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.003961] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.003988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.004005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.004027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.020732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.020757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.020791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.020889] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.020953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.037412] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.037436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.037472] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.056319] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.056338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.056358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.056375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.056393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.056408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.056422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.056439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.056456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.056473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.056489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.056505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.056520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.056534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.056560] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.056582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.056603] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.056619] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.056733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.056743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.056790] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.056809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.056829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.056850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.056867] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.056885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.056903] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.056920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.056937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.056953] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.056968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.056972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.056987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.056991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.057007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.057022] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.057037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.057052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.057069] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.057131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.057154] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.057178] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.057202] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.057229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.057258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.057331] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.057356] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.057380] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.057421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.057447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.057471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.057494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.057518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.057543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.057569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.057595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.057620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.057644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.057667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.057694] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.057719] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.059733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.059751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.059766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.059781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.061289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.061305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.061319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.062811] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.062827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.064632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.067563] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.067641] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.067658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.067679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.084383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.084410] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.084447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.084548] [drm:drm_mode_addfb2] [FB:79]
>[ 1377.084616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.101083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.101124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.101160] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.120003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.120022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.120043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.120060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.120077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.120136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.120160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.120187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.120217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.120244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.120270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.120295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.120316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.120338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.120382] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.120416] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.120447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.120472] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.120585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.120601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.120643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.120660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.120677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.120695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.120709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.120725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.120740] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.120755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.120769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.120782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.120795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.120798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.120811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.120814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.120831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.120849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.120866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.120883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.120901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.120918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.120936] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.120953] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.120971] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.120989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.121008] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.121045] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.121059] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.121073] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.121147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.121172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.121197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.121220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.121243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.121267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.121293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.121318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.121342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.121364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.121386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.121413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.121437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.123447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.123464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.123479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.123494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.125032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.125050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.125068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.126659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.126677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.128486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.131431] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.131495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.131512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.131534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.148238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.148264] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.148299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.148399] [drm:drm_mode_addfb2] [FB:75]
>[ 1377.148465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.164939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.164964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.165000] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.183765] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.183784] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.183805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.183822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.183839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.183854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.183869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.183885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.183903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.183920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.183936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.183952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.183966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.183980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.184007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.184030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.184055] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.184072] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.184221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.184236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.184305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.184329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.184357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.184386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.184409] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.184435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.184459] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.184483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.184506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.184529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.184550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.184556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.184578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.184583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.184606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.184627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.184650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.184670] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.184695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.184716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.184739] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.184759] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.184781] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.184805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.184831] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.184900] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.184924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.184947] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.184987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.185009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.185032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.185054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.185076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.185123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.185148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.185172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.185197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.185217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.185238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.185264] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.185286] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.187272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.187288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.187302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.187317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.188819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.188834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.188848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.190342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.190358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.192160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.195083] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.195170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.195189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.195215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.211911] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.211938] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.211975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.212110] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.212200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.228592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.228616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.228652] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.247504] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.247523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.247543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.247561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.247579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.247594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.247609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.247625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.247643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.247659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.247675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.247691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.247709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.247728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.247756] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.247779] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.247804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.247821] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.247928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.247939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.247986] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.248005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.248025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.248046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.248063] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.248081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.248147] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.248175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.248202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.248227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.248251] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.248258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.248281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.248288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.248312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.248336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.248361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.248384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.248411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.248435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.248459] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.248482] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.248506] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.248534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.248562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.248621] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.248646] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.248671] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.248712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.248737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.248761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.248785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.248809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.248834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.248861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.248887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.248914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.248937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.248959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.248987] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.249012] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.251016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.251034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.251049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.251065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.252599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.252615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.252629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.254147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.254164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.255966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.258898] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.258976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.258992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.259014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.275717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.275743] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.275777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.275875] [drm:drm_mode_addfb2] [FB:79]
>[ 1377.275932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.292428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.292453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.292489] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.311343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.311362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.311383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.311400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.311417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.311433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.311448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.311464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.311482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.311499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.311515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.311531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.311545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.311564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.311592] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.311615] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.311639] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.311656] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.311770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.311780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.311827] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.311848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.311869] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.311893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.311913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.311934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.311954] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.311974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.311995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.312015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.312035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.312039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.312059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.312062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.312083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.312149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.312178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.312203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.312231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.312257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.312283] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.312308] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.312332] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.312361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.312389] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.312450] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.312475] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.312500] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.312541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.312567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.312592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.312617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.312641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.312665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.312692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.312718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.312743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.312766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.312788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.312814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.312840] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.314843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.314860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.314875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.314890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.317474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.317493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.317510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.319007] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.319024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.320829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.323762] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.323839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.323856] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.323877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.340581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.340607] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.340642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.340743] [drm:drm_mode_addfb2] [FB:75]
>[ 1377.340807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.357282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.357307] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.357345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.376200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.376218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.376239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.376256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.376273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.376289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.376308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.376328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.376349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.376370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.376391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.376411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.376430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.376449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.376477] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.376500] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.376525] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.376542] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.376656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.376666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.376713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.376732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.376752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.376776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.376796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.376817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.376838] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.376858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.376879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.376899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.376919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.376923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.376943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.376947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.376967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.376988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.377008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.377028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.377048] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.377068] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.377088] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.377154] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.377183] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.377212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.377241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.377301] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.377326] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.377351] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.377393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.377419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.377444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.377468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.377493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.377519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.377554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.377578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.377601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.377623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.377644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.377669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.377693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.379702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.379720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.379734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.379749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.381256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.381272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.381285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.382780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.382796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.384601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.387552] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.387610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.387627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.387649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.404351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.404378] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.404415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.404510] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.404579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.421052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.421077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.421157] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.440000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.440019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.440040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.440057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.440074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.440089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.440148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.440173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.440203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.440230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.440256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.440283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.440304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.440327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.440370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.440405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.440436] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.440462] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.440571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.440581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.440627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.440645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.440664] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.440684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.440700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.440717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.440734] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.440750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.440766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.440780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.440795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.440798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.440813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.440816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.440831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.440849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.440868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.440887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.440911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.440926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.440940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.440953] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.440966] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.440981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.440997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.441033] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.441046] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.441059] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.441083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.441097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.441155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.441179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.441201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.441225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.441251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.441276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.441301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.441323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.441345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.441371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.441395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.443405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.443424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.443441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.443459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.444966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.444982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.444997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.446494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.446510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.448314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.451259] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.451324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.451344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.451370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.468065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.468091] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.468177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.468292] [drm:drm_mode_addfb2] [FB:79]
>[ 1377.468357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.484746] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.484770] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.484807] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.503660] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.503679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.503700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.503717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.503735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.503750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.503765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.503781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.503799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.503816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.503832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.503847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.503862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.503876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.503903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.503924] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.503945] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.503961] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.504058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.504069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.504163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.504191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.504222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.504252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.504278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.504305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.504333] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.504365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.504388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.504411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.504433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.504440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.504460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.504466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.504488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.504509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.504532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.504554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.504578] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.504599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.504621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.504642] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.504662] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.504687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.504712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.504767] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.504790] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.504812] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.504850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.504872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.504893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.504915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.504936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.504959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.504984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.505008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.505032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.505053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.505075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.505100] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.505146] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.507142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.507158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.507172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.507186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.508695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.508710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.508724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.510241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.510260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.512069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.515000] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.515028] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.515048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.515074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.531770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.531796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.531832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.531931] [drm:drm_mode_addfb2] [FB:75]
>[ 1377.531998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.548471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.548496] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.548532] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.567388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.567407] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.567427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.567445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.567462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.567478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.567493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.567509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.567527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.567543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.567559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.567579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.567598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.567617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.567645] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.567668] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.567692] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.567709] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.567816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.567826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.567878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.567896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.567914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.567934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.567950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.567966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.567983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.568002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.568022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.568041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.568060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.568064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.568083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.568086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.568106] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.568166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.568193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.568218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.568244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.568268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.568293] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.568316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.568339] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.568366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.568392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.568448] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.568472] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.568495] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.568533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.568558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.568582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.568604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.568626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.568650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.568674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.568698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.568723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.568744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.568764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.568789] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.568813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.570819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.570835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.570849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.570863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.572373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.572391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.572409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.573905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.573921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.575735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.578673] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.578744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.578761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.578783] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.595514] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.595541] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.595579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.595685] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.595746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.612185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.612210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.612248] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.631106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.631143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.631163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.631180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.631198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.631214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.631229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.631245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.631262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.631279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.631295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.631311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.631325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.631339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.631367] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.631390] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.631414] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.631431] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.631540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.631551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.631598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.631619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.631640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.631663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.631683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.631704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.631725] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.631745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.631765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.631785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.631805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.631809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.631829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.631832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.631853] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.631873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.631893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.631913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.631934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.631954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.631974] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.631994] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.632014] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.632035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.632057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.632099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.632163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.632190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.632235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.632263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.632290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.632316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.632341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.632368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.632397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.632423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.632450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.632474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.632499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.632528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.632553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.634576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.634593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.634607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.634621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.636148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.636164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.636178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.637683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.637699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.639526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.642471] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.642534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.642550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.642570] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.659278] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.659304] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.659338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.659439] [drm:drm_mode_addfb2] [FB:79]
>[ 1377.659504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.675958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.675984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.676030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.694849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.694868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.694888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.694905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.694922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.694937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.694952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.694968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.694986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.695003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.695019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.695034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.695053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.695072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.695100] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.695169] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.695204] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.695229] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.695342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.695356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.695412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.695430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.695449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.695469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.695485] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.695502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.695519] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.695536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.695555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.695575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.695594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.695598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.695617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.695622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.695642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.695661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.695681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.695701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.695720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.695739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.695765] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.695781] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.695796] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.695813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.695830] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.695872] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.695885] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.695899] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.695927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.695946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.695963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.695981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.696000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.696018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.696037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.696056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.696075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.696093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.696111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.696158] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.696181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.698171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.698187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.698201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.698216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.699722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.699738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.699751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.701249] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.701265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.703070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.705992] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.706027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.706046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.706072] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.722770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.722796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.722831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.722929] [drm:drm_mode_addfb2] [FB:75]
>[ 1377.722994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.739471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.739496] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.739541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.758402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.758421] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.758442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.758459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.758477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.758492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.758508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.758524] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.758542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.758558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.758574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.758590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.758604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.758618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.758645] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.758667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.758688] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.758703] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.758816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.758827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.758874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.758893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.758913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.758934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.758950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.758968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.758988] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.759009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.759030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.759050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.759070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.759074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.759094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.759098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.759118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.759186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.759212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.759238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.759263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.759288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.759311] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.759336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.759358] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.759385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.759413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.759473] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.759497] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.759521] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.759564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.759590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.759614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.759638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.759662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.759686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.759714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.759740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.759766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.759789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.759811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.759838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.759860] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.761863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.761880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.761894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.761908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.763419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.763434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.763447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.764953] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.764971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.766778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.769698] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.769737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.769756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.769782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.786479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.786504] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.786539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.786639] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.786705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.803181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.803206] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.803251] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.822109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.822146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.822166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.822183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.822200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.822220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.822239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.822259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.822281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.822301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.822321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.822342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.822361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.822380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.822408] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.822431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.822456] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.822472] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.822588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.822598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.822651] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.822669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.822687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.822709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.822727] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.822746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.822765] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.822784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.822802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.822821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.822839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.822843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.822861] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.822864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.822883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.822902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.822920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.822939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.822957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.822976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.822994] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.823012] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.823031] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.823050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.823071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.823109] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.823161] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.823183] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.823222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.823245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.823269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.823289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.823311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.823333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.823358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.823383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.823408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.823428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.823449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.823475] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.823497] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.825499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.825517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.825531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.825546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.827073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.827088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.827102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.828627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.828643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.830478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.833422] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.833487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.833504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.833526] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.850230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.850256] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.850291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.850391] [drm:drm_mode_addfb2] [FB:79]
>[ 1377.850457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.866909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.866936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.866982] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.885844] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.885863] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.885883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.885900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.885918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.885933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.885948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.885964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.885982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.885998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.886014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.886030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.886045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.886059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.886085] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.886107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.886128] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.886202] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.886329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.886343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.886412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.886438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.886466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.886495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.886520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.886547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.886573] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.886598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.886623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.886647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.886670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.886676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.886699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.886705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.886729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.886752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.886773] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.886796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.886823] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.886846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.886869] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.886892] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.886915] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.886939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.886966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.887040] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.887062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.887085] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.887122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.887167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.887189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.887212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.887234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.887258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.887284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.887308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.887333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.887355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.887378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.887404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.887427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.889416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.889433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.889450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.889468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.890972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.890988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.891003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.892498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.892515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.894319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.897258] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.897329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.897346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.897371] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.914071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.914097] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.914132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.914314] [drm:drm_mode_addfb2] [FB:75]
>[ 1377.914378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.930764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.930787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.930832] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1377.949691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1377.949710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1377.949730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.949748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.949766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.949781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.949796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.949812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.949830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.949847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.949863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.949879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.949893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.949907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.949934] [drm:intel_power_well_disable [i915]] disabling display
>[ 1377.949956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1377.949977] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.949992] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1377.950081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1377.950092] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1377.950184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1377.950211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1377.950241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1377.950271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1377.950294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1377.950322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1377.950347] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1377.950372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1377.950396] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1377.950427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1377.950447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1377.950454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.950475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1377.950480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1377.950503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1377.950523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1377.950544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1377.950564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1377.950587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1377.950606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1377.950629] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1377.950649] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1377.950670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1377.950693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.950718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1377.950773] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1377.950795] [drm:intel_power_well_enable [i915]] enabling display
>[ 1377.950817] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1377.950853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1377.950874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1377.950896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1377.950915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1377.950936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1377.950956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1377.950979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1377.951002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1377.951025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.951044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1377.951065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1377.951088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1377.951110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1377.953117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1377.953142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1377.953157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.953172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1377.954685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1377.954703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1377.954721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1377.956231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1377.956249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1377.958084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1377.961025] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1377.961093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1377.961110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1377.961176] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1377.977836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1377.977862] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1377.977897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1377.978006] [drm:drm_mode_addfb2] [FB:78]
>[ 1377.978079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1377.994515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1377.994541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1377.994587] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.013435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.013454] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.013475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.013491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.013509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.013528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.013548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.013567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.013589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.013610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.013630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.013651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.013670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.013689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.013717] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.013740] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.013765] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.013781] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.013895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.013905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.013951] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.013971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.013992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.014015] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.014034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.014054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.014074] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.014094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.014114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.014133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.014193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.014201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.014224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.014230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.014253] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.014275] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.014297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.014318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.014342] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.014363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.014384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.014405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.014426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.014450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.014475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.014547] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.014570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.014593] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.014635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.014660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.014684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.014707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.014730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.014754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.014780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.014797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.014813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.014827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.014841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.014858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.014881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.016869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.016887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.016901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.016916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.018425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.018440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.018454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.019946] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.019962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.021768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.024700] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.024777] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.024793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.024815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.041519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.041546] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.041584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.041685] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.041751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.058220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.058244] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.058289] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.077135] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.077171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.077191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.077208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.077226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.077241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.077256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.077273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.077290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.077307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.077323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.077339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.077353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.077367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.077394] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.077415] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.077436] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.077452] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.077564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.077574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.077621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.077642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.077663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.077686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.077706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.077727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.077748] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.077768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.077788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.077808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.077828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.077832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.077852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.077856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.077877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.077897] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.077917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.077938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.077958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.077978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.077998] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.078018] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.078039] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.078060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.078081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.078132] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.078189] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.078212] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.078255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.078280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.078304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.078326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.078349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.078372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.078398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.078423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.078448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.078470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.078492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.078518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.078541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.080555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.080573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.080587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.080602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.082111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.082127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.082177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.083677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.083693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.085525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.088465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.088533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.088548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.088569] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.105277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.105303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.105340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.105444] [drm:drm_mode_addfb2] [FB:75]
>[ 1378.105512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.121957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.121982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.122027] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.140874] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.140893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.140913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.140930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.140948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.140963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.140978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.140994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.141012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.141028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.141044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.141059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.141074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.141092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.141120] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.141189] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.141224] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.141251] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.141364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.141379] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.141447] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.141473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.141500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.141530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.141554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.141580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.141606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.141630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.141654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.141678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.141701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.141715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.141736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.141741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.141763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.141784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.141803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.141824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.141848] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.141869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.141891] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.141912] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.141933] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.141955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.141979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.142043] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.142065] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.142088] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.142126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.142148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.142188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.142211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.142233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.142256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.142282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.142307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.142331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.142353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.142376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.142402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.142425] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.144417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.144433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.144447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.144461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.145963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.145979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.145996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.147492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.147508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.149312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.152249] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.152321] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.152338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.152360] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.169062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.169088] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.169123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.169303] [drm:drm_mode_addfb2] [FB:78]
>[ 1378.169374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.185757] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.185781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.185826] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.203745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.203764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.203786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.203806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.203828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.203848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.203867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.203886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.203908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.203929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.203949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.203969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.203988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.204007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.204034] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.204057] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.204082] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.204099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.204218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.204235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.204313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.204340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.204370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.204400] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.204421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.204439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.204456] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.204472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.204488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.204503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.204518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.204522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.204536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.204540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.204554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.204568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.204582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.204596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.204612] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.204627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.204641] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.204655] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.204669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.204685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.204703] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.204754] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.204769] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.204783] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.204810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.204830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.204849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.204869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.204889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.204908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.204930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.204952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.204973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.204992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.205012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.205033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.205053] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.207042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.207060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.207075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.207089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.208597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.208613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.208626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.210121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.210137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.211969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.214901] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.214978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.214997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.215023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.231720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.231747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.231785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.231898] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.231965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.248421] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.248446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.248491] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.267351] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.267370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.267390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.267407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.267425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.267440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.267455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.267471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.267489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.267506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.267522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.267538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.267552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.267566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.267593] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.267614] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.267635] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.267651] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.267758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.267768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.267815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.267837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.267858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.267881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.267901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.267922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.267943] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.267963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.267984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.268004] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.268023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.268027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.268047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.268051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.268072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.268092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.268112] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.268132] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.268153] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.268211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.268239] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.268266] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.268291] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.268319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.268348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.268407] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.268432] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.268457] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.268499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.268524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.268550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.268574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.268598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.268630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.268656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.268680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.268704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.268726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.268748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.268774] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.268798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.270801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.270818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.270832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.270847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.272355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.272371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.272384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.273875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.273891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.275696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.278631] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.278705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.278722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.278744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.295448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.295474] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.295509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.295609] [drm:drm_mode_addfb2] [FB:75]
>[ 1378.295666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.312138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.312176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.312221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.331082] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.331100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.331121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.331138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.331196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.331223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.331248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.331272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.331301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.331328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.331353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.331379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.331399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.331421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.331464] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.331498] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.331529] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.331555] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.331657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.331668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.331714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.331732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.331751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.331771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.331786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.331803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.331821] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.331837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.331852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.331867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.331881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.331885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.331899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.331902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.331916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.331930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.331944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.331958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.331974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.331988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.332010] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.332022] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.332034] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.332049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.332065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.332100] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.332113] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.332126] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.332150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.332205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.332229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.332252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.332275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.332298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.332324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.332349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.332373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.332395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.332417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.332443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.332467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.334465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.334483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.334500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.334519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.336027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.336043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.336057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.337557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.337573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.339394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.342340] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.342404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.342420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.342443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.359146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.359189] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.359224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.359323] [drm:drm_mode_addfb2] [FB:78]
>[ 1378.359387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.375815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.375836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.375878] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.394735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.394754] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.394775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.394796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.394817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.394837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.394856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.394875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.394897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.394918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.394938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.394957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.394976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.394995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.395023] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.395046] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.395071] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.395088] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.395220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.395237] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.395313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.395341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.395369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.395399] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.395424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.395451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.395478] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.395503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.395535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.395557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.395578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.395584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.395605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.395610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.395631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.395653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.395674] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.395695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.395719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.395741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.395762] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.395781] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.395802] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.395826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.395851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.395920] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.395943] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.395965] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.396003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.396026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.396049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.396071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.396093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.396114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.396139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.396162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.396206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.396228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.396251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.396277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.396300] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.398296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.398313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.398327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.398342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.399844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.399860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.399873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.401368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.401384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.403188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.406117] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.406145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.406201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.406240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.422887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.422913] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.422948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.423049] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.423114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.439568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.439593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.439630] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.458482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.458501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.458521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.458538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.458556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.458575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.458595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.458614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.458636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.458657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.458677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.458698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.458717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.458736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.458764] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.458787] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.458811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.458828] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.458951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.458960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.459004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.459023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.459041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.459061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.459076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.459093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.459110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.459126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.459142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.459157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.459210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.459217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.459241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.459247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.459270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.459293] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.459317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.459340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.459366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.459389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.459412] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.459435] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.459458] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.459484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.459510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.459828] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.459851] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.459875] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.459914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.459946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.459969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.459991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.460013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.460034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.460059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.460083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.460107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.460128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.460149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.460194] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.460217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.462338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.462354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.462368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.462383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.463888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.463906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.463923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.465424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.465441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.467251] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.470196] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.470262] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.470281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.470307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.487010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.487036] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.487074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.487299] [drm:drm_mode_addfb2] [FB:75]
>[ 1378.487366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.503696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.503720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.503758] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.522632] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.522651] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.522671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.522688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.522709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.522729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.522749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.522768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.522790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.522811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.522831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.522851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.522870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.522889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.522917] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.522940] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.522965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.522981] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.523097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.523107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.523155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.523220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.523251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.523281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.523305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.523339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.523362] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.523387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.523409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.523432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.523453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.523460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.523481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.523487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.523510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.523531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.523553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.523573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.523597] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.523617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.523638] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.523659] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.523681] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.523706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.523732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.523790] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.523813] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.523835] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.523874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.523897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.523918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.523939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.523960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.523982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.524007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.524031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.524055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.524076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.524097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.524122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.524143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.526162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.526191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.526205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.526220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.527726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.527744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.527761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.529261] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.529279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.531114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.534046] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.534124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.534141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.534163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.550866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.550893] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.550930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.551033] [drm:drm_mode_addfb2] [FB:78]
>[ 1378.551102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.567547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.567571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.567608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.586459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.586478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.586498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.586515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.586533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.586548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.586562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.586578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.586596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.586613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.586629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.586645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.586659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.586673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.586700] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.586721] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.586742] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.586758] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.586865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.586875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.586922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.586941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.586961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.586981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.586998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.587016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.587035] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.587052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.587068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.587084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.587102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.587106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.587126] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.587130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.587151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.587171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.587228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.587253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.587277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.587300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.587323] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.587344] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.587366] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.587392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.587417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.587479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.587503] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.587525] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.587567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.587593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.587616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.587640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.587663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.587688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.587715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.587741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.587773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.587794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.587815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.587833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.587848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.589829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.589845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.589860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.589874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.591384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.591402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.591419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.592926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.592944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.594752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.597659] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.597712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.597729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.597750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.614461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.614488] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.614525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.614622] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.614684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.631151] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.631175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.631265] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.649936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.649955] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.649975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.649992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.650010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.650025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.650040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.650056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.650073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.650090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.650105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.650121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.650135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.650148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.650220] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.650257] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.650290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.650307] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.650380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.650390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.650433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.650449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.650469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.650488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.650503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.650521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.650537] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.650553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.650569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.650584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.650598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.650602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.650616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.650620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.650635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.650650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.650664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.650678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.650695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.650710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.650724] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.650738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.650757] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.650778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.650800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.650838] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.650854] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.650870] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.650900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.650920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.650940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.650960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.650980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.650999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.651021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.651041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.651063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.651082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.651102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.651122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.651142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.653154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.653171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.653218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.653243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.654771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.654790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.654807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.656316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.656333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.658154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.661115] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.661163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.661220] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.661258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.677896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.677921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.677955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.678054] [drm:drm_mode_addfb2] [FB:75]
>[ 1378.678115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.694607] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.694632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.694669] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.713522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.713541] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.713562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.713579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.713596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.713611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.713626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.713642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.713660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.713676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.713692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.713707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.713721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.713735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.713762] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.713783] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.713804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.713819] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.713933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.713943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.713990] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.714010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.714031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.714054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.714074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.714095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.714115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.714136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.714157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.714177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.714234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.714242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.714266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.714272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.714295] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.714318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.714340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.714361] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.714386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.714408] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.714430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.714452] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.714473] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.714499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.714525] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.714586] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.714609] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.714633] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.714676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.714701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.714725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.714749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.714780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.714803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.714828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.714852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.714876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.714895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.714909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.714925] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.714940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.716929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.716947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.716961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.716977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.718486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.718501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.718515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.720008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.720025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.721833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.724752] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.724791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.724810] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.724836] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.741535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.741560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.741595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.741692] [drm:drm_mode_addfb2] [FB:78]
>[ 1378.741757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.758234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.758259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.758296] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.777131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.777150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.777170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.777235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.777264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.777289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.777313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.777338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.777367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.777394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.777420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.777446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.777469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.777492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.777535] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.777570] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.777602] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.777628] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.777761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.777771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.777819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.777838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.777858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.777879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.777895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.777913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.777931] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.777948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.777964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.777980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.777995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.777999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.778014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.778018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.778033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.778048] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.778068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.778088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.778109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.778129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.778149] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.778170] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.778244] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.778270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.778294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.778348] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.778369] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.778389] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.778428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.778452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.778473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.778496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.778518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.778541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.778566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.778590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.778614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.778635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.778657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.778683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.778706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.780734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.780751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.780765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.780780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.782305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.782322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.782337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.783833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.783850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.785655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.788599] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.788665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.788682] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.788704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.805406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.805432] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.805466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.805572] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.805639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.822108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.822133] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.822169] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.841056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.841075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.841095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.841112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.841129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.841145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.841160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.841175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.841247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.841275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.841301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.841328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.841349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.841373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.841417] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.841450] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.841482] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.841507] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.841627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.841644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.841706] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.841724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.841749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.841767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.841782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.841797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.841813] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.841828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.841842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.841856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.841869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.841872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.841885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.841888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.841902] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.841915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.841927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.841940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.841955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.841968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.841981] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.841993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.842005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.842020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.842037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.842073] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.842087] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.842099] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.842124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.842138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.842151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.842165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.842177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.842239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.842266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.842290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.842315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.842337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.842359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.842385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.842409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.844413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.844430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.844445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.844460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.845963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.845978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.845991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.847487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.847503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.849308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.852254] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.852317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.852334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.852357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.869059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.869085] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.869120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.869324] [drm:drm_mode_addfb2] [FB:75]
>[ 1378.869393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.885760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.885785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.885821] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.903862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.903881] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.903901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.903918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.903935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.903951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.903965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.903981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.903999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.904016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.904031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.904047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.904061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.904075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.904102] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.904124] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.904145] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.904161] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.904302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.904317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.904387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.904414] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.904439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.904459] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.904475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.904492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.904509] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.904525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.904541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.904556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.904570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.904574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.904588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.904592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.904612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.904632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.904652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.904671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.904691] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.904710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.904730] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.904749] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.904769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.904790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.904810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.904856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.904872] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.904888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.904917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.904937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.904958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.904977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.904997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.905016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.905038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.905058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.905079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.905105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.905121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.905138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.905154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.907142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.907158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.907173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.907187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.908789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.908806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.908824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.910326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.910343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.912148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.915078] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.915105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.915122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.915144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.931849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.931874] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.931909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.932008] [drm:drm_mode_addfb2] [FB:78]
>[ 1378.932066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.948529] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1378.948553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1378.948589] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1378.967443] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1378.967462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1378.967484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.967504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.967526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.967545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.967565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.967584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.967606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.967627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.967648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.967667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.967686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.967705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.967733] [drm:intel_power_well_disable [i915]] disabling display
>[ 1378.967755] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1378.967780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.967796] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1378.967903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1378.967913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1378.967960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1378.967979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1378.967999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1378.968020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1378.968037] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1378.968055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1378.968073] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1378.968090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1378.968106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1378.968122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1378.968137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1378.968141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.968156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1378.968160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1378.968178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1378.968233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1378.968255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1378.968278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1378.968302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1378.968324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1378.968346] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1378.968367] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1378.968388] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1378.968413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1378.968439] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1378.968514] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1378.968538] [drm:intel_power_well_enable [i915]] enabling display
>[ 1378.968563] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1378.968606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1378.968631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1378.968656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1378.968680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1378.968704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1378.968729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1378.968756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1378.968783] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1378.968809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.968833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1378.968856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1378.968876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1378.968893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1378.970891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1378.970908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1378.970922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.970937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1378.972446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1378.972462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1378.972476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1378.973970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1378.973985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1378.975791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1378.978724] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1378.978807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1378.978823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1378.978843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1378.995542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1378.995568] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1378.995603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1378.995703] [drm:drm_mode_addfb2] [FB:79]
>[ 1378.995767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.012244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.012270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.012309] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.031161] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.031182] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.031249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.031278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.031309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.031334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.031358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.031384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.031414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.031441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.031467] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.031492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.031516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.031539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.031583] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.031617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.031649] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.031675] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.031807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.031817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.031865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.031884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.031904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.031927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.031948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.031968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.031989] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.032009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.032030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.032050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.032075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.032079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.032095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.032098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.032114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.032129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.032143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.032156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.032173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.032187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.032241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.032262] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.032281] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.032303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.032327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.032382] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.032405] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.032427] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.032465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.032489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.032511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.032532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.032554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.032578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.032602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.032626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.032650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.032672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.032692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.032712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.032730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.034745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.034762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.034777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.034792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.036319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.036336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.036351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.037846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.037863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.039669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.042613] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.042678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.042695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.042717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.059420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.059446] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.059481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.059581] [drm:drm_mode_addfb2] [FB:75]
>[ 1379.059645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.076101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.076125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.076162] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.094991] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.095011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.095034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.095054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.095075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.095095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.095114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.095134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.095155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.095176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.095197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.095266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.095295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.095321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.095365] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.095401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.095437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.095464] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.095581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.095598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.095676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.095698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.095732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.095759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.095779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.095803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.095825] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.095848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.095869] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.095890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.095909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.095915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.095934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.095940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.095960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.095979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.095999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.096018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.096041] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.096060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.096081] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.096100] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.096121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.096142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.096166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.096244] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.096267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.096289] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.096327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.096349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.096371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.096391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.096413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.096434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.096459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.096483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.096506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.096525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.096547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.096572] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.096593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.098587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.098604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.098618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.098633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.100143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.100158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.100172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.101665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.101681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.103486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.106431] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.106495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.106512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.106534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.123238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.123264] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.123298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.123399] [drm:drm_mode_addfb2] [FB:78]
>[ 1379.123464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.139918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.139944] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.139982] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.158550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.158569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.158589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.158606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.158624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.158639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.158654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.158670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.158688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.158705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.158721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.158737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.158751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.158765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.158791] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.158813] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.158834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.158849] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.158963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.158973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.159020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.159039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.159066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.159086] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.159103] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.159121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.159138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.159155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.159171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.159187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.159202] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.159239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.159263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.159270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.159294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.159316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.159339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.159360] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.159386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.159407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.159430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.159451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.159474] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.159500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.159527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.159587] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.159610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.159633] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.159674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.159697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.159719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.159741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.159762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.159785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.159811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.159835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.159860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.159881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.159902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.159928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.159950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.161950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.161967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.161981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.161996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.163504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.163522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.163540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.165033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.165050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.166855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.169786] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.169813] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.169830] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.169853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.186555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.186581] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.186615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.186715] [drm:drm_mode_addfb2] [FB:79]
>[ 1379.186781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.203257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.203283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.203321] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.222175] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.222194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.222261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.222291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.222320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.222345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.222369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.222392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.222421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.222448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.222474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.222500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.222523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.222546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.222590] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.222625] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.222657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.222683] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.222819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.222830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.222877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.222896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.222916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.222937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.222954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.222972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.222990] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.223010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.223031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.223051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.223071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.223075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.223095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.223099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.223120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.223140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.223161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.223181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.223202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.223264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.223288] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.223312] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.223334] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.223360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.223394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.223451] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.223473] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.223494] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.223534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.223557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.223580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.223602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.223624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.223648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.223673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.223697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.223722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.223743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.223757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.223774] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.223789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.225783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.225800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.225814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.225829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.227340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.227356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.227370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.228864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.228880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.230684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.233636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.233693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.233710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.233731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.250435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.250461] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.250496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.250596] [drm:drm_mode_addfb2] [FB:75]
>[ 1379.250654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.267137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.267162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.267199] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.286094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.286113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.286133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.286152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.286174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.286194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.286213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.286277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.286312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.286340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.286367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.286394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.286417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.286441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.286485] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.286520] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.286552] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.286578] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.286683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.286698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.286744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.286762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.286781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.286801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.286816] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.286833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.286850] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.286866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.286881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.286896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.286910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.286921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.286934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.286937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.286951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.286964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.286981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.286999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.287018] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.287035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.287054] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.287072] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.287089] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.287108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.287128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.287164] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.287178] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.287193] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.287260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.287284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.287306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.287327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.287349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.287371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.287395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.287419] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.287442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.287463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.287483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.287508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.287532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.289539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.289556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.289571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.289586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.291089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.291105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.291118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.292613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.292629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.294431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.297004] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.297035] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.297051] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.297073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.313778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.313803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.313838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.313938] [drm:drm_mode_addfb2] [FB:78]
>[ 1379.313996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.330480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.330504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.330541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.348747] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.348766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.348786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.348803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.348821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.348835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.348850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.348866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.348884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.348901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.348917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.348933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.348947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.348961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.348987] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.349009] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.349029] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.349045] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.349139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.349150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.349203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.349262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.349291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.349322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.349347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.349375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.349400] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.349432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.349454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.349476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.349496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.349503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.349523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.349529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.349551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.349572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.349594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.349613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.349637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.349656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.349677] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.349697] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.349719] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.349742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.349766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.349823] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.349845] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.349866] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.349904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.349926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.349946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.349967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.349987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.350008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.350032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.350055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.350079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.350098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.350119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.350141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.350164] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.352171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.352188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.352203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.352248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.353755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.353769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.353783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.355299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.355317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.357121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.360054] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.360131] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.360148] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.360170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.376873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.376899] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.376933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.377032] [drm:drm_mode_addfb2] [FB:79]
>[ 1379.377096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.393575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.393599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.393636] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.412491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.412510] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.412532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.412552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.412574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.412593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.412613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.412632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.412652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.412673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.412693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.412714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.412733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.412751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.412779] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.412802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.412827] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.412843] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.412964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.412973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.413016] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.413034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.413053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.413072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.413087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.413104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.413120] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.413136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.413151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.413165] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.413179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.413183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.413196] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.413200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.413214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.413268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.413289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.413312] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.413334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.413356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.413376] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.413398] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.413417] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.413441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.413467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.413523] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.413546] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.413568] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.413605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.413628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.413649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.413670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.413689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.413711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.413735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.413759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.413782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.413801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.413821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.413843] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.413866] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.415863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.415881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.415899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.415917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.417430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.417447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.417462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.418959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.418975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.420786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.423727] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.423795] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.423811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.423833] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.440530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.440557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.440594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.440696] [drm:drm_mode_addfb2] [FB:75]
>[ 1379.440764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.457254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.457279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.457315] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.476156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.476177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.476198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.476218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.476286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.476317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.476343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.476371] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.476401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.476428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.476454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.476480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.476503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.476527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.476570] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.476604] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.476636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.476662] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.476765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.476775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.476821] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.476839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.476858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.476878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.476894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.476911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.476928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.476944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.476959] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.476974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.476988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.476992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.477006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.477009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.477023] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.477042] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.477061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.477081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.477100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.477119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.477138] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.477157] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.477176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.477196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.477216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.477322] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.477345] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.477369] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.477417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.477441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.477464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.477487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.477508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.477532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.477557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.477581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.477605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.477626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.477648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.477673] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.477694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.479699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.479716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.479731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.479746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.481282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.481297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.481311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.482805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.482821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.484628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.487579] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.487636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.487652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.487672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.504379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.504405] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.504440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.504540] [drm:drm_mode_addfb2] [FB:78]
>[ 1379.504606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.521082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.521106] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.521143] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.540003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.540022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.540043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.540060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.540077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.540092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.540107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.540123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.540141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.540157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.540173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.540189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.540203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.540217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.540296] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.540332] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.540364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.540390] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.540502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.540516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.540585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.540610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.540638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.540668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.540692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.540718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.540744] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.540769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.540794] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.540824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.540845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.540851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.540872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.540877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.540899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.540920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.540942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.540963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.540988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.541008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.541030] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.541050] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.541071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.541094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.541119] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.541183] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.541205] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.541227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.541282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.541306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.541329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.541352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.541374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.541398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.541423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.541448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.541471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.541493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.541515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.541539] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.541562] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.543551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.543567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.543581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.543596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.545097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.545112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.545126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.546634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.546651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.548472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.551410] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.551483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.551500] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.551522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.568224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.568267] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.568302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.568400] [drm:drm_mode_addfb2] [FB:79]
>[ 1379.568467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.584904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.584930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.584967] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.603305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.603324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.603345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.603362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.603380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.603395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.603411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.603429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.603451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.603472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.603493] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.603514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.603533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.603552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.603580] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.603603] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.603628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.603644] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.603753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.603763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.603810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.603830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.603850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.603871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.603890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.603912] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.603932] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.603953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.603973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.603994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.604014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.604018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.604038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.604041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.604062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.604082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.604103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.604123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.604143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.604163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.604184] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.604204] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.604224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.604289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.604319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.604393] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.604418] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.604442] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.604484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.604508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.604533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.604556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.604580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.604604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.604630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.604656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.604682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.604703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.604725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.604753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.604776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.606812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.606829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.606843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.606858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.608360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.608375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.608388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.609877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.609893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.611695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.614649] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.614705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.614722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.614744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.631447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.631474] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.631511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.631609] [drm:drm_mode_addfb2] [FB:75]
>[ 1379.631674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.648125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.648150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.648186] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.667034] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.667053] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.667074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.667091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.667109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.667124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.667139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.667155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.667173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.667190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.667206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.667222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.667282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.667309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.667353] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.667389] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.667424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.667450] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.667556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.667573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.667648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.667680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.667705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.667732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.667752] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.667776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.667798] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.667820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.667841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.667863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.667882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.667888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.667907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.667912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.667934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.667953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.667973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.667992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.668015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.668034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.668055] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.668073] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.668094] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.668115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.668139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.668206] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.668228] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.668270] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.668308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.668330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.668353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.668374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.668395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.668417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.668442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.668466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.668491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.668511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.668532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.668558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.668580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.670577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.670594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.670608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.670623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.672124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.672140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.672154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.673649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.673665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.675467] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.678407] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.678476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.678493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.678515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.695218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.695288] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.695341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.695440] [drm:drm_mode_addfb2] [FB:78]
>[ 1379.695503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.711920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.711946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.711984] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.730825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.730844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.730864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.730881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.730899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.730915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.730929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.730946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.730964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.730980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.730996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.731012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.731031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.731050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.731078] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.731101] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.731126] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.731143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.731262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.731279] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.731355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.731380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.731407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.731437] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.731460] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.731485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.731510] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.731534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.731557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.731580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.731601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.731607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.731628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.731634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.731657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.731678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.731701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.731721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.731746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.731767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.731790] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.731811] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.731833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.731856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.731882] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.731955] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.731979] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.732003] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.732044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.732068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.732098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.732119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.732139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.732161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.732185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.732208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.732231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.732274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.732294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.732320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.732342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.734336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.734353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.734368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.734382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.735884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.735900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.735913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.737408] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.737424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.739226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.742165] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.742192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.742209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.742240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.758935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.758960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.758995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.759086] [drm:drm_mode_addfb2] [FB:79]
>[ 1379.759152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.775629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.775651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.775685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.794536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.794555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.794577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.794597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.794618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.794638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.794657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.794677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.794698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.794719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.794740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.794760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.794779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.794798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.794826] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.794849] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.794874] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.794891] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.795006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.795016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.795063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.795083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.795102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.795123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.795139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.795158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.795176] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.795197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.795217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.795237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.795300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.795308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.795334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.795341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.795367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.795390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.795415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.795436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.795463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.795485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.795509] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.795531] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.795554] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.795582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.795610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.795684] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.795708] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.795733] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.795774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.795797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.795821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.795842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.795865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.795887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.795913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.795939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.795964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.795985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.796007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.796032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.796056] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.798056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.798072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.798086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.798101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.799617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.799634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.799649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.801142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.801159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.802966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.805898] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.805975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.805992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.806014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.822717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.822744] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.822781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.822876] [drm:drm_mode_addfb2] [FB:75]
>[ 1379.822947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.839419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.839445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.839483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.857855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.857875] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.857895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.857912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.857929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.857944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.857959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.857975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.857993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.858010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.858025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.858041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.858060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.858079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.858107] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.858129] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.858154] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.858171] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.858299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.858317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.858392] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.858419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.858447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.858476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.858499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.858525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.858549] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.858573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.858596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.858620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.858641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.858647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.858669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.858674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.858698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.858719] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.858741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.858762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.858787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.858807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.858830] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.858851] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.858873] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.858896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.858923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.859000] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.859022] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.859044] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.859080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.859101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.859122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.859142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.859163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.859183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.859207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.859230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.859273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.859295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.859315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.859340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.859362] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.861358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.861375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.861390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.861405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.862904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.862922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.862939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.864438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.864456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.866273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.869203] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.869237] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.869293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.869328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.885973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.886000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.886037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.886130] [drm:drm_mode_addfb2] [FB:78]
>[ 1379.886202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.902653] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.902677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.902723] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.921568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.921586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.921606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.921623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.921641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.921656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.921671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.921687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.921704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.921721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.921737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.921753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.921772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.921791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.921819] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.921842] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.921867] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.921884] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.922001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.922012] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.922059] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.922078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.922098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.922119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.922136] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.922154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.922174] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.922195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.922215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.922235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.922295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.922303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.922329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.922336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.922361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.922384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.922408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.922430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.922456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.922478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.922503] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.922525] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.922548] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.922575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.922603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.922675] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.922699] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.922723] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.922763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.922788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.922810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.922832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.922856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.922879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.922905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.922930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.922955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.922976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.922998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.923022] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.923046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.925048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.925065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.925080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.925095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.926601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.926617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.926631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.928122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.928138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.929944] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.932875] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.932902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.932919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.932941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1379.949644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.949669] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.949704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.949794] [drm:drm_mode_addfb2] [FB:79]
>[ 1379.949854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.966325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1379.966351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1379.966397] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1379.985240] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1379.985276] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1379.985297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.985314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.985332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.985347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.985362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.985378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1379.985396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.985412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.985428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.985444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.985463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.985482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.985510] [drm:intel_power_well_disable [i915]] disabling display
>[ 1379.985533] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1379.985557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1379.985574] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1379.985681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1379.985691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1379.985738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1379.985759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1379.985780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1379.985803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1379.985823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1379.985853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1379.985873] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1379.985893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1379.985914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1379.985934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1379.985954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1379.985958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.985977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1379.985981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1379.986002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1379.986022] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1379.986042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1379.986062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1379.986082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1379.986102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1379.986122] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1379.986143] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1379.986163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1379.986184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1379.986206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1379.986292] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1379.986315] [drm:intel_power_well_enable [i915]] enabling display
>[ 1379.986339] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1379.986382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1379.986407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1379.986431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1379.986453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1379.986476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1379.986499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1379.986525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1379.986550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1379.986575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1379.986596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1379.986618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1379.986644] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1379.986667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1379.988677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1379.988694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1379.988708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.988723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1379.990229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1379.990244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1379.990292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1379.991798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1379.991816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1379.993639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1379.996578] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1379.996650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1379.996670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1379.996696] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.013392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.013418] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.013452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.013553] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.013617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.030071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.030096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.030141] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.048016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.048034] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.048056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.048076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.048097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.048117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.048137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.048156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.048178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.048199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.048219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.048239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.048257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.048321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.048364] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.048406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.048439] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.048464] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.048576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.048593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.048665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.048690] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.048717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.048746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.048768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.048794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.048817] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.048841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.048863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.048885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.048905] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.048911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.048932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.048937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.048960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.048980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.049002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.049021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.049046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.049066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.049088] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.049108] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.049129] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.049152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.049177] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.049248] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.049298] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.049322] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.049362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.049395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.049416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.049438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.049458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.049481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.049506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.049531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.049555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.049575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.049597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.049622] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.049644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.051644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.051662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.051676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.051691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.053206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.053222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.053236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.054762] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.054777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.056611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.059561] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.059620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.059636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.059657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.076357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.076382] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.076415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.076512] [drm:drm_mode_addfb2] [FB:78]
>[ 1380.076574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.093042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.093068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.093115] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.111977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.111996] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.112017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.112034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.112051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.112066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.112081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.112097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.112114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.112131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.112147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.112162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.112176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.112190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.112217] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.112239] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.112260] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.112323] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.112437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.112452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.112520] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.112546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.112575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.112604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.112630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.112656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.112682] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.112707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.112732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.112755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.112779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.112785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.112807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.112813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.112836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.112867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.112889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.112910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.112932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.112953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.112975] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.112997] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.113018] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.113042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.113067] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.113131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.113153] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.113175] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.113214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.113236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.113259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.113304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.113325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.113349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.113374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.113399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.113424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.113446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.113468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.113494] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.113517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.115508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.115524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.115538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.115552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.117054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.117072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.117090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.118587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.118604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.120407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.123346] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.123417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.123437] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.123462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.140158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.140184] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.140218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.140380] [drm:drm_mode_addfb2] [FB:79]
>[ 1380.140446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.156859] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.156883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.156928] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.175785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.175804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.175824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.175840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.175858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.175873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.175887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.175905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.175927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.175947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.175967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.175987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.176005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.176023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.176050] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.176073] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.176097] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.176113] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.176207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.176218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.176271] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.176327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.176355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.176383] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.176405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.176430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.176453] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.176477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.176499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.176521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.176541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.176548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.176568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.176574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.176595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.176615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.176636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.176656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.176680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.176699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.176720] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.176739] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.176760] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.176782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.176806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.176862] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.176885] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.176906] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.176942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.176963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.176984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.177004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.177025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.177045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.177068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.177091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.177114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.177133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.177153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.177178] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.177199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.179190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.179207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.179221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.179236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.180740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.180755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.180769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.182262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.182286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.184088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.187009] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.187046] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.187063] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.187085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.203788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.203814] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.203848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.203940] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.204008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.220470] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.220494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.220540] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.239387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.239406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.239426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.239443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.239461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.239476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.239491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.239507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.239525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.239541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.239558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.239573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.239588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.239602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.239629] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.239650] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.239671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.239687] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.239801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.239811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.239858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.239878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.239898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.239921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.239941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.239962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.239983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.240003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.240024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.240044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.240064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.240068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.240088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.240092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.240112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.240132] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.240152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.240172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.240193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.240212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.240233] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.240253] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.240273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.240341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.240371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.240432] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.240457] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.240482] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.240524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.240548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.240574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.240597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.240621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.240643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.240676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.240701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.240724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.240744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.240765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.240790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.240812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.242816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.242834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.242852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.242870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.244390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.244407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.244422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.245919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.245936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.247746] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.250693] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.250754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.250771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.250794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.267505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.267531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.267565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.267667] [drm:drm_mode_addfb2] [FB:78]
>[ 1380.267725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.284194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.284219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.284256] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.303137] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.303157] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.303177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.303194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.303212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.303227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.303242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.303258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.303325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.303355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.303382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.303409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.303432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.303457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.303501] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.303536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.303568] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.303594] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.303698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.303715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.303787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.303812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.303840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.303869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.303891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.303917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.303941] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.303965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.303988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.304011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.304032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.304037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.304059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.304064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.304087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.304109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.304131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.304151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.304176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.304197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.304225] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.304244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.304264] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.304317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.304344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.304398] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.304420] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.304443] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.304481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.304501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.304524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.304544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.304565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.304585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.304609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.304632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.304656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.304675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.304696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.304720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.304741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.306748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.306764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.306778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.306793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.308327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.308342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.308355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.309848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.309864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.311673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.314620] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.314683] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.314699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.314721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.331424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.331450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.331485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.331594] [drm:drm_mode_addfb2] [FB:79]
>[ 1380.331663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.348127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.348151] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.348196] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.367069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.367088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.367108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.367125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.367142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.367158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.367173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.367189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.367206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.367223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.367239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.367255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.367269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.367325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.367368] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.367402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.367434] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.367460] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.367569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.367584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.367652] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.367675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.367702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.367738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.367759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.367782] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.367803] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.367825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.367846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.367867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.367886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.367891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.367911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.367916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.367937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.367956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.367977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.367995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.368018] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.368037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.368058] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.368077] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.368098] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.368119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.368142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.368205] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.368227] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.368248] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.368304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.368326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.368349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.368369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.368391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.368413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.368437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.368461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.368486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.368506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.368528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.368551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.368574] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.370561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.370577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.370591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.370606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.372108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.372123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.372137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.373631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.373650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.375456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.378392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.378466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.378486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.378512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.395207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.395233] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.395267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.395431] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.395502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.411908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.411934] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.411981] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.430836] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.430855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.430876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.430893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.430910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.430926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.430941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.430957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.430975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.430991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.431007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.431023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.431037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.431051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.431078] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.431100] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.431124] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.431141] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.431238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.431250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.431351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.431380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.431411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.431441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.431465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.431493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.431517] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.431541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.431564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.431588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.431609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.431615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.431637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.431643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.431666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.431688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.431710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.431731] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.431756] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.431777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.431799] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.431820] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.431842] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.431865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.431892] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.431955] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.431979] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.432002] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.432042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.432065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.432089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.432111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.432133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.432155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.432181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.432206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.432238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.432257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.432277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.432322] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.432345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.434343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.434360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.434375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.434390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.435894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.435908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.435922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.437419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.437435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.439237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.442168] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.442195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.442212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.442234] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.458939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.458965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.459002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.459104] [drm:drm_mode_addfb2] [FB:78]
>[ 1380.459173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.475610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.475633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.475677] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.494520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.494539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.494559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.494576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.494594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.494609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.494623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.494639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.494657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.494674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.494689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.494705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.494719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.494733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.494760] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.494781] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.494802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.494818] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.494934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.494944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.494991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.495012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.495033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.495057] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.495077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.495097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.495118] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.495138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.495159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.495179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.495199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.495203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.495223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.495226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.495247] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.495268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.495288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.495347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.495373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.495400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.495424] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.495448] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.495471] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.495499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.495527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.495587] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.495610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.495634] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.495675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.495697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.495721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.495743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.495765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.495788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.495819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.495842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.495865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.495884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.495905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.495927] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.495950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.497959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.497976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.497991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.498007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.499515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.499530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.499544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.501034] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.501049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.502853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.505785] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.505862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.505880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.505902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.522604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.522630] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.522665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.522762] [drm:drm_mode_addfb2] [FB:79]
>[ 1380.522828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.539276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.539321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.539366] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.558210] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.558229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.558249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.558266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.558284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.558344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.558362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.558378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.558397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.558414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.558430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.558446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.558461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.558475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.558501] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.558523] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.558544] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.558560] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.558638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.558648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.558690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.558706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.558725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.558745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.558760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.558777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.558794] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.558813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.558832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.558852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.558871] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.558876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.558895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.558898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.558919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.558938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.558958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.558977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.558998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.559016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.559037] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.559056] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.559074] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.559094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.559115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.559154] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.559169] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.559185] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.559221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.559237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.559253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.559267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.559285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.559330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.559354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.559376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.559399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.559419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.559439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.559463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.559484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.561477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.561492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.561507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.561521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.563022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.563038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.563051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.564544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.564560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.566361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.569272] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.569370] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.569386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.569416] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.586100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.586123] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.586156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.586251] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.586371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.602794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.602820] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.602866] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.621650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.621669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.621690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.621707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.621725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.621741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.621756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.621772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.621790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.621806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.621822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.621838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.621853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.621867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.621894] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.621916] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.621937] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.621952] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.622044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.622056] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.622108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.622128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.622148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.622171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.622191] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.622212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.622233] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.622253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.622274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.622295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.622348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.622355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.622382] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.622388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.622414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.622438] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.622462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.622484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.622511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.622533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.622558] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.622580] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.622604] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.622632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.622660] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.622734] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.622759] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.622784] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.622827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.622852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.622876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.622900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.622923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.622948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.622975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.623001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.623026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.623047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.623069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.623094] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.623118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.625122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.625139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.625153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.625168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.626674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.626689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.626703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.628194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.628210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.630016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.632937] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.632973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.632989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.633011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.649717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.649743] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.649777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.649879] [drm:drm_mode_addfb2] [FB:78]
>[ 1380.649937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.666419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.666443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.666490] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.685338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.685357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.685377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.685394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.685412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.685428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.685442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.685458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.685476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.685493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.685509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.685524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.685539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.685553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.685579] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.685601] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.685621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.685637] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.685743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.685753] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.685800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.685822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.685843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.685866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.685886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.685907] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.685928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.685948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.685969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.685989] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.686009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.686013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.686032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.686036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.686057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.686077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.686098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.686118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.686138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.686158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.686178] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.686198] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.686218] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.686239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.686261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.686351] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.686377] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.686401] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.686445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.686470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.686496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.686520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.686544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.686568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.686596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.686622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.686649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.686671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.686694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.686722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.686746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.688768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.688785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.688800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.688815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.690353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.690368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.690382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.691876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.691892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.693699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.696644] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.696708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.696725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.696747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.713451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.713478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.713515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.713621] [drm:drm_mode_addfb2] [FB:79]
>[ 1380.713688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.730131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.730155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.730200] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.749074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.749093] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.749113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.749130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.749148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.749164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.749179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.749195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.749213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.749230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.749245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.749261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.749275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.749289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.749366] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.749402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.749435] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.749461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.749573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.749588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.749659] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.749693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.749718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.749745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.749768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.749792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.749817] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.749839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.749862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.749884] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.749905] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.749911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.749932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.749937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.749959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.749980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.750001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.750022] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.750045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.750066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.750086] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.750107] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.750128] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.750151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.750176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.750238] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.750260] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.750282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.750342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.750368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.750391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.750414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.750436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.750460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.750485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.750510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.750534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.750556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.750578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.750604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.750627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.752616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.752632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.752646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.752660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.754162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.754180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.754197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.755694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.755711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.757516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.760210] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.760272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.760291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.760353] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.777015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.777041] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.777077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.777177] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.777243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.793714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.793739] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.793776] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.812625] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.812644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.812664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.812681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.812702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.812722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.812742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.812761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.812783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.812804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.812824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.812844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.812863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.812882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.812910] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.812933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.812958] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.812975] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.813097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.813107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.813151] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.813169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.813188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.813208] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.813224] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.813241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.813258] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.813274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.813290] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.813334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.813356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.813364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.813386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.813392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.813416] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.813436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.813459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.813479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.813504] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.813524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.813547] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.813567] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.813589] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.813615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.813641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.813698] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.813721] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.813744] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.813782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.813805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.813826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.813848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.813868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.813890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.813915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.813939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.813962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.813982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.814003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.814028] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.814049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.816055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.816072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.816089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.816108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.817617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.817634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.817648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.819140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.819156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.820962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.823894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.823970] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.823987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.824009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.840714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.840740] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.840777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.840879] [drm:drm_mode_addfb2] [FB:78]
>[ 1380.840947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.857394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.857418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.857454] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.876301] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.876337] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.876358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.876375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.876396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.876416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.876435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.876454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.876476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.876497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.876518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.876537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.876556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.876575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.876603] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.876626] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.876651] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.876668] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.876783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.876793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.876840] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.876860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.876880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.876901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.876917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.876935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.876953] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.876971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.876987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.877003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.877019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.877023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.877038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.877041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.877057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.877072] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.877087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.877102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.877119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.877134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.877150] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.877164] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.877179] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.877196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.877216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.877265] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.877282] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.877298] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.877375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.877400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.877426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.877448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.877472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.877496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.877523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.877550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.877578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.877600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.877623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.877652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.877676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.879687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.879706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.879723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.879742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.881258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.881275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.881289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.882816] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.882832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.884663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.887639] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.887672] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.887695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.887716] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.904416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.904442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.904477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.904577] [drm:drm_mode_addfb2] [FB:79]
>[ 1380.904643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.921095] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.921120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.921156] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1380.940007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1380.940027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1380.940047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.940064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.940082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.940097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.940112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.940131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.940152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.940173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.940194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.940214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.940233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.940253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.940280] [drm:intel_power_well_disable [i915]] disabling display
>[ 1380.940303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1380.940376] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.940404] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1380.940520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1380.940534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1380.940606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1380.940633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1380.940661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1380.940691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1380.940715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1380.940741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1380.940767] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1380.940793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1380.940817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1380.940841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1380.940864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1380.940870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.940893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1380.940899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1380.940930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1380.940951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1380.940973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1380.940992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1380.941016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1380.941037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1380.941059] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1380.941080] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1380.941101] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1380.941122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.941146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1380.941210] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1380.941233] [drm:intel_power_well_enable [i915]] enabling display
>[ 1380.941256] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1380.941294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1380.941316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1380.941357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1380.941379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1380.941402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1380.941425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1380.941451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1380.941475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1380.941499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.941521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1380.941543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1380.941569] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1380.941593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1380.943581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1380.943597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1380.943613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.943631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1380.945135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1380.945151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1380.945165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1380.946660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1380.946676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1380.948479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1380.951416] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1380.951488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1380.951505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1380.951527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1380.968230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1380.968255] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1380.968290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1380.968458] [drm:drm_mode_addfb2] [FB:75]
>[ 1380.968516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1380.984932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1380.984956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1380.984993] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.003850] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.003868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.003889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.003906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.003924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.003939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.003954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.003970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.003988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.004004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.004020] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.004036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.004050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.004064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.004091] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.004113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.004134] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.004149] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.004239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.004250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.004303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.004361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.004392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.004423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.004453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.004478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.004501] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.004525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.004546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.004568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.004588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.004595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.004617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.004623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.004645] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.004664] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.004687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.004706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.004730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.004749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.004770] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.004788] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.004810] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.004834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.004859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.004914] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.004937] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.004958] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.004995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.005016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.005038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.005057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.005078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.005099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.005123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.005146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.005169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.005188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.005209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.005231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.005253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.007246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.007263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.007278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.007293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.008831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.008849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.008866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.010401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.010419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.012223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.015155] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.015234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.015254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.015279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.031975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.032001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.032035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.032135] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.032198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.048677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.048703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.048741] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.067596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.067615] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.067635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.067652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.067670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.067685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.067700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.067716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.067737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.067758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.067779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.067800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.067819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.067838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.067865] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.067888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.067913] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.067930] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.068043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.068054] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.068100] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.068120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.068141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.068164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.068184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.068205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.068225] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.068246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.068266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.068286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.068306] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.068347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.068376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.068383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.068410] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.068434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.068459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.068481] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.068508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.068530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.068555] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.068577] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.068601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.068629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.068657] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.068731] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.068755] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.068779] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.068823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.068848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.068872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.068895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.068918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.068942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.068969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.068995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.069021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.069043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.069063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.069090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.069113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.071117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.071134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.071149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.071164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.072670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.072685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.072699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.074190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.074206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.076010] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.078949] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.079018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.079035] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.079056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.095762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.095789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.095826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.095928] [drm:drm_mode_addfb2] [FB:79]
>[ 1381.095996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.112442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.112466] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.112502] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.131377] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.131395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.131415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.131433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.131451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.131466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.131481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.131497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.131514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.131530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.131546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.131562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.131577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.131591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.131617] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.131639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.131660] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.131676] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.131789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.131799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.131846] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.131866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.131886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.131908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.131928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.131949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.131969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.131990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.132010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.132030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.132050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.132054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.132074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.132078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.132098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.132119] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.132139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.132159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.132179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.132199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.132220] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.132240] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.132260] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.132281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.132303] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.132399] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.132424] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.132449] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.132492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.132519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.132543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.132568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.132590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.132616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.132644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.132670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.132697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.132719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.132743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.132771] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.132794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.134812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.134830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.134844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.134859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.136387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.136402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.136415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.137908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.137924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.139730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.142674] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.142739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.142757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.142779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.159481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.159508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.159546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.159649] [drm:drm_mode_addfb2] [FB:75]
>[ 1381.159717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.176177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.176199] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.176233] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.195098] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.195117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.195137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.195157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.195179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.195198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.195218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.195237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.195259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.195280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.195300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.195320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.195386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.195415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.195460] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.195495] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.195529] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.195555] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.195668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.195683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.195758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.195782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.195808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.195835] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.195857] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.195881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.195905] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.195927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.195950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.195972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.195992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.195998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.196019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.196024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.196046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.196067] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.196088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.196109] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.196131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.196152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.196174] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.196194] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.196213] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.196236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.196261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.196323] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.196367] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.196389] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.196428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.196452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.196476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.196498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.196521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.196544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.196570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.196594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.196619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.196640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.196662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.196688] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.196712] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.198703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.198719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.198734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.198752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.200269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.200285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.200299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.201793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.201808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.203614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.206555] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.206623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.206640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.206665] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.223368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.223393] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.223428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.223527] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.223593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.240045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.240070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.240106] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.258973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.258992] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.259012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.259029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.259051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.259070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.259090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.259109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.259131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.259152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.259172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.259192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.259211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.259230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.259258] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.259280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.259305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.259322] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.259471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.259485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.259555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.259583] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.259611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.259641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.259667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.259694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.259720] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.259746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.259771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.259795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.259818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.259824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.259846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.259853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.259876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.259899] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.259923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.259946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.259970] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.259993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.260018] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.260041] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.260064] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.260090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.260124] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.260188] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.260210] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.260232] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.260271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.260294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.260316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.260358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.260381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.260403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.260429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.260453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.260478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.260500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.260523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.260549] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.260572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.262561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.262577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.262591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.262605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.264107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.264123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.264136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.265631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.265647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.267452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.270389] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.270461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.270477] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.270499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.287203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.287229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.287267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.287425] [drm:drm_mode_addfb2] [FB:79]
>[ 1381.287500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.303883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.303908] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.303944] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.322812] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.322831] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.322852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.322869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.322887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.322903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.322918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.322935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.322953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.322969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.322984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.323000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.323014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.323029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.323055] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.323077] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.323098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.323113] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.323220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.323231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.323278] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.323297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.323317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.323379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.323404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.323430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.323457] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.323481] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.323507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.323529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.323553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.323560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.323583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.323589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.323621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.323642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.323665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.323685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.323710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.323731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.323754] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.323774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.323797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.323823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.323850] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.323907] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.323931] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.323954] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.323992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.324015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.324038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.324058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.324081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.324102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.324127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.324151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.324175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.324195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.324217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.324241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.324265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.326263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.326280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.326294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.326309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.327828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.327843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.327857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.329361] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.329379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.331182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.335215] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.335253] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.335270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.335292] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.351996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.352021] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.352057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.352159] [drm:drm_mode_addfb2] [FB:75]
>[ 1381.352219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.368698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.368722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.368759] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.387605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.387624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.387644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.387661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.387678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.387693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.387708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.387724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.387742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.387758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.387774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.387790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.387804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.387818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.387845] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.387867] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.387888] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.387904] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.388015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.388025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.388079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.388098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.388125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.388145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.388161] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.388179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.388196] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.388212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.388228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.388243] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.388258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.388261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.388276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.388279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.388294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.388309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.388324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.388374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.388402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.388423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.388444] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.388467] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.388488] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.388514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.388541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.388598] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.388622] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.388647] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.388688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.388712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.388736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.388760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.388783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.388807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.388833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.388858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.388884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.388906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.388928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.388955] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.388980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.390980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.390997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.391011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.391026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.392532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.392547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.392560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.394051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.394067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.395876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.398809] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.398886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.398903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.398925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.415630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.415655] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.415692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.415796] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.415863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.432299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.432322] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.432403] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.451103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.451122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.451142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.451159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.451177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.451192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.451207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.451223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.451241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.451257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.451272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.451288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.451302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.451315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.451387] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.451425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.451458] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.451484] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.451597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.451611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.451680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.451706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.451733] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.451762] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.451787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.451813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.451839] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.451863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.451888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.451911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.451935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.451941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.451964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.451970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.451994] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.452017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.452040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.452063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.452089] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.452112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.452133] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.452156] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.452179] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.452204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.452232] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.452301] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.452324] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.452348] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.452413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.452439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.452472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.452494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.452517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.452540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.452566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.452590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.452614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.452636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.452658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.452684] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.452707] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.454698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.454714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.454727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.454742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.456245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.456263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.456280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.457777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.457794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.459597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.462528] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.462554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.462570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.462592] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.479299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.479325] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.479408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.479531] [drm:drm_mode_addfb2] [FB:79]
>[ 1381.479595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.495979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.496005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.496043] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.514895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.514915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.514935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.514953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.514971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.514986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.515001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.515020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.515042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.515063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.515083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.515104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.515123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.515142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.515170] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.515193] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.515217] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.515234] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.515331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.515364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.515438] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.515464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.515491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.515520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.515542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.515568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.515592] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.515617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.515639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.515662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.515683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.515689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.515711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.515716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.515739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.515760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.515782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.515803] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.515828] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.515848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.515871] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.515898] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.515919] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.515940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.515964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.516020] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.516041] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.516063] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.516100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.516120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.516141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.516161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.516182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.516202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.516226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.516249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.516272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.516291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.516311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.516336] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.516375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.518371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.518389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.518404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.518419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.519923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.519939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.519952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.521450] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.521466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.523295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.526226] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.526304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.526321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.526343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.543048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.543074] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.543109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.543208] [drm:drm_mode_addfb2] [FB:75]
>[ 1381.543273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.559748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.559773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.559809] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.578672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.578691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.578711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.578728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.578746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.578762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.578777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.578793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.578811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.578827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.578843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.578859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.578873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.578887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.578914] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.578935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.578956] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.578972] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.579086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.579096] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.579144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.579165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.579186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.579210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.579230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.579251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.579271] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.579292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.579313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.579333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.579353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.579386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.579415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.579422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.579449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.579473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.579498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.579521] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.579548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.579570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.579594] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.579616] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.579640] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.579668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.579696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.579757] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.579783] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.579806] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.579847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.579870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.579894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.579915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.579938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.579960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.579986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.580012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.580037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.580058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.580081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.580108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.580131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.582132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.582149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.582164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.582179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.583685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.583700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.583717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.585210] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.585227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.587031] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.589956] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.589989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.590006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.590028] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.606733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.606759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.606793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.606887] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.606957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.623434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.623458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.623495] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.642338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.642375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.642395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.642412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.642430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.642446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.642461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.642477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.642495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.642511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.642527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.642543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.642562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.642581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.642609] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.642632] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.642657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.642674] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.642789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.642799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.642844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.642863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.642881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.642901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.642916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.642933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.642950] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.642966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.642981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.642996] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.643010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.643013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.643027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.643031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.643045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.643059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.643073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.643087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.643103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.643117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.643134] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.643153] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.643172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.643192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.643213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.643251] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.643266] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.643282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.643312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.643332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.643351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.643412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.643436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.643462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.643489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.643515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.643541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.643562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.643585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.643609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.643634] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.645643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.645660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.645674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.645689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.647192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.647208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.647222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.648718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.648733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.650537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.653479] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.653547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.653566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.653592] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.670289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.670315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.670350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.670523] [drm:drm_mode_addfb2] [FB:79]
>[ 1381.670581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.686969] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.686993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.687030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.705878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.705897] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.705917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.705935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.705952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.705968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.705987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.706006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.706028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.706049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.706070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.706090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.706109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.706128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.706156] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.706179] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.706204] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.706220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.706310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.706321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.706417] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.706444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.706474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.706504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.706528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.706555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.706580] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.706605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.706629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.706653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.706675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.706682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.706704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.706709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.706732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.706754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.706777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.706799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.706824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.706845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.706867] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.706888] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.706910] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.706935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.706963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.707036] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.707060] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.707083] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.707123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.707146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.707169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.707191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.707221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.707241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.707265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.707287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.707310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.707329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.707350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.707398] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.707423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.709423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.709440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.709455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.709470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.710975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.710993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.711010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.712508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.712524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.714330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.717262] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.717339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.717356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.717429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.734082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.734108] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.734146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.734250] [drm:drm_mode_addfb2] [FB:75]
>[ 1381.734315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.750761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.750785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.750821] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.769673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.769694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.769716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.769736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.769757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.769777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.769796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.769816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.769838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.769858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.769879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.769899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.769918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.769936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.769964] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.769987] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.770012] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.770028] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.770142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.770152] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.770199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.770219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.770240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.770263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.770283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.770304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.770324] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.770345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.770365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.770419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.770445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.770453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.770476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.770483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.770508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.770530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.770554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.770576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.770603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.770624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.770648] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.770669] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.770692] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.770720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.770748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.770822] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.770846] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.770870] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.770910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.770934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.770956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.770979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.771001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.771024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.771050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.771076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.771101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.771122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.771144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.771168] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.771193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.773200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.773218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.773235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.773253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.774761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.774778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.774792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.776305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.776323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.778129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.781048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.781086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.781102] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.781124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.797830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.797856] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.797891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.797982] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.798050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.814510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.814536] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.814574] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.833424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.833443] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.833463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.833480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.833498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.833513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.833527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.833543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.833561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.833577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.833593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.833609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.833623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.833637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.833664] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.833686] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.833707] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.833722] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.833835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.833845] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.833892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.833912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.833932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.833952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.833969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.833987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.834005] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.834022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.834039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.834055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.834070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.834074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.834089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.834093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.834113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.834133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.834154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.834174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.834194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.834214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.834235] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.834255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.834275] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.834296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.834318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.834407] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.834429] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.834453] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.834496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.834520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.834544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.834567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.834589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.834613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.834639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.834665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.834689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.834710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.834732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.834758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.834782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.836793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.836810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.836824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.836839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.838348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.838363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.838411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.839911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.839927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.841748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.844702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.844757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.844775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.844797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.861500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.861526] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.861564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.861666] [drm:drm_mode_addfb2] [FB:79]
>[ 1381.861734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.878180] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.878204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.878241] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.897097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.897116] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.897136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.897155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.897177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.897197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.897216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.897236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.897257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.897278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.897299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.897319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.897338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.897357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.897436] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.897472] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.897507] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.897533] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.897651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.897668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.897743] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.897776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.897801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.897827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.897848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.897872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.897894] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.897916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.897937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.897958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.897978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.897984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.898003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.898008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.898030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.898049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.898069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.898088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.898112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.898131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.898152] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.898171] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.898191] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.898213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.898237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.898301] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.898323] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.898344] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.898410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.898432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.898455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.898476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.898498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.898520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.898546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.898571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.898595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.898616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.898637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.898663] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.898685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.900681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.900698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.900714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.900732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.902239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.902255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.902269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.903764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.903780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.905583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.908528] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.908593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.908610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.908632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.925335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.925362] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.925451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.925568] [drm:drm_mode_addfb2] [FB:75]
>[ 1381.925634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.942015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1381.942040] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1381.942076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1381.960926] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1381.960945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1381.960967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.960987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.961009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.961028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.961048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.961067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.961089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.961109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.961130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.961150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.961169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.961188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.961216] [drm:intel_power_well_disable [i915]] disabling display
>[ 1381.961238] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1381.961263] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.961279] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1381.961403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1381.961421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1381.961665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1381.961691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1381.961718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1381.961748] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1381.961770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1381.961796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1381.961820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1381.961845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1381.961867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1381.961890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1381.961910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1381.961917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.961938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1381.961943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1381.961967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1381.961988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1381.962010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1381.962030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1381.962055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1381.962076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1381.962099] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1381.962119] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1381.962141] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1381.962165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1381.962192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1381.962268] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1381.962290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1381.962311] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1381.962348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1381.962369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1381.962410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1381.962430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1381.962453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1381.962474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1381.962499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1381.962524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1381.962548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.962568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1381.962589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1381.962616] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1381.962637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1381.964900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1381.964917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1381.964932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.964948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1381.966470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1381.966487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1381.966502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1381.968000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1381.968017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1381.969825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1381.972759] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1381.972834] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1381.972850] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1381.972872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1381.989575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1381.989598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1381.989630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1381.989729] [drm:drm_mode_addfb2] [FB:78]
>[ 1381.989786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.006273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.006298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.006337] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.025183] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.025202] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.025222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.025239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.025257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.025273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.025287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.025306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.025328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.025349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.025370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.025437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.025467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.025492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.025538] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.025573] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.025606] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.025639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.025735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.025751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.025820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.025844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.025869] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.025896] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.025917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.025941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.025963] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.025985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.026006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.026027] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.026047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.026052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.026072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.026077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.026098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.026117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.026138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.026156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.026179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.026198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.026219] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.026238] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.026258] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.026280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.026304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.026357] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.026379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.026425] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.026463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.026484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.026507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.026528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.026549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.026571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.026595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.026619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.026644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.026664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.026685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.026709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.026731] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.028728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.028744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.028758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.028773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.030276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.030292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.030305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.031801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.031817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.033621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.036566] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.036630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.036649] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.036675] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.053373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.053415] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.053450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.053562] [drm:drm_mode_addfb2] [FB:79]
>[ 1382.053635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.070070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.070093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.070138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.088998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.089016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.089037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.089054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.089071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.089087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.089102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.089117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.089135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.089151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.089167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.089187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.089207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.089226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.089254] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.089276] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.089303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.089330] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.089466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.089481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.089552] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.089577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.089604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.089634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.089657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.089683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.089707] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.089731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.089754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.089777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.089797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.089803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.089825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.089830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.089854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.089875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.089897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.089917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.089943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.089963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.089986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.090006] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.090028] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.090051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.090077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.090148] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.090170] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.090191] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.090227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.090248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.090269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.090289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.090310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.090330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.090353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.090376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.090418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.090440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.090460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.090485] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.090507] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.092500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.092516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.092531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.092545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.094049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.094064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.094078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.095574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.095590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.097408] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.100340] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.100454] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.100479] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.100515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.117160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.117185] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.117220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.117332] [drm:drm_mode_addfb2] [FB:75]
>[ 1382.117455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.133854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.133878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.133923] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.152774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.152793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.152815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.152835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.152856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.152876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.152896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.152915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.152936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.152957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.152977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.152997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.153016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.153035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.153063] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.153086] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.153111] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.153127] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.153241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.153251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.153298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.153317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.153337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.153361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.153381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.153439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.153466] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.153493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.153519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.153544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.153568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.153576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.153599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.153606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.153630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.153655] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.153679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.153703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.153730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.153754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.153778] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.153803] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.153827] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.153854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.153882] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.153956] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.153981] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.154005] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.154046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.154072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.154096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.154118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.154142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.154166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.154194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.154220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.154246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.154270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.154293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.154320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.154344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.156366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.156383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.156424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.156451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.157959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.157974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.157987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.159485] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.159502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.161325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.164257] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.164283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.164299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.164321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.181022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.181046] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.181080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.181191] [drm:drm_mode_addfb2] [FB:78]
>[ 1382.181263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.197707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.197731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.197777] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.216632] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.216651] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.216671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.216688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.216706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.216722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.216736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.216753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.216771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.216787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.216804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.216820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.216834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.216849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.216876] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.216897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.216918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.216934] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.217048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.217058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.217106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.217126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.217146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.217170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.217190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.217211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.217232] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.217252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.217272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.217292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.217312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.217316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.217336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.217340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.217361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.217381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.217448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.217477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.217505] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.217531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.217557] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.217581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.217606] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.217634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.217662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.217723] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.217748] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.217773] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.217814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.217840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.217864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.217888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.217912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.217936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.217963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.217988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.218014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.218045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.218064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.218088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.218111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.220110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.220126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.220140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.220155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.221665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.221680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.221693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.223189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.223204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.225015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.227950] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.228025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.228041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.228063] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.244798] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.244824] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.244858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.244958] [drm:drm_mode_addfb2] [FB:79]
>[ 1382.245025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.261460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.261484] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.261520] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.280372] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.280391] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.280460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.280489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.280517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.280541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.280566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.280591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.280620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.280647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.280673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.280699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.280722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.280745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.280789] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.280823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.280855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.280880] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.281011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.281021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.281069] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.281090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.281111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.281134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.281154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.281175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.281196] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.281216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.281237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.281257] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.281277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.281281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.281301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.281305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.281325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.281346] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.281366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.281386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.281450] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.281476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.281500] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.281523] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.281552] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.281575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.281599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.281656] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.281678] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.281698] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.281737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.281761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.281783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.281805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.281827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.281850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.281875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.281900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.281924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.281945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.281963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.281983] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.282001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.283997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.284016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.284033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.284052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.285561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.285579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.285596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.287091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.287108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.288914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.291847] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.291924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.291944] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.291970] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.308666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.308692] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.308727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.308828] [drm:drm_mode_addfb2] [FB:75]
>[ 1382.308885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.325368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.325394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.325483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.344159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.344179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.344199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.344216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.344237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.344256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.344276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.344295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.344317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.344338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.344359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.344378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.344398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.344461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.344504] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.344539] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.344573] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.344598] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.344699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.344713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.344782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.344806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.344832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.344861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.344884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.344910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.344933] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.344957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.344980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.345002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.345023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.345029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.345050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.345055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.345078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.345099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.345122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.345142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.345174] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.345192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.345213] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.345232] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.345252] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.345274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.345298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.345359] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.345381] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.345421] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.345459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.345482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.345503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.345525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.345545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.345568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.345593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.345618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.345642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.345662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.345683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.345709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.345730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.347719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.347734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.347748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.347763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.349266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.349281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.349297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.350795] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.350811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.352614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.355549] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.355623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.355642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.355668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.372365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.372390] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.372475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.372592] [drm:drm_mode_addfb2] [FB:78]
>[ 1382.372648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.389046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.389071] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.389107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.407960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.407980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.408000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.408017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.408035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.408054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.408074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.408094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.408116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.408137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.408158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.408178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.408197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.408216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.408244] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.408267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.408292] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.408308] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.408433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.408449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.408528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.408555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.408590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.408617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.408639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.408664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.408688] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.408712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.408735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.408757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.408778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.408783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.408804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.408809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.408831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.408852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.408874] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.408895] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.408919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.408940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.408962] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.408984] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.409003] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.409026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.409052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.409106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.409129] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.409151] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.409189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.409212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.409235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.409256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.409279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.409301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.409325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.409349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.409373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.409395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.409438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.409462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.409486] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.411484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.411501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.411516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.411531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.413036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.413051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.413068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.414565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.414582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.416386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.419329] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.419444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.419471] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.419505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.436149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.436175] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.436210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.436300] [drm:drm_mode_addfb2] [FB:79]
>[ 1382.436367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.452828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.452853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.452889] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.471740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.471759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.471779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.471796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.471814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.471830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.471845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.471861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.471879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.471895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.471911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.471927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.471942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.471955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.471982] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.472004] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.472025] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.472040] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.472153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.472163] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.472210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.472230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.472250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.472271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.472287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.472305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.472323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.472340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.472357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.472372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.472388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.472391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.472456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.472463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.472489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.472514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.472539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.472563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.472590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.472615] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.472640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.472664] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.472688] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.472716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.472744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.472803] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.472828] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.472852] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.472893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.472917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.472942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.472965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.472989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.473011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.473038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.473063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.473097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.473118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.473139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.473164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.473187] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.475185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.475201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.475215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.475230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.476748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.476766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.476780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.478274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.478290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.480097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.483029] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.483107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.483124] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.483146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.499849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.499874] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.499909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.500008] [drm:drm_mode_addfb2] [FB:75]
>[ 1382.500073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.516550] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.516574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.516610] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.535468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.535487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.535508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.535525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.535542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.535558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.535573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.535589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.535607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.535623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.535643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.535664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.535683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.535702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.535730] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.535753] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.535777] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.535794] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.535907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.535917] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.535964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.535983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.536003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.536024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.536044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.536065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.536085] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.536106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.536126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.536147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.536166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.536170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.536190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.536194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.536214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.536235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.536255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.536275] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.536296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.536316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.536336] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.536356] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.536376] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.536397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.536468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.536529] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.536555] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.536581] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.536624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.536651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.536677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.536703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.536727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.536753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.536781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.536807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.536833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.536857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.536881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.536909] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.536934] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.538946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.538964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.538978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.538993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.540517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.540535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.540550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.542047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.542063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.543873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.546827] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.546881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.546896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.546916] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.563653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.563679] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.563714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.563817] [drm:drm_mode_addfb2] [FB:78]
>[ 1382.563884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.580322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.580348] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.580387] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.599257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.599276] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.599297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.599314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.599332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.599347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.599361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.599378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.599395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.599457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.599487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.599515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.599539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.599563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.599608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.599642] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.599674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.599700] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.599820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.599837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.599914] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.599942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.599970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.600000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.600023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.600056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.600080] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.600103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.600126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.600147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.600168] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.600173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.600194] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.600199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.600220] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.600241] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.600261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.600282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.600305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.600325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.600346] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.600366] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.600386] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.600409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.600455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.600523] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.600545] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.600568] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.600607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.600630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.600652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.600672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.600693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.600715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.600739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.600762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.600786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.600806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.600827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.600851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.600873] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.602894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.602918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.602940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.602963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.604487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.604509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.604530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.606044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.606063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.607877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.610827] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.610886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.610903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.610929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.627629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.627654] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.627689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.627792] [drm:drm_mode_addfb2] [FB:79]
>[ 1382.627859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.644330] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.644354] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.644400] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.663267] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.663286] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.663306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.663323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.663341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.663356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.663371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.663387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.663405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.663466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.663494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.663522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.663545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.663566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.663608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.663643] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.663675] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.663700] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.663806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.663823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.663900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.663928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.663956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.663987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.664012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.664039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.664066] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.664091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.664116] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.664140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.664161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.664168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.664190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.664196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.664219] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.664243] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.664264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.664287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.664313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.664336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.664358] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.664381] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.664404] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.664465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.664492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.664560] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.664582] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.664605] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.664643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.664666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.664688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.664710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.664731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.664754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.664778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.664802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.664826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.664847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.664868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.664893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.664916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.666935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.666952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.666966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.666981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.668502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.668518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.668532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.670025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.670041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.671847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.674778] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.674804] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.674820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.674843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.691549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.691574] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.691609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.691710] [drm:drm_mode_addfb2] [FB:75]
>[ 1382.691767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.708228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.708253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.708298] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.727144] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.727163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.727183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.727200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.727217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.727232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.727247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.727263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.727281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.727297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.727313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.727328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.727342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.727356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.727383] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.727405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.727472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.727499] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.727599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.727613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.727682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.727705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.727732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.727761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.727784] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.727810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.727833] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.727857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.727880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.727903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.727924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.727930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.727951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.727957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.727980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.728000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.728030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.728049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.728072] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.728091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.728111] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.728130] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.728150] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.728172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.728196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.728257] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.728279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.728301] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.728338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.728358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.728380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.728399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.728420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.728463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.728488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.728512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.728536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.728556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.728578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.728604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.728625] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.730614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.730630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.730643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.730659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.732163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.732178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.732192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.733689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.733705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.735508] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.738440] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.738516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.738533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.738555] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.755255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.755280] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.755315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.755451] [drm:drm_mode_addfb2] [FB:78]
>[ 1382.755550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.771940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.771964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.772009] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.790892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.790911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.790931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.790948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.790966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.790981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.790996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.791015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.791037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.791058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.791078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.791099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.791118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.791137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.791166] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.791188] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.791213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.791230] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.791344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.791354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.791401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.791420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.791483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.791520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.791545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.791573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.791599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.791624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.791648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.791672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.791695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.791702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.791724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.791730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.791753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.791776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.791799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.791822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.791848] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.791870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.791893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.791915] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.791938] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.791964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.791990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.792059] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.792080] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.792102] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.792141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.792164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.792188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.792210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.792233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.792255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.792280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.792304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.792329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.792351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.792373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.792399] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.792423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.794454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.794470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.794485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.794499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.796008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.796026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.796043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.797547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.797563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.799384] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.802316] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.802395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.802411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.802480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.819136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.819163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.819200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.819295] [drm:drm_mode_addfb2] [FB:79]
>[ 1382.819366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.835817] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.835841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.835878] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.854724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.854742] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.854763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.854780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.854798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.854813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.854828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.854845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.854863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.854879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.854895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.854911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.854925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.854939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.854966] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.854987] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.855008] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.855024] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.855138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.855148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.855195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.855214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.855234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.855255] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.855271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.855291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.855312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.855332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.855353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.855373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.855393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.855397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.855417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.855459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.855488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.855517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.855543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.855569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.855596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.855622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.855647] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.855671] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.855696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.855724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.855752] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.855826] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.855851] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.855875] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.855916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.855941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.855965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.855989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.856018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.856041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.856065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.856087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.856111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.856132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.856153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.856178] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.856201] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.858202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.858219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.858234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.858249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.859757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.859772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.859786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.861279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.861297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.863105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.866024] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.866063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.866082] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.866108] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.882805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.882831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.882866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.882956] [drm:drm_mode_addfb2] [FB:75]
>[ 1382.883024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.899477] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.899499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.899533] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.918383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.918401] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.918421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.918481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.918511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.918535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.918559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.918582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.918610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.918636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.918662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.918688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.918708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.918731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.918775] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.918808] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.918840] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.918865] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.918984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.918994] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.919042] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.919061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.919081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.919102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.919122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.919143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.919163] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.919184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.919204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.919224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.919244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.919248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.919268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.919272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.919292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.919313] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.919333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.919353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.919373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.919393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.919414] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.919434] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.919498] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.919535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.919562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.919630] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.919654] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.919677] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.919715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.919739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.919762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.919783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.919805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.919827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.919853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.919877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.919900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.919922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.919941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.919966] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.919989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.921992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.922009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.922023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.922038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.923557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.923575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.923590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.925087] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.925103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.926931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.929871] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.929940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.929957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.929979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1382.946683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.946709] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.946746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.946838] [drm:drm_mode_addfb2] [FB:78]
>[ 1382.946909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.963356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1382.963379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1382.963425] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1382.982287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1382.982306] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1382.982326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.982343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.982361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.982377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.982392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.982408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1382.982426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.982489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.982517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.982544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.982566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.982590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.982632] [drm:intel_power_well_disable [i915]] disabling display
>[ 1382.982667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1382.982701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1382.982727] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1382.982846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1382.982863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1382.982942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1382.982967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1382.982993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1382.983020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1382.983042] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1382.983066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1382.983091] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1382.983114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1382.983137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1382.983158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1382.983180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1382.983185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.983206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1382.983212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1382.983233] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1382.983254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1382.983275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1382.983294] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1382.983317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1382.983338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1382.983358] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1382.983379] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1382.983398] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1382.983421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1382.983480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1382.983547] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1382.983570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1382.983593] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1382.983631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1382.983654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1382.983676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1382.983698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1382.983720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1382.983744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1382.983768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1382.983792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1382.983815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1382.983837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1382.983858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1382.983883] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1382.983906] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1382.985908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1382.985926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1382.985940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.985955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1382.987494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1382.987509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1382.987523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1382.989016] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1382.989032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1382.990840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1382.993784] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1382.993849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1382.993866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1382.993888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.010592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.010618] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.010655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.010751] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.010813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.027292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.027319] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.027365] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.046208] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.046227] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.046247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.046263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.046281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.046296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.046311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.046327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.046345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.046361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.046377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.046392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.046406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.046420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.046490] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.046525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.046558] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.046584] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.046687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.046703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.046778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.046806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.046834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.046864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.046889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.046915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.046941] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.046967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.046992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.047016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.047039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.047045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.047068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.047074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.047097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.047121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.047144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.047166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.047190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.047213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.047236] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.047259] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.047280] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.047305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.047332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.047407] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.047438] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.047483] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.047523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.047547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.047570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.047594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.047616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.047640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.047665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.047690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.047714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.047735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.047757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.047783] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.047805] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.049804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.049821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.049835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.049850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.051384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.051399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.051413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.052908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.052926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.054730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.057671] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.057741] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.057760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.057786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.074477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.074502] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.074535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.074627] [drm:drm_mode_addfb2] [FB:75]
>[ 1383.074690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.091191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.091217] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.091264] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.110122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.110141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.110162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.110179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.110197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.110212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.110227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.110244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.110261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.110277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.110293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.110313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.110332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.110351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.110380] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.110402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.110427] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.110486] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.110598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.110613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.110683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.110708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.110735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.110764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.110786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.110811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.110835] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.110860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.110882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.110905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.110926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.110932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.110961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.110966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.110987] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.111007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.111027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.111046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.111069] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.111088] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.111108] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.111127] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.111148] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.111170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.111194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.111246] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.111267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.111289] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.111325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.111346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.111367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.111387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.111407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.111427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.111470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.111495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.111519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.111539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.111560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.111587] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.111608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.113597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.113613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.113627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.113641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.115144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.115159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.115173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.116670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.116686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.118489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.121420] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.121485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.121512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.121547] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.138190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.138216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.138251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.138348] [drm:drm_mode_addfb2] [FB:78]
>[ 1383.138413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.154871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.154896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.154935] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.173780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.173800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.173820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.173837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.173855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.173871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.173886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.173902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.173920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.173936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.173952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.173972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.173991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.174010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.174038] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.174061] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.174086] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.174102] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.174215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.174225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.174272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.174292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.174313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.174339] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.174366] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.174393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.174418] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.174442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.174502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.174526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.174548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.174555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.174578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.174584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.174607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.174630] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.174652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.174674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.174700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.174722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.174744] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.174766] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.174789] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.174815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.174842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.175151] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.175175] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.175197] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.175240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.175264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.175288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.175310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.175325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.175341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.175358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.175374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.175389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.175403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.175425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.175444] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.175474] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.177453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.177480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.177495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.177509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.179017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.179033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.179046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.180547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.180563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.182394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.185318] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.185351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.185367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.185389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.202095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.202121] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.202156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.202256] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.202322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.218796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.218820] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.218857] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.237700] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.237719] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.237740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.237757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.237774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.237789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.237804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.237823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.237844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.237866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.237885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.237906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.237925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.237944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.237972] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.237995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.238019] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.238036] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.238152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.238162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.238209] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.238228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.238248] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.238269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.238285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.238303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.238321] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.238338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.238355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.238370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.238386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.238389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.238404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.238408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.238423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.238438] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.238496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.238518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.238546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.238568] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.238592] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.238613] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.238637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.238664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.238692] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.238765] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.239077] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.239101] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.239142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.239166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.239190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.239212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.239234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.239257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.239283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.239308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.239334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.239355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.239377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.239402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.239427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.241452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.241480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.241498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.241516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.243026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.243042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.243057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.244555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.244571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.246403] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.249335] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.249413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.249430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.249495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.266154] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.266180] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.266214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.266315] [drm:drm_mode_addfb2] [FB:75]
>[ 1383.266380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.282855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.282879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.282916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.301754] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.301773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.301793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.301810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.301828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.301843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.301858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.301875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.301892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.301909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.301925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.301940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.301959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.301978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.302006] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.302029] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.302054] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.302071] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.302188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.302198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.302245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.302265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.302285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.302306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.302322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.302340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.302358] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.302375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.302392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.302408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.302423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.302427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.302442] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.302481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.302507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.302529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.302553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.302575] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.302601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.302622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.302646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.302667] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.302690] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.302717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.302745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.302819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.303125] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.303149] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.303190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.303214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.303238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.303259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.303283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.303305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.303331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.303357] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.303382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.303403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.303432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.303455] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.303496] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.305616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.305634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.305648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.305663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.307166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.307181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.307195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.308690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.308706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.310510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.313440] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.313519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.313536] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.313558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.330261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.330286] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.330321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.330422] [drm:drm_mode_addfb2] [FB:78]
>[ 1383.330532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.346963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.346989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.347028] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.365882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.365901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.365921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.365939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.365956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.365972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.365987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.366003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.366021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.366037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.366053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.366069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.366083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.366097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.366124] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.366146] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.366167] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.366182] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.366288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.366298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.366345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.366364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.366384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.366405] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.366422] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.366440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.366458] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.366519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.366544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.366569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.366591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.366599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.366621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.366628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.366653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.366675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.366698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.366720] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.366746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.366768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.366792] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.366813] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.366838] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.366862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.366890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.366963] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.366988] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.367013] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.367056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.367081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.367105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.367129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.367153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.367177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.367205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.367229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.367255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.367277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.367299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.367324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.367348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.369361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.369380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.369397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.369415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.370924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.370941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.370958] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.372496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.372512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.374314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.377235] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.377271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.377288] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.377310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.394015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.394040] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.394075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.394178] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.394235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.410696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.410720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.410756] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.429610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.429629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.429649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.429666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.429683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.429698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.429713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.429729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.429747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.429764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.429780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.429796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.429810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.429824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.429851] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.429872] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.429893] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.429909] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.430023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.430033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.430080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.430101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.430122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.430146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.430166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.430187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.430207] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.430228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.430248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.430268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.430288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.430292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.430312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.430316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.430336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.430357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.430377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.430397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.430417] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.430437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.430458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.430523] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.430550] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.430579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.430608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.430682] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.430706] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.430730] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.430772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.430796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.430820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.430844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.430868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.430893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.430921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.430947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.430973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.430996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.431019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.431046] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.431071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.433086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.433103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.433118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.433133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.434641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.434657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.434671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.436163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.436179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.437985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.440917] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.440994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.441011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.441033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.457735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.457762] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.457800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.457903] [drm:drm_mode_addfb2] [FB:75]
>[ 1383.457970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.474437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.474461] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.474552] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.493227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.493245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.493265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.493282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.493300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.493315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.493330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.493346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.493364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.493380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.493396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.493412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.493426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.493440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.493515] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.493551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.493585] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.493611] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.493722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.493737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.493805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.493831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.493858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.493894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.493917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.493941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.493965] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.493988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.494010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.494032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.494054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.494060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.494080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.494086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.494108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.494129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.494151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.494172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.494196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.494217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.494236] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.494257] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.494278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.494302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.494327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.494388] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.494410] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.494432] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.494471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.494513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.494537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.494559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.494582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.494605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.494631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.494656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.494681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.494703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.494725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.494751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.494775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.496763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.496779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.496793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.496809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.498314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.498331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.498349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.499846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.499862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.501666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.504606] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.504675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.504692] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.504714] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.521417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.521442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.521524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.521648] [drm:drm_mode_addfb2] [FB:78]
>[ 1383.521712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.538098] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.538124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.538162] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.556601] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.556620] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.556640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.556657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.556674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.556690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.556704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.556721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.556738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.556755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.556771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.556786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.556800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.556814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.556841] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.556862] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.556883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.556898] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.557010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.557020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.557067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.557086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.557106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.557127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.557143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.557161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.557181] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.557202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.557222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.557243] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.557263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.557267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.557287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.557290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.557311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.557331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.557351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.557371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.557392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.557412] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.557432] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.557452] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.557472] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.557536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.557567] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.557642] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.557667] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.557691] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.557733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.558061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.558085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.558109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.558131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.558155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.558182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.558208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.558233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.558254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.558284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.558307] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.558330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.560326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.560343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.560358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.560372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.561880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.561898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.561915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.563420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.563437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.565243] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.568162] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.568200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.568216] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.568238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.584939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.584963] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.584996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.585094] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.585158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.601645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.601669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.601706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.620560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.620579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.620600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.620617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.620635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.620651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.620666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.620684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.620706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.620727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.620748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.620768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.620787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.620806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.620834] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.620857] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.620882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.620898] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.621014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.621024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.621071] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.621091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.621111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.621134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.621154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.621175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.621195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.621216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.621236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.621256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.621276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.621280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.621300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.621304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.621324] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.621344] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.621365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.621384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.621405] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.621425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.621445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.621465] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.621530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.621559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.621586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.621658] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.621683] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.621707] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.621750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.621776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.621801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.621824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.621848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.621880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.621906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.621931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.621955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.621977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.621999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.622018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.622034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.624024] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.624040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.624054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.624069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.625581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.625596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.625610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.627117] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.627135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.628942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.631882] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.631952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.631969] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.631997] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.648694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.648720] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.648756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.648860] [drm:drm_mode_addfb2] [FB:75]
>[ 1383.648929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.665395] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.665419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.665455] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.684338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.684357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.684378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.684398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.684420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.684440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.684459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.684478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.684547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.684578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.684607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.684635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.684659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.684685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.684729] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.684763] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.684796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.684822] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.684926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.684943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.685015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.685041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.685068] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.685097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.685120] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.685146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.685171] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.685195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.685218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.685240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.685261] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.685267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.685289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.685294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.685317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.685338] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.685360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.685381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.685413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.685432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.685453] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.685472] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.685524] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.685550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.685577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.685633] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.685657] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.685681] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.685718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.685743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.685765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.685786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.685806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.685829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.685854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.685878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.685902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.685922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.685942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.685965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.685989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.688006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.688023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.688038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.688053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.689585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.689602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.689617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.691113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.691129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.692942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.695887] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.695952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.695969] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.695991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.712692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.712718] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.712752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.712853] [drm:drm_mode_addfb2] [FB:78]
>[ 1383.712911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.729373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.729398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.729434] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.748280] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.748301] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.748323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.748343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.748364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.748384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.748404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.748423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.748444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.748464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.748530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.748561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.748587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.748612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.748657] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.748692] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.748726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.748752] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.748854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.748878] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.748946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.748969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.748994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.749021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.749043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.749066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.749088] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.749111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.749131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.749152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.749171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.749177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.749197] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.749202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.749223] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.749242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.749262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.749281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.749304] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.749323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.749343] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.749362] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.749382] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.749403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.749428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.749518] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.749541] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.749562] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.749600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.749621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.749643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.749663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.749685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.749706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.749730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.749754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.749777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.749796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.749816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.749841] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.749861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.751863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.751880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.751894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.751910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.753430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.753445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.753459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.754985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.755001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.756834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.759761] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.759791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.759807] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.759829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.776535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.776561] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.776596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.776695] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.776758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.793216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.793240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.793276] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.811133] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.811152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.811172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.811189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.811207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.811222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.811237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.811252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.811271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.811287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.811303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.811319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.811334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.811348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.811375] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.811398] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.811422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.811439] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.811553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.811695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.811745] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.811764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.811783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.811803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.811819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.811838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.811857] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.811877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.811897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.811916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.811935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.811940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.811959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.811963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.811982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.812002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.812022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.812041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.812061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.812080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.812100] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.812119] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.812139] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.812159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.812181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.812237] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.812251] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.812264] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.812292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.812308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.812322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.812336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.812350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.812365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.812382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.812397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.812411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.812425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.812438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.812454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.812469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.814509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.814526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.814540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.814555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.816061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.816077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.816090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.817591] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.817609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.819436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.822356] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.822393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.822417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.822437] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.839137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.839164] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.839201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.839303] [drm:drm_mode_addfb2] [FB:75]
>[ 1383.839369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.855816] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.855841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.855876] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.874725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.874744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.874764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.874781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.874799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.874815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.874829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.874846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.874863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.874880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.874896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.874912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.874926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.874944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.874972] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.874996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.875021] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.875037] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.875152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.875162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.875209] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.875229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.875249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.875269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.875288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.875309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.875329] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.875350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.875370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.875390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.875410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.875414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.875434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.875438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.875458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.875479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.875545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.875574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.875603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.875629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.875655] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.875680] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.875705] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.875733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.875762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.875835] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.875859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.875883] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.875925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.875950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.875975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.875999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.876023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.876047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.876074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.876100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.876126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.876149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.876172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.876199] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.876225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.878234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.878252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.878270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.878288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.879797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.879815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.879832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.881326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.881343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.883149] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.886081] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.886158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.886175] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.886197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.902901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.902927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.902965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.903067] [drm:drm_mode_addfb2] [FB:78]
>[ 1383.903136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.919581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.919605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.919641] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1383.938496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1383.938532] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1383.938552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.938569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.938587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.938602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.938617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.938633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.938651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.938672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.938692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.938713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.938732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.938751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.938779] [drm:intel_power_well_disable [i915]] disabling display
>[ 1383.938802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1383.938827] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.938843] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1383.938958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1383.938968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1383.939015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1383.939035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1383.939055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1383.939076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1383.939093] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1383.939111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1383.939130] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1383.939147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1383.939164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1383.939180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1383.939195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1383.939199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.939214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1383.939218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1383.939234] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1383.939249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1383.939264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1383.939283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1383.939304] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1383.939324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1383.939345] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1383.939365] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1383.939385] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1383.939406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.939428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1383.939479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1383.939538] [drm:intel_power_well_enable [i915]] enabling display
>[ 1383.939561] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1383.939606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1383.939634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1383.939660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1383.939685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1383.939710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1383.939736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1383.939765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1383.939792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1383.939819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.939844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1383.939868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1383.939897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1383.939922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1383.942267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1383.942283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1383.942297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.942312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1383.943823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1383.943838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1383.943851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1383.945356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1383.945374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1383.947182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1383.950101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1383.950139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1383.950155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1383.950177] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1383.966883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1383.966909] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1383.966944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1383.967044] [drm:drm_mode_addfb2] [FB:79]
>[ 1383.967111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1383.983583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1383.983608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1383.983644] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.002497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.002534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.002554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.002571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.002589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.002604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.002619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.002634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.002652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.002669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.002685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.002701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.002715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.002729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.002756] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.002778] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.002799] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.002815] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.002930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.002941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.002988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.003007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.003027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.003048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.003065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.003083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.003101] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.003119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.003135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.003151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.003167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.003170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.003186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.003189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.003205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.003220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.003234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.003249] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.003266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.003281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.003297] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.003311] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.003326] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.003346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.003369] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.003418] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.003435] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.003452] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.003483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.003547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.003572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.003599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.003625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.003652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.003681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.003708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.003736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.003760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.003784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.003813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.003838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.005849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.005867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.005882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.005897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.007400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.007416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.007429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.008926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.008941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.010744] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.013677] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.013753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.013777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.013797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.030496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.030539] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.030574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.030675] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.030733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.047177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.047201] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.047237] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.066106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.066125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.066145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.066162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.066179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.066194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.066209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.066225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.066243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.066259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.066274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.066290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.066304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.066318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.066344] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.066366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.066387] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.066403] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.066516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.066533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.066794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.066822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.066851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.066881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.066906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.066933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.066960] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.066985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.067010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.067035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.067058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.067065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.067088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.067094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.067118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.067141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.067165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.067195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.067219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.067240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.067260] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.067281] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.067302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.067326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.067351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.067420] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.067443] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.067466] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.067503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.067549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.067571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.067595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.067618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.067642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.067667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.067692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.067717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.067739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.067761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.067787] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.067811] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.070057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.070076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.070093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.070112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.071624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.071641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.071655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.073148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.073164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.074969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.077896] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.077926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.077942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.077964] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.094669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.094695] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.094729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.094827] [drm:drm_mode_addfb2] [FB:78]
>[ 1384.094891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.111350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.111375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.111411] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.130273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.130292] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.130312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.130329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.130347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.130362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.130376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.130392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.130410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.130426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.130442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.130458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.130472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.130486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.130559] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.130594] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.130627] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.130652] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.130765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.130779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.130847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.130871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.130897] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.130926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.130948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.130974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.130997] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.131021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.131043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.131066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.131086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.131092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.131114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.131119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.131142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.131163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.131185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.131205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.131230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.131250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.131273] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.131294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.131316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.131339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.131365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.131432] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.131456] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.131479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.131541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.131572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.131595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.131616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.131638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.131659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.131684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.131708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.131733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.131753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.131775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.131800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.131822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.134906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.134925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.134945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.134965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.136477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.136493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.136542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.138051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.138067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.139894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.142843] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.142903] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.142920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.142942] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.159647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.159674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.159711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.159812] [drm:drm_mode_addfb2] [FB:79]
>[ 1384.159880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.176327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.176353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.176390] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.195235] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.195254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.195275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.195292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.195309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.195324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.195339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.195355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.195373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.195389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.195405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.195420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.195434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.195453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.195481] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.195504] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.195574] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.195601] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.195715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.195729] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.195798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.195822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.195848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.195877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.195900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.195925] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.195948] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.195973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.195995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.196018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.196039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.196052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.196072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.196077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.196099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.196118] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.196138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.196157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.196180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.196199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.196220] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.196238] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.196259] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.196280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.196304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.196366] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.196388] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.196410] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.196447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.196468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.196489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.196509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.196546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.196568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.196594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.196618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.196643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.196663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.196684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.196710] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.196732] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.199818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.199837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.199853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.199869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.201380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.201396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.201409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.202907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.202923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.204730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.207673] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.207741] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.207760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.207786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.224482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.224508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.224593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.224733] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.224798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.241162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.241186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.241221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.259267] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.259285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.259306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.259322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.259340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.259355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.259370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.259385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.259403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.259420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.259440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.259460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.259480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.259499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.259572] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.259606] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.259641] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.259668] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.259780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.259795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.259863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.259887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.259914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.259943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.259966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.259992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.260016] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.260040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.260063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.260086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.260107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.260112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.260134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.260139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.260162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.260183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.260206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.260226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.260251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.260272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.260295] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.260316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.260338] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.260362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.260388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.260456] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.260480] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.260509] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.260563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.260585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.260608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.260628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.260650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.260672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.260697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.260721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.260745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.260765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.260787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.260810] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.260833] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.262823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.262841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.262858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.262876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.265448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.265466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.265482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.266978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.266994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.268799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.271730] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.271757] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.271776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.271808] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.288495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.288560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.288613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.288745] [drm:drm_mode_addfb2] [FB:78]
>[ 1384.288811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.305180] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.305204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.305240] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.324093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.324111] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.324132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.324149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.324167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.324182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.324197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.324214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.324231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.324248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.324264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.324280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.324295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.324309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.324335] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.324357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.324378] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.324394] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.324492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.324537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.324613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.324641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.324669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.324698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.324723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.324750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.324777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.324802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.324827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.324851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.324875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.324881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.324903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.324909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.324932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.324956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.324979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.325002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.325028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.325050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.325074] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.325096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.325119] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.325146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.325179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.325235] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.325258] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.325280] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.325317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.325340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.325363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.325385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.325406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.325427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.325451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.325475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.325499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.325539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.325560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.325586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.325610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.327607] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.327623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.327637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.327652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.329168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.329185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.329200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.330698] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.330715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.332543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.335474] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.335501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.335548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.335587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.352244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.352270] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.352304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.352404] [drm:drm_mode_addfb2] [FB:79]
>[ 1384.352461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.368945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.368969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.369006] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.387848] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.387867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.387887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.387904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.387922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.387937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.387952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.387968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.387986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.388002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.388018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.388034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.388048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.388062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.388089] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.388111] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.388132] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.388147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.388253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.388263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.388310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.388330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.388350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.388373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.388393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.388414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.388434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.388455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.388476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.388496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.388516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.388562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.388591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.388599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.388626] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.388652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.388678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.388702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.388730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.388754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.388780] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.388804] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.388828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.388856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.388885] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.388944] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.388968] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.388993] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.389034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.389059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.389083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.389107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.389130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.389155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.389182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.389208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.389234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.389256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.389278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.389306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.389331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.391345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.391364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.391381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.391400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.392912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.392928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.392942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.394468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.394485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.396291] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.399223] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.399300] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.399317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.399339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.416042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.416068] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.416103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.416205] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.416263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.432743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.432767] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.432803] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.451660] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.451679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.451699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.451715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.451733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.451748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.451762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.451778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.451795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.451811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.451827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.451843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.451857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.451870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.451897] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.451919] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.451940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.451956] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.452069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.452079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.452133] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.452153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.452174] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.452196] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.452216] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.452236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.452256] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.452276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.452296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.452315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.452334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.452338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.452358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.452361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.452381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.452401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.452420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.452440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.452459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.452479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.452498] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.452518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.452580] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.452610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.452639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.452697] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.452722] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.452746] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.452788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.452813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.452839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.452863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.452886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.452911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.452937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.452962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.452987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.453010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.453033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.453060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.453084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.455103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.455120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.455134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.455149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.456664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.456682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.456699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.458194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.458210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.460032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.462972] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.463040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.463056] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.463078] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.479784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.479810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.479845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.479944] [drm:drm_mode_addfb2] [FB:78]
>[ 1384.480008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.496464] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.496489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.496527] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.515405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.515424] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.515444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.515461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.515479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.515495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.515509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.515525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.515592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.515619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.515646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.515673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.515696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.515720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.515754] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.515777] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.515799] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.515814] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.515892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.515902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.515945] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.515965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.515985] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.516008] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.516027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.516048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.516068] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.516087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.516107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.516126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.516145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.516149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.516167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.516171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.516191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.516211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.516230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.516249] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.516268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.516288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.516308] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.516326] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.516347] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.516367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.516388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.516428] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.516443] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.516466] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.516494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.516511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.516532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.516575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.516596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.516618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.516641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.516665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.516688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.516707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.516728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.516753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.516774] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.518768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.518784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.518798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.518816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.520322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.520339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.520356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.521854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.521870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.524756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.527697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.527767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.527784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.527806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.544509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.544575] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.544627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.544727] [drm:drm_mode_addfb2] [FB:79]
>[ 1384.544790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.561189] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.561215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.561252] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.580108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.580127] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.580147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.580164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.580181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.580196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.580211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.580227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.580248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.580269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.580290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.580310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.580329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.580348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.580376] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.580399] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.580424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.580440] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.580568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.580585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.580661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.580690] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.580718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.580748] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.580772] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.580799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.580826] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.580859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.580882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.580904] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.580925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.580931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.580951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.580956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.580978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.580999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.581021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.581042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.581064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.581085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.581107] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.581128] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.581149] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.581174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.581199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.581269] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.581292] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.581314] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.581352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.581375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.581397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.581420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.581441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.581464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.581490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.581514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.581560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.581584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.581606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.581632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.581656] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.583652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.583668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.583682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.583696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.585211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.585228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.585243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.586742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.586758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.588562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.591480] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.591520] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.591570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.591611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.608264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.608290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.608324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.608426] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.608491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.624943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.624969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.625007] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.643858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.643877] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.643897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.643914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.643936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.643955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.643975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.643994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.644016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.644037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.644057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.644077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.644096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.644115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.644143] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.644166] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.644191] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.644208] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.644324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.644334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.644387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.644406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.644424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.644444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.644460] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.644478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.644495] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.644512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.644532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.644587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.644609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.644616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.644638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.644645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.644668] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.644691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.644714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.644737] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.644762] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.644785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.644808] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.644830] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.644853] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.644878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.644905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.644975] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.644998] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.645021] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.645059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.645082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.645105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.645125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.645146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.645167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.645192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.645217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.645241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.645263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.645285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.645310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.645334] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.647340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.647357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.647371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.647386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.648896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.648913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.648930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.650427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.650444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.652253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.655189] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.655263] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.655280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.655302] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.672032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.672058] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.672092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.672194] [drm:drm_mode_addfb2] [FB:78]
>[ 1384.672260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.688702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.688726] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.688764] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.706685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.706704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.706724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.706741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.706759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.706774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.706789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.706805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.706823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.706840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.706856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.706872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.706886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.706900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.706927] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.706949] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.706970] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.706985] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.707090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.707100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.707147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.707166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.707186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.707207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.707224] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.707242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.707261] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.707278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.707295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.707311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.707326] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.707330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.707345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.707349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.707364] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.707384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.707404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.707425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.707445] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.707465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.707486] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.707506] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.707526] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.707589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.707618] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.707679] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.707701] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.707723] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.707766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.707793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.707817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.707839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.707863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.707889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.707916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.707948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.707973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.707995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.708017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.708043] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.708068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.710068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.710085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.710099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.710114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.711718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.711737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.711754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.715403] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.715423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.717234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.720173] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.720243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.720259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.720280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.736986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.737013] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.737050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.737154] [drm:drm_mode_addfb2] [FB:79]
>[ 1384.737213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.753666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.753691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.753736] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.772589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.772608] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.772628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.772645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.772663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.772679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.772694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.772710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.772728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.772744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.772760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.772776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.772790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.772804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.772831] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.772853] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.772873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.772889] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.772995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.773005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.773052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.773073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.773094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.773118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.773138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.773159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.773179] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.773200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.773220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.773240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.773260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.773264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.773284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.773288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.773308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.773329] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.773349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.773369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.773389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.773409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.773429] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.773450] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.773470] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.773491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.773513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.773601] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.773626] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.773652] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.773695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.773723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.773749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.773775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.773800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.773827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.773855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.773882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.773909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.773933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.773958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.773986] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.774012] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.776021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.776038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.776053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.776068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.777610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.777626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.777640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.780228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.780248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.782056] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.784989] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.785066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.785083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.785105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.801809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.801835] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.801869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.801970] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.802035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.818488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.818513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.818596] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.837437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.837458] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.837480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.837500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.837522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.837541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.837602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.837628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.837660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.837688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.837714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.837740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.837761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.837784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.837828] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.837861] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.837894] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.837926] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.838026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.838036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.838079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.838095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.838112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.838130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.838145] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.838160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.838176] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.838190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.838205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.838218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.838231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.838234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.838247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.838250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.838264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.838277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.838290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.838302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.838317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.838330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.838343] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.838355] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.838367] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.838382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.838399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.838435] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.838449] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.838463] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.838491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.838509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.838527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.838544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.838604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.838630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.838657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.838683] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.838708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.838730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.838753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.838780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.838804] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.840805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.840822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.840836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.840850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.842366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.842384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.842398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.843897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.843913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.845719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.848665] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.848729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.848749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.848774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.865469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.865495] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.865529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.865710] [drm:drm_mode_addfb2] [FB:78]
>[ 1384.865780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.882171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.882196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.882242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.901100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.901119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.901139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.901159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.901181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.901200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.901220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.901239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.901261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.901282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.901302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.901323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.901342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.901361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.901389] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.901411] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.901437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.901453] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.901591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.901608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.901685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.901713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.901741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.901769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.901786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.901803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.901820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.901836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.901853] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.901868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.901883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.901887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.901901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.901905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.901920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.901934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.901949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.901963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.901979] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.901994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.902008] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.902022] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.902036] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.902053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.902071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.902107] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.902122] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.902137] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.902163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.902180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.902195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.902214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.902234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.902253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.902275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.902295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.902317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.902336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.902362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.902380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.902395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.904385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.904403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.904418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.904433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.905941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.905956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.905970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.907465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.907482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.909289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.912221] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.912299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.912316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.912338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.929041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.929067] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.929104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.929206] [drm:drm_mode_addfb2] [FB:79]
>[ 1384.929274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.945721] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1384.945746] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1384.945792] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1384.964638] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1384.964657] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1384.964677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.964694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.964712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.964728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.964743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.964759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.964777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.964794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.964810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.964826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.964840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.964854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.964880] [drm:intel_power_well_disable [i915]] disabling display
>[ 1384.964902] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1384.964923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.964939] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1384.965051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1384.965061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1384.965108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1384.965127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1384.965147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1384.965168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1384.965185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1384.965203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1384.965222] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1384.965239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1384.965255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1384.965271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1384.965287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1384.965291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.965306] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1384.965309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1384.965325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1384.965340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1384.965355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1384.965369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1384.965387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1384.965405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1384.965425] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1384.965445] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1384.965466] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1384.965487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1384.965509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1384.965551] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1384.965610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1384.965633] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1384.965676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1384.965701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1384.965724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1384.965747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1384.965769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1384.965792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1384.965818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1384.965843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1384.965868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.965889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1384.965911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1384.965937] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1384.965960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1384.967961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1384.967979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1384.967996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.968015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1384.969536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1384.969554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1384.969608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1384.971109] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1384.971125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1384.972978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1384.975900] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1384.975936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1384.975952] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1384.975981] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1384.992675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1384.992700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1384.992733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1384.992833] [drm:drm_mode_addfb2] [FB:75]
>[ 1384.992898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.009360] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.009385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.009430] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.028275] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.028294] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.028314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.028331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.028349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.028364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.028378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.028394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.028412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.028428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.028444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.028464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.028483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.028503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.028531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.028554] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.028626] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.028654] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.028772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.028786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.028856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.028882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.028910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.028940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.028965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.028991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.029017] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.029042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.029067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.029091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.029114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.029120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.029143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.029149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.029172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.029195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.029219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.029242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.029268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.029298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.029319] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.029338] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.029359] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.029381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.029406] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.029470] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.029492] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.029515] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.029553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.029594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.029616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.029639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.029661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.029685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.029711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.029736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.029760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.029782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.029804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.029830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.029853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.031844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.031862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.031879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.031898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.033403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.033419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.033433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.034930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.034946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.036749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.039684] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.039758] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.039775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.039798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.056501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.056526] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.056561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.056736] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.056793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.073181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.073206] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.073251] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.092123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.092142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.092162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.092180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.092198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.092213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.092228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.092244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.092262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.092279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.092294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.092310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.092325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.092339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.092366] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.092387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.092408] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.092424] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.092512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.092523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.092615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.092641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.092668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.092697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.092720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.092746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.092770] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.092801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.092824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.092846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.092867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.092873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.092892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.092898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.092920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.092941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.092962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.092983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.093007] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.093028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.093049] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.093070] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.093091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.093110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.093128] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.093167] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.093180] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.093193] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.093218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.093232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.093246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.093259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.093272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.093286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.093302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.093316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.093330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.093343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.093355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.093372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.093389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.095377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.095395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.095410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.095425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.096933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.096949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.096964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.098458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.098474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.100280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.103200] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.103238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.103254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.103276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.119982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.120008] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.120042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.120143] [drm:drm_mode_addfb2] [FB:79]
>[ 1385.120207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.136682] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.136708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.136755] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.155609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.155628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.155648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.155665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.155683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.155699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.155713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.155730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.155747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.155764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.155784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.155805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.155824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.155843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.155871] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.155894] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.155918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.155935] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.156043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.156053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.156099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.156117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.156136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.156158] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.156177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.156196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.156216] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.156235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.156254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.156273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.156291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.156295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.156314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.156318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.156337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.156356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.156375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.156394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.156413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.156432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.156451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.156470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.156489] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.156510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.156530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.156622] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.156648] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.156673] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.156717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.156742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.156768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.156791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.156816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.156839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.156867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.156895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.156922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.156944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.156968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.156996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.157030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.159038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.159056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.159070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.159085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.160618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.160634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.160647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.162143] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.162159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.163967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.166907] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.166978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.166997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.167023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.183715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.183739] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.183773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.183874] [drm:drm_mode_addfb2] [FB:75]
>[ 1385.183937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.200400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.200424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.200469] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.219348] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.219367] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.219387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.219404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.219421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.219437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.219451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.219467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.219485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.219501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.219517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.219533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.219547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.219561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.219639] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.219674] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.219707] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.219733] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.219847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.219861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.219931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.219957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.219984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.220014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.220038] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.220064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.220090] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.220115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.220140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.220163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.220186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.220192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.220215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.220221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.220245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.220268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.220291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.220312] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.220337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.220360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.220383] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.220404] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.220427] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.220452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.220480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.220556] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.220595] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.220619] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.220657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.220681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.220704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.220726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.220748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.220772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.220798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.220823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.220847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.220869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.220891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.220917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.220940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.222929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.222945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.222961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.222980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.224485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.224502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.224520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.226017] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.226034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.227840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.230772] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.230850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.230869] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.230895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.247607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.247633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.247668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.247765] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.247831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.264273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.264299] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.264345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.283219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.283238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.283259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.283276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.283293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.283308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.283323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.283339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.283356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.283372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.283388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.283404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.283418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.283432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.283459] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.283481] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.283502] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.283517] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.283630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.283647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.283723] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.283748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.283775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.283805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.283828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.283854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.283878] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.283902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.283925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.283948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.283969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.283975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.283996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.284001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.284024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.284045] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.284067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.284094] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.284117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.284136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.284157] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.284176] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.284196] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.284217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.284241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.284296] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.284318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.284340] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.284377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.284397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.284418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.284438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.284458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.284478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.284502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.284524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.284547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.284566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.284612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.284639] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.284660] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.286657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.286673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.286687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.286701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.288217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.288235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.288249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.289748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.289764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.291570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.294500] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.294538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.294555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.294619] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.311282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.311308] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.311342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.311442] [drm:drm_mode_addfb2] [FB:79]
>[ 1385.311508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.327962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.327986] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.328031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.346884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.346903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.346923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.346940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.346957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.346972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.346987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.347003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.347020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.347037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.347053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.347068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.347083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.347096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.347124] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.347147] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.347172] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.347188] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.347305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.347315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.347362] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.347381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.347401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.347425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.347445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.347466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.347487] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.347507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.347527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.347548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.347568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.347599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.347628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.347635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.347663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.347687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.347712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.347734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.347762] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.347784] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.347809] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.347831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.347854] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.347882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.347911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.347970] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.347994] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.348018] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.348059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.348082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.348105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.348127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.348149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.348172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.348197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.348223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.348248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.348269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.348291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.348318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.348341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.350344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.350361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.350375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.350390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.351897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.351912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.351926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.353418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.353434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.355240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.358159] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.358196] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.358213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.358235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.374920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.374944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.374978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.375092] [drm:drm_mode_addfb2] [FB:75]
>[ 1385.375158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.391642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.391666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.391712] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.409683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.409704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.409727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.409747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.409768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.409788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.409807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.409827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.409848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.409869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.409890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.409909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.409928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.409947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.409975] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.409998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.410023] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.410040] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.410149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.410159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.410206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.410226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.410246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.410269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.410289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.410310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.410330] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.410351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.410371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.410391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.410411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.410415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.410435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.410439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.410459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.410479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.410499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.410519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.410540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.410560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.410580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.410638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.410663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.410692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.410721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.410793] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.410818] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.410842] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.410884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.410907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.410932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.410955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.410978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.411001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.411027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.411053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.411079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.411100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.411123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.411150] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.411172] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.413179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.413196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.413210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.413225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.414752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.414770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.414785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.416281] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.416298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.418105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.421045] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.421114] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.421130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.421152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.437857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.437882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.437917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.438007] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.438068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.454537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.454561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.454645] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.473491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.473512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.473534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.473554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.473576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.473637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.473663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.473687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.473716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.473742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.473768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.473793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.473814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.473836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.473880] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.473915] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.473947] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.473972] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.474078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.474089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.474135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.474154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.474175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.474197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.474215] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.474235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.474255] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.474274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.474293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.474312] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.474331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.474335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.474354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.474357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.474377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.474396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.474415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.474433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.474453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.474471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.474490] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.474509] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.474528] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.474548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.474569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.474669] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.474694] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.474718] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.474761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.474784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.474809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.474831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.474854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.474877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.474903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.474929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.474954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.474975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.474998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.475025] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.475048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.478168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.478188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.478207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.478227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.480821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.480840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.480856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.483425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.483445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.486325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.489249] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.489283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.489299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.489320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.506047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.506073] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.506110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.506213] [drm:drm_mode_addfb2] [FB:79]
>[ 1385.506280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.522706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.522732] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.522778] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.541635] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.541654] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.541674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.541692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.541709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.541725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.541740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.541756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.541774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.541790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.541806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.541822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.541836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.541850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.541877] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.541898] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.541919] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.541935] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.542042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.542051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.542097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.542115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.542134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.542153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.542169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.542185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.542202] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.542218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.542233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.542247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.542262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.542265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.542279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.542283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.542297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.542315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.542335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.542353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.542372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.542391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.542411] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.542430] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.542448] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.542468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.542489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.542537] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.542552] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.542567] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.542638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.542664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.542689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.542712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.542736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.542760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.542787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.542815] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.542841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.542870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.542892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.542919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.542941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.546034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.546053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.546072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.546092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.548702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.548722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.548741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.551309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.551329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.554214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.557139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.557170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.557189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.557215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.573904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.573927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.573962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.574060] [drm:drm_mode_addfb2] [FB:75]
>[ 1385.574126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.590630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.590655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.590699] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.609554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.609572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.609593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.609634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.609654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.609675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.609695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.609716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.609739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.609761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.609782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.609802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.609821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.609840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.609868] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.609891] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.609916] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.609933] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.610030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.610046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.610112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.610131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.610149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.610169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.610185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.610201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.610219] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.610235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.610251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.610266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.610280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.610284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.610297] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.610301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.610323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.610336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.610348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.610365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.610383] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.610400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.610418] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.610436] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.610453] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.610472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.610490] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.610535] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.610549] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.610563] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.610590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.610646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.610669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.610692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.610713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.610735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.610761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.610784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.610809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.610829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.610850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.610876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.610898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.613997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.614016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.614032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.614048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.616643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.616671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.616696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.619268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.619287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.622196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.625119] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.625154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.625171] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.625193] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.641898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.641924] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.641959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.642064] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.642131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.658597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.658639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.658684] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.677538] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.677557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.677577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.677594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.677656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.677680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.677705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.677729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.677758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.677784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.677810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.677835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.677857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.677879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.677923] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.677958] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.677989] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.678015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.678133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.678143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.678191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.678212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.678233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.678257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.678277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.678298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.678318] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1385.678338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1385.678359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.678379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.678399] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.678403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.678423] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.678427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.678447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.678467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.678487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.678507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.678528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.678547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.678568] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1385.678588] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1385.678655] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1385.678686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.678716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1385.678792] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.679037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.679060] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.679099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.679123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.679146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.679168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.679190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.679213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.679238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.679262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.679286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.679307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.679329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.679354] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1385.679376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.682462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.682480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.682498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.682519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.685101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.685119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.685134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.687737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.687754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.690646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.693580] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1385.693665] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.693691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1385.693727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.710406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.710433] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.710470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.710576] [drm:drm_mode_addfb2] [FB:79]
>[ 1385.710707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.727097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1385.727121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.727159] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1385.746019] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1385.746038] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.746059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.746076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.746094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.746109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.746124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.746140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.746157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.746174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.746190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.746205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.746219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.746233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.746260] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.746282] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.746303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1385.746318] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.746545] [drm:drm_mode_addfb2] [FB:75]
>[ 1385.746570] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.769845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1385.769926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1385.769977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.770031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.770041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.770088] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.770105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.770123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.770141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.770155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.770171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.770186] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1385.770200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1385.770215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.770228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.770241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.770244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.770257] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.770260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.770273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.770286] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.770303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.770320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.770339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.770356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.770373] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1385.770391] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1385.770408] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1385.770426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.770446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1385.773073] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.773089] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.773104] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.773134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.773151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.773167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.773182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.773197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.773212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.773229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.773245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.773260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.773274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.773287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.773305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1385.773320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.775303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.775319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.775333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.775348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.776855] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.776870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.776883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.778376] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.778392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.780198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.783124] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1385.783156] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.783172] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1385.783194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.799901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.799927] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.799962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.816582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.816630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.833333] [drm:drm_mode_addfb2] [FB:79]
>[ 1385.833403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.849943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1385.849967] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.850004] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1385.868900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1385.868919] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.868940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.868957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.868975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.868990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.869005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.869021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.869039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.869055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.869071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.869086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.869101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.869114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.869141] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.869163] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.869184] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.869200] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.869313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.869323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.869370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.869390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.869410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.869433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.869453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.869474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.869495] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1385.869515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1385.869536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.869556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.869576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.869580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.869600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.869644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.869674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.869700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.869726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.869749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.869776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.869799] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.869823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1385.869845] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1385.869869] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1385.869896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.869924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1385.869983] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.870007] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.870031] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.870072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.870094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.870118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.870139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.870162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.870184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.870211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.870236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.870261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.870282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.870304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.870329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1385.870353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.872365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.872382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.872396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.872410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.873918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.873934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.873952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.875446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.875464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.877272] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.880196] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1385.880230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.880249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1385.880275] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.896972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.896999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.897034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.897134] [drm:drm_mode_addfb2] [FB:75]
>[ 1385.897200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.913654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1385.913680] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.913718] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1385.932570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1385.932589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.932609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.932671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.932700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.932725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.932749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.932775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.932795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.932813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.932829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.932846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.932860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.932875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.932902] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.932924] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.932946] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.932962] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.933042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.933052] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.933096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.933112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.933131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.933150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.933165] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.933183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.933200] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1385.933216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1385.933231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.933246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.933260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.933264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.933278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.933282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.933297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.933319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.933332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.933344] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.933360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.933373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.933387] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1385.933400] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1385.933413] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1385.933428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.933445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1385.933479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.933493] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.933506] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.933531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.933545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.933560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.933573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.933587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.933601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.933648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.933671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.933694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.933713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.933733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.933757] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1385.933778] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.935775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.935791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.935806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.935820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1385.937323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1385.937338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1385.937355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.938853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1385.938869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1385.940672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1385.943608] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1385.943682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1385.943699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1385.943721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1385.960424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.960450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.960485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.960583] [drm:drm_mode_addfb2] [FB:78]
>[ 1385.960711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.977104] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1385.977129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1385.977167] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1385.996027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1385.996046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1385.996067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.996083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.996101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.996117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.996132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.996148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1385.996166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.996182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.996198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.996214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.996228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.996242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.996269] [drm:intel_power_well_disable [i915]] disabling display
>[ 1385.996291] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1385.996312] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1385.996328] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1385.996435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1385.996445] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1385.996493] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1385.996512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1385.996533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1385.996557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1385.996577] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1385.996598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1385.996618] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1385.996673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1385.996698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1385.996721] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1385.996744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1385.996751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.996772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1385.996778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1385.996801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1385.996822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1385.996844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1385.996865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1385.996889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1385.996911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1385.996932] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1385.996954] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1385.996975] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1385.997000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1385.997026] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1385.997086] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1385.997108] [drm:intel_power_well_enable [i915]] enabling display
>[ 1385.997132] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1385.997174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1385.997199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1385.997223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1385.997248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1385.997272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1385.997297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1385.997324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1385.997350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1385.997376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1385.997394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1385.997413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1385.997434] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1385.997454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1385.999447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1385.999464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1385.999478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1385.999493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.001003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.001018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.001032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.002524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.002540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.004346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.007269] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.007303] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.007319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.007341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.024047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.024073] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.024108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.024209] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.024267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.040758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.040785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.040823] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.059663] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.059682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.059702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.059719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.059737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.059757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.059776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.059796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.059817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.059838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.059859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.059879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.059898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.059917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.059945] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.059968] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.059993] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.060009] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.060115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.060125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.060173] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.060194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.060215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.060238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.060258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.060279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.060300] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.060320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.060341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.060360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.060380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.060384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.060404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.060408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.060429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.060449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.060469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.060489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.060509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.060529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.060550] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.060571] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.060591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.060612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.060682] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.060741] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.060766] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.060791] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.060833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.060858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.060884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.060906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.060929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.060954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.060981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.061007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.061033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.061055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.061077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.061102] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.061126] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.063163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.063180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.063194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.063209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.064724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.064740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.064754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.066246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.066262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.068068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.071003] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.071079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.071098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.071124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.087820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.087846] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.087881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.087981] [drm:drm_mode_addfb2] [FB:75]
>[ 1386.088045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.104522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.104546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.104583] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.123450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.123468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.123489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.123505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.123523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.123542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.123562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.123581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.123603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.123624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.123688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.123718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.123741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.123764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.123807] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.123844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.123878] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.123904] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.123988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.123997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.124041] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.124058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.124076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.124096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.124111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.124129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.124146] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.124166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.124185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.124205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.124224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.124229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.124248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.124252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.124272] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.124291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.124310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.124329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.124349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.124368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.124388] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.124407] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.124426] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.124447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.124468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.124619] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.124666] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.124688] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.124731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.124755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.124785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.124805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.124826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.124847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.124871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.124894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.124916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.124936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.124956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.124981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.125004] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.126999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.127016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.127034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.127052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.128572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.128589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.128603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.130128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.130144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.131980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.134928] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.134990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.135006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.135035] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.151732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.151758] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.151793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.151892] [drm:drm_mode_addfb2] [FB:78]
>[ 1386.151957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.168431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.168455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.168493] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.187335] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.187354] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.187375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.187393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.187411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.187426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.187441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.187457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.187475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.187492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.187508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.187528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.187547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.187566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.187594] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.187618] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.187688] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.187713] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.187824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.187839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.187910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.187928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.187947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.187967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.187983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.188000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.188017] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.188032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.188048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.188067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.188086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.188090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.188110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.188115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.188133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.188152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.188172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.188191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.188211] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.188230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.188249] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.188269] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.188288] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.188314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.188333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.188375] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.188388] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.188401] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.188426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.188442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.188456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.188470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.188483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.188497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.188512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.188528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.188542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.188555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.188568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.188584] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.188599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.190594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.190611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.190625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.190674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.192185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.192201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.192218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.193729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.193745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.195570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.198501] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.198533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.198548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.198568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.215271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.215297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.215332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.215434] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.215501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.231951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.231976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.232012] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.250865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.250883] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.250903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.250920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.250941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.250961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.250980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.251000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.251022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.251043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.251063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.251083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.251102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.251121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.251149] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.251172] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.251196] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.251213] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.251329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.251339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.251386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.251406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.251426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.251447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.251464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.251482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.251502] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.251523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.251543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.251564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.251584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.251588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.251608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.251611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.251632] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.251693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.251717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.251741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.251768] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.251792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.251817] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.251839] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.251863] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.251888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.251916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.251976] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.252000] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.252025] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.252066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.252088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.252112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.252133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.252156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.252178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.252204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.252229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.252254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.252275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.252297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.252321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.252345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.254362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.254379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.254394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.254408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.255917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.255932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.255946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.257438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.257454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.259260] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.262183] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.262217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.262234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.262256] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.278962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.278989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.279027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.279128] [drm:drm_mode_addfb2] [FB:75]
>[ 1386.279196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.295664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.295686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.295721] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.314576] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.314595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.314615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.314632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.314695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.314720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.314744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.314770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.314800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.314820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.314837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.314852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.314867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.314885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.314913] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.314936] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.314961] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.314978] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.315059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.315069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.315114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.315131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.315149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.315169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.315185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.315202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.315219] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.315235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.315259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.315272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.315286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.315289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.315302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.315305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.315318] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.315336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.315354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.315371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.315389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.315407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.315424] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.315443] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.315461] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.315480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.315499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.315535] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.315549] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.315563] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.315591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.315609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.315630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.315675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.315698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.315720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.315746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.315769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.315792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.315811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.315831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.315855] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.315877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.317873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.317889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.317904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.317918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.319422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.319437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.319450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.320947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.320963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.322769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.325717] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.325779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.325796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.325818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.342522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.342548] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.342583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.342791] [drm:drm_mode_addfb2] [FB:78]
>[ 1386.342849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.359221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.359246] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.359283] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.378118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.378137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.378158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.378175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.378192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.378208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.378222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.378238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.378256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.378273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.378293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.378314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.378333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.378352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.378380] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.378403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.378428] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.378444] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.378535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.378546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.378600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.378621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.378644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.378699] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.378732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.378759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.378783] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.378808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.378830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.378853] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.378873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.378879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.378900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.378905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.378927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.378947] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.378970] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.378990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.379014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.379033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.379055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.379074] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.379095] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.379119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.379145] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.379202] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.379225] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.379247] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.379285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.379306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.379328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.379348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.379369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.379390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.379414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.379438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.379461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.379481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.379502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.379525] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.379548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.381558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.381575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.381593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.381611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.383140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.383156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.383170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.384695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.384711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.386513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.389437] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.389471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.389487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.389508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.406215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.406241] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.406276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.406376] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.406440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.422895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.422919] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.422956] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.441803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.441822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.441843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.441860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.441877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.441892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.441908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.441923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.441943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.441964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.441984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.442004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.442023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.442042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.442070] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.442093] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.442118] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.442134] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.442250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.442260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.442307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.442326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.442346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.442367] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.442384] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.442402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.442420] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.442437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.442453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.442469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.442484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.442487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.442502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.442506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.442521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.442536] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.442551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.442566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.442583] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.442598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.442618] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.442638] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.442698] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.442723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.442752] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.442812] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.442837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.442861] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.442903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.442926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.442950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.442973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.442997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.443020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.443046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.443078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.443102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.443122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.443143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.443168] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.443190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.445203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.445221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.445238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.445257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.446779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.446796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.446811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.448309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.448325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.450152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.453108] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.453161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.453178] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.453201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.469912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.469938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.469973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.470075] [drm:drm_mode_addfb2] [FB:75]
>[ 1386.470139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.486602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.486627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.486709] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.505409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.505427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.505448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.505465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.505482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.505498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.505513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.505529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.505547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.505563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.505579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.505594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.505609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.505622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.505693] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.505729] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.505764] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.505790] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.505904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.505919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.505989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.506012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.506038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.506068] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.506091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.506116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.506140] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.506164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.506187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.506209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.506230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.506236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.506257] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.506262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.506285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.506306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.506328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.506349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.506374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.506395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.506417] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.506438] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.506460] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.506483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.506509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.506581] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.506603] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.506624] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.506686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.506710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.506731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.506754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.506774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.506797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.506822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.506846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.506871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.506891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.506913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.506938] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.506960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.508964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.508982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.508996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.509011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.510519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.510535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.510549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.512045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.512061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.513865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.516805] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.516875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.516892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.516914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.533616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.533642] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.533731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.533855] [drm:drm_mode_addfb2] [FB:78]
>[ 1386.533920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.550318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.550342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.550378] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.568360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.568379] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.568399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.568416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.568433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.568448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.568463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.568479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.568497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.568514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.568529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.568545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.568559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.568573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.568600] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.568622] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.568643] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.568702] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.568816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.568830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.568901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.568929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.568950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.568973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.568993] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.569013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.569040] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.569057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.569072] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.569085] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.569098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.569102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.569115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.569119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.569132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.569145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.569158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.569171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.569186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.569199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.569213] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.569226] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.569239] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.569254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.569271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.569313] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.569326] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.569339] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.569364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.569378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.569393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.569406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.569420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.569434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.569450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.569464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.569479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.569491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.569505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.569520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.569536] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.571508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.571524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.571538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.571552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.573062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.573077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.573091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.574599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.574615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.576422] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.579347] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.579381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.579400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.579426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.596123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.596149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.596184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.596282] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.596348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.612803] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.612827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.612863] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.631718] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.631737] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.631758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.631778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.631800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.631820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.631840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.631859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.631880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.631901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.631922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.631941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.631960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.631979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.632007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.632030] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.632054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.632071] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.632188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.632198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.632245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.632265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.632284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.632305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.632322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.632340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.632360] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.632381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.632401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.632422] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.632442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.632445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.632465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.632469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.632489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.632510] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.632530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.632550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.632570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.632590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.632611] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.632631] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.632651] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.632712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.632743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.632816] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.632841] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.632865] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.632908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.632932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.632957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.632980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.633004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.633027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.633053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.633079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.633105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.633126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.633148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.633175] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.633198] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.635213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.635232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.635249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.635268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.636782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.636799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.636817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.638314] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.638331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.640159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.643118] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.643169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.643186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.643208] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.659918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.659945] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.659979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.660072] [drm:drm_mode_addfb2] [FB:75]
>[ 1386.660131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.676597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.676621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.676657] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.695550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.695569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.695590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.695607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.695625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.695640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.695655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.695716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.695746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.695770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.695787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.695803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.695817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.695831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.695858] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.695880] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.695901] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.695917] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.695989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.695999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.696048] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.696063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.696080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.696098] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.696112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.696128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.696143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.696158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.696172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.696185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.696198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.696201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.696214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.696218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.696231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.696244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.696257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.696269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.696284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.696298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.696311] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.696323] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.696336] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.696352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.696368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.696412] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.696425] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.696438] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.696463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.696477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.696491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.696504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.696517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.696531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.696547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.696561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.696576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.696589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.696602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.696618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.696632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.698641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.698660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.698705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.698731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.700245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.700260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.700274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.701773] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.701789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.703608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.706543] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.706617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.706635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.706657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.723359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.723385] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.723420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.723521] [drm:drm_mode_addfb2] [FB:78]
>[ 1386.723579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.740039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.740064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.740101] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.758948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.758966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.758987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.759003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.759024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.759044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.759064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.759083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.759105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.759126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.759147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.759166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.759185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.759204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.759232] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.759254] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.759279] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.759295] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.759409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.759419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.759466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.759486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.759506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.759528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.759548] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.759569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.759589] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.759609] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.759630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.759650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.759716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.759723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.759747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.759755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.759780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.759804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.759829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.759852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.759879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.759901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.759926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.759948] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.759971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.759999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.760028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.760092] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.760116] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.760141] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.760181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.760204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.760228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.760249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.760272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.760294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.760321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.760345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.760370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.760391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.760413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.760438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.760462] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.762477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.762495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.762509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.762524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.764034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.764049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.764063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.765556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.765572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.767378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.770302] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.770337] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.770356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.770382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.787079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.787105] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.787141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.787239] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.787303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.803758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.803782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.803818] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.822669] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.822706] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.822726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.822746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.822768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.822788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.822807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.822826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.822848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.822869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.822890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.822909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.822928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.822947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.822975] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.822999] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.823023] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.823040] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.823154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.823165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.823212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.823232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.823251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.823275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.823295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.823316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.823337] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.823358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.823378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.823398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.823418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.823422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.823442] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.823446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.823467] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.823487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.823507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.823527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.823547] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.823567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.823588] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.823608] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.823628] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.823649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.823712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.823771] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.823796] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.823821] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.823864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.823889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.823915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.823938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.823963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.823987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.824014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.824041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.824073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.824093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.824115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.824139] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.824161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.826166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.826184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.826198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.826213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.827737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.827753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.827766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.829261] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.829277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.831084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.834027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.834093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.834110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.834132] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.850836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.850861] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.850897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.850995] [drm:drm_mode_addfb2] [FB:75]
>[ 1386.851059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.867515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.867541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.867579] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.886439] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.886459] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.886478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.886495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.886513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.886528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.886543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.886559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.886576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.886592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.886607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.886623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.886637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.886651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.886726] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.886762] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.886795] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.886821] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.886935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.886949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.887017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.887043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.887071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.887101] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.887125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.887152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.887177] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.887202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.887227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.887250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.887274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.887280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.887303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.887308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.887332] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.887355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.887379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.887403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.887429] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.887451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.887475] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.887496] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.887519] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.887544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.887571] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.887644] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.887666] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.887708] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.887748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.887772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.887795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.887818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.887840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.887863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.887890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.887914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.887939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.887960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.887983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.888008] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.888031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.890022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.890038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.890051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.890066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.891569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.891584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.891597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.893093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.893109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.894913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.897857] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.897922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.897940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.897965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.914664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.914707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.914742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.914842] [drm:drm_mode_addfb2] [FB:78]
>[ 1386.914908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.931366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.931390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.931428] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1386.950269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1386.950290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1386.950312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.950332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.950354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.950373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.950393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.950412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.950434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.950455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.950475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.950495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.950514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.950533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.950561] [drm:intel_power_well_disable [i915]] disabling display
>[ 1386.950583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1386.950608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.950625] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1386.950742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1386.950759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1386.950837] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1386.950865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1386.950894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1386.950925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1386.950946] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1386.950964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1386.950982] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1386.950999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1386.951014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1386.951030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1386.951048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1386.951052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.951071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1386.951075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1386.951095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1386.951115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1386.951135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1386.951161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1386.951179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1386.951196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1386.951210] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1386.951225] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1386.951238] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1386.951254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.951271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1386.951309] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1386.951322] [drm:intel_power_well_enable [i915]] enabling display
>[ 1386.951335] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1386.951361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1386.951375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1386.951389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1386.951403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1386.951416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1386.951430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1386.951446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1386.951461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1386.951475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.951489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1386.951501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1386.951518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1386.951532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1386.953521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1386.953539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1386.953554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.953569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1386.955077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1386.955092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1386.955106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1386.956625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1386.956641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1386.958448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1386.961359] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1386.961405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1386.961423] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1386.961447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1386.978149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1386.978175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1386.978210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1386.978310] [drm:drm_mode_addfb2] [FB:79]
>[ 1386.978376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1386.994829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1386.994853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1386.994888] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.013076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.013094] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.013114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.013131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.013149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.013164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.013179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.013195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.013213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.013230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.013245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.013261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.013275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.013289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.013316] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.013338] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.013362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.013379] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.013495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.013505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.013551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.013570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.013589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.013609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.013625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.013643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.013660] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.013677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.013731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.013755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.013776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.013784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.013806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.013813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.013836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.013858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.013881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.013902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.013927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.013948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.013972] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.013993] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.014016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.014039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.014066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.014125] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.014148] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.014172] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.014212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.014234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.014257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.014279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.014301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.014322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.014347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.014372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.014396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.014417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.014438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.014462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.014493] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.016494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.016510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.016524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.016539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.018059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.018077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.018094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.019592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.019609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.021416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.024352] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.024425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.024442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.024464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.041169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.041195] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.041230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.041328] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.041386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.057869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.057895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.057934] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.076788] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.076807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.076827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.076844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.076862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.076877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.076892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.076908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.076926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.076946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.076967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.076988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.077007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.077026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.077054] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.077077] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.077102] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.077118] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.077225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.077235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.077282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.077302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.077321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.077345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.077365] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.077386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.077407] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.077427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.077447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.077468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.077487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.077491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.077511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.077515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.077535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.077555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.077575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.077595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.077615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.077635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.077656] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.077676] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.077738] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.077765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.077795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.077868] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.077893] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.077917] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.077959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.077982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.078007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.078030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.078055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.078078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.078110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.078134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.078158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.078177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.078198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.078222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.078244] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.080246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.080264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.080278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.080293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.081821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.081839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.081853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.083351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.083367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.085186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.088127] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.088194] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.088211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.088236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.104938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.104964] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.105000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.105094] [drm:drm_mode_addfb2] [FB:78]
>[ 1387.105163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.121617] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.121642] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.121677] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.140557] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.140576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.140597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.140613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.140631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.140646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.140661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.140677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.140743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.140772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.140800] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.140828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.140850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.140874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.140918] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.140955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.140988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.141014] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.141126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.141138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.141188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.141206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.141225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.141247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.141266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.141286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.141305] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.141324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.141344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.141363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.141381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.141385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.141404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.141407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.141427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.141445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.141464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.141483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.141502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.141521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.141540] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.141559] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.141578] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.141605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.141623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.141667] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.141681] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.141726] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.141765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.141788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.141811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.141832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.141854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.141876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.141901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.141926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.141951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.141971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.141992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.142018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.142040] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.144038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.144056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.144074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.144092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.145598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.145615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.145632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.147130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.147147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.148952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.151896] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.151962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.151979] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.152001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.168720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.168746] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.168782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.168880] [drm:drm_mode_addfb2] [FB:79]
>[ 1387.168944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.185384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.185408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.185444] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.204293] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.204313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.204333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.204350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.204368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.204383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.204398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.204414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.204432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.204448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.204464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.204481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.204495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.204509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.204536] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.204559] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.204584] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.204601] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.204728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.204744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.204816] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.204835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.204854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.204876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.204895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.204916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.204936] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.204962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.204978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.204992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.205006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.205010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.205023] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.205027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.205040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.205053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.205066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.205079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.205094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.205107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.205120] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.205132] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.205145] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.205161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.205177] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.205223] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.205237] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.205250] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.205275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.205290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.205303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.205317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.205329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.205347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.205367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.205386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.205405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.205424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.205440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.205459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.205477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.207473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.207492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.207509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.207527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.209038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.209054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.209069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.210565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.210582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.212389] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.215314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.215347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.215363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.215385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.232091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.232117] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.232152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.232251] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.232317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.248771] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.248796] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.248832] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.267620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.267639] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.267661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.267681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.267749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.267778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.267804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.267831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.267861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.267887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.267913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.267939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.267962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.267982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.268025] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.268060] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.268092] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.268118] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.268226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.268236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.268282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.268300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.268319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.268341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.268360] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.268380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.268399] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.268426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.268443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.268458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.268472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.268475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.268489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.268492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.268506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.268519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.268532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.268545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.268560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.268573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.268585] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.268598] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.268610] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.268626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.268642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.268676] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.268727] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.268748] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.268786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.268807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.268827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.268847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.268867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.268887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.268911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.268933] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.268956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.268975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.268995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.269018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.269039] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.271046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.271063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.271078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.271093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.272600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.272618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.272635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.274134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.274151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.275957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.278906] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.278966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.278983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.279005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.295724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.295751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.295786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.295884] [drm:drm_mode_addfb2] [FB:78]
>[ 1387.295950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.312388] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.312412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.312449] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.331297] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.331316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.331336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.331353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.331371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.331386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.331402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.331418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.331436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.331452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.331468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.331484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.331499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.331512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.331539] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.331561] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.331582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.331598] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.331718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.331735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.331811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.331836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.331864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.331893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.331916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.331949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.331971] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.331994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.332014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.332036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.332055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.332060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.332080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.332085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.332106] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.332126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.332146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.332165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.332188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.332207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.332228] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.332247] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.332267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.332288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.332312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.332365] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.332388] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.332409] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.332446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.332467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.332489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.332508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.332528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.332549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.332572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.332595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.332618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.332637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.332657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.332682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.332722] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.334721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.334737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.334751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.334766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.336275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.336291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.336304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.337807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.337823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.339648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.342582] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.342658] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.342675] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.342740] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.359400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.359426] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.359462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.359553] [drm:drm_mode_addfb2] [FB:79]
>[ 1387.359613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.376081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.376105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.376141] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.394982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.395001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.395021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.395038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.395056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.395071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.395086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.395103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.395120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.395137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.395153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.395168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.395182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.395196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.395223] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.395245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.395265] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.395281] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.395387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.395398] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.395445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.395465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.395484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.395505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.395521] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.395540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.395558] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.395575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.395592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.395608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.395623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.395627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.395642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.395645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.395661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.395676] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.395691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.395739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.395767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.395789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.395812] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.395836] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.395857] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.395884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.395912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.395986] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.396010] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.396034] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.396075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.396098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.396121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.396142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.396166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.396188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.396214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.396239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.396265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.396285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.396315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.396337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.396359] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.398370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.398388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.398405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.398424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.399935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.399952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.399966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.401458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.401474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.403280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.406216] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.406290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.406306] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.406328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.423033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.423060] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.423095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.423187] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.423253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.439734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.439757] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.439792] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.458643] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.458662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.458682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.458699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.458765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.458791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.458815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.458841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.458870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.458897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.458923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.458949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.458972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.458995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.459039] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.459076] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.459109] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.459135] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.459243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.459253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.459298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.459317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.459336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.459356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.459371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.459388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.459405] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.459421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.459436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.459455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.459473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.459477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.459496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.459500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.459520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.459539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.459558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.459577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.459596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.459614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.459634] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.459652] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.459671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.459692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.459758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.459837] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.459859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.459881] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.459922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.459947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.459969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.459992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.460014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.460038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.460063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.460087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.460112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.460133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.460150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.460166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.460184] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.462186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.462203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.462218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.462233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.463770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.463785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.463799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.465295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.465311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.467117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.470072] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.470126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.470142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.470163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.486869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.486895] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.486931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.487029] [drm:drm_mode_addfb2] [FB:78]
>[ 1387.487093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.503570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.503594] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.503631] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.522177] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.522196] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.522216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.522232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.522250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.522265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.522280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.522296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.522314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.522330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.522350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.522371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.522390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.522409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.522437] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.522460] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.522484] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.522501] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.522617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.522627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.522674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.522694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.522754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.522784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.522807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.522836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.522861] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.522887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.522911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.522935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.522957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.522965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.522987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.522993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.523017] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.523039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.523063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.523084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.523110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.523132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.523155] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.523177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.523200] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.523485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.523511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.523578] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.523601] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.523621] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.523660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.523683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.523704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.523746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.523767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.523791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.523817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.523843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.523867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.524037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.524057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.524082] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.524104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.526109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.526126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.526141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.526156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.527664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.527679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.527693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.529237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.529255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.531096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.534044] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.534105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.534122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.534144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.550848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.550874] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.550909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.551008] [drm:drm_mode_addfb2] [FB:79]
>[ 1387.551074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.567548] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.567574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.567611] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.586481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.586499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.586519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.586536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.586553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.586568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.586583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.586599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.586617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.586634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.586650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.586666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.586684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.586703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.586781] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.586817] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.586850] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.586884] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.586993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.587008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.587074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.587099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.587126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.587155] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.587179] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.587204] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.587230] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.587254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.587278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.587301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.587324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.587330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.587352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.587358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.587381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.587404] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.587426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.587448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.587473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.587495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.587515] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.587538] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.587560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.587585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.587611] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.587677] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.587700] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.587742] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.587785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.587810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.587835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.587860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.587891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.587915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.587941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.587965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.587990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.588012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.588034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.588060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.588084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.590074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.590090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.590104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.590118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.591622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.591637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.591651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.593149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.593164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.594969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.597901] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.597976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.597992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.598014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.614720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.614763] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.614801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.614904] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.614973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.631400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.631425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.631461] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.650315] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.650336] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.650358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.650378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.650400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.650419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.650439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.650458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.650480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.650501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.650521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.650541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.650560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.650579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.650607] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.650630] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.650655] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.650671] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.650798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.650813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.650884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.650908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.650937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.650966] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.650988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.651014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.651038] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.651062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.651085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.651108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.651129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.651135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.651156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.651162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.651185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.651206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.651229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.651249] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.651274] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.651302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.651323] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.651342] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.651363] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.651384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.651408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.651472] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.651494] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.651516] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.651552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.651573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.651594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.651614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.651635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.651655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.651678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.651701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.651742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.651763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.651783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.651809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.651830] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.653821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.653837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.653851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.653865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.655369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.655385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.655399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.656895] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.656911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.658712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.661657] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.661793] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.661811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.661834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.678475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.678501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.678536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.678634] [drm:drm_mode_addfb2] [FB:78]
>[ 1387.678692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.695177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.695201] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.695237] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.714081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.714100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.714120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.714137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.714154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.714170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.714185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.714201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.714218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.714235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.714250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.714266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.714280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.714298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.714326] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.714349] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.714375] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.714391] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.714500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.714510] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.714557] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.714576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.714596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.714618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.714638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.714659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.714680] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.714700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.714720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.714778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.714802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.714810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.714835] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.714842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.714867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.714892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.714917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.714941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.714968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.714992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.715017] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.715041] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.715065] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.715092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.715120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.715184] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.715209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.715234] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.715274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.715299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.715323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.715347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.715371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.715394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.715421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.715447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.715472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.715495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.715518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.715545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.715571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.717586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.717603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.717618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.717633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.719141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.719157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.719170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.720669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.720686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.722493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.725428] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.725503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.725520] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.725543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.742245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.742271] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.742308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.742412] [drm:drm_mode_addfb2] [FB:79]
>[ 1387.742472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.758946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.758971] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.759008] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.777849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.777868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.777888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.777905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.777923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.777943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.777962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.777982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.778003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.778024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.778045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.778065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.778084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.778103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.778131] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.778153] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.778178] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.778195] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.778309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.778319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.778366] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.778386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.778413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.778432] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.778447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.778465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.778482] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.778500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.778520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.778539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.778557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.778561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.778580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.778583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.778603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.778622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.778641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.778660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.778679] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.778698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.778717] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.778779] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.778807] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.778835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.778862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.778918] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.778942] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.778966] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.779005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.779031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.779054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.779077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.779100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.779125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.779151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.779175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.779200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.779222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.779244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.779270] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.779294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.781299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.781316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.781331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.781346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.782859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.782875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.782888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.784382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.784398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.786215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.789168] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.789224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.789241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.789263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.805968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.805994] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.806029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.806131] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.806196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.822667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.822692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.822729] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.841606] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.841625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.841645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.841662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.841680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.841695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.841710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.841726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.841788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.841816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.841843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.841870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.841891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.841915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.841959] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.841994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.842026] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.842051] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.842169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.842185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.842256] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.842284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.842312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.842342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.842367] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.842394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.842420] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.842445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.842471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.842494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.842516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.842522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.842544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.842550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.842573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.842596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.842618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.842640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.842666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.842690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.842711] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.842770] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.842794] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.842822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.842856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.842911] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.842933] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.842956] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.842994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.843017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.843040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.843062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.843084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.843106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.843131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.843154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.843178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.843200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.843220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.843245] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.843268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.845279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.845295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.845310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.845326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.846854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.846871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.846886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.848381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.848398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.850224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.853158] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.853234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.853253] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.853279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.869975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.870002] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.870040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.870143] [drm:drm_mode_addfb2] [FB:78]
>[ 1387.870211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.886677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.886702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.886777] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.905623] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.905642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.905662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.905679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.905697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.905713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.905727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.905787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.905817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.905845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.905872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.905897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.905921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.905942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.905985] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.906019] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.906051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.906076] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.906186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.906198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.906248] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.906266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.906285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.906312] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.906327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.906343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.906359] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.906374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.906388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.906402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.906415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.906419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.906431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.906434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.906448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.906461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.906474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.906486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.906502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.906515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.906527] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.906540] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.906557] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.906576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.906595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.906634] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.906648] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.906662] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.906690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.906709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.906727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.906778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.906801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.906824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.906848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.906871] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.906893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.906913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.906932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.906955] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.906977] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.908983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.909001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.909015] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.909031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.910535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.910551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.910565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.912063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.912080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.913886] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.916821] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.916894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.916911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.916933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.933637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.933664] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.933699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.933910] [drm:drm_mode_addfb2] [FB:79]
>[ 1387.933975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.950338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1387.950362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1387.950398] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1387.968884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1387.968903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1387.968924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.968944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.968966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.968986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.969005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.969024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.969046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.969067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.969087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.969107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.969126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.969145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.969173] [drm:intel_power_well_disable [i915]] disabling display
>[ 1387.969196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1387.969220] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.969237] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1387.969353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1387.969364] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1387.969410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1387.969430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1387.969450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1387.969471] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1387.969491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1387.969512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1387.969533] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1387.969553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1387.969574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1387.969594] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1387.969614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1387.969618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.969638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1387.969641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1387.969662] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1387.969682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1387.969702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1387.969722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1387.969787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1387.969813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1387.969840] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1387.969863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1387.969887] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1387.969915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1387.969944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1387.970002] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1387.970027] [drm:intel_power_well_enable [i915]] enabling display
>[ 1387.970051] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1387.970092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1387.970118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1387.970140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1387.970164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1387.970185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1387.970210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1387.970236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1387.970261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1387.970286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.970307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1387.970329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1387.970356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1387.970379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1387.972392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1387.972411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1387.972428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.972447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1387.973957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1387.973974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1387.973988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1387.975482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1387.975498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1387.977306] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1387.980230] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1387.980262] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1387.980279] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1387.980301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1387.997006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1387.997033] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1387.997071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1387.997173] [drm:drm_mode_addfb2] [FB:75]
>[ 1387.997242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.013706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.013731] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.013819] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.032499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.032518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.032538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.032557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.032579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.032599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.032618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.032638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.032659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.032680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.032701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.032721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.032740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.032804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.032849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.032877] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.032903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.032920] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.033004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.033018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.033083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.033101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.033121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.033143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.033162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.033183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.033203] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.033223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.033250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.033267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.033282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.033286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.033300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.033303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.033317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.033331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.033344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.033358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.033375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.033392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.033410] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.033428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.033446] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.033464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.033484] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.033519] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.033533] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.033548] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.033576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.033594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.033612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.033630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.033649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.033666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.033686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.033705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.033724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.033773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.033796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.033820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.033842] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.035839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.035856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.035870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.035885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.037389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.037404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.037418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.038917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.038933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.040742] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.043688] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.043804] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.043831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.043867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.060505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.060532] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.060567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.060666] [drm:drm_mode_addfb2] [FB:78]
>[ 1388.060723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.077185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.077210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.077255] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.096100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.096119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.096139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.096156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.096173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.096189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.096203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.096219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.096237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.096253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.096269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.096284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.096303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.096322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.096350] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.096373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.096398] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.096415] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.096522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.096532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.096579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.096599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.096618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.096639] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.096656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.096674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.096692] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.096709] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.096726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.096742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.096797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.096804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.096827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.096834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.096858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.096880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.096905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.096926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.096953] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.096975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.096998] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.097020] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.097044] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.097071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.097099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.097172] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.097196] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.097220] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.097260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.097283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.097307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.097328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.097350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.097372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.097399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.097424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.097449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.097470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.097492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.097516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.097541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.099557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.099574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.099589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.099604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.101113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.101128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.101142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.102634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.102650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.104457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.107391] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.107466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.107485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.107511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.124208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.124234] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.124269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.124371] [drm:drm_mode_addfb2] [FB:79]
>[ 1388.124436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.140889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.140915] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.140962] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.159821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.159840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.159860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.159877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.159894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.159909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.159924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.159940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.159961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.159982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.160003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.160023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.160042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.160061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.160089] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.160112] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.160137] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.160153] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.160265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.160275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.160321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.160340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.160359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.160379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.160395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.160413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.160433] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.160453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.160473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.160492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.160512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.160515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.160535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.160538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.160558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.160578] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.160598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.160617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.160637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.160656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.160676] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.160695] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.160715] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.160735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.160803] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.160873] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.160897] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.160921] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.160962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.160985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.161010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.161032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.161055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.161077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.161103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.161128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.161153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.161174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.161196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.161228] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.161249] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.163245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.163261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.163275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.163290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.164819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.164837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.164851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.166350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.166367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.168193] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.171137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.171203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.171223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.171249] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.187950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.187976] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.188011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.188115] [drm:drm_mode_addfb2] [FB:75]
>[ 1388.188193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.204667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.204691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.204728] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.223624] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.223643] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.223664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.223681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.223699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.223714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.223729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.223745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.223806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.223834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.223859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.223885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.223904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.223924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.223952] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.223975] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.224001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.224018] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.224100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.224110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.224156] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.224174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.224192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.224214] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.224233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.224254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.224273] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.224293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.224313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.224332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.224351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.224356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.224375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.224379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.224399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.224416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.224435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.224454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.224474] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.224493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.224513] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.224532] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.224552] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.224572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.224594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.224648] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.224663] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.224676] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.224703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.224719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.224733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.224754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.224794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.224815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.224839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.224862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.224884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.224904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.224924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.224948] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.224970] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.226977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.226994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.227009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.227024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.228533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.228548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.228562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.230060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.230076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.231881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.234829] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.234889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.234904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.234924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.251632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.251658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.251693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.251887] [drm:drm_mode_addfb2] [FB:78]
>[ 1388.251953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.268332] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.268356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.268402] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.287263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.287282] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.287302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.287319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.287337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.287352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.287367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.287383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.287400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.287417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.287432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.287448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.287462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.287476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.287503] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.287524] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.287545] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.287561] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.287673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.287683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.287730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.287750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.287807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.287836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.287860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.287885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.287910] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.287933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.287957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.287979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.288001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.288007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.288028] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.288035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.288056] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.288078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.288099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.288120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.288146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.288169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.288190] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.288218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.288238] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.288263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.288289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.288359] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.288383] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.288406] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.288446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.288470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.288493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.288515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.288530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.288544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.288562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.288576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.288592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.288605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.288619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.288635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.288651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.290640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.290658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.290672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.290687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.292197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.292213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.292227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.293725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.293741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.295568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.298492] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.298526] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.298542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.298564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.315268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.315294] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.315331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.315436] [drm:drm_mode_addfb2] [FB:79]
>[ 1388.315505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.331949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.331974] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.332018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.350877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.350896] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.350916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.350933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.350951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.350967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.350981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.351000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.351022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.351043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.351064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.351084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.351103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.351122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.351150] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.351173] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.351198] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.351214] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.351332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.351342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.351389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.351409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.351428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.351452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.351472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.351493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.351514] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.351534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.351554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.351574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.351594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.351598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.351618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.351622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.351643] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.351662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.351683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.351703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.351723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.351743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.351811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.351836] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.351862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.351888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.351917] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.351990] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.352014] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.352038] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.352080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.352103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.352127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.352149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.352172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.352194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.352220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.352246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.352271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.352292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.352314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.352341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.352364] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.354378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.354396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.354412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.354430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.355949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.355967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.355981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.357487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.357505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.359313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.362239] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.362270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.362287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.362309] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.379010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.379035] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.379072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.379172] [drm:drm_mode_addfb2] [FB:75]
>[ 1388.379230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.395695] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.395719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.395764] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.413593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.413612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.413632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.413650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.413668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.413683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.413698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.413714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.413732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.413752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.413812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.413841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.413863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.413887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.413933] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.413967] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.413999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.414030] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.414128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.414143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.414214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.414239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.414265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.414292] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.414315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.414339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.414363] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.414386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.414409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.414431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.414452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.414457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.414479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.414484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.414505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.414527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.414548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.414567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.414590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.414611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.414631] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.414651] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.414670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.414693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.414718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.414796] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.414822] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.414846] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.414885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.414909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.414933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.414956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.414979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.415003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.415029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.415054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.415078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.415100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.415123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.415148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.415171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.417175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.417192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.417207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.417223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.418729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.418745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.418759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.420287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.420304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.422140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.425083] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.425149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.425166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.425195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.441901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.441927] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.441962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.442056] [drm:drm_mode_addfb2] [FB:78]
>[ 1388.442123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.458590] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.458614] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.458653] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.477467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.477485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.477505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.477522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.477540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.477555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.477570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.477586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.477603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.477620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.477636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.477652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.477666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.477680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.477707] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.477728] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.477749] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.477807] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.477920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.477935] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.478004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.478027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.478054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.478083] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.478105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.478131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.478155] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.478179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.478201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.478224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.478245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.478251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.478273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.478278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.478301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.478323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.478345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.478366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.478391] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.478411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.478434] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.478454] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.478483] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.478504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.478528] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.478580] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.478601] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.478623] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.478659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.478679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.478701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.478720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.478740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.478761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.478806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.478831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.478856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.478875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.478897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.478923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.478944] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.480942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.480960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.480975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.480990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.483576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.483595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.483613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.485115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.485132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.486938] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.489882] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.489948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.489968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.489994] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.506681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.506707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.506743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.506914] [drm:drm_mode_addfb2] [FB:79]
>[ 1388.506982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.523370] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.523396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.523442] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.542299] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.542318] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.542338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.542355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.542373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.542388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.542403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.542419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.542436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.542453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.542469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.542484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.542499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.542517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.542545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.542568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.542593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.542609] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.542706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.542718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.542772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.542824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.542851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.542882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.542906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.542934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.542959] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.542985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.543015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.543037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.543057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.543064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.543084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.543089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.543110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.543130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.543151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.543169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.543193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.543212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.543233] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.543252] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.543272] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.543294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.543318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.543372] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.543394] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.543416] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.543453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.543474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.543495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.543514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.543535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.543555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.543578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.543601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.543624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.543643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.543664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.543686] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.543708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.545726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.545743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.545757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.545804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.547326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.547344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.547359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.548862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.548878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.550680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.553614] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.553690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.553707] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.553729] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.570432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.570459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.570497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.570599] [drm:drm_mode_addfb2] [FB:75]
>[ 1388.570668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.587112] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.587136] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.587181] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.606026] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.606046] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.606066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.606083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.606101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.606117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.606132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.606148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.606166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.606182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.606198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.606214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.606228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.606242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.606269] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.606290] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.606311] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.606327] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.606451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.606461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.606507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.606525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.606545] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.606567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.606586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.606607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.606627] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.606646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.606666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.606686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.606705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.606709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.606728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.606732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.606752] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.606771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.606832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.606856] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.606883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.606906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.606931] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.606953] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.606976] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.607003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.607031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.607089] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.607113] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.607136] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.607176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.607198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.607221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.607242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.607264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.607285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.607311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.607335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.607360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.607380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.607401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.607425] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.607449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.609470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.609487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.609501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.609516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.611025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.611040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.611054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.612550] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.612566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.614373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.617296] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.617330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.617346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.617368] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.634074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.634101] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.634136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.634234] [drm:drm_mode_addfb2] [FB:78]
>[ 1388.634301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.650745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.650766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.650854] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.669539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.669558] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.669578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.669595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.669612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.669627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.669641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.669657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.669675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.669691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.669707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.669723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.669737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.669751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.669822] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.669859] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.669892] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.669909] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.670004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.670019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.670087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.670105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.670123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.670143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.670159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.670176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.670193] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.670209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.670224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.670239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.670253] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.670257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.670270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.670274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.670288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.670302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.670316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.670330] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.670346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.670361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.670374] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.670388] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.670402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.670419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.670436] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.670475] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.670489] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.670504] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.670531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.670546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.670562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.670577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.670592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.670607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.670623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.670639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.670655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.670669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.670683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.670700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.670716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.672694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.672710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.672725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.672739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.674252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.674270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.674287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.675804] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.675822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.677626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.680550] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.680584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.680600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.680622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.697322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.697346] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.697382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.697484] [drm:drm_mode_addfb2] [FB:79]
>[ 1388.697542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.714027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.714051] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.714088] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.732546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.732565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.732585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.732602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.732620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.732635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.732650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.732666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.732684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.732700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.732716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.732731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.732746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.732759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.732832] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.732868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.732902] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.732928] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.733018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.733028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.733071] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.733088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.733107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.733126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.733142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.733159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.733176] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.733192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.733208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.733223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.733238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.733250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.733263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.733266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.733279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.733293] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.733306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.733319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.733334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.733347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.733360] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.733372] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.733385] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.733400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.733416] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.733451] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.733465] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.733478] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.733502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.733520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.733538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.733555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.733573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.733591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.733611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.733630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.733650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.733667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.733685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.733703] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.733722] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.735696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.735714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.735732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.735750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.737258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.737275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.737289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.738805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.738821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.740625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.743560] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.743634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.743654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.743680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.760376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.760402] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.760437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.760537] [drm:drm_mode_addfb2] [FB:75]
>[ 1388.760595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.777077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.777101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.777138] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.795980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.796000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.796022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.796042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.796064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.796084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.796103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.796122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.796144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.796165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.796185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.796205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.796224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.796243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.796271] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.796293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.796318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.796334] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.796449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.796459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.796506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.796526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.796546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.796566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.796583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.796602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.796620] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.796637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.796654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.796670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.796685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.796689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.796704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.796707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.796723] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.796739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.796754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.796768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.796786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.796839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.796862] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.796884] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.796908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.796935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.796964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.797024] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.797048] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.797073] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.797113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.797136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.797162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.797185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.797207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.797230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.797256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.797281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.797306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.797326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.797349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.797375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.797398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.799413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.799430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.799445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.799460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.800967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.800983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.800997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.802491] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.802507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.804314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.807250] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.807323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.807340] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.807362] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.824066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.824093] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.824131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.824234] [drm:drm_mode_addfb2] [FB:78]
>[ 1388.824301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.840746] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.840770] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.840856] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.859548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.859567] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.859588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.859604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.859622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.859637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.859651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.859667] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.859685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.859702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.859718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.859734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.859748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.859762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.859834] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.859870] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.859903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.859920] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.860013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.860028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.860100] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.860116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.860132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.860153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.860171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.860189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.860207] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.860225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.860242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.860260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.860277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.860282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.860299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.860303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.860321] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.860339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.860355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.860372] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.860390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.860407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.860425] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.860443] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.860460] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.860479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.860498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.860536] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.860549] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.860564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.860592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.860610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.860627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.860646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.860664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.860681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.860701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.860720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.860737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.860754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.860773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.860827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.860851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.862847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.862863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.862877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.862892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.864408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.864425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.864440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.865948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.865967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.867770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.870717] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.870779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.870834] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.870858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.887517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.887542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.887577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.887676] [drm:drm_mode_addfb2] [FB:79]
>[ 1388.887740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.904204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.904228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.904273] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.922733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.922752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.922773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.922789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.922853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.922874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.922893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.922913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.922935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.922956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.922977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.922999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.923018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.923037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.923065] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.923089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.923114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.923131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.923212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.923221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.923267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.923285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.923304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.923324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.923340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.923357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.923374] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.923391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.923407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.923422] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.923436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.923441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.923459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.923464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.923484] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.923503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.923523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.923546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.923563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.923578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.923592] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.923606] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.923619] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.923634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.923651] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.923688] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.923701] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.923714] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.923739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.923754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.923767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.923782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.923826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.923848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.923872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.923895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.923918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.923937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.923957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.923981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.924002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.925995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.926011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.926025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.926039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.927546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.927562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.927576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.929072] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.929088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.930894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.933844] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.933903] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.933919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.933941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1388.950646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.950672] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.950707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.950930] [drm:drm_mode_addfb2] [FB:75]
>[ 1388.950998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.967345] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1388.967370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1388.967415] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1388.986278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1388.986298] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1388.986318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.986334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.986352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.986367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.986381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.986397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1388.986415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.986431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.986447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.986463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.986477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.986491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.986518] [drm:intel_power_well_disable [i915]] disabling display
>[ 1388.986539] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1388.986560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1388.986575] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1388.986691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1388.986701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1388.986749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1388.986768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1388.986789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1388.986858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1388.986883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1388.986910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1388.986934] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1388.986958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1388.986981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1388.987004] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1388.987025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1388.987040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.987060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1388.987066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1388.987087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1388.987108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1388.987129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1388.987151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1388.987176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1388.987196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1388.987218] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1388.987238] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1388.987261] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1388.987286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1388.987313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1388.987373] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1388.987398] [drm:intel_power_well_enable [i915]] enabling display
>[ 1388.987421] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1388.987462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1388.987487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1388.987511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1388.987528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1388.987543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1388.987559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1388.987576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1388.987592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1388.987607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1388.987622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1388.987636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1388.987653] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1388.987669] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1388.989664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1388.989681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1388.989696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.989711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1388.991220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1388.991236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1388.991252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1388.992750] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1388.992767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1388.994575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1388.997500] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1388.997533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1388.997549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1388.997571] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.014282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.014308] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.014343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.014444] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.014510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.030956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.030981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.031026] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.049873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.049891] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.049912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.049929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.049946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.049962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.049977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.049993] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.050010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.050027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.050043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.050059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.050073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.050087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.050114] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.050135] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.050156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.050172] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.050277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.050287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.050334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.050354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.050373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.050396] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.050417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.050438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.050458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.050478] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.050499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.050519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.050539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.050543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.050563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.050567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.050587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.050607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.050628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.050648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.050668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.050688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.050708] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.050729] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.050749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.050770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.050792] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.050886] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.050912] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.050936] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.050979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.051007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.051031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.051056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.051079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.051104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.051132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.051158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.051184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.051206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.051230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.051258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.051281] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.053294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.053312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.053330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.053348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.054879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.054897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.054912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.056420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.056439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.058251] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.061200] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.061260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.061277] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.061299] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.078003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.078029] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.078064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.078164] [drm:drm_mode_addfb2] [FB:79]
>[ 1389.078222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.094683] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.094709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.094755] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.113573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.113592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.113612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.113629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.113647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.113663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.113678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.113694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.113712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.113729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.113745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.113761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.113775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.113789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.113868] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.113905] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.113939] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.113966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.114057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.114066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.114110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.114128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.114147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.114167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.114183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.114201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.114218] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.114235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.114251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.114266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.114280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.114284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.114298] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.114301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.114316] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.114330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.114345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.114358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.114374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.114389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.114403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.114417] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.114432] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.114456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.114475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.114513] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.114528] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.114542] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.114569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.114584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.114599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.114614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.114628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.114644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.114660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.114677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.114692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.114706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.114719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.114737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.114753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.116728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.116745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.116759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.116774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.118280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.118295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.118308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.119823] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.119841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.121646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.124569] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.124603] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.124622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.124648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.141342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.141367] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.141401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.141499] [drm:drm_mode_addfb2] [FB:75]
>[ 1389.141563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.158027] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.158052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.158098] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.176956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.176975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.176995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.177012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.177030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.177045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.177059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.177075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.177093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.177110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.177126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.177141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.177156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.177170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.177197] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.177220] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.177245] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.177261] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.177375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.177385] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.177433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.177452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.177472] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.177493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.177509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.177529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.177550] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.177570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.177591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.177611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.177631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.177634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.177654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.177658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.177679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.177699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.177719] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.177739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.177760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.177780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.177800] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.177861] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.177887] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.177915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.177944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.178004] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.178029] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.178053] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.178095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.178118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.178142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.178165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.178189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.178212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.178239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.178265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.178290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.178311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.178333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.178368] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.178389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.180403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.180421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.180435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.180450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.181972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.181990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.182008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.183513] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.183531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.185340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.188263] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.188297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.188314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.188336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.205037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.205061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.205095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.205194] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.205257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.221722] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.221748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.221795] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.240663] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.240682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.240703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.240720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.240738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.240753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.240767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.240783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.240801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.240862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.240889] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.240917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.240938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.240962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.241007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.241042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.241074] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.241099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.241215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.241232] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.241306] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.241333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.241362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.241392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.241417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.241444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.241470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.241496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.241521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.241545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.241569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.241574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.241597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.241603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.241627] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.241650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.241673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.241696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.241720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.241743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.241766] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.241795] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.241848] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.241875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.241902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.241957] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.241981] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.242002] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.242042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.242066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.242089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.242111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.242132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.242155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.242181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.242204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.242228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.242249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.242271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.242296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.242319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.244349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.244365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.244379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.244394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.245926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.245944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.245958] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.247453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.247471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.249278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.252227] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.252288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.252305] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.252327] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.269029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.269054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.269089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.269187] [drm:drm_mode_addfb2] [FB:79]
>[ 1389.269253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.285709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.285735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.285782] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.304584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.304603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.304625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.304645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.304667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.304686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.304706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.304725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.304747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.304767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.304788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.304807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.304869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.304893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.304937] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.304974] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.305009] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.305035] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.305132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.305141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.305186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.305203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.305221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.305242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.305266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.305282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.305297] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.305311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.305329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.305347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.305365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.305369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.305386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.305390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.305408] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.305426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.305443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.305461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.305478] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.305496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.305514] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.305531] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.305549] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.305567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.305587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.305623] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.305637] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.305651] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.305679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.305698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.305716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.305734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.305752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.305770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.305789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.305812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.305858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.305880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.305901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.305925] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.305947] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.307943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.307959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.307973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.307988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.309493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.309511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.309528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.311024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.311041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.312846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.315718] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.315753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.315770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.315792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.332505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.332531] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.332566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.332670] [drm:drm_mode_addfb2] [FB:75]
>[ 1389.332735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.349194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.349220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.349269] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.368129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.368148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.368168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.368185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.368203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.368218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.368233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.368249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.368267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.368283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.368299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.368315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.368329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.368343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.368370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.368391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.368412] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.368428] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.368543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.368553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.368600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.368620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.368640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.368661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.368678] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.368696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.368714] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.368731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.368748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.368764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.368779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.368783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.368798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.368802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.368817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.368876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.368898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.368920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.368948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.368970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.368994] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.369015] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.369039] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.369066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.369095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.369155] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.369178] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.369202] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.369243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.369266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.369289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.369311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.369333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.369356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.369383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.369408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.369433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.369455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.369477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.369501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.369525] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.371528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.371544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.371558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.371573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.373084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.373100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.373114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.374608] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.374624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.376433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.379357] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.379391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.379407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.379429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.396134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.396161] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.396196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.396308] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.396374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.412823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.412862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.412898] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.431758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.431777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.431797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.431814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.431874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.431897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.431921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.431944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.431973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.431999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.432024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.432050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.432070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.432093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.432135] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.432169] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.432200] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.432225] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.432337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.432347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.432391] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.432408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.432427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.432448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.432467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.432486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.432505] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.432523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.432542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.432560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.432579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.432582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.432600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.432604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.432623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.432641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.432660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.432678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.432697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.432715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.432733] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.432752] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.432770] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.432789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.432810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.432913] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.432933] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.432956] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.432997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.433020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.433044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.433067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.433088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.433111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.433136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.433160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.433185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.433206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.433227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.433253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.433276] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.435263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.435280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.435295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.435310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.436887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.436904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.436922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.438431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.438458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.440281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.443200] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.443239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.443257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.443281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.459990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.460017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.460056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.460181] [drm:drm_mode_addfb2] [FB:79]
>[ 1389.460251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.476664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.476691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.476731] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.495600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.495619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.495640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.495657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.495675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.495690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.495705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.495720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.495738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.495754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.495770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.495785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.495799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.495813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.495892] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.495929] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.495963] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.495989] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.496092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.496102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.496147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.496167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.496188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.496211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.496230] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.496250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.496270] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.496291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.496311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.496330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.496350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.496354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.496373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.496377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.496397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.496416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.496435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.496454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.496474] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.496492] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.496512] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.496531] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.496551] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.496571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.496593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.496647] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.496660] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.496673] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.496701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.496718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.496733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.496747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.496760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.496776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.496793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.496808] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.496823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.496867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.496888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.496912] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.496934] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.498925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.498941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.498955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.498970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.500474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.500490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.500505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.502002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.502018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.503822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.506752] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.506799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.506814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.506881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.523535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.523561] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.523596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.523698] [drm:drm_mode_addfb2] [FB:75]
>[ 1389.523762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.540236] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.540261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.540297] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.559146] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.559165] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.559185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.559202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.559220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.559235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.559250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.559265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.559283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.559300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.559316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.559331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.559346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.559360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.559387] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.559408] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.559429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.559444] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.559557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.559567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.559614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.559634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.559654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.559677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.559698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.559718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.559739] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.559759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.559780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.559800] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.559820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.559862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.559890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.559897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.559924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.559948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.559973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.559995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.560022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.560044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.560067] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.560089] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.560112] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.560139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.560167] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.560242] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.560265] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.560289] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.560332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.560355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.560378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.560399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.560422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.560445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.560471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.560497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.560522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.560542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.560564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.560591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.560614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.562621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.562637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.562651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.562666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.564185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.564204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.564222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.565719] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.565736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.567545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.570469] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.570503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.570519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.570541] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.587242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.587266] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.587300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.587397] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.587460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.603949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.603973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.604010] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.622867] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.622885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.622907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.622927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.622949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.622968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.622988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.623008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.623029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.623050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.623071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.623090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.623110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.623128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.623157] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.623180] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.623205] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.623221] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.623340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.623351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.623399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.623418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.623438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.623461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.623481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.623502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.623522] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.623543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.623563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.623583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.623603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.623607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.623627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.623630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.623651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.623671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.623691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.623711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.623731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.623751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.623772] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.623792] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.623812] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.623833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.623884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.623960] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.623985] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.624009] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.624052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.624078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.624101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.624126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.624148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.624174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.624201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.624226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.624251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.624273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.624295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.624321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.624344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.626373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.626390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.626405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.626420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.627935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.627951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.627965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.629463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.629479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.631286] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.634234] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.634296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.634315] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.634341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.651039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.651065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.651100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.651201] [drm:drm_mode_addfb2] [FB:79]
>[ 1389.651269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.667719] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.667745] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.667783] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.686636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.686655] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.686675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.686692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.686710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.686726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.686741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.686757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.686775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.686791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.686807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.686823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.686880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.686902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.686946] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.686982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.687016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.687042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.687137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.687146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.687186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.687202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.687219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.687237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.687253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.687272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.687290] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.687308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.687326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.687344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.687362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.687366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.687383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.687387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.687405] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.687422] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.687441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.687458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.687476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.687494] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.687512] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.687530] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.687548] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.687566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.687586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.687622] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.687636] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.687651] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.687678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.687697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.687715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.687732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.687750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.687768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.687787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.687806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.687826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.687875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.687898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.687924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.687945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.689941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.689957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.689971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.689986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.691490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.691506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.691520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.693018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.693035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.694870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.697803] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.697909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.697938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.697973] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.714623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.714649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.714685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.714784] [drm:drm_mode_addfb2] [FB:75]
>[ 1389.714841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.731302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.731329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.731368] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.750226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.750246] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.750266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.750282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.750300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.750316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.750330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.750347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.750365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.750381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.750397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.750413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.750431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.750450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.750478] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.750501] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.750526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.750543] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.750658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.750668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.750714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.750733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.750752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.750772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.750791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.750812] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.750832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.750893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.750918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.750942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.750964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.750971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.750995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.751001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.751024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.751045] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.751069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.751090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.751115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.751136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.751159] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.751180] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.751202] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.751228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.751256] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.751316] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.751340] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.751363] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.751402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.751426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.751448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.751469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.751489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.751513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.751538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.751562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.751594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.751613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.751633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.751658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.751679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.753679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.753696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.753710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.753725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.755246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.755263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.755278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.756790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.756807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.758614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.761552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.761624] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.761643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.761669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.778362] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.778386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.778420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.778509] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.778567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.795046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.795072] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.795110] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.813961] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.813980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.814000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.814017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.814035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.814050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.814065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.814081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.814099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.814116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.814132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.814148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.814162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.814181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.814209] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.814232] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.814257] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.814273] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.814368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.814378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.814426] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.814445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.814465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.814486] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.814502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.814520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.814540] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.814561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.814582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.814602] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.814622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.814626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.814646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.814649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.814670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.814690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.814711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.814731] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.814751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.814771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.814791] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.814812] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.814832] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.814897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.814928] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.814990] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.815015] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.815039] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.815081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.815107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.815130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.815153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.815175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.815200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.815227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.815253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.815278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.815299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.815321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.815348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.815371] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.817404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.817421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.817436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.817450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.818967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.818983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.818998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.820493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.820509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.822316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.825265] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.825324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.825342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.825366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.842068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.842094] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.842129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.842228] [drm:drm_mode_addfb2] [FB:79]
>[ 1389.842294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.858759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.858782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.858816] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.877691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.877710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.877730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.877747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.877765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.877780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.877794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.877811] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.877829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.877845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.877906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.877933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.877956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.877978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.878016] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.878038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.878060] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.878076] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.878154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.878164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.878207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.878224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.878243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.878264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.878283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.878304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.878324] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.878344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.878363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.878383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.878402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.878407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.878425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.878429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.878449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.878469] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.878488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.878507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.878534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.878551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.878566] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.878580] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.878594] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.878610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.878626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.878661] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.878674] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.878688] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.878713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.878727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.878741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.878754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.878767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.878782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.878797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.878816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.878835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.878881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.878903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.878926] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.878949] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.880944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.880960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.880974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.880989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.882494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.882509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.882524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.884022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.884039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.885849] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.888799] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.888897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.888924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.888959] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.905610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.905637] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.905672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.905763] [drm:drm_mode_addfb2] [FB:75]
>[ 1389.905830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.922290] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.922315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.922351] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1389.940611] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1389.940632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1389.940654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.940674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.940695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.940715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.940734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.940754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.940775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.940796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.940817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.940836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.940855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.940917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.940961] [drm:intel_power_well_disable [i915]] disabling display
>[ 1389.940991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1389.941017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.941034] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1389.941128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1389.941143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1389.941203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1389.941221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1389.941240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1389.941260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1389.941275] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1389.941294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1389.941311] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1389.941328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1389.941343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1389.941359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1389.941373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1389.941378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.941392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1389.941396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1389.941410] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1389.941425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1389.941440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1389.941458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1389.941478] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1389.941497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1389.941518] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1389.941537] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1389.941557] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1389.941577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.941598] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1389.941645] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1389.941660] [drm:intel_power_well_enable [i915]] enabling display
>[ 1389.941675] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1389.941705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1389.941725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1389.941745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1389.941765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1389.941784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1389.941803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1389.941825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1389.941850] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1389.941901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.941924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1389.941953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1389.941978] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1389.942000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1389.943999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1389.944015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1389.944030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.944044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1389.945550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1389.945566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1389.945580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1389.947078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1389.947094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1389.948901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1389.951834] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1389.951916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1389.951934] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1389.951956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1389.968653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1389.968679] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1389.968714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1389.968804] [drm:drm_mode_addfb2] [FB:78]
>[ 1389.968920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1389.985354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1389.985378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1389.985414] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.004258] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.004277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.004297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.004317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.004339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.004358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.004378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.004397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.004419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.004440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.004460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.004480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.004499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.004518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.004546] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.004568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.004593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.004610] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.004726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.004736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.004783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.004804] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.004825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.004848] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.004912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.004940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.004967] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.004991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.005016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.005039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.005062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.005069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.005092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.005099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.005123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.005145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.005168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.005190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.005216] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.005238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.005261] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.005283] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.005306] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.005333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.005361] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.005422] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.005446] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.005469] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.005509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.005532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.005555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.005576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.005598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.005620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.005646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.005671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.005696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.005716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.005739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.005763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.005787] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.007792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.007809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.007823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.007837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.009380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.009398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.009413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.010928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.010947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.012754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.015688] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.015763] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.015780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.015802] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.032506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.032532] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.032567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.032660] [drm:drm_mode_addfb2] [FB:79]
>[ 1390.032730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.049196] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.049218] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.049253] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.068098] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.068117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.068137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.068154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.068172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.068187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.068202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.068218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.068236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.068252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.068269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.068285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.068299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.068313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.068339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.068361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.068382] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.068399] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.068506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.068517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.068564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.068583] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.068603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.068623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.068640] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.068660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.068681] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.068701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.068722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.068742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.068762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.068766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.068786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.068790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.068810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.068830] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.068851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.068917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.068944] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.068970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.068994] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.069018] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.069041] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.069068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.069096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.069156] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.069181] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.069205] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.069248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.069273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.069299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.069323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.069346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.069371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.069398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.069424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.069451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.069474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.069497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.069524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.069547] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.071563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.071580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.071596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.071614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.073125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.073141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.073156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.074651] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.074667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.076473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.079397] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.079432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.079452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.079478] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.096170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.096195] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.096229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.096327] [drm:drm_mode_addfb2] [FB:75]
>[ 1390.096383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.112863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.112900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.112937] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.131789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.131810] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.131832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.131853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.131919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.131947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.131973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.131999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.132023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.132041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.132057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.132073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.132092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.132111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.132140] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.132162] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.132188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.132204] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.132277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.132287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.132339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.132355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.132372] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.132391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.132405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.132421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.132437] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.132452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.132467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.132480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.132494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.132497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.132510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.132514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.132527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.132540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.132553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.132566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.132584] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.132601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.132619] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.132638] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.132655] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.132674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.132693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.132737] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.132751] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.132765] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.132793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.132811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.132830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.132848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.132873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.132917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.132942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.132965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.132988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.133008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.133027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.133051] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.133073] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.135072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.135088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.135102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.135117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.136621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.136636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.136649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.138145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.138160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.139966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.142914] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.142976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.142996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.143021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.159717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.159743] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.159778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.159925] [drm:drm_mode_addfb2] [FB:78]
>[ 1390.160020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.176419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.176443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.176480] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.195349] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.195368] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.195388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.195405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.195422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.195437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.195452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.195468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.195485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.195501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.195517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.195532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.195547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.195560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.195587] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.195609] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.195633] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.195650] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.195772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.195782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.195828] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.195847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.195866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.195928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.195950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.195976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.196000] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.196023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.196045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.196067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.196088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.196094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.196115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.196121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.196142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.196163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.196184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.196206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.196230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.196251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.196272] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.196292] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.196315] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.196336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.196355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.196393] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.196407] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.196422] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.196448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.196464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.196479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.196493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.196507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.196522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.196539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.196554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.196574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.196593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.196612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.196632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.196651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.198642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.198660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.198675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.198690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.200200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.200216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.200229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.201723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.201739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.203545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.206469] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.206502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.206518] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.206540] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.223247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.223274] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.223311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.223415] [drm:drm_mode_addfb2] [FB:79]
>[ 1390.223483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.239926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.239951] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.239987] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.258842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.258862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.258927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.258953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.258982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.259004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.259027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.259050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.259078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.259104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.259130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.259155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.259176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.259198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.259241] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.259274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.259306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.259331] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.259431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.259441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.259487] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.259505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.259524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.259543] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.259558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.259575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.259592] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.259607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.259622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.259636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.259650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.259654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.259668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.259672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.259686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.259700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.259714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.259732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.259752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.259771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.259790] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.259809] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.259828] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.259848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.259869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.259962] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.259985] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.260007] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.260051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.260077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.260100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.260128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.260150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.260173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.260198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.260222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.260246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.260267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.260288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.260314] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.260338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.262345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.262361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.262375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.262390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.263942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.263959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.263974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.265477] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.265495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.267314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.270262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.270321] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.270337] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.270357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.287094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.287120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.287155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.287258] [drm:drm_mode_addfb2] [FB:75]
>[ 1390.287338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.303762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.303788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.303827] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.322679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.322698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.322720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.322740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.322762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.322781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.322801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.322821] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.322842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.322863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.322930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.322959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.322983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.323005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.323049] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.323087] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.323121] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.323147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.323229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.323240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.323285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.323305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.323326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.323349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.323368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.323388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.323414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.323431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.323445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.323460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.323473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.323477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.323494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.323498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.323516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.323534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.323552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.323570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.323588] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.323605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.323623] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.323641] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.323659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.323677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.323696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.323739] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.323753] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.323768] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.323796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.323814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.323831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.323850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.323869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.323914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.323939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.323962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.323985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.324005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.324025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.324050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.324071] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.326072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.326090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.326105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.326120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.327627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.327645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.327662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.329161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.329178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.330982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.333929] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.333991] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.334008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.334030] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.350734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.350761] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.350799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.350947] [drm:drm_mode_addfb2] [FB:78]
>[ 1390.351050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.367434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.367459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.367496] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.386352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.386371] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.386391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.386408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.386426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.386441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.386456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.386472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.386490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.386507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.386523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.386539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.386553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.386566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.386593] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.386614] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.386635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.386651] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.386766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.386776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.386823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.386845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.386866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.386934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.386959] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.386988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.387013] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.387038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.387062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.387086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.387108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.387115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.387137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.387144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.387168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.387190] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.387213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.387234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.387261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.387283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.387306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.387327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.387350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.387377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.387403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.387474] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.387497] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.387520] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.387561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.387584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.387606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.387629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.387650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.387674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.387700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.387725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.387750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.387771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.387793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.387817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.387841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.389874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.389908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.389925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.389944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.391463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.391480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.391494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.393003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.393019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.394831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.397754] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.397789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.397805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.397831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.414533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.414559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.414594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.414696] [drm:drm_mode_addfb2] [FB:79]
>[ 1390.414755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.431234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.431260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.431298] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.450142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.450161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.450183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.450203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.450224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.450244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.450263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.450283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.450305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.450325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.450346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.450365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.450384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.450403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.450431] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.450454] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.450478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.450495] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.450603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.450613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.450661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.450680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.450701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.450723] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.450743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.450764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.450784] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.450804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.450825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.450845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.450865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.450869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.450927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.450936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.450963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.450988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.451013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.451035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.451063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.451085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.451109] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.451131] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.451154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.451181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.451209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.451568] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.451592] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.451616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.451658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.451682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.451705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.451727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.451750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.451773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.451799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.451824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.451849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.451870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.451913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.451939] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.451965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.454155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.454172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.454186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.454201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.455707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.455722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.455736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.457234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.457251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.459055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.461990] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.462063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.462079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.462101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.478806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.478834] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.478871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.479046] [drm:drm_mode_addfb2] [FB:75]
>[ 1390.479109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.495481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.495506] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.495542] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.514384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.514403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.514423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.514440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.514458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.514473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.514488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.514504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.514522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.514538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.514554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.514570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.514584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.514598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.514625] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.514647] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.514668] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.514684] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.514781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.514792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.514841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.514859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.514877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.514936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.514959] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.514986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.515011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.515035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.515058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.515081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.515102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.515110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.515131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.515137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.515161] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.515182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.515205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.515225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.515503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.515526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.515550] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.515571] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.515593] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.515616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.515643] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.515711] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.515734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.515756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.515803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.515825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.515845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.515866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.515885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.515927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.515952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.515977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.516001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.516021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.516043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.516066] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.516089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.518275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.518291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.518305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.518320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.519835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.519850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.519863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.521359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.521375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.523182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.526116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.526191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.526207] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.526229] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.542959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.542985] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.543020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.543124] [drm:drm_mode_addfb2] [FB:78]
>[ 1390.543189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.559631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.559655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.559693] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.578541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.578560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.578580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.578597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.578614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.578629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.578644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.578660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.578678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.578695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.578711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.578727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.578741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.578755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.578781] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.578803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.578825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.578840] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.578953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.578971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.579047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.579075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.579109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.579136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.579156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.579180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.579202] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.579223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.579244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.579265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.579283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.579289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.579308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.579313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.579334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.579354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.579374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.579393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.579415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.579434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.579455] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.579474] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.579494] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.579515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.579539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.579593] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.579614] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.579635] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.579672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.579694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.579714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.579735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.579754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.579775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.579799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.579821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.579844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.579863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.579883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.579935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.579957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.581953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.581969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.581983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.581998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.583509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.583525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.583538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.585048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.585064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.586873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.589818] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.589881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.589933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.589971] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.606607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.606631] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.606664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.606775] [drm:drm_mode_addfb2] [FB:79]
>[ 1390.606848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.623326] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.623350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.623387] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.641642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.641662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.641681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.641699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.641716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.641732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.641747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.641763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.641781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.641797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.641813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.641829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.641843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.641857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.641884] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.641955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.641988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.642015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.642096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.642107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.642151] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.642167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.642186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.642205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.642221] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.642238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.642255] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.642271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.642286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.642301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.642316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.642321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.642335] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.642338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.642353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.642367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.642382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.642395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.642412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.642426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.642441] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.642455] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.642469] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.642493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.642510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.642545] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.642558] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.642572] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.642596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.642610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.642624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.642637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.642650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.642664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.642679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.642693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.642708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.642721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.642733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.642749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.642763] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.644738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.644754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.644768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.644782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.646289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.646305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.646318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.647840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.647857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.649666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.652589] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.652623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.652640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.652661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.669366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.669392] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.669427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.669528] [drm:drm_mode_addfb2] [FB:75]
>[ 1390.669594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.686054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.686080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.686119] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.704945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.704964] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.704984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.705001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.705019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.705034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.705049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.705065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.705083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.705099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.705115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.705131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.705145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.705160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.705187] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.705208] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.705230] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.705245] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.705361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.705372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.705420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.705439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.705459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.705480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.705497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.705514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.705533] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.705550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.705566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.705582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.705597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.705601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.705619] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.705622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.705643] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.705663] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.705684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.705704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.705724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.705744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.705765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.705785] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.705805] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.705826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.705849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.705899] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.705961] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.705987] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.706031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.706058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.706082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.706107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.706130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.706155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.706183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.706210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.706237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.706259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.706283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.706310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.706335] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.708687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.708703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.708718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.708732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.710248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.710266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.710281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.711775] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.711791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.714670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.717634] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.717680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.717699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.717725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.734412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.734437] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.734471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.734572] [drm:drm_mode_addfb2] [FB:78]
>[ 1390.734629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.751124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.751150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.751188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.770021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.770040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.770060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.770077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.770095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.770111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.770126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.770142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.770160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.770177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.770193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.770209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.770223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.770237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.770264] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.770286] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.770307] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.770323] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.770428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.770438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.770486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.770505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.770525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.770546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.770562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.770580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.770598] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.770616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.770633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.770651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.770671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.770675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.770695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.770699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.770720] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.770740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.770760] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.770780] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.770801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.770821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.770841] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.770861] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.770882] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.770903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.770970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.771043] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.771068] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.771092] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.771135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.771457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.771479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.771501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.771521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.771543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.771567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.771591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.771615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.771634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.771655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.771680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.771701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.774793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.774812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.774828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.774844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.778532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.778548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.778562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.781127] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.781144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.784022] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.786971] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.787032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.787049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.787071] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.803774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.803800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.803837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.804017] [drm:drm_mode_addfb2] [FB:79]
>[ 1390.804074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.820475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.820500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.820536] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.839379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.839398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.839419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.839436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.839457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.839477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.839496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.839516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.839537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.839558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.839578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.839598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.839617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.839636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.839664] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.839687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.839712] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.839728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.839825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.839837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.839895] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.839955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.839983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.840011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.840034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.840060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.840083] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.840106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.840129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.840151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.840172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.840179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.840200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.840206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.840228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.840249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.840271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.840290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.840313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.840334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.840355] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.840375] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.840396] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.840421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.840446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.840513] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.840535] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.840557] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.840595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.840617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.840638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.840659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.840679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.840702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.840726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.840751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.840774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.840794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.840814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.840838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.840868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.843979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.843998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.844014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.844030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.846606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.846623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.846639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.849207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.849224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.852098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.855035] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.855107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.855123] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.855145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.871849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.871875] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.871910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.872101] [drm:drm_mode_addfb2] [FB:75]
>[ 1390.872165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.888530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.888556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.888594] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.907441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.907460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.907481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.907497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.907515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.907530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.907544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.907561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.907582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.907603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.907624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.907644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.907663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.907683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.907711] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.907733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.907758] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.907775] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.907872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.907883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.908009] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.908034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.908061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.908090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.908113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.908139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.908163] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.908188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.908210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.908233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.908254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.908260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.908281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.908287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.908310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.908331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.908353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.908374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.908398] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.908419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.908442] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.908469] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.908489] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.908510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.908534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.908599] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.908621] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.908643] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.908680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.908701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.908723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.908743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.908764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.908785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.908808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.908831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.908854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.908873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.908893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.908916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.908956] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.912050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.912069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.912085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.912102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.914673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.914690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.914706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.917274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.917292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.920175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.923123] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.923184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.923201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.923223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1390.939942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.939968] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.940003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.940101] [drm:drm_mode_addfb2] [FB:78]
>[ 1390.940166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.956606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1390.956630] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1390.956666] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1390.975509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1390.975530] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1390.975552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.975572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.975593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.975613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.975632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.975651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1390.975673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.975694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.975714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.975734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.975753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.975772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.975800] [drm:intel_power_well_disable [i915]] disabling display
>[ 1390.975822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1390.975847] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1390.975864] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1390.976091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1390.976101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1390.976148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1390.976165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1390.976182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1390.976201] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1390.976215] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1390.976232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1390.976248] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1390.976263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1390.976277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1390.976291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1390.976304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1390.976309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.976321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1390.976325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1390.976339] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1390.976356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1390.976374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1390.976392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1390.976410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1390.976427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1390.976445] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1390.976462] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1390.976481] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1390.976499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1390.976519] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1390.976563] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1390.976578] [drm:intel_power_well_enable [i915]] enabling display
>[ 1390.976592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1390.976621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1390.976639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1390.976657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1390.976675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1390.976693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1390.976712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1390.976729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1390.976748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1390.976767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1390.976785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1390.976803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1390.976821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1390.976840] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1390.979946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1390.979963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1390.979977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.980000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1390.982588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1390.982605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1390.982620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1390.985184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1390.985202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1390.988083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1390.991018] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1390.991092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1390.991111] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1390.991137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.007834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.007860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.007895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.008078] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.008150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.024527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.024551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.024586] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.043440] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.043459] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.043479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.043496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.043514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.043529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.043544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.043560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.043578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.043594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.043610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.043626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.043640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.043654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.043681] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.043703] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.043723] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.043739] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.043836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.043847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.043901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.043921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.043974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.044004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.044028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.044056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.044080] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.044106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.044129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.044153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.044175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.044182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.044205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.044211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.044235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.044257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.044280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.044302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.044327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.044603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.044625] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.044648] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.044668] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.044692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.044718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.044783] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.044806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.044828] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.044866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.044889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.044909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.044949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.044970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.044994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.045020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.045045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.045070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.045091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.045113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.045319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.045342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.048438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.048456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.048470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.048485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.052222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.052241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.052257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.054825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.054843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.057729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.060652] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.060687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.060703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.060725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.077425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.077451] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.077486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.077597] [drm:drm_mode_addfb2] [FB:75]
>[ 1391.077673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.094131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.094157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.094195] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.113050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.113069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.113090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.113106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.113124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.113143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.113163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.113182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.113204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.113225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.113245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.113265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.113285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.113304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.113332] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.113354] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.113379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.113396] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.113503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.113513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.113560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.113580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.113600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.113620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.113636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.113654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.113672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.113689] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.113706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.113722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.113737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.113741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.113755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.113759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.113774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.113789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.113809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.113829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.113850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.113870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.113890] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.113910] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.113971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.113999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.114027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.114099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.114123] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.114147] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.114189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.114502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.114526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.114550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.114572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.114596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.114623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.114648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.114673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.114694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.114716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.114741] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.114766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.116766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.116783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.116797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.116812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.118318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.118333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.118347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.119865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.119882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.121691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.124626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.124701] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.124717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.124739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.141442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.141468] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.141504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.141602] [drm:drm_mode_addfb2] [FB:78]
>[ 1391.141660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.158144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.158170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.158207] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.177051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.177071] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.177091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.177108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.177129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.177149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.177169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.177188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.177210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.177231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.177252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.177271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.177290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.177309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.177337] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.177360] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.177384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.177401] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.177514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.177524] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.177568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.177587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.177605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.177628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.177647] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.177666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.177686] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.177705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.177724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.177743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.177762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.177766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.177784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.177788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.177808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.177826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.177845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.177864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.177884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.177902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.177922] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.177979] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.178004] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.178030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.178058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.178126] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.178150] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.178173] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.178212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.178497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.178519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.178541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.178561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.178584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.178608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.178632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.178656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.178675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.178695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.178718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.178741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.180736] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.180753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.180767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.180783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.182295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.182311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.182325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.183820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.183838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.185649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.188592] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.188666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.188681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.188702] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.205400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.205427] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.205462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.205564] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.205628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.222102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.222126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.222162] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.241004] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.241023] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.241043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.241060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.241081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.241101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.241120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.241139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.241161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.241182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.241202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.241222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.241241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.241260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.241288] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.241311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.241336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.241352] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.241466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.241476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.241523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.241542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.241562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.241583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.241600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.241618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.241636] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.241654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.241674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.241694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.241715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.241719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.241738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.241742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.241763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.241783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.241803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.241823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.241844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.241864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.241884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.241905] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.241925] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.241989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.242020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.242092] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.242117] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.242141] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.242184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.242524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.242549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.242572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.242595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.242618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.242645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.242671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.242696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.242717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.242739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.242764] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.242788] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.244789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.244806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.244821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.244836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.246343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.246358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.246372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.247881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.247897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.249705] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.252628] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.252661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.252678] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.252700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.269406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.269432] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.269469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.269570] [drm:drm_mode_addfb2] [FB:75]
>[ 1391.269638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.286106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.286131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.286167] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.305011] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.305030] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.305050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.305067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.305084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.305100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.305114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.305131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.305148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.305165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.305180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.305196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.305210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.305223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.305251] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.305272] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.305293] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.305309] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.305421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.305431] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.305486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.305504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.305523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.305544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.305560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.305578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.305595] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.305612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.305628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.305643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.305658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.305662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.305676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.305680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.305695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.305710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.305724] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.305743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.305763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.305782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.305802] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.305822] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.305841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.305862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.305883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.305932] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.305989] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.306015] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.306057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.306083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.306106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.306130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.306152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.306176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.306203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.306230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.306256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.306277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.306300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.306327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.306350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.308691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.308708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.308723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.308737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.310248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.310266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.310283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.311780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.311797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.313608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.316549] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.316617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.316634] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.316656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.333360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.333387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.333424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.333526] [drm:drm_mode_addfb2] [FB:78]
>[ 1391.333594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.350061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.350086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.350122] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.368977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.368995] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.369016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.369032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.369050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.369066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.369081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.369097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.369115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.369131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.369147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.369163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.369177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.369191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.369217] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.369239] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.369260] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.369276] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.369388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.369398] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.369445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.369465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.369485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.369505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.369522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.369540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.369558] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.369575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.369591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.369607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.369623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.369627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.369642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.369645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.369661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.369681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.369701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.369721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.369742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.369762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.369782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.369803] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.369823] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.369845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.369867] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.369917] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.369934] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.369992] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.370035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.370060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.370086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.370109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.370134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.370158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.370186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.370213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.370240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.370262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.370286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.370314] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.370338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.372704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.372722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.372739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.372757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.374267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.374284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.374298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.375791] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.375808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.377613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.380549] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.380623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.380640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.380662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.397367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.397393] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.397428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.397527] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.397593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.414066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.414090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.414126] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.432994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.433012] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.433032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.433049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.433067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.433082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.433097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.433113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.433130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.433147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.433163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.433179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.433193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.433207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.433234] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.433256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.433277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.433293] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.433407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.433417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.433465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.433485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.433505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.433526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.433543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.433561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.433580] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.433601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.433622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.433642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.433662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.433666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.433686] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.433690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.433710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.433730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.433751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.433771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.433791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.433811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.433831] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.433851] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.433871] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.433893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.433915] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.434012] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.434037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.434062] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.434105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.434132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.434156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.434181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.434204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.434229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.434257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.434284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.434311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.434341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.434362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.434389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.434411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.436724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.436742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.436756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.436771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.438279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.438295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.438309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.439801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.439816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.441622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.444566] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.444632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.444651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.444676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.461374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.461400] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.461435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.461535] [drm:drm_mode_addfb2] [FB:75]
>[ 1391.461593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.478043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.478068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.478105] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.496983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.497004] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.497026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.497046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.497068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.497087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.497107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.497126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.497148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.497169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.497189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.497209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.497228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.497247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.497275] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.497297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.497322] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.497339] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.497446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.497456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.497503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.497522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.497542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.497563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.497579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.497598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.497616] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.497633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.497650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.497665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.497681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.497684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.497699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.497703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.497719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.497734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.497748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.497763] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.497781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.497800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.497821] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.497841] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.497862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.497883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.497905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.497976] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.498005] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.498027] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.498073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.498098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.498123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.498145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.498169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.498193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.498220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.498246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.498274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.498296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.498320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.498349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.498372] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.500716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.500733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.500748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.500762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.502274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.502289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.502303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.503795] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.503811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.505620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.508555] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.508630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.508646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.508668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.525372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.525398] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.525433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.525532] [drm:drm_mode_addfb2] [FB:78]
>[ 1391.525596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.542041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.542066] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.542102] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.560949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.560985] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.561006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.561026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.561048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.561068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.561088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.561107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.561129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.561149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.561170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.561190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.561209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.561228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.561255] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.561278] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.561303] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.561320] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.561434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.561444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.561491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.561511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.561531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.561552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.561569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.561587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.561605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.561622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.561639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.561654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.561669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.561673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.561688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.561692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.561707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.561722] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.561737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.561751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.561769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.561787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.561807] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.561828] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.561848] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.561869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.561891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.561942] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.562000] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.562027] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.562070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.562098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.562122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.562147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.562169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.562194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.562222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.562249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.562276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.562298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.562329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.562355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.562377] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.564715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.564732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.564746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.564761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.566268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.566284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.566298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.567790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.567807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.569615] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.572556] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.572623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.572639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.572660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.589366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.589393] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.589431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.589533] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.589600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.606047] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.606071] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.606108] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.624960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.624995] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.625015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.625035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.625057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.625077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.625096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.625115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.625137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.625158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.625178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.625198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.625217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.625237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.625265] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.625288] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.625313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.625329] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.625444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.625454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.625502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.625521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.625541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.625562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.625579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.625597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.625615] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.625632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.625649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.625665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.625680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.625683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.625698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.625702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.625718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.625733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.625747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.625762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.625780] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.625794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.625810] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.625825] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.625839] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.625857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.625878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.625929] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.625945] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.626002] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.626045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.626069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.626094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.626117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.626140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.626164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.626191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.626218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.626244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.626266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.626290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.626318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.626342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.628365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.628383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.628397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.628412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.629920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.629936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.629949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.631492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.631509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.633341] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.636289] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.636351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.636370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.636396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.653094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.653120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.653155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.653255] [drm:drm_mode_addfb2] [FB:75]
>[ 1391.653321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.669772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.669798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.669835] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.688681] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.688701] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.688723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.688743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.688765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.688784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.688804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.688823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.688845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.688865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.688886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.688906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.688925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.688944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.689022] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.689058] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.689093] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.689119] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.689233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.689247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.689318] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.689345] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.689373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.689403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.689434] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.689458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.689483] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.689505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.689528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.689550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.689571] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.689577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.689599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.689604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.689626] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.689647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.689668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.689689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.689713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.689734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.689754] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.689775] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.689796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.689819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.689844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.689907] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.689929] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.689951] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.690011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.690034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.690058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.690081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.690104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.690127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.690153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.690178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.690203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.690225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.690247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.690273] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.690297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.692288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.692303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.692317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.692332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.693837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.693852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.693865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.695362] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.695378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.697183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.700123] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.700192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.700209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.700231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.716931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.716955] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.717045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.717162] [drm:drm_mode_addfb2] [FB:78]
>[ 1391.717228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.733616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.733640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.733676] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.752530] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.752549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.752569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.752587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.752604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.752620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.752635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.752651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.752672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.752693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.752714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.752734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.752753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.752772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.752800] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.752823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.752849] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.752865] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.752989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.753006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.753289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.753316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.753342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.753371] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.753394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.753420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.753445] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.753469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.753492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.753515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.753536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.753542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.753563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.753569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.753592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.753613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.753636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.753656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.753681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.753702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.753724] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.753745] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.753767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.753790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.753822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.753888] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.753910] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.753932] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.753990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.754015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.754036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.754059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.754079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.754102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.754127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.754152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.754176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.754197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.754218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.754244] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.754265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.756517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.756535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.756549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.756564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.758076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.758092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.758106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.759599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.759615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.761422] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.764366] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.764431] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.764448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.764470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.781174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.781201] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.781238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.781339] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.781400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.797855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.797881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.797918] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.816767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.816786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.816806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.816824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.816842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.816857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.816872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.816889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.816906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.816923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.816938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.816954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.817014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.817039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.817081] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.817116] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.817148] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.817174] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.817279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.817296] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.817377] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.817400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.817425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.817452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.817473] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.817497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.817519] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.817541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.817561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.817583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.817602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.817607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.817627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.817632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.817653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.817672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.817692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.817711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.817735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.817754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.817774] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.817793] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.817814] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.817835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.817859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.817928] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.817950] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.817997] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.818035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.818057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.818079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.818100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.818121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.818143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.818169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.818193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.818218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.818238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.818259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.818285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.818306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.820307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.820324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.820339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.820355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.821860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.821875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.821889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.823385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.823401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.825208] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.828157] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.828218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.828235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.828256] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.844959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.845025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.845060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.845159] [drm:drm_mode_addfb2] [FB:75]
>[ 1391.845216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.861660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.861684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.861720] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.880558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.880577] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.880597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.880614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.880632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.880647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.880662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.880678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.880696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.880712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.880728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.880745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.880763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.880782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.880811] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.880833] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.880858] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.880875] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.880996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.881014] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.881287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.881313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.881341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.881370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.881392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.881418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.881442] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.881466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.881489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.881512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.881533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.881539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.881561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.881566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.881590] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.881611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.881633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.881654] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.881679] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.881699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.881721] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.881742] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.881764] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.881787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.881814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.881892] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.881913] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.881935] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.881972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.882014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.882036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.882059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.882079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.882102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.882127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.882150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.882175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.882195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.882216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.882242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.882264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.884514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.884532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.884546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.884561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.886077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.886093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.886107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.887601] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.887619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.889427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.892358] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.892384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.892400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.892422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.909129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.909155] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.909190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.909291] [drm:drm_mode_addfb2] [FB:78]
>[ 1391.909355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.925801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.925825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.925859] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1391.944673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1391.944692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1391.944712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.944729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.944747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.944762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.944777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.944793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.944811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.944827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.944843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.944859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.944878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.944897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.944925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1391.944948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1391.944973] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.945033] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1391.945145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1391.945159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1391.945230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1391.945257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1391.945279] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1391.945299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1391.945315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1391.945332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1391.945356] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1391.945371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1391.945385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1391.945399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1391.945412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1391.945415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.945428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1391.945431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1391.945445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1391.945458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1391.945471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1391.945484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1391.945500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1391.945513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1391.945526] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1391.945539] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1391.945553] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1391.945568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.945587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1391.945630] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1391.945644] [drm:intel_power_well_enable [i915]] enabling display
>[ 1391.945659] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1391.945686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1391.945705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1391.945723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1391.945741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1391.945758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1391.945775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1391.945795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1391.945814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1391.945833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.945851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1391.945866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1391.945886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1391.945904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1391.947880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1391.947897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1391.947911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.947926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1391.949435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1391.949450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1391.949464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1391.950959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1391.950987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1391.952791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1391.955715] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1391.955749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1391.955765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1391.955790] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1391.972493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1391.972519] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1391.972555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1391.972659] [drm:drm_mode_addfb2] [FB:79]
>[ 1391.972727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1391.989173] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1391.989198] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1391.989234] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.008082] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.008102] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.008122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.008139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.008157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.008172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.008188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.008204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.008222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.008239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.008254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.008270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.008285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.008299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.008326] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.008348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.008373] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.008390] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.008505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.008515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.008562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.008582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.008602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.008623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.008639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.008658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.008676] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.008693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.008710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.008726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.008742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.008745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.008761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.008764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.008780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.008795] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.008810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.008824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.008842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.008857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.008872] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.008886] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.008901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.008918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.008940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.009035] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.009058] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.009083] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.009125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.009151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.009175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.009199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.009222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.009247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.009275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.009302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.009329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.009351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.009375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.009401] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.009426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.011440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.011456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.011473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.011492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.013030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.013048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.013065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.014571] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.014589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.016400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.019336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.019410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.019430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.019456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.036151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.036179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.036216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.036320] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.036389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.052852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.052876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.052913] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.071778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.071798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.071820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.071840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.071862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.071882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.071901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.071921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.071942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.071963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.071984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.072051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.072076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.072099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.072143] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.072182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.072216] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.072243] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.072333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.072343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.072388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.072405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.072423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.072443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.072460] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.072477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.072494] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.072510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.072525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.072543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.072562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.072567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.072586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.072590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.072610] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.072629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.072648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.072668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.072687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.072707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.072726] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.072745] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.072765] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.072785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.072806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.072845] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.072860] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.072876] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.072906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.072927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.072947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.072975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.073018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.073042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.073067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.073089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.073112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.073132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.073152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.073176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.073198] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.075193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.075209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.075223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.075238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.076742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.076757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.076770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.078266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.078283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.080089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.083035] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.083098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.083115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.083137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.099835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.099860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.099894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.100031] [drm:drm_mode_addfb2] [FB:78]
>[ 1392.100131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.116542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.116566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.116602] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.134750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.134769] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.134789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.134806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.134823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.134838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.134853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.134869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.134887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.134903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.134920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.134936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.134950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.134964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.135040] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.135076] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.135109] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.135135] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.135236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.135251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.135320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.135345] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.135373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.135402] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.135427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.135453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.135479] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.135503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.135528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.135558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.135580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.135586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.135607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.135612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.135634] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.135656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.135677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.135698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.135722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.135743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.135765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.135784] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.135805] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.135829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.135854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.135918] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.135940] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.135962] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.136024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.136048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.136072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.136094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.136117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.136140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.136166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.136191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.136215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.136237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.136259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.136285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.136308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.138299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.138315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.138329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.138343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.139849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.139864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.139880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.141378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.141394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.143198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.146142] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.146207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.146224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.146246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.162949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.162976] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.163070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.163185] [drm:drm_mode_addfb2] [FB:79]
>[ 1392.163242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.179651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.179675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.179713] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.198565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.198584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.198604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.198621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.198639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.198654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.198673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.198692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.198714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.198735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.198756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.198776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.198795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.198814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.198842] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.198864] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.198889] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.198905] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.199024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.199041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.199298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.199322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.199348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.199376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.199398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.199422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.199445] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.199469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.199490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.199512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.199532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.199538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.199558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.199563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.199585] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.199605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.199626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.199646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.199669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.199689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.199710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.199730] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.199751] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.199776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.199801] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.199870] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.199892] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.199914] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.199952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.199974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.200015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.200046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.200067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.200089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.200114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.200140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.200164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.200184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.200205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.200231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.200253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.202508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.202526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.202540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.202555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.204077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.204094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.204108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.205609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.205626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.207440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.210389] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.210450] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.210470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.210496] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.227191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.227218] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.227253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.227359] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.227424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.243893] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.243917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.243953] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.262817] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.262836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.262856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.262873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.262891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.262906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.262921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.262937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.262955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.262971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.262987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.263051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.263079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.263103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.263148] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.263184] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.263217] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.263243] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.263360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.263377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.263451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.263477] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.263511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.263538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.263558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.263582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.263604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.263626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.263646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.263667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.263687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.263692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.263712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.263717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.263738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.263757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.263778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.263797] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.263819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.263838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.263859] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.263878] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.263898] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.263922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.263947] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.264042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.264065] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.264089] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.264128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.264152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.264173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.264195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.264215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.264239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.264265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.264290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.264314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.264335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.264357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.264383] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.264406] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.266409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.266426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.266441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.266456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.267962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.267977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.267991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.269529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.269545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.271375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.274323] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.274385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.274404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.274430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.291126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.291152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.291187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.291285] [drm:drm_mode_addfb2] [FB:78]
>[ 1392.291349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.307828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.307852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.307888] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.326730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.326749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.326769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.326786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.326804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.326819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.326833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.326849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.326867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.326883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.326899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.326914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.326928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.326942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.326969] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.326991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.327061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.327088] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.327201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.327215] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.327282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.327308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.327335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.327365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.327390] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.327417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.327442] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.327467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.327493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.327516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.327539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.327546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.327568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.327574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.327598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.327621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.327644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.327665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.327691] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.327715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.327738] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.327761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.327784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.327810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.327837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.327907] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.327932] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.327956] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.328006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.328047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.328071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.328094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.328117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.328141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.328167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.328191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.328215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.328237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.328260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.328286] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.328309] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.330301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.330318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.330335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.330353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.331859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.331875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.331889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.333385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.333401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.335205] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.338147] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.338221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.338236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.338257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.354957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.354983] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.355069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.355192] [drm:drm_mode_addfb2] [FB:79]
>[ 1392.355256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.371657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.371683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.371721] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.390564] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.390583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.390603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.390623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.390645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.390665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.390684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.390703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.390725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.390746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.390766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.390787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.390805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.390824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.390852] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.390875] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.390900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.390916] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.391043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.391060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.391337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.391363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.391390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.391419] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.391442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.391474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.391496] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.391518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.391539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.391560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.391579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.391585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.391604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.391609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.391631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.391650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.391671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.391690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.391713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.391732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.391753] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.391772] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.391793] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.391814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.391838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.391905] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.391927] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.391948] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.391985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.392028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.392053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.392073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.392094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.392116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.392141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.392165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.392189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.392209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.392230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.392256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.392277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.394533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.394551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.394566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.394581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.396112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.396129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.396144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.397641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.397658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.399466] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.402413] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.402475] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.402492] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.402514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.419217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.419243] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.419278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.419381] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.419447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.435920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.435945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.435982] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.454877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.454896] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.454916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.454933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.454951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.454966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.454981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.454997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.455062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.455092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.455119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.455146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.455170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.455195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.455239] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.455273] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.455306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.455331] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.455452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.455469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.455529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.455548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.455567] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.455587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.455602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.455619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.455636] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.455652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.455668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.455682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.455696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.455700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.455714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.455717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.455731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.455745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.455759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.455772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.455788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.455809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.455823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.455836] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.455848] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.455863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.455880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.455925] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.455939] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.455952] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.455977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.455992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.456046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.456067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.456088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.456109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.456133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.456157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.456179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.456200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.456220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.456244] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.456266] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.458482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.458500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.458517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.458536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.460062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.460078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.460093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.461595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.461611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.463423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.466371] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.466431] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.466448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.466471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.483174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.483201] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.483238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.483339] [drm:drm_mode_addfb2] [FB:78]
>[ 1392.483399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.499875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.499899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.499935] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.518807] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.518826] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.518846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.518864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.518881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.518897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.518911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.518928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.518946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.518963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.518979] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.518994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.519055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.519080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.519121] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.519156] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.519189] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.519214] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.519319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.519336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.519417] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.519440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.519466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.519492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.519513] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.519537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.519559] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.519582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.519602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.519623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.519643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.519648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.519668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.519673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.519694] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.519713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.519733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.519752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.519775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.519794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.519814] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.519833] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.519853] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.519875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.519899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.519966] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.519988] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.520009] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.520070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.520092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.520115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.520136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.520158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.520179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.520203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.520227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.520252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.520271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.520293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.520319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.520340] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.522334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.522351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.522365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.522380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.523884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.523899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.523913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.525411] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.525427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.527233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.530175] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.530243] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.530260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.530282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.546985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.547011] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.547161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.547260] [drm:drm_mode_addfb2] [FB:79]
>[ 1392.547323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.563665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.563691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.563729] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.582573] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.582592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.582612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.582629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.582650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.582670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.582690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.582709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.582731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.582752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.582772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.582792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.582811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.582830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.582858] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.582881] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.582905] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.582922] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.583046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.583063] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.583141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.583169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.583197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.583227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.583252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.583271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.583289] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.583305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.583321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.583336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.583351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.583355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.583369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.583373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.583388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.583402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.583416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.583430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.583448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.583462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.583478] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.583492] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.583506] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.583522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.583543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.583593] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.583609] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.583624] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.583655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.583676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.583695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.583715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.583734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.583760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.583778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.583794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.583810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.583823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.583837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.583854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.583870] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.585857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.585874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.585889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.585904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.587413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.587429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.587442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.588963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.588981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.590789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.593714] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.593748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.593768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.593794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.610491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.610517] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.610552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.610652] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.610717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.627192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.627216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.627252] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.646112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.646131] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.646152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.646169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.646187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.646202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.646217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.646233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.646251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.646267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.646283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.646299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.646313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.646327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.646354] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.646375] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.646396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.646412] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.646525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.646536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.646583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.646602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.646622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.646643] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.646661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.646682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.646703] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.646723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.646744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.646764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.646784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.646788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.646808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.646812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.646832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.646852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.646873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.646893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.646913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.646933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.646953] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.646974] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.646994] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.647015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.647082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.647154] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.647176] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.647198] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.647241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.647478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.647495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.647511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.647527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.647544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.647562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.647579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.647595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.647610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.647625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.647644] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.647660] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.649660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.649678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.649695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.649714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.651226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.651243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.651257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.652751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.652769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.654578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.657500] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.657535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.657552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.657573] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.674279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.674305] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.674339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.674439] [drm:drm_mode_addfb2] [FB:78]
>[ 1392.674504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.690959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.690983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.691018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.709882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.709901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.709921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.709938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.709956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.709971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.709986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.710002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.710063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.710091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.710119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.710146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.710170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.710195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.710239] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.710274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.710306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.710332] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.710449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.710466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.710531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.710550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.710569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.710589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.710604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.710621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.710638] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.710654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.710670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.710684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.710698] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.710702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.710724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.710727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.710741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.710758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.710777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.710794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.710813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.710830] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.710848] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.710866] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.710884] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.710903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.710922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.710967] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.710981] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.710996] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.711062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.711086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.711108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.711130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.711151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.711173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.711198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.711221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.711245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.711265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.711285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.711310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.711332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.713329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.713345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.713359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.713374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.714881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.714896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.714913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.716415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.716431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.718239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.721180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.721249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.721266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.721288] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.737999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.738026] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.738115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.738239] [drm:drm_mode_addfb2] [FB:79]
>[ 1392.738305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.754688] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.754712] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.754758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.773622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.773641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.773661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.773679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.773696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.773711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.773726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.773742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.773760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.773776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.773792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.773807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.773822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.773836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.773862] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.773884] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.773905] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.773920] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.774042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.774059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.774136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.774164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.774200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.774229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.774252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.774273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.774290] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.774305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.774319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.774333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.774346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.774351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.774363] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.774367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.774380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.774398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.774416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.774434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.774453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.774470] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.774489] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.774507] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.774525] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.774543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.774563] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.774601] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.774615] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.774630] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.774658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.774677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.774695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.774713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.774731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.774749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.774769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.774788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.774807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.774825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.774843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.774862] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.774880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.776864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.776880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.776895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.776913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.778424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.778440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.778455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.780057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.780073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.781877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.784811] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.784887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.784906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.784932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.801628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.801654] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.801689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.801800] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.801867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.818321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.818345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.818381] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.837224] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.837243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.837263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.837280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.837298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.837313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.837328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.837344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.837362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.837379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.837395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.837411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.837426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.837440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.837467] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.837489] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.837511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.837527] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.837636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.837647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.837694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.837716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.837737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.837761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.837781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.837802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.837822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.837842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.837863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.837883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.837903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.837907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.837927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.837931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.837951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.837972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.837992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.838012] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.838076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.838101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.838126] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.838149] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.838172] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.838198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.838224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.838297] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.838322] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.838343] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.838386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.838411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.838435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.838459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.838483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.838508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.838543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.838567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.838590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.838612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.838633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.838654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.838670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.840665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.840683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.840701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.840719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.842231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.842248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.842262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.843756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.843772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.845581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.848516] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.848590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.848607] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.848629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.865333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.865359] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.865394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.865505] [drm:drm_mode_addfb2] [FB:78]
>[ 1392.865572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.882020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.882057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.882092] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.900945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.900964] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.900984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.901001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.901019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.901077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.901102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.901130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.901160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.901187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.901212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.901238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.901261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.901285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.901328] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.901363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.901394] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.901420] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.901517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.901528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.901576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.901596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.901616] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.901638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.901657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.901677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.901696] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.901715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.901734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.901753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.901772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.901776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.901794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.901798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.901817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.901836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.901855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.901874] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.901894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.901913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.901932] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.901951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.901970] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.901989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.902010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.902098] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.902121] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.902144] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.902184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.902208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.902230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.902253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.902273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.902297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.902322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.902347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.902373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.902393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.902414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.902439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.902462] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.904465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.904483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.904498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.904513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.906105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.906121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.906135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.907630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.907647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.909456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.912404] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.912466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.912483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.912505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.929207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.929233] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.929268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.929381] [drm:drm_mode_addfb2] [FB:79]
>[ 1392.929455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.945900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1392.945923] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1392.945958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1392.964827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1392.964846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1392.964866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.964882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.964900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.964915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.964930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.964946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.964964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.964981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.964997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.965013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.965027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.965086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.965130] [drm:intel_power_well_disable [i915]] disabling display
>[ 1392.965165] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1392.965198] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.965224] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1392.965334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1392.965350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1392.965418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1392.965444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1392.965471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1392.965500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1392.965531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1392.965555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1392.965579] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1392.965602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1392.965625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1392.965646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1392.965667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1392.965673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.965694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1392.965699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1392.965721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1392.965742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1392.965763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1392.965784] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1392.965808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1392.965830] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1392.965852] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1392.965873] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1392.965895] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1392.965917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1392.965941] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1392.966003] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1392.966025] [drm:intel_power_well_enable [i915]] enabling display
>[ 1392.966066] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1392.966106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1392.966131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1392.966154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1392.966177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1392.966199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1392.966223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1392.966248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1392.966272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1392.966297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.966319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1392.966341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1392.966367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1392.966390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1392.968381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1392.968397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1392.968411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.968425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1392.969928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1392.969943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1392.969956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1392.971451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1392.971467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1392.973272] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1392.975875] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1392.975927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1392.975943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1392.975965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1392.992669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1392.992695] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1392.992730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1392.992840] [drm:drm_mode_addfb2] [FB:75]
>[ 1392.992915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.009362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.009386] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.009421] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.028007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.028027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.028094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.028123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.028152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.028177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.028201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.028226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.028255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.028282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.028308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.028333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.028357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.028380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.028423] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.028457] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.028489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.028515] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.028610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.028620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.028666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.028684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.028703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.028725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.028744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.028764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.028783] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.028802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.028822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.028841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.028859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.028863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.028888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.028891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.028907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.028921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.028935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.028949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.028964] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.028977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.028990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.029003] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.029016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.029031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.029088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.029142] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.029162] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.029182] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.029221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.029244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.029266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.029288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.029309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.029332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.029357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.029381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.029405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.029427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.029448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.029473] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.029496] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.031501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.031519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.031533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.031549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.033083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.033099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.033112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.034615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.034633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.036449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.039399] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.039458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.039475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.039497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.056209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.056236] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.056274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.056369] [drm:drm_mode_addfb2] [FB:78]
>[ 1393.056440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.072898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.072922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.072960] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.091822] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.091840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.091861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.091878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.091895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.091910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.091925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.091942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.091959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.091976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.091991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.092007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.092021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.092036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.092114] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.092149] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.092181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.092206] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.092324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.092341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.092420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.092445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.092472] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.092499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.092522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.092546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.092571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.092594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.092617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.092639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.092661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.092667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.092688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.092693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.092715] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.092736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.092758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.092779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.092801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.092823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.092845] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.092866] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.092888] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.092912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.092937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.093005] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.093028] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.093075] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.093115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.093139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.093163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.093186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.093208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.093232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.093258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.093282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.093307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.093329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.093351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.093377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.093401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.095395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.095413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.095430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.095449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.096955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.096971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.096985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.098483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.098499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.100305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.103248] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.103314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.103334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.103360] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.120071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.120097] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.120133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.120245] [drm:drm_mode_addfb2] [FB:79]
>[ 1393.120320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.136749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.136773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.136807] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.155659] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.155678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.155698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.155715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.155732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.155752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.155771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.155791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.155813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.155834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.155854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.155874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.155893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.155912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.155940] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.155962] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.155987] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.156004] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.156119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.156134] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.156205] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.156231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.156259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.156290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.156314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.156341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.156367] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.156392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.156417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.156441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.156464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.156470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.156492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.156498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.156522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.156545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.156568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.156591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.156617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.156640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.156663] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.156684] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.156707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.156733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.156760] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.156830] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.156855] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.156880] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.156920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.156945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.156977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.156999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.157021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.157042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.157085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.157109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.157134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.157157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.157179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.157205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.157229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.159221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.159237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.159250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.159265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.160769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.160784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.160797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.162294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.162310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.164113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.167047] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.167124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.167143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.167174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.183865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.183891] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.183926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.184071] [drm:drm_mode_addfb2] [FB:75]
>[ 1393.184158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.200558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.200582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.200616] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.219468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.219487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.219507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.219525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.219543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.219558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.219573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.219589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.219607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.219627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.219648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.219676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.219695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.219714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.219742] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.219764] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.219789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.219806] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.219908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.219918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.219966] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.219985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.220006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.220030] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.220050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.220107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.220134] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.220161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.220187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.220212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.220236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.220244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.220267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.220274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.220298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.220323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.220348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.220372] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.220399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.220423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.220448] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.220472] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.220496] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.220523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.220552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.220615] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.220640] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.220664] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.220705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.220730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.220753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.220776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.220801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.220826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.220853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.220879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.220906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.220929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.220952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.220980] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.221005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.223027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.223044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.223091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.223118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.224627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.224643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.224657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.226158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.226175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.227992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.230934] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.231001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.231018] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.231040] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.247743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.247771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.247808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.247923] [drm:drm_mode_addfb2] [FB:78]
>[ 1393.247997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.264436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.264459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.264494] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.283333] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.283354] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.283376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.283396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.283417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.283437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.283457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.283476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.283498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.283519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.283539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.283559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.283578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.283597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.283625] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.283647] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.283672] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.283689] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.283804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.283813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.283861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.283880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.283901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.283925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.283945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.283966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.283986] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.284006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.284027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.284047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.284112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.284119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.284147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.284154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.284180] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.284205] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.284231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.284256] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.284283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.284308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.284333] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.284357] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.284381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.284409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.284437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.284498] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.284522] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.284549] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.284589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.284615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.284639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.284663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.284687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.284712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.284738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.284762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.284788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.284811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.284834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.284862] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.284887] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.286892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.286908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.286923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.286938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.288449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.288463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.288477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.290006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.290023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.291837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.294780] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.294846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.294866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.294892] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.311589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.311615] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.311650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.311753] [drm:drm_mode_addfb2] [FB:79]
>[ 1393.311831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.328281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.328304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.328339] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.347181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.347200] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.347220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.347237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.347255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.347275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.347294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.347314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.347336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.347357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.347377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.347397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.347416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.347435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.347463] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.347486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.347511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.347528] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.347643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.347653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.347700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.347720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.347740] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.347761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.347778] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.347796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.347815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.347832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.347849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.347864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.347879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.347883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.347903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.347907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.347927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.347948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.347968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.347988] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.348008] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.348028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.348048] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.348116] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.348144] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.348174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.348203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.348279] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.348304] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.348330] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.348372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.348398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.348424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.348448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.348472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.348497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.348524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.348550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.348576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.348599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.348621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.348649] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.348674] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.350685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.350702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.350716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.350731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.352244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.352259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.352273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.353771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.353789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.355600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.358535] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.358609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.358626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.358648] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.375333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.375360] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.375397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.375505] [drm:drm_mode_addfb2] [FB:75]
>[ 1393.375573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.392041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.392106] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.392161] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.410824] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.410843] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.410863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.410880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.410898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.410913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.410928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.410944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.410962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.410978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.410994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.411009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.411024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.411037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.411114] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.411150] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.411183] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.411209] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.411325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.411339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.411410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.411436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.411464] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.411494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.411518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.411544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.411570] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.411595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.411620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.411644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.411668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.411674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.411696] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.411702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.411726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.411750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.411773] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.411795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.411821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.411852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.411873] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.411894] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.411913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.411936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.411960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.412022] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.412044] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.412087] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.412125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.412150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.412173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.412197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.412219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.412243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.412269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.412293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.412318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.412340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.412362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.412388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.412411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.414413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.414430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.414448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.414466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.415973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.415989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.416004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.418581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.418601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.420427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.423342] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.423384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.423400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.423422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.440128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.440154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.440189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.440290] [drm:drm_mode_addfb2] [FB:78]
>[ 1393.440370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.456820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.456844] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.456879] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.475732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.475751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.475771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.475788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.475806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.475821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.475835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.475851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.475869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.475886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.475902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.475918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.475932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.475946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.475972] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.475993] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.476014] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.476030] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.476167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.476182] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.476251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.476282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.476307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.476333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.476354] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.476377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.476399] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.476421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.476441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.476462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.476481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.476487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.476506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.476512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.476532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.476551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.476571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.476590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.476613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.476631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.476652] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.476671] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.476691] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.476712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.476735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.476786] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.476808] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.476830] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.476866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.476887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.476908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.476927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.476947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.476967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.476990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.477013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.477036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.477055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.477096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.477122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.477144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.479136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.479153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.479167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.479182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.480686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.480704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.480722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.482221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.482239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.484044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.486965] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.487001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.487017] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.487039] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.503745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.503771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.503806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.503917] [drm:drm_mode_addfb2] [FB:79]
>[ 1393.503983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.520437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.520460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.520495] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.539346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.539365] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.539385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.539402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.539420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.539435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.539450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.539466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.539484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.539500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.539516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.539532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.539546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.539560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.539587] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.539609] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.539630] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.539645] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.539755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.539765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.539813] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.539832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.539852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.539873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.539890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.539910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.539931] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.539952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.539972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.539992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.540012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.540016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.540036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.540040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.540061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.540118] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.540146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.540172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.540200] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.540226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.540252] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.540277] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.540301] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.540330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.540358] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.540432] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.540457] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.540482] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.540522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.540548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.540572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.540596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.540619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.540644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.540671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.540697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.540722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.540747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.540771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.540799] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.540823] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.542827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.542843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.542857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.542874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.544387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.544402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.544415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.545912] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.545929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.547739] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.550681] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.550748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.550765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.550787] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.567490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.567517] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.567552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.567667] [drm:drm_mode_addfb2] [FB:75]
>[ 1393.567740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.584183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.584207] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.584242] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.603112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.603131] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.603151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.603168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.603186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.603202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.603217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.603233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.603250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.603267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.603282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.603298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.603312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.603326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.603353] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.603375] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.603396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.603412] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.603526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.603537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.603584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.603604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.603624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.603647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.603667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.603688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.603709] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.603729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.603750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.603770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.603790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.603794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.603814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.603817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.603838] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.603859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.603879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.603899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.603919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.603939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.603959] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.603980] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.604000] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.604021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.604043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.604133] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.604159] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.604184] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.604227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.604255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.604282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.604308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.604333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.604359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.604396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.604422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.604447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.604470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.604493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.604520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.604545] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.606551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.606568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.606583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.606598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.608135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.608151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.608165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.609659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.609675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.611484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.614432] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.614494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.614511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.614532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.631236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.631262] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.631297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.631410] [drm:drm_mode_addfb2] [FB:78]
>[ 1393.631483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.647916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.647941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.647979] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.666859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.666878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.666898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.666915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.666932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.666948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.666962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.666978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.666996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.667013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.667028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.667044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.667058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.667072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.667149] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.667183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.667216] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.667242] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.667352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.667367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.667437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.667460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.667487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.667516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.667538] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.667564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.667587] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.667611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.667633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.667656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.667676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.667682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.667704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.667710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.667733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.667754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.667776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.667796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.667821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.667842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.667872] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.667891] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.667911] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.667932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.667956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.668018] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.668040] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.668062] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.668117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.668139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.668163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.668184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.668206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.668227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.668252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.668276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.668301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.668321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.668342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.668368] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.668389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.670379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.670395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.670412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.670430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.671935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.671952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.671966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.673464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.673482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.675287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.678227] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.678297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.678314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.678336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.695040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.695066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.695152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.695266] [drm:drm_mode_addfb2] [FB:79]
>[ 1393.695330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.711720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.711744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.711780] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.730634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.730653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.730673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.730691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.730708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.730724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.730739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.730755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.730773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.730793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.730814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.730835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.730854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.730873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.730901] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.730924] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.730949] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.730966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.731064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.731110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.731188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.731215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.731244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.731274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.731298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.731333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.731358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.731381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.731404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.731426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.731447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.731453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.731473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.731479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.731500] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.731521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.731543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.731564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.731587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.731608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.731630] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.731651] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.731673] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.731697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.731722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.731791] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.731814] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.731836] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.731873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.731896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.731919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.731941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.731963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.731984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.732008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.732032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.732056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.732077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.732121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.732145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.732169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.734166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.734183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.734198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.734212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.735717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.735732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.735746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.737242] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.737258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.739062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.742006] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.742070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.742121] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.742159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.758813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.758839] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.758874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.758974] [drm:drm_mode_addfb2] [FB:75]
>[ 1393.759040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.775967] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.775991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.776028] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.792842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.792861] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.792881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.792898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.792916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.792931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.792946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.792962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.792980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.792996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.793012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.793028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.793042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.793057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.793083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.793154] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.793187] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.793213] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.793328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.793343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.793389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.793406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.793425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.793448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.793467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.793488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.793508] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.793527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.793548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.793567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.793586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.793591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.793609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.793613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.793633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.793652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.793678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.793694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.793710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.793725] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.793739] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.793753] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.793766] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.793782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.793798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.793840] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.793853] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.793866] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.793891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.793906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.793920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.793933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.793946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.793961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.793976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.793991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.794005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.794019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.794031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.794048] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.794062] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.796080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.796107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.796125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.796143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.797650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.797666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.797680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.799184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.799200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.801037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.803972] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.804047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.804064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.804116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.820788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.820814] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.820849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.820949] [drm:drm_mode_addfb2] [FB:78]
>[ 1393.821007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.837470] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.837494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.837531] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.856379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.856398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.856418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.856434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.856452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.856467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.856482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.856498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.856516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.856532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.856548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.856564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.856578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.856592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.856619] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.856641] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.856661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.856677] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.856782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.856792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.856839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.856859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.856879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.856899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.856916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.856934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.856952] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.856969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.856985] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.857001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.857015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.857019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.857038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.857042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.857063] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.857083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.857143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.857167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.857195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.857220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.857245] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.857270] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.857294] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.857321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.857349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.857409] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.857434] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.857458] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.857499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.857524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.857550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.857574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.857598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.857622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.857649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.857674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.857700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.857723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.857745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.857771] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.857796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.859813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.859832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.859850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.859868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.861379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.861395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.861409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.862902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.862918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.864724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.867660] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.867734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.867750] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.867772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.884476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.884502] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.884537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.884628] [drm:drm_mode_addfb2] [FB:79]
>[ 1393.884689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.901176] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.901200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.901237] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.920096] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.920133] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.920155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.920175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.920196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.920216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.920236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.920255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.920277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.920297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.920318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.920338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.920357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.920376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.920404] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.920427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.920451] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.920468] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.920587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.920596] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.920643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.920662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.920681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.920701] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.920717] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.920735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.920753] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.920778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.920794] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.920809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.920824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.920827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.920842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.920845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.920860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.920875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.920889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.920903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.920920] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.920935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.920950] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.920964] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.920978] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.920995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.921013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.921052] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.921068] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.921084] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.921159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.921184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.921210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.921234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.921258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.921283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.921310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.921336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.921362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.921385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.921408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.921436] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.921461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.923475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.923492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.923507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.923522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.925041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.925058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.925076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.926600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.926617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.928451] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.931396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.931461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.931478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.931500] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1393.948202] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.948228] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.948263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.948364] [drm:drm_mode_addfb2] [FB:75]
>[ 1393.948428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.964883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.964907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.964943] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.982563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1393.982582] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1393.982602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.982619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.982637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.982653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.982667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.982683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1393.982701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.982717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.982733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.982749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.982767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.982786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.982814] [drm:intel_power_well_disable [i915]] disabling display
>[ 1393.982837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1393.982862] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1393.982879] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1393.982994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1393.983004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1393.983052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1393.983071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1393.983092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1393.983156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1393.983183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1393.983212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1393.983239] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1393.983266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1393.983292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1393.983317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1393.983341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1393.983348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.983371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1393.983378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1393.983402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1393.983426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1393.983450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1393.983474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1393.983500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1393.983524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1393.983549] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1393.983573] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1393.983597] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1393.983623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1393.983650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1393.983710] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1393.983734] [drm:intel_power_well_enable [i915]] enabling display
>[ 1393.983759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1393.983799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1393.983824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1393.983849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1393.983872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1393.983901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1393.983924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1393.983948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1393.983971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1393.983995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1393.984016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1393.984037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1393.984063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1393.984086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1393.986117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1393.986134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1393.986149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.986163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1393.987673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1393.987688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1393.987702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1393.989201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1393.989219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1393.991039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1393.993974] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1393.994048] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1393.994065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1393.994093] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.010792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.010819] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.010857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.010951] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.011022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.027462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.027485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.027520] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.046374] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.046393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.046413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.046430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.046447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.046463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.046477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.046494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.046512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.046528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.046544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.046560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.046575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.046589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.046615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.046637] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.046661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.046678] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.046794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.046804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.046852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.046872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.046892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.046914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.046934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.046955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.046976] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.046996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.047016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.047037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.047056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.047061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.047080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.047084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.047105] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.047163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.047191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.047218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.047245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.047271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.047296] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.047321] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.047345] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.047373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.047401] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.047460] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.047485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.047510] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.047551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.047575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.047600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.047623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.047647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.047670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.047697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.047723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.047749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.047772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.047793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.047820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.047845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.049852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.049869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.049884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.049899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.051407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.051422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.051436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.052929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.052945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.054751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.057674] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.057709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.057725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.057747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.074453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.074479] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.074514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.074614] [drm:drm_mode_addfb2] [FB:79]
>[ 1394.074680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.091154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.091178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.091215] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.110056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.110075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.110096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.110155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.110185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.110209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.110233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.110257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.110286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.110313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.110339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.110364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.110385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.110407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.110450] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.110484] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.110515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.110541] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.110654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.110664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.110712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.110733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.110762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.110783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.110799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.110817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.110834] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.110850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.110865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.110880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.110894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.110897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.110911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.110914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.110929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.110943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.110956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.110970] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.110986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.111000] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.111018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.111036] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.111055] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.111074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.111094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.111185] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.111207] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.111230] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.111270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.111294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.111319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.111341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.111364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.111387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.111412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.111436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.111460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.111482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.111503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.111526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.111549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.113563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.113579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.113597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.113615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.115140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.115156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.115170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.116666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.116682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.118506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.121467] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.121514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.121530] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.121552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.138258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.138284] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.138319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.138411] [drm:drm_mode_addfb2] [FB:75]
>[ 1394.138479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.154959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.154983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.155021] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.173882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.173901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.173921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.173938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.173956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.173971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.173986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.174003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.174021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.174037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.174053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.174069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.174083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.174097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.174170] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.174204] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.174237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.174263] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.174363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.174378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.174446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.174471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.174497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.174525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.174547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.174572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.174595] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.174619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.174641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.174664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.174684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.174690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.174711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.174717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.174739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.174760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.174783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.174803] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.174827] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.174848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.174871] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.174891] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.174913] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.174937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.174962] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.175018] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.175051] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.175074] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.175116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.175161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.175183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.175206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.175235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.175257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.175281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.175304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.175326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.175345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.175366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.175390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.175411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.177403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.177419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.177434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.177448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.178952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.178967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.178981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.180478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.180494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.182300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.185240] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.185309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.185326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.185348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.202052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.202078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.202152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.202290] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.202353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.218754] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.218780] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.218819] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.237674] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.237693] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.237713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.237730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.237747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.237762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.237777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.237796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.237818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.237839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.237859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.237879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.237898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.237917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.237945] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.237968] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.237992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.238009] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.238100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.238137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.238215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.238243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.238271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.238301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.238325] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.238352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.238378] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.238403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.238429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.238453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.238476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.238482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.238504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.238510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.238533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.238564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.238585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.238606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.238629] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.238651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.238672] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.238694] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.238715] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.238736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.238762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.238816] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.238838] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.238860] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.238898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.238921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.238943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.238965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.238984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.239006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.239031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.239055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.239079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.239100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.239139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.239165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.239187] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.241185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.241204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.241221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.241239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.242747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.242764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.242782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.244280] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.244298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.246102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.249048] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.249160] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.249188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.249222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.265864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.265892] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.265929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.266023] [drm:drm_mode_addfb2] [FB:79]
>[ 1394.266092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.282544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.282569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.282605] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.301456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.301475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.301495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.301512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.301530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.301546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.301561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.301577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.301595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.301612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.301628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.301644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.301658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.301672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.301699] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.301721] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.301742] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.301757] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.301870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.301880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.301927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.301947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.301967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.301987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.302004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.302023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.302041] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.302058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.302074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.302090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.302105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.302148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.302173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.302180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.302205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.302229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.302253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.302277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.302304] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.302328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.302353] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.302376] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.302401] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.302428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.302456] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.302515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.302539] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.302564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.302607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.302630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.302655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.302678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.302702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.302727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.302754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.302780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.302806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.302830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.302853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.302880] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.302905] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.304909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.304926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.304943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.304962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.306481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.306499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.306517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.308014] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.308032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.309838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.312775] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.312848] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.312865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.312887] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.329591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.329617] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.329652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.329744] [drm:drm_mode_addfb2] [FB:75]
>[ 1394.329811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.346271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.346295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.346331] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.365180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.365199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.365219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.365236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.365257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.365277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.365296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.365316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.365337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.365358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.365379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.365399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.365418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.365437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.365465] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.365488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.365512] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.365529] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.365642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.365652] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.365700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.365721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.365742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.365766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.365786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.365807] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.365828] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.365848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.365868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.365888] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.365908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.365912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.365932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.365936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.365957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.365977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.365997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.366017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.366038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.366058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.366078] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.366098] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.366118] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.366183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.366215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.366275] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.366300] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.366324] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.366367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.366394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.366420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.366445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.366470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.366497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.366525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.366551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.366576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.366607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.366630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.366655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.366678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.368684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.368702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.368719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.368737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.370250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.370266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.370282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.371777] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.371795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.373614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.376552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.376623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.376641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.376663] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.393365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.393392] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.393430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.393522] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.393593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.410067] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.410093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.410168] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.429021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.429040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.429060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.429077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.429095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.429110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.429168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.429193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.429223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.429250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.429275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.429302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.429323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.429346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.429389] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.429423] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.429455] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.429481] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.429591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.429601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.429647] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.429665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.429684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.429703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.429718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.429736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.429753] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.429769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.429784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.429799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.429813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.429817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.429831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.429835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.429850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.429864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.429878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.429892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.429909] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.429923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.429937] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.429950] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.429964] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.429980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.430007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.430042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.430056] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.430068] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.430095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.430114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.430171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.430196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.430221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.430245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.430272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.430297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.430321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.430344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.430366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.430393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.430416] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.432427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.432445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.432459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.432474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.433980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.433996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.434009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.435510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.435526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.437335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.440283] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.440344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.440361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.440383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.457086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.457112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.457199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.457315] [drm:drm_mode_addfb2] [FB:79]
>[ 1394.457381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.473787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.473811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.473848] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.492701] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.492720] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.492740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.492758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.492776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.492791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.492806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.492822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.492840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.492856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.492872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.492888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.492902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.492916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.492943] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.492966] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.492991] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.493008] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.493105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.493147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.493223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.493250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.493279] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.493308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.493341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.493365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.493390] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.493413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.493436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.493458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.493480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.493485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.493506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.493511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.493532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.493554] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.493575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.493596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.493620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.493641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.493662] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.493683] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.493704] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.493728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.493753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.493807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.493829] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.493851] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.493889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.493911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.493932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.493953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.493975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.493997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.494022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.494046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.494070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.494092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.494113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.494155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.494180] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.496178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.496195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.496209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.496224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.497728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.497744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.497762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.499260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.499278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.501085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.504007] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.504042] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.504059] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.504081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.520786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.520813] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.520848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.520948] [drm:drm_mode_addfb2] [FB:75]
>[ 1394.521005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.537487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.537512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.537548] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.556400] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.556419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.556439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.556457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.556474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.556489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.556504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.556520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.556538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.556554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.556570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.556586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.556605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.556624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.556652] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.556675] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.556700] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.556717] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.556827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.556837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.556884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.556904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.556923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.556944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.556961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.556979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.556997] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.557015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.557031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.557047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.557062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.557066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.557081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.557085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.557101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.557116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.557178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.557201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.557228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.557253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.557277] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.557301] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.557325] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.557352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.557380] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.557439] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.557465] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.557490] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.557531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.557555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.557580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.557604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.557628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.557652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.557678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.557704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.557729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.557753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.557782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.557807] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.557831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.559831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.559850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.559867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.559885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.561394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.561412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.561429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.562924] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.562941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.564748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.567683] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.567758] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.567774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.567796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.584497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.584523] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.584559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.584657] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.584721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.601182] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.601208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.601246] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.620101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.620120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.620185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.620210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.620238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.620260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.620283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.620306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.620334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.620360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.620385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.620411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.620432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.620454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.620498] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.620531] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.620564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.620589] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.620701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.620711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.620758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.620778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.620798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.620818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.620834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.620853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.620871] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.620887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.620904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.620919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.620934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.620938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.620952] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.620956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.620971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.620986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.621001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.621015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.621033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.621052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.621073] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.621093] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.621114] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.621135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.621194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.621259] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.621283] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.621307] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.621348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.621373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.621397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.621421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.621444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.621469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.621495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.621520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.621544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.621567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.621589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.621615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.621639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.623669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.623685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.623699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.623714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.625306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.625324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.625342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.626838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.626857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.628665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.631601] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.631674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.631691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.631713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.648417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.648444] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.648482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.648584] [drm:drm_mode_addfb2] [FB:79]
>[ 1394.648652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.665107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.665129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.665213] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.683900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.683919] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.683939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.683956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.683973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.683988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.684003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.684019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.684037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.684054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.684069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.684085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.684099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.684113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.684183] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.684218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.684252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.684278] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.684394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.684411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.684489] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.684517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.684545] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.684575] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.684599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.684633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.684657] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.684680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.684702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.684724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.684745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.684751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.684772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.684777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.684799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.684820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.684841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.684862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.684885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.684906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.684926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.684947] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.684968] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.684991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.685017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.685085] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.685108] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.685130] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.685191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.685215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.685239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.685262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.685285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.685309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.685334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.685359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.685383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.685405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.685427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.685454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.685477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.687476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.687493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.687508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.687523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.689027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.689042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.689059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.690558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.690575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.692381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.695325] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.695390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.695407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.695429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.712128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.712171] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.712205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.712305] [drm:drm_mode_addfb2] [FB:75]
>[ 1394.712368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.728835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.728859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.728895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.747738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.747757] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.747777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.747794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.747812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.747827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.747846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.747865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.747887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.747908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.747929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.747949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.747968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.747987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.748015] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.748038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.748062] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.748079] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.748201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.748218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.748303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.748329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.748357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.748386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.748411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.748436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.748462] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.748487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.748511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.748534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.748556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.748562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.748584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.748589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.748612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.748635] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.748657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.748679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.748705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.748728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.748751] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.748772] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.748794] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.748819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.748846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.748920] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.748945] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.748968] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.749008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.749032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.749056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.749079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.749100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.749131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.749183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.749206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.749230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.749253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.749274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.749301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.749324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.751323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.751340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.751355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.751370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.752874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.752889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.752903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.754401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.754417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.756221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.759136] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.759178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.759195] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.759217] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.775912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.775938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.775975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.776088] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.776209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.792602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.792626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.792662] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.810900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.810921] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.810943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.810963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.810985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.811005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.811024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.811043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.811065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.811086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.811106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.811126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.811145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.811207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.811251] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.811281] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.811306] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.811322] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.811418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.811432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.811506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.811523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.811539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.811558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.811573] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.811589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.811605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.811620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.811634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.811648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.811662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.811666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.811678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.811682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.811695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.811709] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.811721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.811734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.811749] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.811762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.811775] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.811787] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.811800] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.811815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.811831] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.811867] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.811880] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.811894] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.811918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.811933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.811947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.811960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.811974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.811988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.812004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.812018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.812033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.812046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.812059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.812075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.812090] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.814063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.814079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.814094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.814108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.815615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.815630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.815643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.817141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.817168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.818973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.821909] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.821982] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.821999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.822021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.838725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.838751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.838787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.838886] [drm:drm_mode_addfb2] [FB:79]
>[ 1394.838944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.855405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.855429] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.855465] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.874320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.874339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.874359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.874376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.874394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.874409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.874423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.874439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.874457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.874473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.874489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.874505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.874519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.874533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.874560] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.874582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.874602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.874618] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.874724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.874734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.874781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.874800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.874820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.874841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.874858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.874877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.874895] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.874912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.874928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.874944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.874959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.874963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.874978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.874982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.874998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.875013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.875028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.875042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.875060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.875075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.875090] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.875105] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.875119] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.875137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.875196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.875270] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.875296] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.875321] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.875362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.875387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.875413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.875437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.875461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.875486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.875513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.875538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.875563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.875586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.875609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.875636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.875661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.877696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.877713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.877727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.877743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.879256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.879272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.879286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.880781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.880797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.882606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.885544] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.885615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.885632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.885653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.902355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.902379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.902413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.902504] [drm:drm_mode_addfb2] [FB:75]
>[ 1394.902565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.919037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.919060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.919095] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1394.937929] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1394.937948] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1394.937968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.937985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.938002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.938017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.938032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.938048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.938066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.938083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.938098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.938114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.938128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.938142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.938221] [drm:intel_power_well_disable [i915]] disabling display
>[ 1394.938258] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1394.938292] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.938319] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1394.938412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1394.938422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1394.938467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1394.938487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1394.938508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1394.938538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1394.938555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1394.938574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1394.938592] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1394.938611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1394.938628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1394.938647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1394.938664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1394.938668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.938685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1394.938689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1394.938707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1394.938724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1394.938742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1394.938759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1394.938776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1394.938794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1394.938811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1394.938829] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1394.938847] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1394.938866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.938886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1394.938930] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1394.938945] [drm:intel_power_well_enable [i915]] enabling display
>[ 1394.938959] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1394.938987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1394.939005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1394.939023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1394.939041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1394.939059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1394.939077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1394.939096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1394.939115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1394.939135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.939158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1394.939202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1394.939227] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1394.939249] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1394.941243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1394.941259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.941274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.941290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.942795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1394.942810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1394.942824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.944323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.944339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.946141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.949087] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1394.949191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1394.949218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1394.949255] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1394.965904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1394.965930] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1394.965967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1394.966068] [drm:drm_mode_addfb2] [FB:78]
>[ 1394.966136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1394.982585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1394.982611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1394.982649] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.001499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.001518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.001538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.001555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.001573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.001589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.001604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.001620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.001638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.001655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.001671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.001690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.001710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.001729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.001757] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.001780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.001805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.001821] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.001943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.001952] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.001998] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.002017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.002038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.002060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.002080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.002100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.002120] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.002139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.002159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.002214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.002238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.002245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.002269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.002276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.002301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.002325] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.002350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.002373] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.002400] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.002424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.002448] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.002471] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.002494] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.002521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.002548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.002620] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.002644] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.002667] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.002707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.002731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.002755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.002776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.002798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.002820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.002846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.002871] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.002897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.002927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.002948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.002973] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.002996] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.005006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.005024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.005039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.005054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.006564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.006579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.006593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.008109] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.008125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.009933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.012858] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.012891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.012907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.012929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.029635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.029661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.029696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.029796] [drm:drm_mode_addfb2] [FB:79]
>[ 1395.029861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.046315] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.046339] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.046375] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.065226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.065245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.065265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.065282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.065300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.065315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.065329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.065345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.065363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.065380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.065396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.065411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.065425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.065439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.065466] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.065487] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.065508] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.065523] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.065636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.065647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.065694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.065715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.065736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.065759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.065779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.065800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.065821] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.065841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.065861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.065881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.065901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.065905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.065925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.065929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.065950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.065970] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.065990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.066010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.066031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.066050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.066071] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.066091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.066111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.066133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.066155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.066264] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.066290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.066315] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.066358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.066385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.066412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.066437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.066461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.066486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.066513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.066539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.066564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.066587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.066608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.066635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.066660] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.068692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.068710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.068727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.068745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.070267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.070285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.070299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.071793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.071810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.073619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.076398] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.076476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.076493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.076515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.093226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.093252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.093289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.093395] [drm:drm_mode_addfb2] [FB:75]
>[ 1395.093473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.109940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.109964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.110011] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.128241] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.128260] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.128282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.128302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.128323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.128343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.128362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.128382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.128404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.128424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.128445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.128465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.128484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.128503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.128531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.128554] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.128579] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.128595] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.128713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.128723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.128770] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.128791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.128820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.128842] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.128860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.128878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.128897] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.128914] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.128930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.128946] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.128961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.128964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.128979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.128982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.128998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.129012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.129027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.129041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.129058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.129072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.129087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.129101] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.129115] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.129135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.129156] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.129261] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.129283] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.129304] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.129347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.129551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.129571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.129591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.129609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.129629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.129650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.129671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.129691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.129710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.129729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.129749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.129768] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.131841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.131858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.131872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.131886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.133394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.133409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.133423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.134917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.134933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.136740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.139677] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.139751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.139771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.139796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.156492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.156519] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.156553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.156652] [drm:drm_mode_addfb2] [FB:78]
>[ 1395.156718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.173162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.173208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.173242] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.192079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.192100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.192122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.192142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.192163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.192227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.192253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.192280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.192310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.192337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.192364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.192381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.192395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.192410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.192437] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.192459] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.192481] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.192497] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.192568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.192577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.192621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.192637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.192655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.192674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.192691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.192708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.192724] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.192739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.192755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.192769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.192783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.192788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.192801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.192805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.192820] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.192834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.192849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.192862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.192879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.192898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.192918] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.192937] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.192957] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.192978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.192999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.193037] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.193053] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.193068] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.193098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.193118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.193138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.193159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.193214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.193240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.193267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.193293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.193325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.193345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.193365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.193389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.193411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.195407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.195424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.195438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.195453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.196957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.196972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.196986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.198483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.198499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.200306] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.203249] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.203315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.203332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.203354] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.220053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.220079] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.220116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.220283] [drm:drm_mode_addfb2] [FB:79]
>[ 1395.220368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.236758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.236784] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.236822] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.255679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.255698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.255719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.255739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.255761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.255780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.255799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.255819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.255841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.255861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.255882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.255902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.255920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.255939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.255967] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.255990] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.256015] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.256031] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.256122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.256134] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.256231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.256260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.256290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.256321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.256346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.256375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.256402] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.256429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.256454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.256479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.256503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.256511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.256534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.256540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.256565] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.256589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.256612] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.256637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.256663] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.256687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.256710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.256733] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.256763] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.256787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.256813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.256868] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.256890] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.256913] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.256950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.256973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.256995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.257016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.257037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.257060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.257085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.257109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.257132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.257154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.257174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.257215] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.257238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.259250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.259269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.259286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.259304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.260811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.260828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.260842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.262340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.262358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.264162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.267092] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.267127] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.267143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.267165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.283871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.283897] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.283932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.284031] [drm:drm_mode_addfb2] [FB:75]
>[ 1395.284095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.300551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.300576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.300612] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.319465] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.319484] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.319504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.319521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.319539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.319555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.319570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.319586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.319604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.319620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.319636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.319652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.319666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.319680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.319707] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.319729] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.319750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.319765] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.319879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.319889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.319936] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.319956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.319976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.319998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.320018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.320039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.320060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.320080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.320101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.320121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.320141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.320145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.320164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.320207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.320237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.320265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.320292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.320317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.320344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.320369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.320395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.320419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.320443] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.320471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.320500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.320574] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.320598] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.320623] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.320664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.320690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.320714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.320739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.320762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.320787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.320814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.320840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.320864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.320887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.320907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.320934] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.320959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.322977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.322994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.323009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.323024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.324533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.324549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.324562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.326057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.326073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.327882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.330817] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.330892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.330908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.330931] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.347633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.347660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.347697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.347789] [drm:drm_mode_addfb2] [FB:78]
>[ 1395.347859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.364313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.364338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.364373] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.383223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.383241] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.383261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.383281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.383303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.383322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.383342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.383361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.383383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.383403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.383424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.383443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.383462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.383481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.383509] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.383532] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.383557] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.383574] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.383693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.383703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.383747] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.383765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.383784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.383803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.383819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.383836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.383853] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.383869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.383885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.383900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.383914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.383918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.383936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.383939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.383959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.383978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.383997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.384016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.384036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.384054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.384073] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.384092] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.384111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.384131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.384152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.384242] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.384267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.384291] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.384332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.384358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.384382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.384407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.384431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.384455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.384482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.384508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.384533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.384556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.384579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.384605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.384630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.386661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.386680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.386697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.386716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.388246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.388264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.388281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.389776] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.389793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.391600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.394547] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.394610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.394629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.394655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.411353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.411379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.411414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.411511] [drm:drm_mode_addfb2] [FB:79]
>[ 1395.411575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.428032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.428057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.428093] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.446958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.446976] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.446996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.447016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.447038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.447057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.447077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.447096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.447118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.447138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.447159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.447179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.447240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.447265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.447310] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.447344] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.447377] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.447403] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.447522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.447539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.447612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.447640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.447668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.447698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.447722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.447749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.447775] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.447800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.447825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.447849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.447873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.447879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.447902] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.447907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.447931] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.447954] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.447977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.447998] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.448024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.448047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.448070] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.448091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.448113] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.448139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.448166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.448271] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.448295] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.448317] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.448354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.448378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.448401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.448422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.448444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.448465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.448490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.448514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.448537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.448559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.448580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.448606] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.448629] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.450646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.450665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.450682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.450700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.452224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.452240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.452255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.453755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.453772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.455583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.458524] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.458593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.458610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.458631] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.475321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.475345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.475379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.475470] [drm:drm_mode_addfb2] [FB:75]
>[ 1395.475537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.492015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.492038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.492073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.510893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.510914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.510936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.510956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.510978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.510997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.511017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.511036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.511058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.511079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.511100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.511120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.511139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.511158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.511186] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.511256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.511293] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.511319] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.511434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.511445] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.511491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.511511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.511532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.511554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.511573] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.511594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.511614] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.511631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.511651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.511677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.511693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.511698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.511712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.511716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.511730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.511743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.511757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.511769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.511785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.511798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.511811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.511824] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.511837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.511853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.511870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.511904] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.511917] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.511930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.511955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.511969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.511983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.511997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.512010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.512024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.512040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.512055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.512070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.512082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.512095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.512114] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.512136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.514144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.514161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.514175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.514222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.515734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.515750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.515763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.517278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.517296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.519144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.522085] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.522154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.522174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.522241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.538896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.538923] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.538961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.539063] [drm:drm_mode_addfb2] [FB:78]
>[ 1395.539123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.555575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.555600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.555635] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.574482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.574502] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.574522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.574539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.574557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.574573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.574588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.574604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.574622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.574638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.574655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.574671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.574685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.574699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.574726] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.574747] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.574768] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.574784] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.574890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.574900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.574948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.574969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.574990] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.575021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.575039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.575058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.575076] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.575093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.575117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.575133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.575147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.575151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.575170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.575174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.575196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.575247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.575271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.575294] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.575321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.575344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.575368] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.575391] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.575415] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.575441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.575468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.575530] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.575553] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.575577] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.575619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.575645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.575668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.575691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.575714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.575738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.575764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.575789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.575814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.575837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.575859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.575886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.575910] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.577924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.577943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.577960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.577979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.579489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.579507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.579524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.581019] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.581036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.582843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.585765] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.585800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.585817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.585839] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.602533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.602559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.602595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.602695] [drm:drm_mode_addfb2] [FB:79]
>[ 1395.602761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.619224] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.619249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.619285] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.637185] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.637222] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.637243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.637260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.637278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.637294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.637309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.637325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.637343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.637359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.637375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.637391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.637405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.637419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.637446] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.637468] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.637492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.637509] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.637626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.637637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.637686] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.637707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.637728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.637752] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.637772] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.637793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.637814] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.637834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.637855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.637875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.637894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.637898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.637918] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.637922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.637942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.637963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.637982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.638002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.638023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.638043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.638063] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.638083] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.638103] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.638125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.638147] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.638188] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.638247] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.638272] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.638317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.638345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.638371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.638397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.638421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.638448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.638477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.638503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.638531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.638555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.638579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.638608] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.638634] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.640665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.640682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.640697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.640712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.642222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.642238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.642251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.643758] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.643776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.645612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.648561] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.648621] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.648638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.648660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.665373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.665399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.665434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.665540] [drm:drm_mode_addfb2] [FB:75]
>[ 1395.665605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.682062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.682087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.682133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.700973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.700992] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.701012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.701029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.701047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.701062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.701077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.701094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.701111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.701127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.701143] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.701159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.701173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.701186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.701260] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.701295] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.701327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.701353] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.701465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.701479] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.701548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.701571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.701597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.701626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.701648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.701674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.701697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.701721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.701743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.701766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.701786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.701792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.701813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.701819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.701847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.701866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.701886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.701905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.701928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.701946] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.701967] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.701985] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.702006] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.702026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.702050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.702111] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.702134] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.702155] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.702192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.702230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.702253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.702273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.702295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.702316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.702341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.702364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.702388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.702407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.702428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.702454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.702475] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.704476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.704493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.704508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.704523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.706027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.706042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.706056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.707551] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.707569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.709376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.712319] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.712385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.712403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.712425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.729127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.729153] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.729188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.729401] [drm:drm_mode_addfb2] [FB:78]
>[ 1395.729473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.745821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.745845] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.745880] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.764733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.764752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.764773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.764789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.764807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.764823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.764837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.764853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.764871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.764888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.764904] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.764920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.764934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.764948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.764974] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.764996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.765017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.765033] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.765130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1395.765141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1395.765194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.765251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.765280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.765308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.765331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.765357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.765381] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1395.765405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1395.765428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.765450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.765471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.765478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.765500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.765506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.765529] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.765551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.765573] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.765596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1395.765622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.765644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.765667] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1395.765690] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1395.765713] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1395.765739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.765766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1395.765835] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.765850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.765865] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.765892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.765912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.765932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.765952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.765971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.765991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.766012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.766034] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.766054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.766073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.766093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.766114] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1395.766140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.768118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.768134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.768149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.768164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.769679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.769696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.769711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.771248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.771267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.773070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.776221] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1395.776289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.776304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1395.776324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.793025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.793051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.793088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.793321] [drm:drm_mode_addfb2] [FB:79]
>[ 1395.793397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.809732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1395.809756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1395.809794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1395.827406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1395.827425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1395.827446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.827463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.827481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.827496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.827511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.827527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.827545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.827562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.827577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.827593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.827607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.827621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.827649] [drm:intel_power_well_disable [i915]] disabling display
>[ 1395.827672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1395.827698] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1395.827715] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1395.830360] [IGT] kms_flip: exiting, ret=0
>[ 1395.858640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1395.858661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1395.858682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1395.858705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1395.858722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1395.858742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1395.858762] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1395.858782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1395.858802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1395.858822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1395.858841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1395.858846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.858865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1395.858868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1395.858888] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1395.858908] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1395.858927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1395.858947] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1395.858967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1395.858986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1395.859006] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1395.859026] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1395.859045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1395.859066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1395.859088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1395.859155] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1395.859172] [drm:intel_power_well_enable [i915]] enabling display
>[ 1395.859188] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1395.859236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1395.859256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1395.859276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1395.859296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1395.859316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1395.859336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1395.859358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1395.859379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1395.859400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.859420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1395.859439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1395.859461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1395.859480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1395.861478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1395.861494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1395.861507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.861521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1395.863034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1395.863047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1395.863063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1395.864567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1395.864582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1395.866399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1395.869428] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1395.869458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1395.869474] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1395.869497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1395.869554] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1395.869578] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1395.886215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1395.886259] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1395.886296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1395.886423] Console: switching to colour frame buffer device 240x75
>[ 1396.020164] Console: switching to colour dummy device 80x25
>[ 1396.020310] [IGT] kms_flip: executing
>[ 1396.043442] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1396.043472] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1396.045278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1396.045299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1396.047282] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1396.047289] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1396.049277] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1396.049298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1396.051285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1396.051291] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1396.051295] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1396.051311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1396.051331] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1396.052360] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1396.053262] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1396.053279] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1396.053294] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1396.053307] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1396.054288] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1396.054304] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1396.055409] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1396.055412] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1396.055490] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1396.055492] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1396.055497] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1396.055498] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1396.055502] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1396.055504] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1396.055511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1396.055514] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1396.055517] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.055519] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.055522] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1396.055524] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1396.055526] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1396.055529] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1396.055531] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.055534] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.055536] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1396.055539] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1396.055541] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1396.055543] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1396.055546] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1396.055548] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1396.055551] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1396.055553] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1396.055556] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1396.055558] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1396.055561] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1396.055563] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1396.055565] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1396.055568] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1396.055570] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1396.055573] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1396.055575] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1396.055577] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1396.055580] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1396.055582] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1396.055585] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1396.055615] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1396.055632] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1396.057273] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1396.057291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1396.059288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1396.059294] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1396.061278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1396.061299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1396.063286] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1396.063292] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1396.063295] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1396.063495] [IGT] kms_flip: starting subtest 2x-blocking-absolute-wf_vblank
>[ 1396.065830] [IGT] kms_flip: exiting, ret=77
>[ 1396.086483] Console: switching to colour frame buffer device 240x75
>[ 1396.221720] Console: switching to colour dummy device 80x25
>[ 1396.221812] [IGT] kms_flip: executing
>[ 1396.235783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1396.235812] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1396.237292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1396.237311] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1396.239296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1396.239302] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1396.241291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1396.241312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1396.243290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1396.243296] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1396.243301] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1396.243317] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1396.243341] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1396.244375] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1396.245279] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1396.245305] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1396.245327] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1396.245349] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1396.246352] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1396.246377] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1396.247433] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1396.247436] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1396.247515] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1396.247517] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1396.247521] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1396.247523] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1396.247527] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1396.247529] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1396.247537] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1396.247539] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1396.247542] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.247544] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.247547] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1396.247549] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1396.247552] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1396.247554] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1396.247557] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.247559] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1396.247562] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1396.247564] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1396.247566] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1396.247569] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1396.247571] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1396.247574] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1396.247576] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1396.247578] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1396.247581] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1396.247583] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1396.247586] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1396.247588] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1396.247591] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1396.247593] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1396.247595] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1396.247598] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1396.247600] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1396.247603] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1396.247605] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1396.247607] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1396.247610] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1396.247640] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1396.247658] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1396.249285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1396.249303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1396.251297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1396.251303] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1396.253292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1396.253311] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1396.255292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1396.255297] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1396.255301] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1396.255513] [IGT] kms_flip: starting subtest 2x-flip-vs-panning
>[ 1396.257878] [IGT] kms_flip: exiting, ret=77
>[ 1396.286621] Console: switching to colour frame buffer device 240x75
>[ 1396.426567] [IGT] debugfs_emon_crash: executing
>[ 1398.542479] [IGT] debugfs_emon_crash: exiting, ret=0

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